3.4.3. Debugging Guidelines for the JTAG Configuration Scheme. Intel Stratix 10

3. Intel Stratix 10 Configuration Schemes

UG-S10CONFIG | 2018.11.02

3.4.2.1. JTAG Multi-Device Configuration using Download Cable

Figure 34.

Connection Setup for JTAG Multi Device Configuration using Download Cable

Download cable

10-pin male header

(JTAG mode)

Pin 1

V

V

CCIO_SDM

CCIO_SDM

V

CCIO_SDM

10 kΩ 10 kΩ

Intel Stratix 10 nSTATUS nCONFIG

CONF_DONE

MSEL[2:0]

V

CCIO_SDM

10 kΩ 10 kΩ

Intel Stratix 10 nSTATUS nCONFIG

CONF_DONE

MSEL[2:0]

V

CCIO_SDM

10 kΩ 10 kΩ

Intel Stratix 10 nSTATUS nCONFIG

CONF_DONE

MSEL[2:0]

V

CCIO_SDM

TDI

TMS TCK

TDO TDI

TMS TCK

TDO

TDI

TMS TCK

TDO

1 kΩ

GND

Resistor values can vary between 1 k Ω to 10 k Ω .

Perform signal integrity to select the resistor value for your setup.

For JTAG configuration only:

Connect MSEL [2:0] of Intel Stratix 10 devices to VCCIO_SDM through 4.7 k Ω external pull-up resistor.

For JTAG in conjunction with another configuration scheme:

Connect MSEL [2:0] of Intel Stratix 10 devices based on the non-JTAG configuration scheme.

3.4.3. Debugging Guidelines for the JTAG Configuration Scheme

The JTAG configuration scheme overrides all other configuration schemes. The SDM is always ready to accept configuration over JTAG unless a security feature disables the

JTAG interface. JTAG is particularly useful in recovering a device that may be in an unrecoverable state reached when trying to configure using a corrupted image.

An nSTATUS

falling edge terminates any JTAG access and the device reverts to the

MSEL

-specified boot source. nSTATUS

must be stable during JTAG configuration.

nSTATUS

follows nCONFIG

during JTAG configuration. Consequently, nCONFIG

also must be stable.

Unlike other configuration schemes, nSTATUS

does not assert if an error occurs during

JTAG configuration. You must monitor the error messages that the Intel Quartus Prime

Pro Edition Programmer generates for error reporting.

Debugging Suggestions

Here are some debugging tips for JTAG:

• If JTAG configuration is failing, check that the FPGA has successfully powered up and exited POR. One way is to check the hand shaking behavior between nCONFIG and nSTATUS

by driving nCONFIG

low and ensuring that nSTATUS

also goes low.

• Another way to determine whether the device has exited the POR state is to use the Intel Quartus Prime Programmer to detect the device. If the programmer can detect the Intel Stratix 10 device, it has exited the POR state.

• If using an Intel FPGA Download Cable II, reduce the cable clock speed to 6 MHz.

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3. Intel Stratix 10 Configuration Schemes

UG-S10CONFIG | 2018.11.02

• If you have multiple devices in the JTAG chain, try to disconnect other devices from the JTAG chain to isolate the Intel Stratix 10 device.

• If you specify the

OSC_CLK_1

as the clock source for configuration, ensure that

OSC_CLK_1

is running at the frequency you specify in the Intel Quartus Prime software.

• For designs including the High Bandwidth Memory (HBM2) IP or any IP using transceivers, you must provide a free running and stable reference clock to the device before device configuration begins. All transceiver power supplies must be at the required voltage before configuration begins.

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