RM0401
Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex
®
-M4 with FPU CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F4xx microcontrollers implement a special mechanism to be able to boot from other memories (like the internal SRAM).
In the STM32F410, three different boot modes can be selected through the BOOT[1:0] pins
as shown in Table 2 .
Table 2. Boot modes
Boot mode selection pins
BOOT1 x
0
1
BOOT0
0
1
1
Boot mode Aliasing
Main Flash memory Main Flash memory is selected as the boot space
System memory System memory is selected as the boot space
Embedded SRAM Embedded SRAM is selected as the boot space
Note:
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.
BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been sampled, the corresponding GPIO pin is free and can be used for other purposes.
The BOOT pins are also resampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode. After this startup delay is over, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.
When the device boots from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and the offset register.
Embedded bootloader
The embedded bootloader mode is used to reprogram the Flash memory using interfaces
that depend on the package (refer to Table 3
):
Table 3. Embedded bootloader interfaces
Package USART1 USART2 I2C1 I2C2 I2C4 FM+
WLCSP36 X PA2/PA3 PB6/PB7
UFQFPN48 PA9/PA10 PA2/PA3 PB6/PB7
X
X
PB10/PB3
PB14/PB15
LQFP64 PA9/PA10 PA2/PA3 PB6/PB7 PB10/PB11 PB14/PB15
UFBGA64 PA9/PA10 PA2/PA3 PB6/PB7 PB10/PB11 PB14/PB15
SPI1
PA15/PA5/
PB4/PB5
PA4/PA5/
PA6/PA7
PA4/PA5/
PA6/PA7
PA4/PA5/
PA6/PA7
SPI3
X
X
PB12/PB13/
PC2/PC3
PB12/PB13/
PC2/PC3
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The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency.
The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.
Physical remap in STM32F410
Once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in
place of the System bus). This modification is performed by programming the Section 7.2.1:
SYSCFG memory remap register (SYSCFG_MEMRMP)
in the SYSCFG controller.
The following memories can thus be remapped:
• Main Flash memory
• System memory
• Embedded SRAM
Table 4. Memory mapping vs. Boot mode/physical remap in STM32F410
Addresses
Boot/Remap in main
Flash memory
Boot/Remap in embedded SRAM
Boot/Remap in
System memory
0x2000 0000 - 0x2002 7FFF
0x1FFF 0000 - 0x1FFF 77FF
0x0802 0000 - 0x1FFE FFFF
0x0800 0000 - 0x0801 FFFF
0x0400 000 - 0x07FF FFFF
0x0000 0000 - 0x0001 FFFF
(1)
SRAM (32 KB)
System memory
Reserved
Flash memory
Reserved
Flash (128 KB) Aliased
SRAM (32KB)
System memory
Reserved
Flash memory
Reserved
SRAM1 (32 KB)
Aliased
SRAM (32KB)
System memory
Reserved
Flash memory
Reserved
System memory
(30 KB) Aliased
1. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.
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RM0401 Rev 3
