Power controller (PWR) RM0401
Sleep-now mode
Table 15. Sleep-now entry and exit (continued)
Description
Mode exit
Wakeup latency
If WFI or Return from ISR was used for entry:
Interrupt: Refer to Table 39: Vector table
If WFE was used for entry and SEVONPEND = 0
Wakeup event: Refer to
Section 9.2.3: Wakeup event management
f WFE was used for entry and SEVONPEND = 1
Interrupt even when disabled in NVIC: refer to Table 39: Vector table or
Wakeup event (see Section 9.2.3: Wakeup event management ).
None
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
Table 16. Sleep-on-exit entry and exit
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex
®
-M4 with FPU System Control register.
On Return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex
®
-M4 with FPU System Control register.
Interrupt: refer to Table 39: Vector table
None
Entering BAM
The BAM is entered according to Section : Entering low-power mode , when the
SLEEPDEEP bit in the Cortex
®
-M4 with FPU System Control register is cleared.
Refer to Table 17
and
Table 18 for details on how to enter Sleep mode.
Before entering Sleep mode, the Flash memory must be configured by software to operate in the required low- power mode. If data need to be transferred from peripheral to RAM during BAM, the DMA must be enabled before entering Sleep mode.
Exiting BAM
The BAM is exited according to
Section : Exiting low-power mode
.
Refer to Table 17
and
Table 18 for more details on how to exit Sleep mode.
After waking up from BAM, the Flash memory must first to be waked up if code execution restarts from Flash memory.
This wakeup time must be managed by software running from the internal SRAM.
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RM0401 Rev 3
