ST10R272L - INTERRUPT AND TRAP FUNCTIONS
DSTP7
SRCP7
DSTP6
SRCP6
DSTP5
SRCP5
DSTP4
SRCP4
RAM
Address
00’FCFEh
00’FCFCh
00’FCFAh
00’FCF8h
00’FCF6h
00’FCF4h
00’FCF2h
00’FCF0h
DSTP3
SRCP3
DSTP2
SRCP2
DSTP1
SRCP1
DSTP0
SRCP0
RAM
Address
00’FCEEh
00’FCECh
00’FCEAh
00’FCE8h
00’FCE6h
00’FCE4h
00’FCE2h
00’FCE0h
Figure 21 Mapping of PEC pointers into the internal RAM
6.3
Prioritizing interrupt and PEC service requests
Interrupt and PEC service requests from all sources can be enabled for arbitration and service (if chosen), or they may be disabled.
Interrupt requests can be enabled and disabled in three ways:
•
control bits are used to switch each individual source ‘ON’ or ‘OFF’. The control bits
(xxIE) are located in the interrupt control registers. All interrupt requests may be enabled or disabled generally by bit IEN in the PSW register. This control bit is the ‘main switch’ that determines whether a selected is selected.
Before a request can be arbitrated, its source’s enable bit and the global enable bit must both be set.
•
The priority level automatically selects a group of interrupt requests to be acknowledged, disregarding all other requests. The priority level of the source that wins the arbitration is compared against the CPU’s current level. The source is only serviced if its level is higher than the current CPU level. Changing the CPU level to a specific value by software, blocks all requests on the same or lower level. An interrupt source that is assigned to level 0 will be disabled and never serviced.
•
ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1...4 instructions. This is useful e.g. for semaphore handling and
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