Electrical characteristics
6.3.8 External clock source characteristics
STM32MP157A/D
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
Digital and analog bypass modes are available.
The external clock signal has to respect the Table 52: I/O static characteristics . However,
the recommended clock input waveform is shown in Figure 15 for digital bypass mode and
in
Figure 16
for analog bypass mode. In analog bypass mode the clock can be a sinusoidal waveform.
Symbol
Table 29. High-speed external user clock characteristics
(digital bypass) (1)
Parameter Min Typ Max f
HSE_ext
V
SW
(V
HSEH -
V
HSEL)
V
DC t
W(HSE)
User external clock source frequency
OSC_IN amplitude
OSC_IN input voltage
OSC_IN high or low time
1. Guaranteed by design.
8
0.7×V
DD
V
SS
7 -
-
24
-
48
V
DD
0.3×V
SS
-
Unit
MHz
V ns
Figure 15. High-speed external clock source AC timing diagram (digital bypass)
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VHSEH
90 %
VHSEL
10 % tr(HSE)
THSE tf(HSE) tW(HSE) tW(HSE) t
External clock source fHSE_ext
OSC_IN
IL
STM32
Symbol f
HSE_ext
V
HSE
Table 30. High-speed external user clock characteristics
(analog bypass) (1)
Parameter Min Typ Max
User external clock source frequency duty cycle (Square wave) duty cycle deterioration
Absolute input range
8
45
0
0
24
50
±10
(2)
-
48
55
±20
(3)
V
DD ai17528b
Unit
MHz
%
%
-
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STM32MP157A/D Electrical characteristics
Table 30. High-speed external user clock characteristics
(analog bypass) (1) (continued)
Parameter Min Typ Max Symbol Unit
V
PP t
SU
(5)
OSC_IN peak-to-peak amplitude
Time to start
0.2
-
(4)
-
1
0.67×V
10 (6)
DD
V
µs tr/tf
(HSE)
Rise and Fall time
(10% to 90% threshold levels of the input peak-to-peak amplitude)
0.05 ×T
HSE
0.3 ×T
HSE ns
I
(HSE)
Power consumption 150
(7)
500
(8)
µA
1. Guaranteed by design.
2. Guaranteed by design with a square wave signal (@25 °C, V
V
DC is the DC component of the input signal.
DD
=3.3 V /V
PP
= 400 mV / V
DC
=1 V) where
3. Guaranteed by design with a square wave signal (@25 °C, V
V
DC is the DC component of the input signal.
DD
=1.71 V /V
PP
= 200 mV / V
DC
=0.8 V) where
4. minimum peak-to-peak amplitude (@25 °C, 0.1<V input signal.
DC
<V
DD
-0.1 V) where V
DC is the DC component of the
5. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized analog bypass clock interface is reached. This value is measured with 200 mV peak-to-peak amplitude.
6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.
7. with a sine wave signal (V
PP
= 400 mV / V
DC
=0.4 V) where V
DC
is the DC component of the input signal.
8. with a sine wave signal (V input signal.
DD
= 3.6 V / V
PP
= 800 mV / V
DC
= 1.8 V) where V
DC is the DC component of the
Figure 16. High-speed external clock source AC timing diagram (analog bypass)
V
HSE
V
PP
T
HSE t r(HSE)
90% t
10%
External clock source f
HSE_ext
OSC_IN
I
L
STM32
Table 31. Low-speed external user clock characteristics
(analog bypass) (1)
Parameter Min Typ Max Symbol f
LSE_ext
V
LSE
User external clock source frequency
Absolute input range
-
0
32.768
-
-
V
SW
(2)
MSv47498V1
Unit kHz
-
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Electrical characteristics STM32MP157A/D
Table 31. Low-speed external user clock characteristics
(analog bypass) (1) (continued)
Parameter Min Typ Max Symbol Unit
V
PP
I
(LSE)
OSC32_IN peak-to-peak amplitude
Power consumption
0.2
-
(3)
1
120 -
-
1. Guaranteed by design.
2. V
SW
is equal to V
DD
when present or V
BAT
otherwise
3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < V the input signal.
DC
< V
SW
- 0.1 V) where V
DC is the DC component of
V nA
Figure 17. Low-speed external clock source AC timing diagram (analog bypass)
V
LSE
V
PP
T
LSE t
Note:
External clock source f
LSE_ext
OSC32_IN
I
L
STM32
MSv63037V1
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 52: I/O static characteristics . However, the
recommended clock input waveform is shown in Figure 18 for digital bypass and
Figure 17
for analog bypass.
Table 32. Low-speed external user clock characteristics (digital bypass)
(1)
Symbol Parameter Min Typ Max Unit f
LSE_ext
V
LSEH
V
LSEL t w(LSEH) t w(LSEL)
User external clock source frequency
OSC32_IN input pin high level voltage
OSC32_IN input pin low level voltage
OSC32_IN high or low time
1. Guaranteed by design.
-
0.7 × V
DD
V
SS
250
32.768
-
-
-
1000
V
DD
0.3 V
DD
kHz
V ns
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
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Figure 18. Low-speed external clock source AC timing diagram
VLSEH
VLSEL
90%
10 % tr(LSE)
TLSE tf(LSE) tW(LSE) tW(LSE) t
External clock source fLSE_ext
OSC32_IN
IL
STM32 ai17529b
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 8 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in
Table 33 . In
the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Table 33. 8-48 MHz HSE oscillator characteristics (1)
Parameter Operating conditions
(2)
F
R
F
Oscillator frequency
Feedback resistor
-
-
During startup
(3)
I
DD(HSE)
HSE current consumption
V
DD
= 3 V, Rm = 150 Ω
C
L
= 12 pF at 4 MHz
V
DD
= 3 V, Rm = 120 Ω
C
L
= 12 pF at 16 MHz
V
DD
= 3 V, Rm = 100 Ω
C
L
= 10 pF at 24 MHz
V
DD
= 3 V, Rm = 80 Ω
C
L
= 8 pF at 32 MHz
V
DD
= 3 V, Rm = 80 Ω
C
L
= 8 pF at 48 MHz
Startup Gm critmax t
SU
(4)
Maximum critical crystal gm
Start-up time V
DD
is stabilized
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Min
8
-
-
-
-
-
-
-
-
-
Typ
24
200
-
0.35
0.40
0.45
0.65
0.95
-
2
Max
48
-
4
-
-
-
-
-
1.5
-
Unit
MHz kΩ mA mA/V ms
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3. This consumption level occurs during the first 2/3 of the t
SU(HSE)
startup time.
4. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see
Figure 19
). C
L1
and C
L2
are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C
L2
. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C
L1
and C
L2
.
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
Figure 19. Typical application with a 24 MHz crystal
C
L1
OSC_IN f
HSE
24 MHz crystal
R
F
Bias controlled gain
C
L2
OSC_OUT
STM32
MSv63062V1
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in
Table 34 . In
the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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Symbol
Table 34. Low-speed external user clock characteristics (1)
Parameter Operating conditions
(2)
Min Typ Max Unit
I
F
DD
Oscillator frequency
LSE current consumption
-
LSEDRV[1:0] = 00,
Low drive capability
LSEDRV[1:0] = 01,
Medium Low drive capability
LSEDRV[1:0] = 10,
Medium high drive capability
-
-
-
-
32.768
290
390
550 -
-
-
kHz nA
Gm critmax
Maximum critical crystal gm
LSEDRV[1:0] = 11,
High drive capability
LSEDRV[1:0] = 00,
Low drive capability
LSEDRV[1:0] = 01,
Medium Low drive capability
LSEDRV[1:0] = 10,
Medium high drive capability
-
-
-
900
-
-
-
-
0.5
0.75
1.7
µA/V
LSEDRV[1:0] = 11,
High drive capability
2.7
t
SU
(3)
Startup time V
DD
is stabilized 2 s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. t
SU
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
Figure 20. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors
C
L1
OSC32_IN f
HSE
32.768 kHz resonator
R
F
Bias controlled gain
OSC32_OUT
C
L2
STM32 ai17531c
1. Adding an external resistor between OSC32_IN and OSC32_OUT is forbidden.
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