A3G4250D Mechanical and electrical characteristics
2.4.2 I
2
C - inter IC control interface
Subject to general operating conditions for Vdd and Top.
Table 8.
I
2
C slave timing values
I
2
C standard mode
(1)
Symbol Parameter
Min.
Max.
f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
0
4.7
4.0
250
0
4
100
3.45
t su(SR)
Repeated START condition setup time
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1.
Data based on standard I
2
C protocol requirement; not tested in production.
Figure 5.
I
2
C slave timing diagram
(f)
I
2
C fast mode
(1)
Min.
0
Max.
400
1.3
0.6
100
0
0.6
0.9
0.6
0.6
1.3
µs
Unit kHz
µs ns
µs
6'$
67$57
W
VX65
W
Z6365
5(3($7('
67$57
67$57
W
I6'$
W
U6'$
W
VX6'$
W
K6'$
W
VX63
6723
6&/
W
K67
W
Z6&//
W
Z6&/+
W
U6&/
W
I6&/
!-V f.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Doc 022768 Rev 3 13/44
