A3G4250D Application hints
Figure 11.
A3G4250D electrical connections and external component values
Vdd GND GND
+Ω
Z
100 nF 10 µ F
1
X
+Ω
Y
+Ω
X
(TOP VIEW)
DIRECTION S OF THE
DETECTABLE
ANGULAR RATE S
Vdd_IO
S CL/ S PC
S DA_ S DI_ S DO
S DO/ S A0
1
16
TOP
VIEW
1 3
12
4
5 8
9
10nF
C1
10kOhm
R2
C2
470nF
C S DR INT
Vdd I2C bus
Rp u Rp u = 10kOhm
S CL/ S PC
S DA_ S DI_ S DO
P u llu p to b e a dded when I2C interf a ce i s us ed
AM07949V1
Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should be placed as near as possible to the device (common design practice).
If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors
(100 nF and 10 µF between Vdd and common ground, 100 nF between Vdd_IO and common ground) should be placed as near as possible to the device (common design practice).
The A3G4250D IC includes a PLL (phase locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in
Figure 11 ) to implement a second-order low-pass filter. Table 10
summarizes the PLL lowpass filter component values.
Table 10.
PLL low-pass filter component values
Component
C1
Value
10 nF ± 10%
Doc 022768 Rev 3 21/44
