A5975AD Application information
As a consequence, the maximum output current is:
Equation 46
I
OUT MAX
I
SW MAX
1 D where I
SW MAX
represents the rated current of the device.
Figure 29
shows a tested circuit to implement a boost current source for high current LED driving (350 mA). To implement a boost conversion the LED string must be composed of a minimum device number having a total voltage drop larger than maximum input voltage.
The input voltage can be either a DC or AC thanks to the input bridge rectifier. In the case of a DC voltage source D1, D2, D3, D4, C1, and C2 can be removed from the circuit and 1µF capacitor value can be used for C5.
8.10 Synchronization example
See
Section 5.3
for details.
Figure 30. Synchronization example
A5975AD
A5975AD
AM09673v1
8.11 Compensation network with MLCC at the output
The A5975AD standard compensation network (please refer to
Figure and
Section 7
) introduces a single zero and a low frequency pole in the system bandwidth, so a high ESR output capacitor must be selected to compensate the 180-degree phase shift given by the
LC double pole.
The selection of the output capacitor must guarantee that the zero introduced by this component is inside the designed system bandwidth and close to the frequency of the double pole introduced by the LC filter. A general rule for the selection of this compound for the system stability is provided in Equation 47 .
Equation 47 f
Z ESR
=
2 f
LC
1
f
Z ESR
OUT
bandwidth
LC
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Application information A5975AD
MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF-22 µF and rated voltages in the range of 10 V-25 V are available today at relatively low cost from many manufacturers.
These capacitors have very low ESR values (a few m ) and are therefore occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application.
However, the zero given by the output capacitor falls outside the designed bandwidth and so the system becomes unstable with the standard compensation network.
Figure 31
shows the type III compensation network stabilizing the system with ceramic capacitors at the output (the optimum components value depends on the application). This configuration introduces two zeros and a low frequency pole in the designed bandwidth and so guarantees a proper phase margin.
Figure 31. MLCC compensation network circuit
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