Digital-to-Analog converter characteristics. STMicroelectronics STM32L451CC, STM32L451VE, STM32L451VC, STM32L451RC, STM32L451RE, STM32L451CE

Electrical characteristics

6.3.19 Digital-to-Analog converter characteristics

Symbol

V

DDA

V

REF+

V

REF-

R

L

R

O

R

BON

R

BOFF

Parameter

Table 73. DAC characteristics (1)

Conditions

Analog supply voltage for

DAC ON

DAC output buffer OFF (no resistive load on DAC1_OUT1 pin or internal connection)

Other modes

Min

1.71

1.80

Positive reference voltage

DAC output buffer OFF (no resistive load on DAC1_OUT1 pin or internal connection)

Other modes

1.71

1.80

Negative reference voltage

-

Resistive load

Output Impedance

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

Output impedance sample and hold mode, output buffer ON

V

DD

= 2.7 V

V

DD

= 2.0 V

Output impedance sample and hold mode, output buffer OFF

V

DD

= 2.7 V

V

DD

= 2.0 V

DAC output buffer ON

Sample and hold mode

-

-

-

-

5

25

9.6

-

-

C

L

C

SH

V

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC1_OUT1 output

DAC output buffer ON

DAC output buffer OFF

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC1_OUT1 reaches final value

±0.5LSB, ±1 LSB, ±2 LSB,

±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 kΩ

±0.5 LSB

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

V

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 kΩ, DC

0.2

-

-

-

-

-

-

0

-

-

-

Typ

STM32L451xx

Max Unit

-

3.6

-

-

V

V

DDA

-

-

-

13.8

2

3.5

16.5

18.0

50

1

V

REF+

– 0.2

V

REF+

3

2.9

2.85

2.8

2.75

2.5

kΩ kΩ kΩ kΩ pF

µF

V

µs

-

-

1.7

1.6

1.55

1.48

1.4

2

V

SSA

-

-

11.7

-

-

-

-

-

0.1

4.2

2

-80

7.5

5

-28

µs dB

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STM32L451xx Electrical characteristics

Symbol

T

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

I

DDA

(DAC)

Table 73. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimal time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC1_OUT1 for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

CL ≤ 50 pF, RL ≥ 5 kΩ

CL ≤ 10 pF

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DAC1_OUT1 reaches final value ±1LSB)

DAC1_OUT1 pin connected

DAC1_OUT1 pin not connected

(internal connection only)

Output leakage current

DAC output buffer

ON, C

SH

DAC output buffer

OFF, C

SH

= 100 nF

= 100 nF

DAC output buffer

OFF

Sample and hold mode,

DAC1_OUT1 pin connected

Internal sample and hold capacitor

Middle code offset trim time

-

DAC output buffer ON

Middle code offset for 1 trim code step

V

REF+

= 3.6 V

V

REF+

= 1.8 V

DAC consumption from

V

DDA

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

1

1.4

-

-

-

-

-

-

-

-

-

5.2

50

Sample and hold mode, C

SH

100 nF

=

-

Typ

-

0.7

10.5

2

-

7

-

1500

750

315

450

Max

-

3.5

18

3.5

-

(3)

8.8

-

-

-

500

670

Unit

µs ms

µs nA pF

µs

µV

0.2

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

(4)

µA

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Electrical characteristics STM32L451xx

Symbol

I

DDV

(DAC)

Table 73. DAC characteristics (1) (continued)

Parameter Conditions Min

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

-

-

-

DAC consumption from

V

REF+

Sample and hold mode, buffer ON,

C

SH

= 100 nF, worst case

-

Typ

185

340

155

Max

240

400

205

Unit

185 ₓ

Ton/(Ton

+Toff)

(4)

400 ₓ

Ton/(Ton

+Toff)

(4)

µA

Sample and hold mode, buffer OFF,

C

SH

= 100 nF, worst case

-

155 ₓ

Ton/(Ton

+Toff)

(4)

205 ₓ

Ton/(Ton

+Toff)

(4)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 61: I/O static characteristics .

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0394 reference manual for more details.

Figure 31. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

R

LOAD

12-bit digital to analog converter

DACx_OUT

C

LOAD ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

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STM32L451xx

Symbol

DNL

-

INL

.

Parameter

Table 74. DAC accuracy (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF

CL ≤ 50 pF, no RL

Offset

Offset1

Offset error at code 0x800

(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

V

V

REF+

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

V

REF+

= 3.6 V

V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

-

-

-

Electrical characteristics

-

-

-

-

-

-

-

-

-

-

Min

-

-

Typ

-

guaranteed

Max

±2

±2

±4

±4

-

-

-

-

-

-

-

-

-

-

±5

±7

±0.5

±0.5

±30

±12

±12

±25

±8

±5

Unit

LSB

%

LSB

-

-

71.2

71.6

-78

-79

±23 LSB

-

-

-

dB dB

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Electrical characteristics STM32L451xx

Symbol Parameter

Table 74. DAC accuracy (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

-

-

-

70.4

71

11.4

11.5

-

-

-

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

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