Controller Operating Modes. Schneider Electric Twido, Twido Hardware
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Controller Operation
6.2
Controller Operating Modes
Introduction
This section provides information about scanning, operating modes, power supply outages and restoration, warm and cold start, and objects initialization.
What’s in this Section?
This section contains the following topics:
Topic
Cyclic Scan
Periodic Scan
Checking Scan Time
Operating Modes
Dealing with Power Outages and Restoration
Dealing with a Warm Restart
Dealing with a Cold Start
Initialization of Objects
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Cyclic Scan
Introduction
Cyclic scanning involves linking controller cycles together one after the other. After having effected the output update (third phase of the task cycle), the system executes a certain number of its own tasks and immediately triggers another task cycle.
NOTE: The scan time of the user program is monitored by the controller watchdog timer and must not exceed 500 ms. Otherwise an unintended operation occurs causing the controller to stop immediately in Halt mode. Outputs in this mode are forced to their default fallback state.
Operation
The following drawing shows the running phases of the cyclical scan time.
Description of the phases of a cycle
The following table describes the phases of a cycle.
Address Phase
I.P.
Internal processing
-
%I, %IW Acquisition of input
Program processing
%Q,
%QW
Updating of output
Description
The system implicitly monitors the controller (managing system bits and words, updating current timer values, updating status lights, detecting RUN/STOP switches, etc.) and processes requests from TwidoSuite (modifications and animation).
Writing to the memory the status of discrete and application specific module inputs.
Running the application program written by the user.
Writing output bits or words associated with discrete and application specific modules.
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Controller Operation
Operating mode z z z z z z
Controller in RUN , the processor carries out:
Internal processing
Acquisition of input
Processing the application program
Updating of output
Controller in STOP , the processor carries out:
Internal processing
Acquisition of input
Illustration
The following illustration shows the operating cycles.
Check Cycle
The check cycle is performed by watchdog.
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Periodic Scan
Introduction
In this operating mode, acquiring inputs, processing the application program, and updating outputs are done periodically according to the time defined at configuration
(from 2-150 ms).
At the beginning of the controller scan, a timer, the value of which is initialized at the period defined at configuration, starts to count down. The controller scan must end before the timer has finished and relaunches a new scan.
Operation
The following drawing shows the running phases of the periodic scan time.
Description of Operating Phases
The table below describes the operating phases.
Address
I.P.
Phase Description
Internal processing The system implicitly monitors the controller (managing system bits and words, updating current timer values, updating status lights, detecting RUN/STOP switches, etc.) and processes requests from TwidoSuite (modifications and animation).
-
%I, %IW Acquisition of input Writing to the memory the status of discrete and application specific module inputs.
Program processing
Running the application program written by the user.
%Q, %QW Updating of output Writing output bits or words associated with discrete and application specific modules.
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Controller Operation
Operating mode z z z z
Controller in RUN , the processor carries out:
Internal processing
Acquisition of input
Processing the application program
Updating of output
If the period has not finished, the processor completes its operating cycle until the end of the internal processing period. If the operating time is longer than that allocated to the period, the controller indicates that the period has been exceeded by setting the system bit %S19 to 1. The process continues and is run completely.
However, it must not exceed the watchdog time limit. The following scan is linked in after writing the outputs of the scan in progress implicitly.
z z
Controller in STOP , the processor carries out:
Internal processing
Acquisition of input
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Illustration
The following illustration shows the operating cycles.
Controller Operation
Check Cycle z z
Two checks are carried out:
Period overflow
Watchdog
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Controller Operation
Checking Scan Time
General
The task cycle is monitored by a watchdog timer called Tmax (a maximal duration of the task cycle). It allows the detection of application errors (infinite loops, and so on.) and specifies a maximal duration for output refreshing.
Software WatchDog (Periodic or Cyclic Operation)
In periodic or cyclic operation, the triggering of the watchdog causes a software message. The application passes into a HALT state and sets system bit%S11 to 1.
The relaunching of the task necessitates a connection to Trotskyite in order to analyze the cause of the detected error, modification of the application to correct the error, then reset the program to RUN.
NOTE: The HALT state is when the application is stopped immediately because of detection of an application software error such as a scan overrun. The data retains the current values, which allows for an analysis of the cause of the error. The program stops on the instruction in progress. Communication with the controller is open.
Check on Periodic Operation
In periodic operation an additional check is used to detect the period being exceeded: z
%S19 indicates that the period has been exceeded. It is set to: z z
1 by the system when the scan time is greater that the task period,
0 by the user.
z
%SW0 contains the period value (0-150 ms). It is: z
Initialized when starting from a cold start by the value selected on the z configuration,
Able to be modified by the user.
Using Master Task Running Time
The following system words are used for information on the controller scan cycle time: z z z z
%SW11 initializes to the maximum watchdog time (10 to 500 ms).
%SW30 contains the execution time for the last controller scan cycle.
%SW31 contains the execution time for the longest controller scan cycle since the last cold start.
%SW32 contains the execution time for the shortest controller scan cycle since the last cold start.
NOTE: This different information can also be accessed from the configuration editor.
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Operating Modes
Introduction
TwidoSuite is used to take into account the three main operating mode groups: z
Checking z
Running or production z
Stopping
Starting through Grafcet
These different operating modes can be obtained either starting from or using the following Grafcet methods: z
Grafcet initialization z z z
Presetting of steps
Maintaining a situation
Freezing charts
Preliminary processing and use of system bits provide effective operating mode management without complicating and overburdening the user program.
Grafcet System Bits
Use of bits %S21, %S22 and %S23 is reserved for preliminary processing only.
These bits are automatically reset by the system. They must be written by Set
Instruction S only.
The following table provides Grafcet-related system bits:
Bit
%S21
%S22
Function
GRAFCET initialization
GRAFCET RESET
Description
Normally set to 0, it is set to 1 by: z a cold-start, %S0=1 ; z The user, in the pre-processing program part only, using a Set
Instruction S %S21 or a set coil -(S)- %S21 .
Result: z Deactivation of all active steps.
z Activation of all initial steps.
Normally set to 0, it can only be set to 1 by the program in preprocessing.
Result: z Deactivation of all active steps.
z Scanning of sequential processing stopped.
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Bit
%S23
Function
Preset and freeze GRAFCET
Description
Normally set to 0, it can only be set to 1 by the program in preprocessing.
z z
Prepositioning by setting %S22 to 1.
Preposition the steps to be activated by a series of S Xi z instructions.
Enable prepositioning by setting %S23 to 1.
Freezing a situation: z In initial situation: by maintaining %S21 at 1 by program.
z z
In an "empty" situation: by maintaining %S22 at 1 by program.
In a situation determined by maintaining %S23 at 1.
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Dealing with Power Outages and Restoration
Illustration
The following illustration shows the various power restarts detected by the system.
If the duration of the outage is less than the power supply filtering time (about 10 ms for an alternating current supply or 1 ms for a direct current supply), this is not noticed by the program which runs normally.
RUN
Run
Application
Power outage
Standby power
Power restoration
WAIT
Power outage detected
No
Yes
Auto-test
Save context OK
Yes
No
Memory card identical
No
Yes
Normal execution of program
Warm Start Cold Start
NOTE: The context is saved in a battery backed-up RAM. At power up, the system checks the state of the battery and the saved context to decide if a warm start can occur.
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Controller Operation
Run/Stop Input Bit Versus Auto Run
The Run/Stop input bit has priority over the "Automatic Start in Run" option that is available from the Scan Mode dialog box. If the Run/Stop bit is set, then the controller will restart in the Run Mode when power is restored.
The mode of the controller is determined as follows:
Run/Stop Input Bit
Zero
Zero
Rising edge
One
Not configured in software
Not configured in software
Auto Start in Run
Zero
One
No effect
No effect
Zero
One
Resulting State
Stop
Stop
Run
Run
Stop
Run
NOTE: For all Compact type of controllers of software version V1.0, if the controller was in Run mode when power was interrupted, and the "Automatic Start in Run" flag was not set from the Scan Mode dialog box, the controller will restart in Stop mode when power is restored. Otherwise it will perform a cold restart.
NOTE: For all Modular and Compact type of controllers of software version V1.11, if the battery in the controller is operating normally when power was interrupted, the controller will startup in the mode that was in effect at the time the power was interrupted. The "Automatic Start in Run" flag, that was selected from the Scan
Mode dialog, will have no effect on the mode when the power is restored.
Operation
The table below describes the processing phases for power outages.
Phase Description
1 In the event of a power outage the system stores the application context and the time of the outage.
2 All outputs are set to fallback status (0).
3 When power is restored, the context saved is compared with the one in progress which defines the type of start to run: z If the application context has changed (loss of system context or new application), the controller initializes the application: Cold restart (systematic for z compact).
If the application context is the same, the controller restarts without initializing data: warm restart.
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Dealing with a Warm Restart
Cause of a Warm Restart
A warm restart can occur: z z z
When power is restored without loss of application context,
When bit %S1 is set to state 1 by the program,
From the Operator Display when the controller is in STOP mode
Illustration
The drawing below describes a warm restart operation in RUN mode.
RUN WAIT
Acquisition of inputs
Stop the processor
Save application context Execution of program
TOP if bit %S1=1, possible process with warm restart
Restoration of power
Partial configuration auto-tests
Detection of power outage
>Micro power outage
No
BOT
Yes
Set bit %S1 to 1 for only one cycle
Set bit %S1 to 0
Update outputs
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Restart of the Program Execution
The table below describes the restart phases for running a program after a warm restart.
Phase
1
2
3
Description
The program execution resumes from the same element where it was prior to the power outage, without updating the outputs.
Note: Only the same element from the user code is restarted. The system code
(for example, the updating of outputs) is not restarted.
At the end of the restart cycle, the system: z Unreserves the application if it was reserved (and provokes a STOP z application in case of debugging)
Reinitializes the messages
The system carries out a restart cycle in which it: z Relaunches the task with bits %S1 (warm-start indicator) and %S13 (first z cycle in RUN) set to 1
Resets bits %S1 and %S13 to 0 at the end of the first task cycle
Processing of a Warm-Start
In the event of a warm-start, if a particular application process is required, bit %S1 must be tested at the start of the task cycle, and the corresponding program called up.
Outputs after Power Outage
Once a power outage is detected, outputs are set to (default) fallback status (0).
When power is restored, outputs are at last state until they are updated again by the task.
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Dealing with a Cold Start
Cause of a Cold Start
A cold-start can occur: z z z z
When loading a new application into RAM
When power is restored with loss of application context
When system bit %S0 is set to state 1 by the program
From the Operator Display when the controller is in STOP mode
Illustration
The drawing below describes a cold restart operation in RUN mode.
RUN WAIT
Acquisition of inputs
Stop the processor
Save application context
Execution of program
TOP if bit %S0=1, possible process with cold restart
Detection of power outage
>Micro power outage
No
BOT
Set bit %S0 to 0
Yes
Restoration of power
AUTO-TESTS
Completion of configuration auto-tests
Initialization of application
Set bit %S0 to 1
Update outputs
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Operation
The table below describes the restart phases for running a program after a cold restart.
Phase
1
2
3
Description
At start up, the controller is in RUN.
At a cold restart after a stop due to a detected error, the system forces a cold restart.
The program execution restarts at the beginning of the cycle.
The system: z Resets internal bits and words and the I/O images to 0 z z
Initializes system bits and words
Initializes function blocks from configuration data
For this first restart cycle, the system: z Relaunches the task with bits %S0 (cold-start indicator) and %S13 (first cycle z in RUN) set to 1
Resets bits %S0 and %S13 to 0 at the end of this first task cycle z z
Sets bits %S31 and %S38 (event control indicators) to their initial state 1.
Resets bits %S39 (event control indicator) and word %SW48 (counts all events executed except periodic events).
Processing of a Cold-Start
In the event of a cold-start, if a particular application process is required, bit %S0
(which is at 1) must be tested during the first cycle of the task.
Outputs after Power Outage
Once a power outage is detected, outputs are set to (default) fallback status (0).
When power is restored, outputs are at zero until they are updated again by the task.
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Initialization of Objects
Introduction
The controllers can be initialized by TwidoSuite by setting system bits %S0 (a cold restart) and %S1 (a warm restart).
Cold Start Initialization
For a cold start initialization, system bit %S0 must be set to 1.
Initialization of Objects (Identical to Cold Start) on Power-up using %S0 and %S1
To initialize objects on power-up, system bit %S1 and %S0 must be set to 1.
The following example shows how to program a warm restart object initialization using system bits.
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Twido Programmable Controllers
Operator Display Operation
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Operator Display Operation
7
Introduction
This appendix provides an overview, information about operator display controller
ID, system objects, serial port settings, time of day clock, and real-time correction .
What’s in this Chapter?
This chapter contains the following topics:
Topic
Operator Display
Controller Identification and State Information
System Objects and Variables
Serial Port Settings
Time of Day Clock
Real-Time Correction Factor
Page
203
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