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RL78/G14, RL78/G1C, RL78/L12, RL78/L13, RL78/L1C Group Clock Synchronous Single Master Control Software Using CSI Mode of Serial Array Unit
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RL78/G14, RL78/G1C, RL78/L12, RL78/L13, RL78/L1C Group
Clock Synchronous Single Master Control Software Using CSI Mode of Serial Array Unit
1. Specifications
This software program uses the 3-wire serial I/O communications (CSI mode) of the serial array unit (SAU) of the
RL78 Family microcontroller to control clock synchronous communication. The SPI mode single master can be controlled by adding control of SPI slave device selection through port control.
The major functions are summarized below.
This software is a block-type device driver that uses the 3-wire serial I/O communications (CSI mode) of the SAU of the RL78 Family microcontroller as the master device in clock synchronous single master communication.
The MCU’s internal clock synchronous (3-wire) serial communication function is used. It can only be used with a single user-configured channel; that is, it cannot be used with multiple channels.
The sample code does not support chip-select control. To control the SPI device, the chip-select control must be separately embedded.
This software supports MSB-first transfer.
The software supports transfer by the CPU but not by the DMAC.
It does not support using an interrupt to start the transfer.
Table 1-1 Peripheral Devices Used and their Uses
Peripheral Device
SAU
Port
Use
Clock synchronous (3-wire method) serial
1 channel (required)
For SPI slave device select control signals. As many ports as there are SPI slave devices in use are necessary (required).
Not used by this sample code.
RL78
Port
SAU
Slave device select control signal
Clock synchronous
(3-wire method) serial
Slave Device
Figure 1.1 Sample Configuration
R01AN1195EJ0105 Rev.1.05
Mar 31, 2016
Page 4 of 54
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Table of contents
- 4 1. Specifications
- 5 2. Conditions of Checking the Operation of the Software
- 5 (1) RL78/G14 SAU Integrated Development Environment CS+ for CA,CX (Compiler: CA78K0R)
- 5 (2) RL78/G14 SAU Integrated Development Environment CS+ for CC (Compiler: CC-RL)
- 6 (3) RL78/G14 SAU Integrated Development Environment IAR Embedded Workbench
- 6 (4) RL78/G1C SAU Integrated Development Environment CubeSuite+
- 7 (5) RL78/G1C SAU Integrated Development Environment IAR Embedded Workbench
- 7 (6) RL78/L12 SAU Integrated Development Environment CubeSuite+
- 8 (7) RL78/L12 SAU Integrated Development Environment IAR Embedded Workbench
- 8 (8) RL78/L13 SAU Integrated Development Environment CubeSuite+
- 9 (9) RL78/L13 SAU Integrated Development Environment IAR Embedded Workbench
- 9 (10) RL78/L1C SAU Integrated Development Environment CubeSuite+
- 10 (11) RL78/L1C SAU Integrated Development Environment IAR Embedded Workbench
- 11 3. Related Application Notes
- 12 4. Hardware Description
- 12 4.1 List of Pins
- 12 4.2 Reference Circuit
- 13 5. Software Description
- 13 5.1 Operation Outline
- 14 5.1.1 Clock Synchronous Mode Timing
- 14 5.1.2 SPI Slave Device CE# Pin Control
- 15 5.2 Software Control Outline
- 15 5.2.1 Software Configuration
- 15 5.2.2 Serial Enabling (R_SIO_Enable())
- 16 5.2.3 Serial Disabling (R_SIO_Disable())
- 16 5.2.4 Serial Opening (R_SIO_Open_Port())
- 16 5.2.5 Data Transmission (R_SIO_Tx_Data())
- 16 5.2.6 Data Reception (R_SIO_Rx_Data())
- 16 5.2.7 Data Transmission/Reception (R_SIO_TRx_Data())
- 17 5.3 Sizes of Required Memory
- 17 (1) RL78/G14 SAU Integrated Development Environment CS+ for CA, CX (Compiler: CA78K0R)
- 17 (2) RL78/G14 SAU Integrated Development Environment CS+ for CC (Compiler: CC-RL)
- 17 (3) RL78/G14 SAU Integrated Development Environment IAR Embedded Workbench
- 17 (4) RL78/L13 SAU Integrated Development Environment CubeSuite+
- 18 (5) RL78/L13 SAU Integrated Development Environment IAR Embedded Workbench
- 19 5.4 File Configuration
- 20 5.5 List of Constants
- 20 5.5.1 Return Values
- 20 5.5.2 Miscellaneous Definitions
- 21 5.6 Structures and Unions
- 21 5.7 List of Functions
- 22 5.8 Function Specifications
- 22 5.8.1 Driver Initialization Processing
- 23 5.8.2 Serial I/O Disable Setting Processing
- 25 5.8.3 Serial I/O Enable Setting Processing
- 27 5.8.4 Serial I/O Open Setting Processing
- 28 5.8.5 Serial I/O Data Transmit Processing
- 30 5.8.6 Serial I/O Data Receive Processing
- 32 5.8.7 Serial I/O Data Transmit/Receive Processing
- 34 5.9 Macro Function Specifications
- 34 5.9.1 Macro Function SIO_IO_INIT()
- 34 5.9.2 Macro Function SIO_IO_OPEN()
- 35 5.9.3 Macro Function SIO_DATAI_INIT()
- 35 5.9.4 Macro Function SIO_DATAO_INIT()
- 35 5.9.5 Macro Function SIO_DATAO_OPEN()
- 36 5.9.6 Macro Function SIO_CLK_INIT()
- 36 5.9.7 Macro Function SIO_CLK_OPEN()
- 37 5.9.8 Macro Function SIO_ENABLE()
- 38 5.9.9 Macro Function SIO_DISABLE()
- 39 5.9.10 Macro Function SIO_TX_ENABLE()
- 40 5.9.11 Macro Function SIO_TX_DISABLE()
- 41 5.9.12 Macro Function SIO_TRX_ENABLE()
- 42 5.9.13 Macro Function SIO_TRX_DISABLE()
- 43 5.10 State Transition Diagram
- 44 6. Application Example
- 44 6.1 mtl_com.h (common header file)
- 44 (1) Defining the Header Files for the OS
- 44 (2) Defining the Header File with the Common Access Area Defined
- 44 (3) Defining the Loop Timer
- 44 (4) Defining the Endian Mode
- 45 (5) Defining High-Speed Endian Processing
- 45 (6) Defining the Standard Library to Be Used
- 45 (7) Defining the RAM Area to Be Accessed
- 46 6.1.1 mtl_tim.h
- 47 6.2 Setting up the Control Software for Clock Synchronous Single Master Operation
- 47 6.2.1 R_SIO.h
- 47 (1) Defining the Wait Time after Setting Up the BRR
- 47 6.2.2 R_SIO_csi.h
- 47 (1) Defining the Operating Mode to Be Used
- 47 (2) Defining the Form of CRC Calculation to Be Used
- 48 (3) Defining the Pins to Be Used
- 48 (4) Defining the Peripheral Enable Register
- 48 (5) Defining the CSI Channel to Be Used
- 49 (6) Defining the Operating Clock to Be Used in the Serial Clock Select Register (SPSm)
- 49 (7) Defining the Operating Clock (fMCK) Selection for the Channel to Be Used
- 49 (8) Defining the Serial Output Value
- 50 (9) Defining the Serial Output Level Register (SOLm)
- 50 (10) Defining the Port Input Mode Register (PIM) and the Port Output Mode Register (POM)
- 51 6.3 R_SIO_csi.c
- 51 6.4 Setting the definition of SFR
- 52 7. Usage Notes
- 52 7.1 Usage Notes to be Observed when Building the Sample Code
- 52 7.2 Unnecessary Functions
- 52 7.3 Using Other MCUs
- 52 7.4 Port Control for Serial Data and Clock Output Pins
- 52 7.5 Enabling/Disabling Clock Supply to the Serial Array Unit
- 52 7.6 Prohibition of Data Transmission and Reception
- 53 7.7 Setting Serial Output Level Register (SOLm)
- 53 7.8 About Warnings of Duplicate Type Declaration
- 55 Revision History
- 57 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
- 58 Notice