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RL78/G14, RL78/G1C, RL78/L12, RL78/L13, RL78/L1C Group Clock Synchronous Single Master Control Software Using CSI Mode of Serial Array Unit
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RL78/G14, RL78/G1C, RL78/L12, RL78/L13, RL78/L1C Group
Clock Synchronous Single Master Control Software Using CSI Mode of Serial Array Unit
7. Usage Notes
7.1 Usage Notes to be Observed when Building the Sample Code
To incorporate the sample code, include R_SIO.h and R_SIO_csi.h (after renaming R_SIO_csi.h.XXX).
7.2 Unnecessary Functions
Unused functions waste ROM capacity, so we recommend excluding them by commenting them out and so on.
7.3 Using Other MCUs
Other MCUs can easily be used.
The files to be prepared are as follows:
A common I/O module definition file corresponding to R_SIO_csi.h.XXX
A header definition file corresponding to mtl_com.h.XXX
Make them by referring the attachment.
7.4 Port Control for Serial Data and Clock Output Pins
To set these pins to function as ports, set to 1 the CKOmn and SOmn bits in the serial output register (SOm). The output from these pins is determined by an AND operation using the serial output register (SOm) setting and the output latch setting of the corresponding port registers (Pxx). When the CKOmn bit and SOmn bit are set to 1, the unmodified port register (Pxx) setting value becomes the output value of the corresponding pin.
7.5 Enabling/Disabling Clock Supply to the Serial Array Unit
In the sample code, supply of the clock is started by the serial I/O enable setting processing (R_SIO_Enable()), but no control over stopping the clock is provided by the serial I/O disable setting processing (R_SIO_Disable()). This is because it is assumed that other programs may be using the other channels of the same unit.
Therefore, the user should provide additional program code with the necessary control functions if there is a need to stop operation of individual units in order to reduce power consumption and noise, taking into account the control of channels other than the one used by the sample code.
Note that the sample code does provide the capability to stop operation of the channel used by the application.
7.6 Prohibition of Data Transmission and Reception
Do not perform serial data transmission or reception if the serial I/O function has not been enabled.
In the sample code, supply of the clock to the serial array unit starts when driver initialization processing
(R_SIO_Init_Driver()) is performed. Executing serial I/O data transmit processing (R_SIO_Tx_Data()) or serial I/O data receive processing (R_SIO_Rx_Data()) in this state will cause transmission or reception processing to start even though the correct register settings for the serial I/O function have not been completed. It is not possible for transmission or reception processing to proceed properly in this state because the register settings for items such as the baud rate are not correct.
To perform serial I/O data transmit processing (R_SIO_Tx_Data()) or serial I/O data receive processing
(R_SIO_Rx_Data()), first execute serial I/O enable setting processing (R_SIO_Enable()) to make the necessary register
settings related to serial I/O. Also refer to 5.10, State Transition Diagram.
R01AN1195EJ0105 Rev.1.05
Mar 31, 2016
Page 52 of 54
RL78/G14, RL78/G1C, RL78/L12, RL78/L13, RL78/L1C Group
Clock Synchronous Single Master Control Software Using CSI Mode of Serial Array Unit
7.7 Setting Serial Output Level Register (SOLm)
In CSI mode the inversion setting is prohibited. Set 1 in order to write 0 to the relevant SOLmn bit and reserved bits.
The reason for setting 1 is to contain the operation of writing 0 to the point that is set to 1 in the sample code,
Also refer to 6.2.2 (9), Defining the Serial Output Level Register (SOLm).
7.8 About Warnings of Duplicate Type Declaration
This driver has declared the intN_t and uintN_t that are declared in the "stdint.h". There is a possibility that the warning occurs when including the "stdint.h". If the type of declaration is unnecessary, delete the declaration of this driver.
R01AN1195EJ0105 Rev.1.05
Mar 31, 2016
Page 53 of 54
RL78/G14, RL78/G1C, RL78/L12, RL78/L13, RL78/L1C Group
Clock Synchronous Single Master Control Software Using CSI Mode of Serial Array Unit
Website and Support
Renesas Electronics Website http://www.renesas.com/
Inquiries http://www.renesas.com/contact/
All trademarks and registered trademarks are the property of their respective owners.
R01AN1195EJ0105 Rev.1.05
Mar 31, 2016
Page 54 of 54
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Table of contents
- 4 1. Specifications
- 5 2. Conditions of Checking the Operation of the Software
- 5 (1) RL78/G14 SAU Integrated Development Environment CS+ for CA,CX (Compiler: CA78K0R)
- 5 (2) RL78/G14 SAU Integrated Development Environment CS+ for CC (Compiler: CC-RL)
- 6 (3) RL78/G14 SAU Integrated Development Environment IAR Embedded Workbench
- 6 (4) RL78/G1C SAU Integrated Development Environment CubeSuite+
- 7 (5) RL78/G1C SAU Integrated Development Environment IAR Embedded Workbench
- 7 (6) RL78/L12 SAU Integrated Development Environment CubeSuite+
- 8 (7) RL78/L12 SAU Integrated Development Environment IAR Embedded Workbench
- 8 (8) RL78/L13 SAU Integrated Development Environment CubeSuite+
- 9 (9) RL78/L13 SAU Integrated Development Environment IAR Embedded Workbench
- 9 (10) RL78/L1C SAU Integrated Development Environment CubeSuite+
- 10 (11) RL78/L1C SAU Integrated Development Environment IAR Embedded Workbench
- 11 3. Related Application Notes
- 12 4. Hardware Description
- 12 4.1 List of Pins
- 12 4.2 Reference Circuit
- 13 5. Software Description
- 13 5.1 Operation Outline
- 14 5.1.1 Clock Synchronous Mode Timing
- 14 5.1.2 SPI Slave Device CE# Pin Control
- 15 5.2 Software Control Outline
- 15 5.2.1 Software Configuration
- 15 5.2.2 Serial Enabling (R_SIO_Enable())
- 16 5.2.3 Serial Disabling (R_SIO_Disable())
- 16 5.2.4 Serial Opening (R_SIO_Open_Port())
- 16 5.2.5 Data Transmission (R_SIO_Tx_Data())
- 16 5.2.6 Data Reception (R_SIO_Rx_Data())
- 16 5.2.7 Data Transmission/Reception (R_SIO_TRx_Data())
- 17 5.3 Sizes of Required Memory
- 17 (1) RL78/G14 SAU Integrated Development Environment CS+ for CA, CX (Compiler: CA78K0R)
- 17 (2) RL78/G14 SAU Integrated Development Environment CS+ for CC (Compiler: CC-RL)
- 17 (3) RL78/G14 SAU Integrated Development Environment IAR Embedded Workbench
- 17 (4) RL78/L13 SAU Integrated Development Environment CubeSuite+
- 18 (5) RL78/L13 SAU Integrated Development Environment IAR Embedded Workbench
- 19 5.4 File Configuration
- 20 5.5 List of Constants
- 20 5.5.1 Return Values
- 20 5.5.2 Miscellaneous Definitions
- 21 5.6 Structures and Unions
- 21 5.7 List of Functions
- 22 5.8 Function Specifications
- 22 5.8.1 Driver Initialization Processing
- 23 5.8.2 Serial I/O Disable Setting Processing
- 25 5.8.3 Serial I/O Enable Setting Processing
- 27 5.8.4 Serial I/O Open Setting Processing
- 28 5.8.5 Serial I/O Data Transmit Processing
- 30 5.8.6 Serial I/O Data Receive Processing
- 32 5.8.7 Serial I/O Data Transmit/Receive Processing
- 34 5.9 Macro Function Specifications
- 34 5.9.1 Macro Function SIO_IO_INIT()
- 34 5.9.2 Macro Function SIO_IO_OPEN()
- 35 5.9.3 Macro Function SIO_DATAI_INIT()
- 35 5.9.4 Macro Function SIO_DATAO_INIT()
- 35 5.9.5 Macro Function SIO_DATAO_OPEN()
- 36 5.9.6 Macro Function SIO_CLK_INIT()
- 36 5.9.7 Macro Function SIO_CLK_OPEN()
- 37 5.9.8 Macro Function SIO_ENABLE()
- 38 5.9.9 Macro Function SIO_DISABLE()
- 39 5.9.10 Macro Function SIO_TX_ENABLE()
- 40 5.9.11 Macro Function SIO_TX_DISABLE()
- 41 5.9.12 Macro Function SIO_TRX_ENABLE()
- 42 5.9.13 Macro Function SIO_TRX_DISABLE()
- 43 5.10 State Transition Diagram
- 44 6. Application Example
- 44 6.1 mtl_com.h (common header file)
- 44 (1) Defining the Header Files for the OS
- 44 (2) Defining the Header File with the Common Access Area Defined
- 44 (3) Defining the Loop Timer
- 44 (4) Defining the Endian Mode
- 45 (5) Defining High-Speed Endian Processing
- 45 (6) Defining the Standard Library to Be Used
- 45 (7) Defining the RAM Area to Be Accessed
- 46 6.1.1 mtl_tim.h
- 47 6.2 Setting up the Control Software for Clock Synchronous Single Master Operation
- 47 6.2.1 R_SIO.h
- 47 (1) Defining the Wait Time after Setting Up the BRR
- 47 6.2.2 R_SIO_csi.h
- 47 (1) Defining the Operating Mode to Be Used
- 47 (2) Defining the Form of CRC Calculation to Be Used
- 48 (3) Defining the Pins to Be Used
- 48 (4) Defining the Peripheral Enable Register
- 48 (5) Defining the CSI Channel to Be Used
- 49 (6) Defining the Operating Clock to Be Used in the Serial Clock Select Register (SPSm)
- 49 (7) Defining the Operating Clock (fMCK) Selection for the Channel to Be Used
- 49 (8) Defining the Serial Output Value
- 50 (9) Defining the Serial Output Level Register (SOLm)
- 50 (10) Defining the Port Input Mode Register (PIM) and the Port Output Mode Register (POM)
- 51 6.3 R_SIO_csi.c
- 51 6.4 Setting the definition of SFR
- 52 7. Usage Notes
- 52 7.1 Usage Notes to be Observed when Building the Sample Code
- 52 7.2 Unnecessary Functions
- 52 7.3 Using Other MCUs
- 52 7.4 Port Control for Serial Data and Clock Output Pins
- 52 7.5 Enabling/Disabling Clock Supply to the Serial Array Unit
- 52 7.6 Prohibition of Data Transmission and Reception
- 53 7.7 Setting Serial Output Level Register (SOLm)
- 53 7.8 About Warnings of Duplicate Type Declaration
- 55 Revision History
- 57 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
- 58 Notice