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CHAPTER 17 STANDBY FUNCTION
17.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only during main system clock operation.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V
DD
via a pull-up resistor to suppress the leakage at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to release the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
Table 17-3. STOP Mode Operating Status
STOP Mode
Setting
Item
Clock generator
CPU
Output ports (output latches)
16-bit timer/event counter
8-bit timer/event counter
Watchdog timer
A/D converter
Watch timer
With Subsystem Clock
Only main system clock stops oscillation.
Operation stopped
Status before STOP instruction execution is held.
Operation stopped
Operation enabled only when TI1 and TI2 are selected for the count clock.
Operation stopped
Without Subsystem Clock
Clock output
Operation enabled only when f
XT
is selected for the count clock.
Operation enabled when f
XT
is selected for the output clock.
Operation stopped
PCL is low level.
Buzzer output
VFD controller/driver
Serial interface
Other than automatic transmit/receive function
Automatic transmit/ receive function
BUZ is low level.
Operation disabled
Operation enabled only when external input clock is selected as serial clock.
Operation stopped
External interrupts
INTP0
INTP1 to INTP3
Operation disabled
Operation enabled
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CHAPTER 17 STANDBY FUNCTION
(2) STOP mode release
The STOP mode can be released by the following three sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgment is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out. If interrupt request acknowledgment is disabled, the instruction at the next address is executed.
Figure 17-4. STOP Mode Release by Interrupt Request Generation
Interrupt request
STOP instruction
Standby release signal
Operating mode
Clock
Oscillation
STOP mode
Oscillation stop
Wait
(time set by OSTS)
Oscillation stabilization wait status
Oscillation
Operating mode
Remark The broken line indicates the case when the interrupt request which has released the standby status is acknowledged.
(b) Release by unmasked test input
When an unmasked test signal is input, the STOP mode is released. After the lapse of oscillation stabilization time, the instruction at the next address to the STOP instruction is executed.
User’s Manual U11302EJ5V0UD
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CHAPTER 17 STANDBY FUNCTION
(c) Release by RESET input
When a RESET signal is input, the STOP mode is released. After the lapse of oscillation stabilization time, a reset operation is carried out.
Figure 17-5. STOP Mode Release by RESET Input
Wait
(2 17 /f
X
: 26.2 ms)
STOP instruction
RESET signal
Operating mode
Clock
Oscillation
STOP mode
Oscillation stop
Reset period
Oscillation stabilization wait status
Oscillation
Operating mode
Remarks 1. f
X
: Main system clock oscillation frequency
2. Figures in parentheses apply to operation with f
X
= 5.0 MHz.
Release Source
Maskable interrupt request
Test input
RESET input
Table 17-4. Operation After STOP Mode Release
1
0
0
0
MK
××
PR
××
0 0
0
0
0
1
1
–
1
1
×
–
–
–
1
1
×
×
×
×
0
×
IE
0
0
1
×
×
×
×
ISP
×
×
1
Operation
Next address instruction execution
Interrupt servicing
Next address instruction execution
Interrupt servicing
STOP mode hold
Next address instruction execution
STOP mode hold
Reset processing
×: don’t care
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User’s Manual U11302EJ5V0UD
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