MTS Firmware Engineer

AGESA™--Arch2008

MEMCLK_DIS_MAP

Prototype

MEMCLK_DIS_MAP (SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map,

Bit4Map, Bit5Map, Bit6Map, Bit7Map)

Parameters

SocketID

Mask indicating the physical processor socket or sockets. Possible values are:

SOCKET0

SOCKET1

SOCKET2

SOCKET3

SOCKET4

SOCKET5

SOCKET6

SOCKET7

ANY_SOCKET

These values may be combined as follows: SOCKET0 + SOCKET2

ChannelID

A mask indicates the physical channel. Possible values are:

CHA

CHB

CHC

CHD

ANY_CHANNEL

These values may be combined as follows: CHA + CHC

Bit[7:0]Map

Indicating the memory clock pins connect to which memory chip-selects / ranks.

Description

The memory clock pins are identified based on BKDG definition of MEM_CLK_DIS bitmap.

Disabling unused MemClk may save power.

For example, BKDG definition of MEM_CLK_DIS bitmap is like below:

Bit pin name

0 M[B,A]_CLK_H/L[0]

1 M[B,A]_CLK_H/L[1]

2 M[B,A]_CLK_H/L[2]

3 M[B,A]_CLK_H/L[3]

4 M[B,A]_CLK_H/L[4]

5 M[B,A]_CLK_H/L[5]

6 M[B,A]_CLK_H/L[6]

7 M[B,A]_CLK_H/L[7]

279

Memory Details Appendix C

AGESA™--Arch2008

And platform has the following routing:

CS0 M[B,A]_CLK_H/L[4]

CS1 M[B,A]_CLK_H/L[2]

CS2 M[B,A]_CLK_H/L[3]

CS3 M[B,A]_CLK_H/L[5]

Then platform can specify the following macro:

MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08,

0x00, 0x00)

Appendix C Memory Details

280