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AGESA™--Arch2008
TBLDRV_OVERRIDE_MR0_CL
Prototype
TBLDRV_OVERRIDE_MR0_CL (RegValOfTcl, MR0CL13, MR0CL0)
Parameters
RegValOfTcl
A 8 bits value indicating the value of Tcl bit field value in memory controller register.
MR0CL13
The encoding value of MR0 command CL[3:1] bit field.
MR0CL0
The encoding value of MR0 command CL[0] bit field.
Description
This macro does NOT need to combine with any configuration macro, it specifies the encoding value of MR0 command CL[3:0] bit field to override corresponding to the value of
Tcl bit field in memory controller register. Multiple TBLDRV_OVERRIDE_MR0_CL macros are allowed to put together, they override the encoding value of MR0 command CL[3:0] bit field corresponding to various Tcl value in the register.
319
Memory Details Appendix C
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Table of contents
- 278 MOTHER_BOARD_LAYERS
- 279 MEMCLK_DIS_MAP
- 281 ON_DIMM_THERMAL_CONTROL
- 282 CKE_TRI_MAP
- 283 ODT_TRI_MAP
- 284 CS_TRI_MAP
- 285 NUMBER_OF_DIMMS_SUPPORTED
- 286 NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED
- 287 NUMBER_OF_CHIP_SELECTS_SUPPORTED
- 288 NUMBER_OF_CHANNELS_SUPPORTED
- 289 OVERRIDE_DDR_BUS_SPEED
- 290 DRAM_TECHNOLOGY
- 291 WRITE_LEVELING_SEED
- 292 HW_RXEN_SEED
- 293 NO_LRDIMM_CS67_ROUTING
- 294 SOLDERED_DOWN_SODIMM_TYPE
- 295 MIN_RD_WR_DATAEYE_WIDTH
- 296 CPU_FAMILY_TO_OVERRIDE
- 298 CONDITION_AND
- 299 COND_LOC
- 300 COND_SPD
- 301 ACTION_ODT
- 302 ACTION_ADDRTMG
- 303 ACTION_ODCCTRL
- 304 ACTION_SLEWRATE
- 305 ACTION_SPEEDLIMIT
- 306 TBLDRV_CONFIG_TO_OVERRIDE
- 308 TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE
- 309 TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE
- 311 TBLDRV_CONFIG_ENTRY_SPEEDLIMIT
- 312 TBLDRV_CONFIG_ENTRY_ODT_RTTNOM
- 313 TBLDRV_CONFIG_ENTRY_ODT_RTTWR
- 314 TBLDRV_CONFIG_ENTRY_ODTPATTERN
- 315 TBLDRV_CONFIG_ENTRY_ADDRTMG
- 316 TBLDRV_CONFIG_ENTRY_ODCCTRL
- 317 TBLDRV_CONFIG_ENTRY_SLOWACCMODE
- 318 TBLDRV_CONFIG_ENTRY_RC2_IBT
- 319 TBLDRV_OVERRIDE_MR0_CL
- 320 TBLDRV_OVERRIDE_MR0_WR
- 321 TBLDRV_OVERRIDE_RC10_OPSPEED
- 322 TBLDRV_CONFIG_ENTRY_LRDMM_IBT
- 323 TBLDRV_CONFIG_ENTRY_2D_TRAINING
- 324 TBLDRV_INVALID_CONFIG