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AGESA™--Arch2008
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE
Prototype
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE (DimmPerCH, Dimms, NumOfSR, NumOfDR,
NumOfQR, NumOfLRDIMM)
Parameters
DimmPerCH
Number of DIMM slots in a channel.
Dimms
Number of DIMMs in a channel.
NumOfSR
Number of Single rank DIMMs in a channel
NumOfDR
Number of dual rank DIMMs in a channel
NumOfQR
Number of Quad rank DIMMs in a channel
NumOfLRDIMM
Number of LR-DIMMs (Load reduce DIMMs) in a channel
Description
This configuration macro is only used with memory speed limit override macro, it specifies what kind of configuration that applies the override.
NumOfLRDIMM should be stated as "NA_" in a normal DIMM type platform. NumOfSR,
NumOfDR and NumOfQR should be stated as NA_ in a LR-DIMM type platform, vice versa.
Example:
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE (2, 2, 0, 0, NA_),
TBLDRV_CONFIG_ENTRY_SPEEDLIMIT (DDR1600_FREQUENCY,
DDR1333_FREQUENCY,
DDR1066_FREQUENCY),
Dependencies
Only TBLDRV_CONFIG_ENTRY_SPEEDLIMIT override macro can be associated with this configuration macro.
Appendix C Memory Details
308
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Table of contents
- 278 MOTHER_BOARD_LAYERS
- 279 MEMCLK_DIS_MAP
- 281 ON_DIMM_THERMAL_CONTROL
- 282 CKE_TRI_MAP
- 283 ODT_TRI_MAP
- 284 CS_TRI_MAP
- 285 NUMBER_OF_DIMMS_SUPPORTED
- 286 NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED
- 287 NUMBER_OF_CHIP_SELECTS_SUPPORTED
- 288 NUMBER_OF_CHANNELS_SUPPORTED
- 289 OVERRIDE_DDR_BUS_SPEED
- 290 DRAM_TECHNOLOGY
- 291 WRITE_LEVELING_SEED
- 292 HW_RXEN_SEED
- 293 NO_LRDIMM_CS67_ROUTING
- 294 SOLDERED_DOWN_SODIMM_TYPE
- 295 MIN_RD_WR_DATAEYE_WIDTH
- 296 CPU_FAMILY_TO_OVERRIDE
- 298 CONDITION_AND
- 299 COND_LOC
- 300 COND_SPD
- 301 ACTION_ODT
- 302 ACTION_ADDRTMG
- 303 ACTION_ODCCTRL
- 304 ACTION_SLEWRATE
- 305 ACTION_SPEEDLIMIT
- 306 TBLDRV_CONFIG_TO_OVERRIDE
- 308 TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE
- 309 TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE
- 311 TBLDRV_CONFIG_ENTRY_SPEEDLIMIT
- 312 TBLDRV_CONFIG_ENTRY_ODT_RTTNOM
- 313 TBLDRV_CONFIG_ENTRY_ODT_RTTWR
- 314 TBLDRV_CONFIG_ENTRY_ODTPATTERN
- 315 TBLDRV_CONFIG_ENTRY_ADDRTMG
- 316 TBLDRV_CONFIG_ENTRY_ODCCTRL
- 317 TBLDRV_CONFIG_ENTRY_SLOWACCMODE
- 318 TBLDRV_CONFIG_ENTRY_RC2_IBT
- 319 TBLDRV_OVERRIDE_MR0_CL
- 320 TBLDRV_OVERRIDE_MR0_WR
- 321 TBLDRV_OVERRIDE_RC10_OPSPEED
- 322 TBLDRV_CONFIG_ENTRY_LRDMM_IBT
- 323 TBLDRV_CONFIG_ENTRY_2D_TRAINING
- 324 TBLDRV_INVALID_CONFIG