IDT79RC4640

IDT79RC4640™

Data Sheet Revision History

Changes to version dated December 1995:

Features:

– Added 32-bit bus interface info

– Deleted items from low-power operation descriptions.

Hardware Overview:

– Added detailed descriptions of features.

– Changed Boot Time Mode Stream table values for mode bit

12.

DC Electrical Characteristics:

– The C

IN

and C

OUT

values have been changed.

AC Electrical Characteristics:

– In System Interface Parameters tables (RC4640 and

RV4640), Data Setup and Data Hold minimums changed.

Valid Combinations:

– List of valid combinations has been corrected.

Changes to version dated March 1997:

Features:

– Added preliminary 150 MHz operation frequency

Thermal Considerations:

– Added thermally enhanced packaging (“DU”) and drop-in heat spreader information.

– Upgraded 80 to 133MHz speed grade specs to “final.”

Changes to version dated May 1997:

Features:

– Added 180 MHz spreader information

– Eliminated 80 MHz

Changes to version dated March 1998:

Features:

– Added 200MHz operating frequency

Changes to version dated April 1998:

Features:

– Added 400MB/sec bandwidth reference

Power Consumption (RV4640):

– Upgraded System Condition Icc active parameters

Changes to version dated July 1999:

– Corrected several incorrect references to tables and figures.

Changes to version dated March 2000

– Replaced existing figure in Mode Configuration Interface

Reset Sequence section with 3 reset figures.

– Revised values in System Interface Parameters table.

Changes to version dated July 2000

– Revised package information in the Thermal Considerations section, Physical Specifications section, Ordering Information section, and the Valid Combinations section.

Changes to version dated April 2001

– In the Data Output and Data Output Hold categories of the

System Interface Parameters tables, changed values in the

Min column for all speeds from 1.0 and 2.0 to 0.

Changes to version dated June 2006

– Added Green

PQFP

package for 133MHz DUG on Order Page.

Changes to version dated December 2008

– Removed IDT from ordering codes on Ordering Information page.

MasterClock

SysAD

SysCmd

ValidOut

ValidIn

RdRdy

WrRdy

Release

Addr

Write

Data0 Data1

CData CData

Data6

Data7

CData CEOD

Figure 4 RC4640 Block Write Request

9 of 23 December 5, 2008

IDT79RC4640™

7:5

8

10:9

11

12

Mode bit

0

4s:1

14:13

255:15

Description

Reserved (must be zero)

Writeback data rate:

32-bit

0

→ Ω

1

→ WWx

2

→ WWxx

3

→ WxWx

4

→ WWxxx

5

→ WWxxxx

6

→ WxxWxx

7

→ WWxxxxxx

8

→ WxxxWxxx

9-15 reserved

Clock multiplier:

0

→ 2

1

→ 3

2

→ 4

3

→ 5

4

→ 6

5

→ 7

6

→ 8

7 reserved

0

→ Little endian

1

→ Big endian

00

→ R4000 compatible

01

→ reserved

10

→ pipelined writes

11

→ write re-issue

Disable the timer interrupt on Int[5]

Must be 1

Output driver strength:

10

→ 100% strength (fastest)

11

→ 83% strength

00

→ 67% strength

01

→ 50% strength (slowest)

Must be zero

Table 6 Boot-time mode stream

10 of 23 December 5, 2008