IDT79RC4640

IDT79RC4640™

Pin Description

The following is a list of interface, interrupt, and miscellaneous pins available on the RC4640. Pin names ending with an asterisk (*) identify pins that are active when low.

Pin

Name

Type Description

System Bus Interface

ExtRqst*

Release*

RdRdy*

WrRdy*

ValidIn*

Input

Output

Input

Input

Input

ValidOut* Output

Valid output

Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the

SysCmd bus.

SysAD(31:0) Input/Output System address/data bus

A 32-bit address and data bus for communication between the processor and an external agent.

SysADC(3:0) Input/Output System address/data check bus

A 4-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0) Input/Output System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the processor and an external agent.

SysCmdP Input/Output Reserved system command/data identifier bus parity

For the RC4640 this signal is unused on input and zero on output.

Clock/Control interface

MasterClock Input

V

V

CC

SS

P

P

Input

Input

External request

Signals that the system interface needs to submit an external request.

Release interface

Signals that the processor is releasing the system interface to slave state

Read Ready

Signals that an external agent can now accept a processor read.

Write Ready

Signals that an external agent can now accept a processor write request.

Valid Input

Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the

SysCmd bus.

Master clock

Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization.

Quiet VCC for PLL

Quiet V

CC

for the internal phase locked loop.

Quiet VSS for PLL

Quiet V

SS

for the internal phase locked loop.

Interrupt interface

Int*(5:0) Input

NMI* Input

Interrupt

Six general processor interrupts, bit-wise OR’ d with bits 5:0 of the interrupt register.

Non-maskable interrupt

Non-maskable interrupt, OR’d with bit 6 of the interrupt register.

Initialization interface

V

CCO k Input

VCC is OK

When asserted, this signal indicates to the RC4640 that the power supply has been above Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of V

CCO k initiates the reading of the boot-time mode control serial stream.

11 of 23 December 5, 2008