IDT79RC4640

IDT79RC4640™

Timing Characteristics—RV4640

Cycle

MasterClock

1 t

MCkHigh

2 t

MCkLow

3 t

MCkP

SysAD,SysCmd Driven

SysADC

D D D t

DO t

DM t

DOH

SysAD,SysCmd Received

SysADC

D t

DS t

DH

D D

Control Signal CPU driven

ValidOut*

Release* t

DO t

DOH

Control Signal CPU received

RdRdy*

WrRdy*

ExtRqst*

ValidIn*

NMI*

Int*(5:0)

* = active low signal t

DS t

DH

Figure 5 System Clocks Data Setup, Output, and Hold timing

t

DZ

4

D

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IDT79RC4640™

Mode Configuration Interface Reset Sequence

Vcc

MasterClock

(MClk)

VCCOK

ModeClock

ModeIn

ColdReset*

Reset*

> 100ms

TDS

TDS

TDS

256 MClk cycles

256

MClk cycles

TMDS

Bit 0

TMDH

Bit 1

Bit

255

> 64K MClk cycles

Figure 6 Power-on Reset

Vcc

Master

Clock

(MClk)

VCCOK

TDS

> 100ms

TDS

256 MClk cycles

256

MClk

ModeClock

ModeIn

TDS

ColdReset*

Reset*

TDS

TMDS

Bit

0

TMDH

Bit

1

Bit

255

> 64K MClk cycles

Figure 7 Cold Reset

Vcc

Master

Clock

(MClk)

VCCOK

ModeClock

ModeIn

ColdReset*

Reset*

256 MClk cycles

TDS

> 64 MClk cycles

Figure 8 Warm Reset

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TDS

> 64 MClk cycles

TDS

2.3V

2.3V

TDS

> 64 MClk cycles

TDS

TDS

December 5, 2008