STMicroelectronics L6225 Datasheet
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L6225
DMOS DUAL FULL BRIDGE DRIVER
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OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
2.8A OUTPUT PEAK CURRENT (1.4A DC)
R
DS(ON)
0.73
Ω
TYP. VALUE @ T j
= 25 °C
OPERATING FREQUENCY UP TO 100KHz
NON DISSIPATIVE OVERCURRENT
PROTECTION
PARALLELED OPERATION
CROSS CONDUCTION PROTECTION
THERMAL SHUTDOWN
UNDER VOLTAGE LOCKOUT
INTEGRATED FAST FREE WHEELING DIODES
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TYPICAL APPLICATIONS
BIPOLAR STEPPER MOTOR
DUAL OR QUAD DC MOTOR
DESCRIPTION
The L6225 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPower-
BLOCK DIAGRAM
PowerDIP20
(16+2+2)
PowerSO20
ORDERING NUMBERS:
L6225N (PowerDIP20)
L6225PD (PowerSO20)
L6225D (SO20)
SO20
(16+2+2)
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on the same chip. Available in PowerDIP20 (16+2+2),
PowerSO20 and SO20(16+2+2) packages, the
L6225 features a non-dissipative protection of the high side PowerMOSFETs and thermal shutdown.
VBOOT
VCP
V
BOOT
CHARGE
PUMP
OCD
A
THERMAL
PROTECTION
EN
A
IN1
A
IN2
A
VOLTAGE
REGULATOR
10V
5V
OVER
CURRENT
DETECTION
GATE
LOGIC
V
BOOT
10V
V
BOOT
10V
VS
A
OUT1
A
OUT2
A
SENSE
A
BRIDGE A
EN
B
IN1
B
IN2
B
OCD
B
OVER
CURRENT
DETECTION
GATE
LOGIC
V S
B
OUT1
B
OUT2
B
SENSE
B
BRIDGE B
D99IN1091A
September 2003 1/20
L6225
ABSOLUTE MAXIMUM RATINGS
Symbol
V
S
V
OD
Parameter Test conditions
Supply Voltage V
SA
= V
SB
= V
S
Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
SA
= V
SB
= V
S
= 60V;
V
SENSEA
= V
SENSEB
= GND
Bootstrap Peak Voltage V
SA
= V
SB
= V
S
Input and Enable Voltage Range
V
BOOT
V
IN
,V
EN
V
V
I
SENSEA,
SENSEB
S(peak)
Voltage Range at pins SENSE
A and SENSE
B
Pulsed Supply Current (for each
V
S
pin), internally limited by the overcurrent protection
V
SA
= V
SB
= V
S
; t
PULSE
< 1ms
V
SA
= V
SB
= V
S
I
S
RMS Supply Current (for each
V
S
pin)
T stg
, T
OP
Storage and Operating
Temperature Range
RECOMMENDED OPERATING CONDITIONS
Symbol
V
S
V
OD
V
SENSEA,
V
SENSEB
I
OUT
T j f sw
Parameter Test Conditions
Supply Voltage
Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
Voltage Range at pins SENSE
A and SENSE
B
RMS Output Current
V
SA
= V
SB
= V
S
V
SA
= V
SB
= V
S
;
V
SENSEA
= V
SENSEB
(pulsed t
W
< t rr
)
(DC)
Operating Junction Temperature
Switching Frequency
Value
60
60
V
S
+ 10
-0.3 to +7
-1 to +4
3.55
1.4
-40 to 150
V
V
V
A
A
°
C
Unit
V
V
-6
-1
-25
MIN
8
MAX
52
52
Unit
V
V
6
1
1.4
+125
100
V
V
A
°C
KHz
2/20
L6225
THERMAL DATA
Symbol
R th-j-pins
R th-j-case
R th-j-amb1
R th-j-amb1
R th-j-amb1
R th-j-amb2
Description
MaximumThermal Resistance Junction-Pins
Maximum Thermal Resistance Junction-Case
MaximumThermal Resistance Junction-Ambient
1
Maximum Thermal Resistance Junction-Ambient
2
MaximumThermal Resistance Junction-Ambient
3
Maximum Thermal Resistance Junction-Ambient
4
(1)
(2)
(3)
(4)
PowerDIP20 SO20 PowerSO20
13 15 -
-
41
-
52
2
-
-
-
57
-
-
78
36
16
63
Unit
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm
2
(with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm
2
(with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm
2
(with a thickness of 35µm), 16 via holes and a ground layer.
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
IN1
A
IN2
A
SENSE
A
OUT1
A
GND
GND
OUT1
B
SENSE
B
IN1
B
IN2
B
8
9
6
7
10
3
4
5
1
2
D99IN1093A
PowerDIP20/SO20
20
19
18
17
16
15
14
13
12
11
EN
A
VCP
OUT2
A
VS
A
GND
GND
VS
B
OUT2
B
VBOOT
EN
B
GND
VS
A
OUT2
A
VCP
EN
A
IN1
A
IN2
A
SENSE
A
OUT1
A
GND
3
4
5
6
1
2
7
8
9
10
D99IN1092A
PowerSO20
(5)
15
14
13
12
11
20
19
18
17
16
GND
VS
B
OUT2
B
VBOOT
EN
B
IN2
B
IN1
B
SENSE
B
OUT1
B
GND
(5) The slug is internally connected to pins 1,10,11 and 20 (GND pins).
3/20
L6225
PIN DESCRIPTION
PACKAGE
SO20/
PowerDIP20
PowerSO20
PIN #
1
2
3
4
PIN #
6
7
8
9
5, 6, 15, 16 1, 10, 11,
7
8
9
10
11
12
13
14
17
18
19
20
20
12
13
14
15
16
17
18
19
2
3
4
5
Name
IN1
IN2
A
A
SENSE
OUT1
GND
OUT1
SENSE
IN1
B
IN2
B
EN
B
A
B
VBOOT
OUT2
VS
VS
OUT2
VCP
EN
B
A
A
B
A
A
B
Type Function
Logic Input
Logic Input
Bridge A Logic Input 1.
Bridge A Logic Input 2.
Power Supply Bridge A Source Pin. This pin must be connected to Power
Ground directly or through a sensing power resistor.
Power Output Bridge A Output 1.
GND Signal Ground terminals. In PowerDIP and SO packages, these pins are also used for heat dissipation toward the
PCB.
Power Output Bridge B Output 1.
Power Supply Bridge B Source Pin. This pin must be connected to Power
Ground directly or through a sensing power resistor.
Logic Input Bridge B Logic Input 1.
Logic Input
Logic Input
Supply
Voltage
(6)
Bridge B Logic Input 2.
Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection.
If not used, it has to be connected to +5V through a resistor.
Bootstrap Voltage needed for driving the upper
PowerMOSFETs of both Bridge A and Bridge B.
Power Output Bridge B Output 2.
Power Supply Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VS
A
.
Power Supply Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VS
B
.
Power Output Bridge A Output 2.
Output
Logic Input
(6)
Charge Pump Oscillator Output.
Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection.
If not used, it has to be connected to +5V through a resistor.
(6) Also connected at the output drain of the Overcurrent and Thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2k
Ω
- 180K
Ω
, recommended 100k
Ω
4/20
L6225
ELECTRICAL CHARACTERISTICS
(T amb
= 25 °C, V s
= 48V, unless otherwise specified)
Symbol
V
Sth(ON)
Turn-on Threshold
V
Sth(OFF)
Turn-off Threshold
I
S
Quiescent Supply Current
T j(OFF)
Thermal Shutdown Temperature
Output DMOS Transistors
R
DS(ON)
High-Side + Low-Side Switch ON
Resistance
T j
= 25
°
C
T j
=125
°
C
(7)
I
DSS
Leakage Current EN = Low; OUT = V
S
EN = Low; OUT = GND
Source Drain Diodes
Forward ON Voltage V
SD t rr
Reverse Recovery Time I
I
All Bridges OFF;
T j
= -25°C to 125°C
(7) f
SD
= 1.4A, EN = LOW
= 1.4A
t fr
Forward Recovery Time
Logic Input
Low level logic input voltage V
IL
V
IH
High level logic input voltage
I
IL
I
IH
Low Level Logic Input Current
High Level Logic Input Current
V th(ON)
Turn-on Input Threshold
V th(OFF)
Turn-off Input Threshold
V th(HYS)
Input Threshold Hysteresis
Switching Characteristics
GND Logic Input Voltage
7V Logic Input Voltage t
D(on)EN Enable to out turn ON delay time
(8) t
D(on)IN t
RISE
Input to out turn ON delay time
Output rise time
(8)
I
I
LOAD
=1.4A, Resistive Load
LOAD
=1.4A, Resistive Load
(dead time included)
I
LOAD
=1.4A, Resistive Load t
D(off)EN Enable to out turn OFF delay time
(8) I
LOAD
=1.4A, Resistive Load
Input to out turn OFF delay time t
D(off)IN t
FALL Output Fall Time
(8)
I
LOAD
=1.4A, Resistive Load
I
LOAD
=1.4A, Resistive Load
Min
5.8
5
Typ
6.3
5.5
5
6.8
6
10
165
V
V mA
°
C
-0.3
1.47
2.35
1.69
2.70
2
Ω
Ω mA mA
1.15
300
200
1.3
V ns ns
-0.3
2
-10
0.8
0.25
1.8
1.3
0.5
0.8
7
10
2.0
µA
µA
V
V
V
V
V
500
1.9
800 ns
µs
40
500
500
40
800
800
250
1000
1000
250 ns ns ns ns
5/20
L6225
ELECTRICAL CHARACTERISTICS (continued)
(T amb
= 25 °C, V s
= 48V, unless otherwise specified)
Symbol f t dt
CP
Dead Time Protection
Charge pump frequency
Over Current Protection
-25°C<T j
<125°C
I
SOVER
Input Supply Overcurrent
Protection Threshold
T j
= -25°C to 125°C
(7)
R
OPDR
Open Drain ON Resistance I = 4mA t
OCD(ON)
OCD Turn-on Delay Time (9) I = 4mA; C
EN
< 100pF
(7)
(8)
(9) t
OCD(OFF)
OCD Turn-off Delay Time (9) I = 4mA; C
EN
< 100pF
Tested at 25°C in a restricted range and guaranteed by characterization.
See Fig. 1.
See Fig. 2.
Min
0.5
Typ
1
0.6
1
µs
MHz
2 2.8
40
200
100
3.55
60
A
Ω ns ns
Figure 1. Switching Characteristic Definition
EN
V th(ON)
V th(OFF)
I
OUT
90%
10%
D01IN1316 t
D(OFF)EN t
FALL t
D(ON)EN t
RISE t t
6/20
Figure 2. Overcurrent Detection Timing Definition
I
OUT
I
SOVER
ON
BRIDGE
OFF
V
EN
90%
10% t
OCD(ON) t
OCD(OFF)
D02IN1399
L6225
7/20
L6225
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6225 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rdson=0.73ohm (typical value @25°C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1
µ s typical) between the switch off and switch on of two Power MOS in one leg of a bridge.
Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (Vboot) supply is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
C
BOOT
C
P
R
P
D1
D2
220nF
10nF
100
Ω
1N4148
1N4148
Figure 3. Charge Pump Circuit
V
S
D1
D2
C
BOOT
R
P
C
P
VCP VBOOT VS
A
VS
B
D01IN1328
LOGIC INPUTS
Pins IN1
A
, IN2
A
, IN1
B
and IN2
B
are TTL/CMOS and
µ
C compatible logic inputs. The internal structure is shown in Fig. 4. Typical value for turn-on and turn-off thresholds are respectively Vthon=1.8V and
Vthoff=1.3V.
Pins EN
A
and EN
B
have identical input structure with the exception that the drains of the Overcurrent and thermal protection MOSFETs (one for the Bridge A and one for the Bridge B) are also connected to these pins. Due to these connections some care needs to be taken in driving these pins. The EN
A
and EN
B
inputs may be driven in one of two configurations as shown in figures 5 or 6. If driven by an open drain
(collector) structure, a pull-up resistor R
EN
and a capacitor C
EN
are connected as shown in Fig. 5. If the driver is a standard Push-Pull structure the resistor
R
EN
and the capacitor C
EN
are connected as shown in Fig. 6. The resistor R
EN
should be chosen in the range from 2.2k
Ω
to 180K
Ω
. Recommended values for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF.
More information on selecting the values is found in the Overcurrent Protection section.
Figure 4. Logic Inputs Internal Structure
5V
ESD
PROTECTION
D01IN1329
Figure 5. EN
A
and EN
B
Pins Open Collector
Driving
5V
5V
R
EN
OPEN
COLLECTOR
OUTPUT
EN
A
or EN
B
C
EN
D02IN1349
Figure 6. EN
A
and EN
B
Pins Push-Pull Driving
5V
PUSH-PULL
OUTPUT
R
EN
EN
A
or EN
B
C
EN
D02IN1350
TRUTH TABLE
H
H
H
EN
L
H
INPUTS
IN1
X
L
H
L
H
L
H
H
IN2
X
L
X = Don't care
High Z = High Impedance Output
OUTPUTS
OUT1
High Z
GND
OUT2
High Z
GND
Vs
GND
Vs
GND
Vs
Vs
8/20
L6225
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6225 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 7 shows a simplified schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I
REF
. When the output current in one bridge reaches the detection threshold (typically 2.8A) the relative
OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.
Figure 7. Overcurrent Protection Simplified Schematic
OUT1
A
VS
A
OUT2
A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
µ
C or LOGIC
+5V
R
EN
EN
A
C
EN
I
1A
I
2A
POWER DMOS
TO GATE
LOGIC
OCD
COMPARATOR n cells
I
1A
/ n
INTERNAL
OPEN-DRAIN
+
(I
1A
+I
2A
) / n
I
REF
R
DS(ON)
40 Ω TYP.
OVER TEMPERATURE
POWER DMOS n cells
POWER SENSE
1 cell
I
2A
/ n
D02IN1353
Figure 8 shows the Overcurrent Detection operation. The Disable Time t
DISABLE
before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
C
EN and R
EN
values and its magnitude is reported in Figure 9. The Delay Time t
DELAY
before turning off the bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported in Figure 10.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN should be chosen as big as possible according to the maximum tolerable Delay Time and the R
EN
value should be chosen according to the desired Disable Time.
The resistor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Recommended values for R are respectively 100K
Ω
and 5.6nF that allow obtaining 200
µ s Disable Time.
EN
and C
EN
9/20
L6225
Figure 8. Overcurrent Protection Waveforms
I
OUT
I
SOVER
V
EN
V
DD
V th(ON)
V th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF t
DELAY t
DISABLE t
OCD(ON) t
EN(FALL) t
D(OFF)EN t
OCD(OFF) t
EN(RISE) t
D(ON)EN
D02IN1400
10/20
Figure 9. t
DISABLE
versus C
EN
and R
EN
(V
DD
= 5V).
.
.
1 0
R
E N
= 2 2 0 k
Ω
R
E N
= 1 0 0 k
Ω
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
Ω
L6225
Figure 10. t
DELAY
versus C
EN
(V
DD
= 5V).
10
1
0.1
1 10
Cen [nF]
100
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6225 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value) with 15°C hysteresis (typ. value).
11/20
L6225
APPLICATION INFORMATION
A typical application using L6225 is shown in Fig. 11. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VS
A
and VS
B
) and ground near the L6225 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the EN
A
and EN
B inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is detected (see Overcurrent Protection). The two current sources (SENSE
A
and SENSE
B
) should be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins (except EN
A
and EN
B
) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
C
1
C
2
100uF
100nF
D
1
D
2
220nF C
BOOT
C
P
C
ENA
C
ENB
10nF
5.6nF
5.6nF
R
ENA
R
ENB
R
P
Figure 11. Typical Application
+
VS
8-52V
DC
C
POWER
GROUND
-
1
C
2
VS
A
VS
B
17
14
SIGNAL
GROUND
C
D
1
BOOT
D
2
R
P
VCP
19
C
P
VBOOT
SENSE
A
SENSE
B
12
3
8
LOAD
A
OUT1
A
OUT2
A
4
18
LOAD
B
OUT1
B
OUT2
B
7
13
20
EN
A
R
ENA
C
ENA
11
EN
B
R
ENB
C
ENB
9
10
1
2
16
15
6
5
GND
GND
GND
GND
D02IN1345
IN1
B
IN2
B
IN1
A
IN2
A
1N4148
1N4148
100K
Ω
100K
Ω
100
Ω
ENABLE
A
ENABLE
B
IN1
B
IN2
B
IN1
A
IN2
A
12/20
L6225
PARALLELED OPERATION
The outputs of the L6225 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges.
When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition, the over current detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold.
For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 12. The current in the two devices connected in parallel will share very well since the R
DS(ON)
of the devices on the same die is well matched.
In this configuration the resulting Bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.37
Ω
Typ. Value @ T
J
= 25°C
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
Figure 12. Parallel connection for higher current
+
VS
8-52V
DC
C
POWER
GROUND
-
1
C
2
VS
A
VS
B
17
14 11
20
EN
B
EN
A
R
EN
C
EN
EN
SIGNAL
GROUND
LOAD
C
D
1
BOOT
D
2
R
P VCP
C
P
VBOOT
19
SENSE
A
SENSE
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
12
3
8
4
18
7
13
1
2
9
10
16
15
6
5
IN1
A
IN2
A
IN1
B
IN2
B
GND
GND
GND
GND
IN1
IN2
D02IN1359
To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge
2 of the Bridge A can be connected in parallel and the same done for the Bridge B as shown in Figure 13. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. This configuration, the resulting bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.37
Ω
Typ. Value @ T
J
= 25°C
- 1.4A max RMS Load Current
- 2.8A OCD Threshold
13/20
L6225
Figure 13. Parallel connection with lower Overcurrent Threshold
+
VS
8-52V
DC
C
POWER
GROUND
-
1
C
2
VS
A
VS
B
17
14
SIGNAL
GROUND
LOAD
C
D
1
BOOT
D
2
R
P VCP
C
P
VBOOT
SENSE
A
SENSE
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
19
12
3
8
4
18
7
13
EN
A
20
11
EN
B
R
EN
C
EN
9
10
16
15
6
5
1
2
IN1
A
IN2
A
IN1
B
IN2
B
GND
GND
GND
GND
EN
IN
IN
A
B
D02IN1360
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig. 14 The resulting half bridge has the following characteristics.
- Equivalent Device: HALF BRIDGE
- R
DS(ON)
0.18
Ω
Typ. Value @ T
J
= 25°C
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
Figure 14. Paralleling the four Half Bridges
+
VS
8-52V
DC
C
POWER
GROUND
-
1
SIGNAL
GROUND
C
2
C
BOOT
LOAD
D
1
VS
A
VS
B
D
2
R
P
VCP
C
P
VBOOT
SENSE
A
SENSE
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
17
14
19
12
3
8
4
18
7
13
11
20
9
10
16
15
6
5
1
2
EN
B
EN
A
IN1
A
IN2
A
IN1
B
IN2
B
GND
GND
GND
GND
R
EN
C
EN
EN
IN
D02IN1366
14/20
L6225
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fig. 15 and Fig. 16 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types:
– One Full Bridge ON at a time (Fig. 15) in which only one load at a time is energized.
– Two Full Bridges ON at the same time (Fig. 16) in which two loads at the same time are energized.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum).
Figure 15. IC Power Dissipation versus Output Current with One Full Bridge ON at a time.
10
ONE FULL BRIDGE ON AT A TIME
I
A I
OUT
8
I
B
6
P
D
[W]
4
I
OUT
2
0
0 0.25 0.5 0.75 1 1.25 1.5
I
OUT
[A]
Test Conditions:
Supply Voltage = 24V
No PW M f
SW
= 3 0 kHz (slow decay)
Figure 16. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.
TWO FULL BRIDGES ON AT THE SAME TIME
10
I
A I
OUT
8
I
B
P
D
[W ]
6
4
I
OUT
2
0
0 0.25 0.5 0.75
1 1.25 1.5
I
OUT
[A ]
Test Conditions:
Supply Volt age = 24 V
No PWM f
SW
= 30 kHz (slow decay)
THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 18, 19 and 20 show the Junction-to-
Ambient Thermal Resistance values for the PowerSO20, PowerDIP20 and SO20 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6cm
2
dissipating footprint (copper thickness of 35µm), the R th j-amb
is about 35°C/W. Fig. 17 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15°C/W.
15/20
L6225
Figure 17. Mounting the PowerSO package.
Slug soldered to PCB with dissipating area
Slug soldered to PCB with dissipating area plus ground layer
Slug soldered to PCB with dissipating area plus ground layer contacted through via holes
Figure 18. PowerSO20 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
43
38
33
28
W ith o ut G ro u nd La yer
W ith Gr o un d La yer
W ith Gr o un d La yer + 16 via
H o le s 23
18
On-Board Copper Area
13
1 2 3 4 5 6 7 s q . c m
8 9 10 1 1 1 2 13
Figure 19. PowerDIP20 Junction-Ambient thermal resistance versus on-board copper area.
º C / W
42
41
40
39
38
37
36
35
34
33
Copper Area is on Bottom Side
Copper Area is on Top Side
On-Board Copper Area
1 2 3 4 5 6 7 s q . cm
8 9 10 11 12
Figure 20. SO20 Junction-Ambient thermal resistance versus on-board copper area.
On-Board Copper Area ºC / W
68
66
64
62
60
C o pp er A re a is o n T op S id e
58
56
54
52
50
48
1 2 3 4 5 6 7 s q. cm
8 9 10 11 12
16/20
L6225
DIM.
A a1 mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.1
a2 a3 b c
0
0.4
0.23
D (1) 15.8
D1
E e e3
9.4
13.9
E1 (1) 10.9
E2
E3
G
H h
5.8
0
15.5
1.27
11.43
3.6
0.3
3.3
0.1
0.32
16
9.8
14.5
11.1
2.9
6.2
0.1
15.9
1.1
0.004
0.000
0.53
0.016
0.009
0.622
0.370
0.547
0.429
0.228
0.000
0.610
0.050
0.450
0.142
0.012
0.130
0.004
0.021
0.013
0.630
0.386
0.570
0.437
0.114
0.244
0.004
0.626
0.043
L
N
0.8
1.1
0.031
8˚ (typ.)
0.043
S 8˚ (max.)
T 10 0.394
(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.
N N a2 A b e
DETAIL A e3
H
MECHANICAL DATA
Weight: 1.9gr
R
DETAIL B lead
OUTLINE AND
JEDEC MO-166
PowerSO20
E a1 c
DETAIL A
D slug
20 11 a3
DETAIL B
Gage Plane
BOTTOM VIEW
S
0.35
L
E2 E1
- C -
SEATING PLANE
G C
(COPLANARITY)
T
E3
1 10
D1
PSO20MEC h x 45
0056635
17/20
L6225
L
Z
F
I
E e b1
D e3
DIM.
a1 mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.51
0.020
0.85
1.40
0.033
0.055
B b 0.50
0.020
0.38
0.50
0.015
24.80
0.020
0.976
8.80
2.54
22.86
0.346
0.100
0.900
3.30
7.10
5.10
1.27
0.130
0.280
0.201
0.050
OUTLINE AND
MECHANICAL DATA
Powerdip 20
18/20
h
L
K
E e
H
DIM.
mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
B
C
A
A1
D
2.35
0.1
0.33
0.23
12.6
2.65
0.3
0.51
0.32
13
0.093
0.004
0.013
0.009
0.496
0.104
0.012
0.020
0.013
0.512
7.4
7.6
0.291
0.299
10
0.25
0.4
1.27
10.65
0.394
0.75
0.010
1.27
0.016
0˚ (min.)8˚ (max.)
0.050
0.419
0.030
0.050
B e
OUTLINE AND
MECHANICAL DATA
L6225
SO20
L
A
K h x 45˚
H
A1 C
D
20
1
11
E
SO20MEC
19/20
L6225
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
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