STMicroelectronics L6226Q Datasheet
광고
광고
L6226Q
DMOS dual full bridge driver
Features
■
■
■
■
■
■
■
■
■
■
■
Operating supply voltage from 8 to 52 V
2.8 A output peak current (1.4 A DC)
R
DS(on)
0.73
Ω
typ. value @ T
J
= 25 °C
Operating frequency up to 100 kHz
Programmable high side overcurrent detection and protection
Diagnostic output
Paralleled operation
Cross conduction protection
Thermal shutdown
Under voltage lockout
Integrated fast free wheeling diodes
Applications
■ Bipolar stepper motor
■ Dual or quad DC motor
Figure 1.
Block diagram
VBOOT
VCP
PROGCL
A
OCD
A
V
BOOT
CHARGE
PUMP
OCD
A
OVER
CURRENT
DETECTION
THERMAL
PROTECTION
EN
A
IN1
A
IN2
A
GATE
LOGIC
VOLTAGE
REGULATOR
10V
5V
OCD
B
OCD
B
OVER
CURRENT
DETECTION
PROGCL
B
EN
B
IN1
B
IN2
B
GATE
LOGIC
Description
The L6226Q is a DMOS dual full bridge designed for motor control applications, realized in
BCDmultipower technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. Available in
QFN32 5x5 package, the L6226Q features thermal shutdown and a non-dissipative overcurrent detection on the high side power
MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection.
V
BOOT
10V
V
BOOT
10V
BRIDGE A
BRIDGE B
D99IN1088A
VS
A
OUT1
A
OUT2
A
SENSE
A
V S
B
OUT1
B
OUT2
B
SENSE
B
August 2010 Doc ID 14335 Rev 5 1/29 www.st.com
29
Contents
Contents
L6226Q
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output current capability and IC power dissipation . . . . . . . . . . . . . . 23
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/29 Doc ID 14335 Rev 5
L6226Q Electrical data
1.1 Absolute maximum ratings
Table 1.
Symbol
Absolute maximum ratings
Parameter Parameter
OCD
A
,OCD
B
PROGCL
A
,
PROGCL
B
V
BOOT
V
IN
,V
EN
V
SENSEA,
V
SENSEB
T
I
V
V
I
S
OD
S(peak)
S stg
, T
OP
Supply voltage V
SA
= V
SB
= V
S
Differential voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
OCD pins voltage range
V
SA
= V
SB
= V
S
= 60 V,
V
SENSEA
= V
SENSEB
= GND
PROGCL pins voltage range
Bootstrap peak voltage
Input and enable voltage range
V
SA
= V
SB
= V
S
Voltage range at pins SENSE
A
and
SENSE
B
Pulsed supply current (for each V
S pin), internally limited by the overcurrent protection t
V
SA
= V
PULSE
SB
= V
< 1 ms
S
RMS supply current (for each V
S
pin) V
SA
= V
SB
= V
S
Storage and operating temperature range
,
Value
60
60
-0.3 to + 10
-0.3 to + 7
V
S
+ 10
-0.3 to + 7
-1 to + 4
3.55
1.4
-40 to 150
1.2 Recommended operating conditions
Table 2.
Symbol
V
S
V
OD
V
SENSEA,
V
SENSEB
I
OUT
T
J f sw
Recommended operating conditions
Parameter Parameter
Supply voltage
Voltage range at pins SENSE
SENSE
B
RMS output current
A
and
V
SA
= V
SB
= V
S
Differential voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
SA
= V
SB
= V
S
,
V
SENSEA
= V
SENSEB
(pulsed t
W
< t rr
)
(DC)
Operating junction temperature
Switching frequency
Min
8
-6
-1
-25
Max
52
52
6
1
1.4
+125
100
Unit
V
V
V
V
A
°C kHz
Unit
V
V
V
V
V
V
V
A
A
°
C
Doc ID 14335 Rev 5 3/29
Electrical data L6226Q
Table 3.
Thermal data
Symbol Parameter Value Unit
R th(JA)
Thermal resistance junction-ambient max.
(1)
42
°
C/W
1.
Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm cm
2
ground layer connected through 18 via holes (9 below the IC).
2
on the top side plus 6
4/29 Doc ID 14335 Rev 5
L6226Q
Figure 2.
Pin connection (top view)
Pin connection
Note: 1 The pins 2 to 8 are connected to die PAD.
2 The die PAD must be connected to GND pin.
Doc ID 14335 Rev 5 5/29
Pin connection L6226Q
Table 4.
N°
1, 21
9
11
12
13
14
15
16
17
19
20
22
23
24
25
26
27
28
29
30
31
Pin description
Pin Type Function
GND GND Signal ground terminals.
OUT1B Power output Bridge B output 1.
OCDB
Open drain output
Bridge B overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection.
SENSEB Power supply
Bridge B source pin. This pin must be connected to power ground directly or through a sensing power resistor.
IN1B
IN2B
Logic input
Logic input
Bridge B input 1
Bridge B input 2
PROGCLB
ENB
R pin
Logic input
Bridge B overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for the bridge B.
By connecting this pin to ground the maximum current is set. This pin cannot be left non-connected.
Bridge B enable. LOW logic level switches OFF all power MOSFETs of bridge B.
If not used, it has to be connected to +5 V.
Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B.
VBOOT
Supply voltage
OUT2B Power output Bridge B output 2.
VSB
VSA
Power supply
Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA.
Power supply
Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB.
OUT2A Power output Bridge A output 2.
VCP
ENA
Output
Logic input
Charge pump oscillator output.
Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge A.
If not used, it has to be connected to +5 V.
PROGCLA
IN1A
IN2A
R pin
Logic input
Logic input
Bridge A overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for the bridge A.
By connecting this pin to ground the maximum current is set. This pin cannot be left non-connected.
Bridge A logic input 1.
Bridge A logic input 2.
SENSEA Power supply
Bridge A source pin. This pin must be connected to power ground directly or through a sensing power resistor.
OCDA
Open drain output
Bridge A overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection.
OUT1A Power output Bridge A output 1.
6/29 Doc ID 14335 Rev 5
L6226Q Electrical characteristics
Table 5.
Symbol
V
Sth(ON)
V
Sth(OFF)
T
A
= 25 °C, Vs = 48 V, unless otherwise specified
Electrical characteristics
Parameter
Turn-on threshold
Turn-off threshold
Test condition
I
S
Quiescent supply current
All bridges OFF;
T
J
= -25 °C to 125 °C
(1)
T
J(OFF)
Thermal shutdown temperature
Output DMOS transistors
R
DS(on)
I
DSS
High-side + low-side switch ON resistance
Leakage current
T
J
= 25
°
C
T
J
= 125
°
C
(1)
EN = Low; OUT = V
S
EN = Low; OUT = GND
Source drain diodes
V
SD t rr t fr
Logic input
Forward ON voltage
Reverse recovery time
Forward recovery time
V
IL
V
IH
I
IL
I
IH
V th(ON)
V th(OFF)
V th(HYS)
Low level logic input voltage
High level logic input voltage
Low level logic input current
High level logic input current
Turn-on input threshold
Turn-off input threshold
Input threshold hysteresis
Switching characteristics t
D(on)EN
Enable to out turn ON delay time
(2) t
D(on)IN t
RISE t
D(off)EN t
D(off)IN t
FALL
Input to out turn ON delay time
Output rise time
(2)
Enable to out turn OFF delay time
(2)
Input to out turn OFF delay time
Output fall time
(2)
I
SD
= 2.8 A, EN = LOW
I f
= 1.4 A
GND logic input voltage
7 V logic input voltage
I
LOAD
=1.4 A, resistive load
I
LOAD
=1.4 A, resistive load
(dead time included)
I
LOAD
=1.4 A, resistive load
I
LOAD
=1.4 A, resistive load
I
LOAD
=1.4 A, resistive load
I
LOAD
=1.4 A, resistive load
Min Typ Max Unit
5.8
6.3
5 5.5
6.8
6
V
V
10 5
165 mA
°
C
-0.3
1.47
1.69
2.35
2.70
2
Ω
Ω mA mA
1.15
1.3
300
200
V ns ns
-0.3
2
-10
0.8
7
1.8
0.8
1.3
0.25
0.5
10
2.0
µA
V
V
V
V
V
µA
500 800 ns
µs 1.9
40 250 ns
500 800 1000 ns
500 800 1000 ns
40 250 ns
Doc ID 14335 Rev 5 7/29
Electrical characteristics L6226Q
Table 5.
Symbol
Electrical characteristics (continued)
Parameter Test condition Min Typ Max Unit t dt f
CP
Dead time protection
Charge pump frequency
Over current detection
-25 °C < T
J
< 125 °C
0.5
1
0.6
I s over
Input supply over current detection threshold
Open drain ON resistance
OCD turn-on delay time
(3)
OCD turn-off delay time
(3)
-25 °C<T
J
<125
°
C;RCL=39 k
Ω
-25 °C<T
J
-25 °C<T
J
<125
°
C;RCL= 5 k
Ω
<125
°
C;RCL= GND
-10%
-10%
-30%
I = 4 mA t t
R
OPDR
OCD(ON)
OCD(OFF)
I = 4 mA; C
EN
< 100 pF
I = 4 mA; C
EN
< 100 pF
1.
Tested at 25 °C in a restricted range and guaranteed by characterization.
2.
See
3.
See
0.29
2.21
2.8
40
200
100
1
+10%
+10%
+30%
60
µs
MHz
A
A
A
Ω ns ns
Figure 3.
Switching characteristic definition
(1
9
WK21
9
WK2))
,
287
W
',1
W
'2))(1
W
)$//
W
'21(1
W
5,6(
W
8/29 Doc ID 14335 Rev 5
L6226Q
Figure 4.
Overcurrent detection timing definition
,
287
2&'
7KUHVKROG
9
2&'
Electrical characteristics
W
W
2&'21
W
2&'2))
',1
W
Doc ID 14335 Rev 5 9/29
Circuit description L6226Q
4.1 Power stages and charge pump
The L6226Q integrates two independent power MOS full bridges. Each power MOS has an
R
DS(on)
= 0.73
Ω
(typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1
μ s typical) between the switch off and switch on of two power MOS in one leg of a bridge.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit
. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in
Table 6.
C
BOOT
C
P
D1
D2
Charge pump external components values
Component
220 nF
10 nF
1N4148
1N4148
Value
Figure 5.
Charge pump circuit
9
6
'
'
&
%227
9&3
&
3
9%227 96
$
96
%
',1
10/29 Doc ID 14335 Rev 5
L6226Q Circuit description
Pins IN1
A
, IN2
A
, IN1
B
, IN2
B
, EN
A
and EN
B
are TTL/CMOS and microcontroller compatible logic inputs. The internal structure is shown in
Figure 6 . Typical value for turn-on and turn-off
thresholds are respectively Vthon = 1.8 V and Vthoff = 1.3 V.
Pins EN
A
and EN
B
are commonly used to implement overcurrent and thermal protection by connecting them respectively to the outputs OCD
A
and OCD
B
, which are open-drain outputs. If that type of connection is chosen, some care needs to be taken in driving these
pins. Two configurations are shown in Figure 7
and
Figure 8 . If driven by an open drain
(collector) structure, a pull-up resistor R
EN
and a capacitor C
EN
are connected as shown in
Figure 7 . If the driver is a standard push-pull structure the resistor R
EN
and the capacitor
C
EN
are connected as shown in
EN from 2.2 k
Ω
to 180 k
Ω
. Recommended values for R
EN
should be chosen in the range
and C
EN
are respectively 100 k
Ω
and
5.6 nF. More information on selecting the values is found in the overcurrent protection section.
Figure 6.
Logic inputs internal structure
9
(6'
3527(&7,21
',1
Figure 7.
EN
A
and EN
B
pins open collector driving
Figure 8.
EN
A
and EN
B
pins push-pull driving
Doc ID 14335 Rev 5 11/29
Circuit description L6226Q
4.4
12/29
Table 7.
Truth table
Inputs
EN
L
H
H
H
H
1.
X = Don't care
2.
High Z = High impedance output
IN1
X
(1)
L
H
L
H
IN2
X
L
L
H
H
OUT1
High Z
(2)
GND
Vs
GND
Vs
Outputs
OUT2
High Z
GND
GND
Vs
Vs
Non-dissipative overcurrent detection and protection
An overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides protection against a short circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated.
Figure 9 shows a simplified schematic of the overcurrent detection circuit for the bridge A.
bridge B is provided of an analogous circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I
REF
. When the output current reaches the detection threshold Isover the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4 mA connected to OCD pin is turned on. Figure 10
shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to
EN pin and adding an external R-C as shown in
Figure 9 . The off time before recovering
normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.
I
REF
and, therefore, the output current detection threshold are selectable by R
CL following the equations:
value,
●
●
Isover = 2.8 A ± 30 % at -25 °C < T
J
< 125 °C if R
CL
= 0
Ω
(PROGCL connected to GND)
Isover = ±10 % at -25 °C < T
J
< 125 °C if 5 k
Ω <
R
CL
< 40 k
Ω
R
CL
shows the output current protection threshold versus R
CL to 40 k
Ω
.
value in the range 5 k
Ω
The disable time t
DISABLE
before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by C
EN and R
EN
Doc ID 14335 Rev 5
L6226Q Circuit description values and its magnitude is reported in
. The delay time t
DELAY
before turning off the bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported in
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable
Delay Time and the R
EN
value should be chosen according to the desired Disable Time.
The resistor R
EN values for R
EN
should be chosen in the range from 2.2 k
Ω
to 180 k
Ω
. Recommended
and C
EN
are respectively 100 k
Ω
and 5.6 nF that allow obtaining 200
μ s disable time.
Figure 9.
Overcurrent protection simplified schematic
Doc ID 14335 Rev 5 13/29
Circuit description
Figure 10.
Overcurrent protection waveforms
I
OUT
I
SOVER
L6226Q
V
EN
V
DD
V th(ON)
V th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF t
DELAY t
OCD(ON) t
EN(FALL) t
D(OFF)EN t
OCD(OFF) t
DISABLE t
EN(RISE) t
D(ON)EN
D02IN1400
Figure 11.
Output current protection threshold versus R
CL
value
2 .5
2 .2 5
2
1 .7 5
1 .5
[A ]
1 .2 5
I
S O V E R
1
0 .7 5
0 .5
0 .2 5
0
5 k 1 0 k 1 5 k 2 0 k
R
C L
[ Ω ]
2 5 k 3 0 k 3 5 k 4 0 k
14/29 Doc ID 14335 Rev 5
L6226Q Circuit description
Figure 12.
t
DISABLE
versus C
EN
and R
EN
(V
DD
= 5 V)
= 220 k Ω
.
.
10
= 100 k Ω
R
EN
= 47 k Ω
R
EN
= 33 k Ω
R
EN
= 10 k Ω
Figure 13.
t
DELAY
versus C
EN
(V
DD
= 5 V)
10
1
0.1
1 10
Cen [nF]
100
Doc ID 14335 Rev 5 15/29
Circuit description L6226Q
In addition to the overcurrent detection, the L6226Q integrates a thermal protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).
16/29 Doc ID 14335 Rev 5
L6226Q Application information
A typical application using L6226Q is shown in Figure 14 . Typical component values for the
application are shown in Table 8
. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VS
A
and VS
B
) and ground near the L6226Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the EN
A
/OCD
A
and
EN
B
/OCD
B
nodes to ground set the shut down time for the bridge A and bridge B respectively when an over current is detected (see overcurrent protection). The two current sources (SENSE
A
and SENSE
B
) should be connected to power ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is recommended to keep power ground and Signal Ground separated on PCB.
Table 8.
Component values for typical application
Component
C
1
C
2
D
2
R
CLA
R
CLB
R
ENA
R
ENB
C
BOOT
C
P
C
ENA
C
ENB
C
REF
D
1
Value
100 nF
100 µF
220 nF
10 nF
5.6 nF
5.6 nF
68 nF
1N4148
1N4148
5 k
Ω
5 k
Ω
100 k
Ω
100 k
Ω
Doc ID 14335 Rev 5 17/29
Application information
Figure 14.
Typical application
L6226Q
Note: To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can be connected to GND.
18/29 Doc ID 14335 Rev 5
L6226Q Paralleled operation
The outputs of the L6226Q can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition the over current detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold.
For most applications the recommended configuration is half bridge 1 of bridge A paralleled with the half bridge 1 of the bridge B, and the same for the half bridges 2 as shown in
. The current in the two devices connected in parallel will share very well since the
R
DS(on)
of the devices on the same die is well matched.
When connected in this configuration the over current detection circuit, which senses the current in each bridge (A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. With the enables connected in parallel, the first detection of an over current in either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors R
CLA
or R
CLB
in
Figure 15 . It is recommended to use R
CLA
= R
CLB
.
●
●
●
●
In this configuration the resulting bridge has the following characteristics.
Equivalent device: full bridge
R
DS(on)
0.37
Ω
typ. value @ T
J
= 25 °C
2.8 A max RMS load current
5.6 A max OCD threshold
Doc ID 14335 Rev 5 19/29
Paralleled operation
Figure 15.
Parallel connection for higher current
L6226Q
20/29
To operate the device in parallel and maintain a lower over current threshold, half bridge 1 and the half bridge 2 of the bridge A can be connected in parallel and the same done for the
bridge B as shown in Figure 16 . In this configuration, the peak current for each half bridge is
still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased.
When connected in this configuration the over current detection circuit, senses the sum of the current in upper devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges. Since the circuit senses the total current in the upper devices, the over current threshold is equal to the threshold set the resistor R
CLA
or
R
CLB
. R
CLA
sets the threshold when outputs OUT1
A
and OUT2
A
are high and resistor R
CLB
sets the threshold when outputs OUT1
B
and OUT2
B
are high.
It is recommended to use R
CLA
= R
CLB
.
●
●
●
●
In this configuration, the resulting bridge has the following characteristics.
Equivalent device: FULL BRIDGE
R
DS(on)
0.37
Ω
typ. value @ T
J
= 25 °C
1.4 A max RMS load current
2.8 A max OCD threshold
Doc ID 14335 Rev 5
L6226Q
Figure 16.
Parallel connection with lower overcurrent threshold
Paralleled operation
It is also possible to parallel the four half bridges to obtain a simple half bridge as shown in
. In this configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors R
CLA
or R
CLB
in Figure 17 . It is recommended to use
R
CLA
= R
CLB
.
●
●
●
●
The resulting half bridge has the following characteristics.
Equivalent device: half bridge
R
DS(on)
0.18
Ω
typ. value @ T
J
= 25 °C
2.8 A max RMS load current
5.6 A max OCD threshold
Doc ID 14335 Rev 5 21/29
Paralleled operation
Figure 17.
Paralleling the four half bridges
L6226Q
22/29 Doc ID 14335 Rev 5
L6226Q
7
Output current capability and IC power dissipation
Output current capability and IC power dissipation
●
●
In
Figure 18 and Figure 19 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different driving types:
One full bridge ON at a time ( Figure 18
) in which only one load at a time is energized.
Two full bridges ON at the same time ( are energized.
) in which two loads at the same time
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 18.
IC power dissipation vs output current with one full bridge ON at a time
10
ONE FULL BRIDGE ON AT A TIME
I
A
8
I
B
6
P
D
[W]
4
2
0
0 0.25 0.5 0.75 1 1.25 1.5
I
OUT
[A]
I
OUT
I
OUT
Test Conditions:
Supply Voltage = 24V
No PW M f
SW
= 3 0 kHz (slow decay)
Figure 19.
IC power dissipation vs output current with two full bridges ON at the same time
TWO FULL BRIDGES ON AT THE SAME TIME
10
I
A
8
I
B
P
D
[W ]
6
4
2
0
0 0.25 0.5 0.75
1 1.25 1.5
I
OUT
[A ]
I
OUT
I
OUT
Test Conditions:
Supply Volt age = 24 V
No PWM f
SW
= 30 kHz (slow decay)
Doc ID 14335 Rev 5 23/29
Thermal management L6226Q
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. For instance, using a VFQFPN32L 5x5 package the typical R th(JA)
is about 42 °C/W when mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm
2
on the top side plus 6 cm
2
ground layer connected through 18 via holes (9 below the IC).
24/29 Doc ID 14335 Rev 5
L6226Q
9 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK® is an ST trademark.
Table 9.
VFQFPN32 5x5x1.0 pitch 0.50
Dim.
D3
E
E2
E3 e
A b b1
D
D2
L ddd
Min
0.80
0.18
0.165
4.85
3.00
1.10
4.85
4.20
0.60
Databook (mm)
Typ
0.85
0.25
0.175
5.00
3.10
1.20
5.00
4.30
0.70
0.50
0.40
Max
0.95
0.30
0.185
5.15
3.20
1.30
5.15
4.40
0.80
0.30
0.50
0.08
Note: 1 VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no lead. Very thin profile: 0.80 < A = 1.00 mm.
2 Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features.
Doc ID 14335 Rev 5 25/29
Package mechanical data
Figure 20.
Package dimensions
L6226Q
26/29 Doc ID 14335 Rev 5
L6226Q Order codes
Table 10.
Order code
Order code
L6226Q
L6226QTR
Package
VFQFPN32 5x5x1.0
Packaging
Tube
Tape and reel
Doc ID 14335 Rev 5 27/29
Revision history L6226Q
Table 11.
Document revision history
Date Revision
18-Jan-2008
10-Jun-2008
28-Jan-2009
23-Sep-2009
30-Aug-2010
1
2
3
4
5
Changes
First release
,
Added: Note 1 on page 4
Updated value in Table 3: Thermal data on page 4
Updated value in Table 1: Absolute maximum ratings on page 3
Updated
28/29 Doc ID 14335 Rev 5
L6226Q
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