STMicroelectronics L6206 Datasheet
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Features
Operating supply voltage from 8 to 52 V
5.6 A output peak current (2.8 A DC)
R
DS(ON)
0.3 typ. value at T j
= 25 °C
Operating frequency up to 100 KHz
Programmable high-side overcurrent detection and protection
Diagnostic output
Paralleled operation
Cross conduction protection
L6206
DMOS dual full bridge driver
Datasheet
-
production data
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Applications
Bipolar stepper motor
Dual or quad DC motor
Description
The L6206 device is a DMOS dual full bridge designed for motor control applications, realized in BCD technology, which combines isolated
DMOS power transistors with CMOS and bipolar circuits on the same chip. Available in the
PowerSO36 and SO24 (20 + 2 + 2) packages, the
L6206 device features thermal shutdown and a non-dissipative overcurrent detection on the highside power MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection.
October 2018
This is information on a product in full production.
DocID07617 Rev 4 1/29 www.st.com
Contents
Contents
L6206
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 13
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 21
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/29 DocID07617 Rev 4
L6206
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Maximum ratings L6206
Symbol
Table 1. Absolute maximum ratings
Parameter
V
V
S
OD
OCD
A
,OCD
B
PROGCL
A
,
PROGCL
B
V
BOOT
V
IN
, V
EN
V
SENSEA,
V
SENSEB
Supply voltage
Differential voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
OCD pins voltage range
PROGCL pins voltage range
Bootstrap peak voltage
Input and enable voltage range
I
S(peak)
T stg
I
S
, T
OP
Voltage range at pins SENSE
A
and
SENSE
B
Pulsed supply current (for each V
S
pin), internally limited by the overcurrent protection
RMS supply current (for each V
S
pin)
Storage and operating temperature range
Test conditions
V
SA
= V
SB
= V
S
V
SA
= V
SB
= V
S
= 60 V;
V
SENSEA
= V
SENSEB
= GND
-
-
V
SA
= V
SB
= V
S
-
-
V
SA
= V
SB
= V
S
; t
PULSE
< 1 ms
V
SA
= V
SB
= V
S
-
Value
60
60
-0.3 to +10
-0.3 to +7
V
S
+ 10
-0.3 to +7
-1 to +4
Unit
V
V
V
V
V
V
V
7.1
2.8
-40 to 150
A
A
C
Symbol
V
S
V
OD
V
SENSEA,
V
SENSEB
I
OUT f sw
Table 2. Recommended operating conditions
Parameter Test conditions
Supply voltage
Differential voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
Voltage range at pins SENSE
A
and
SENSE
B
RMS output current
Switching frequency
V
SA
= V
SB
= V
S
V
SA
= V
SB
= V
S
;
V
SENSEA
= V
SENSEB
(pulsed t
W
< t rr
)
(DC)
-
-
Min.
8
Max.
Unit
52 V
-
-
-
-6
-1
52
6
1
2.8
100
V
V
V
A
KHz
4/29 DocID07617 Rev 4
L6206 Maximum ratings
Symbol
R th-j-pins
R th-j-case
Table 3. Thermal data
Description
Maximum thermal resistance junction pins
Maximum thermal resistance junction case
SO24
14
-
4. Mounted on a multilayer FR4 PCB without any heatsinking surface on the board.
PowerSO36 Unit
-
1
R th-j-amb1
R th-j-amb1
Maximum thermal resistance junction ambient
Maximum thermal resistance junction ambient
(1)
(2)
51
-
-
35
R th-j-amb1
R th-j-amb2
Maximum thermal resistance junction ambient
Maximum thermal resistance junction ambient
(3)
(4)
-
77
15
62
1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm 2
(with a thickness of 35 µm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm
2
(with a thickness of 35 µm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2
(with a thickness of 35 µm), 16 via holes and a ground layer.
C/W
C/W
C/W
C/W
C/W
C/W
DocID07617 Rev 4 5/29
29
Pin connections L6206
IN1
A
IN2
A
SENSE
A
OCD
A
OUT1
A
GND
GND
OUT1
B
OCD
B
SENSE
B
IN1
B
IN2
B
4
5
1
2
3
6
7
8
9
10
11
12
D99IN1089A
SO24
20
19
18
17
16
15
14
13
24
23
22
21
PROGCL
A
EN
A
VCP
OUT2
A
VS
A
GND
GND
VS
B
OUT2
B
VBOOT
EN
B
PROGCL
B
Figure 2. Pin connections (top view)
GND
N.C.
N.C.
VS
A
OUT2
A
N.C.
VCP
EN
A
PROGCL
A
IN1
A
IN2
A
SENSE
A
OCD
A
N.C.
OUT1
A
N.C.
N.C.
GND
10
11
12
13
14
15
16
17
18
6
7
8
9
1
2
3
4
5
D99IN1090A
PowerSO36 (1)
27
26
25
24
23
22
21
20
19
31
30
29
28
36
35
34
33
32
GND
N.C.
N.C.
VS
B
OUT2
B
N.C.
VBOOT
EN
B
PROGCL
B
IN2
B
IN1
B
SENSE
B
OCD
B
N.C.
OUT1
B
N.C.
N.C.
GND
1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 4. Pin description
Package
SO24 PowerSO36 Name Type
Pin no.
1
2
Pin no.
10
11
IN1
A
IN2
A
3
4
5
6, 7, 18, 19
8
12
13
15
1, 18, 19, 36
22
SENSE
A
OCD
A
OUT1
A
GND
OUT1
B
Function
Logic input
Logic input
Power supply
Open drain output
Bridge A logic input 1.
Bridge A logic input 2.
Bridge A source pin. This pin must be connected to power ground directly or through a sensing power resistor.
Bridge A overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection.
Power output
GND
Power output
Bridge A output 1.
Signal ground terminals. In SO packages, these pins are also used for heat dissipation toward the
PCB.
Bridge B output 1.
6/29 DocID07617 Rev 4
L6206 Pin connections
SO24
Pin no.
Package
PowerSO36
Pin no.
Table 4. Pin description (continued)
Name Type
9
10
11
12
13
14
15
16
17
20
21
22
23
24
24
25
30
32
5
7
26
27
28
29
33
4
8
9
Function
OCD
B
SENSE
IN1
IN2
EN
VS
VS
EN
B
B
B
OUT2
B
A
OUT2
VCP
A
B
A
B
PROGCL
B
VBOOT
PROGCL
A
Open drain output
Power supply
Logic input
Logic input
Bridge B overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection.
Bridge B source pin. This pin must be connected to power ground directly or through a sensing power resistor.
Bridge B input 1
R pin
Bridge B input 2
Bridge B overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for the bridge B. By connecting this pin to ground the maximum current is set. This pin cannot be left non-connected.
Logic input
Supply voltage
Power output
Power supply
Power supply
Power output
Output
Bridge B Enable. LOW logic level switches OFF all power MOSFETs of Bridge B.
If not used, it has to be connected to +5 V.
Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B.
Bridge B output 2.
Bridge B power supply voltage. It must be connected to the supply voltage together with pin
VS
A
.
Bridge A power supply voltage. It must be connected to the supply voltage together with pin
VS
B
.
Bridge A output 2.
Logic input
R pin
Charge pump oscillator output.
Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge A.
If not used, it has to be connected to +5 V.
Bridge A overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for the bridge A. By connecting this pin to ground the maximum current is set. This pin cannot be left non-connected.
DocID07617 Rev 4 7/29
29
Electrical characteristics L6206
Table 5. Electrical characteristics (T amb
= 25 °C, V s
= 48 V, unless otherwise specified)
Symbol Min.
Typ.
Max.
Unit
V
Sth(ON)
V
Sth(OFF)
Turn-on threshold
Turn-off threshold
I
S
Quiescent supply current
T j(OFF)
Thermal shutdown temperature
Output DMOS transistors
-
-
T j
All bridges OFF;
= -25 °C to 125 °C
(1)
-
6.6
5.6
-
-
7
6
5
165
7.4
6.4
10
-
V
V mA
C
R
DS(ON)
I
DSS
High-side switch ON resistance
Low-side switch ON resistance
Leakage current
T j
= 25 °C
T j
= 125 °C
(1)
T j
= 25 °C
T j
= 125 °C
(1)
EN = low; OUT = V
S
EN = low; OUT = GND
-
-
-
-
-
-0.15
0.34
0.4
0.53
0.59
0.28
0.34
0.47
0.53
-
-
2
-
mA mA
Source drain diodes
V
SD t rr t fr
Logic input
Forward ON voltage
Reverse recovery time
Forward recovery time
V
IL
V
IH
I
IL
I
IH
V th(ON)
V th(OFF)
V th(HYS)
Low level logic input voltage
High level logic input voltage
Low level logic input current
High level logic input current
Turn-on input threshold
Turn-off input threshold
Input threshold hysteresis
Switching characteristics t
D(on)EN
Enable to out turn ON delay time
(2) t
D(on)IN t
RISE t
D(off)EN t
D(off)IN t
FALL
Input to out turn ON delay time
Output rise time
(2)
Enable to out turn OFF delay time
(2)
Input to out turn OFF delay time
Output fall time (2)
I
SD
= 2.8 A, EN = low
I f
= 2.8 A
-
-
-
GND logic input voltage
7 V logic input voltage
-
-
-
I
LOAD
= 2.8 A, resistive load
I
LOAD
= 2.8 A, resistive load
(deadtime included)
I
LOAD
= 2.8 A, resistive load
I
LOAD
= 2.8 A, resistive load
I
LOAD
= 2.8 A, resistive load
I
LOAD
= 2.8 A, resistive load
-
-
-
-0.3
2
-10
-
1.8
0.8
1.3
0.25
0.5
-
-
-
-
100 250
-
1.15
300
200
1.6
40 -
300 550
-
40
600
-
0.8
7
-
10
2.0
-
-
1.3
-
-
400
-
250
800
-
250 ns ns ns ns
V ns ns ns
µs
V
V
µA
µA
V
V
V
8/29 DocID07617 Rev 4
L6206 Electrical characteristics
Table 5. Electrical characteristics (T amb
= 25 °C, V s
= 48 V, unless otherwise specified) (continued)
Symbol Min.
Typ.
Max.
Unit t dt f
CP
Deadtime protection
Charge pump frequency
Overcurrent detection
-
-25 °C < T j
< 125 °C
I s over
Input supply overcurrent detection threshold
Open drain ON resistance
OCD turn-on delay time
(3)
OCD turn-off delay time
(3)
-25 °C < T j
< 125 °C; R
CL
= 39 k
-25 °C < T j
-25 °C <T j
< 125 °C; R
CL
= 5 k
< 125 °C; R
CL
= GND
I = 4 mA t t
R
OPDR
OCD(ON)
OCD(OFF)
I = 4 mA; C
EN
< 100 pF
I = 4 mA; C
EN
< 100 pF
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See
Figure 3: Switching characteristic definition .
3. See
Figure 4: Overcurrent detection timing definition
.
0.5
-
-10%
-10%
-30%
-
-
-
1
0.6
0.57
4.42
5.6
40
200
100
-
1
+10%
+10%
+30%
60
-
-
µs
MHz
ns
A
A
A ns
Figure 3. Switching characteristic definition
EN
V th(ON)
V th(OFF)
I
OUT
90%
10%
D01IN1316 t
D(OFF)EN t
FALL t t
D(ON)EN t
RISE t
DocID07617 Rev 4 9/29
29
Electrical characteristics
Figure 4. Overcurrent detection timing definition
I
OUT
OCD
Threshold
V
OCD
90%
10% t
OCD(ON) t
OCD(OFF)
D01IN1222 t t
L6206
10/29 DocID07617 Rev 4
L6206 Circuit description
5.1 Power stages and charge pump
The L6206 device integrates two independent power MOS full bridges. Each power MOS has an R ds(ON)
= 0.3 (typical value at 25 °C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a deadtime (t d
= 1 and switch on of two power MOS in one leg of a bridge.
s typical) between the switch off
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped (V
BOOT
) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit
. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in
.
Table 6. Charge pump external components values
Component Value
C
BOOT
C
P
R
P
D1
D2
220 nF
10 nF
100
1N4148
1N4148
Figure 5. Charge pump circuit
V
S
D1
D2
C
VCP
R
P
C
P
VBOOT
BOOT
VS
A
VS
B
D01IN1328
DocID07617 Rev 4 11/29
29
Circuit description L6206
Pins IN1
A
, IN2
A
, IN1
B
, IN2
B
, EN
A
and EN
B
are TTL/CMOS compatible logic inputs. The internal structure is shown in
Figure 6 . Typical value for turn-on and turn-off thresholds are
respectively V th(ON)
= 1.8 V and V th(OFF)
= 1.3 V.
Pins EN
A
and EN
B
are commonly used to implement overcurrent and thermal protection by connecting them respectively to the outputs OCD
A
and OCD
B
, which are open drain outputs. If that type of connection is chosen, some care needs to be taken in driving these pins. Two configurations are shown in
. If driven by an open drain
(collector) structure, a pull-up resistor R
EN
and a capacitor C
EN
are connected as shown in
Figure 7 . If the driver is a standard push-pull structure, the resistor R
EN
and the capacitor
C
EN
are connected as shown in
EN from 2.2 k to 180 K . Recommended values for R
EN
should be chosen in the range
and C
EN
are respectively 100 K
Figure 6. Logic inputs internal structure
9
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Figure 7. EN
A
and EN
B
pins open collector driving
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A
and EN
B
pins push-pull driving
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DocID07617 Rev 4
L6206
Inputs
EN
L
H
H
H
H
1. X = don't care.
2. High Z = high impedance output.
IN1
X (1)
L
H
L
H
Circuit description
Table 7. Truth table
IN2
X (1)
H
H
L
L
OUT1
High Z (2)
GND
Vs
GND
Vs
Outputs
OUT2
High Z (2)
GND
GND
Vs
Vs
In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated.
This circuit can be used to provide protection against a short-circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated.
Figure 9 shows a simplified schematic of the
overcurrent detection circuit for the bridge A. Bridge B is provided of an analogous circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high-side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I
REF output current reaches the detection threshold I
SOVER
. When the
the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4 mA connected to OCD pin is turned on. Figure 10 shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to
EN pin and adding an external R-C as shown in
Figure 9 . The off time before recovering
normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.
I
REF
and, therefore, the output current detection threshold are selectable by R following the equations:
CL
value,
–I
SOVER
= 5.6 A ± 30% at -25 °C < T j
< 125 °C if R
CL
= 0 (PROGCL connected to GND)
–I
SOVER
=
R
CL
±10% at -25 °C < T j
< 125 °C if 5 K R
CL
< 40 k
shows the output current protection threshold versus R
CL to 40 k .
value in the range 5 k
The disable time t
DISABLE
before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by C
values and its magnitude is reported in Figure 12 . The delay time t
DELAY the bridge when an overcurrent has been detected depends only by C
EN magnitude is reported in
.
EN and R
EN
before turning off
value. Its
DocID07617 Rev 4 13/29
29
Circuit description
9
L6206
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable delay time and the R
EN
value should be chosen according to the desired disable time.
The resistor R values for R
EN disable time.
EN
should be chosen in the range from 2.2 K to 180 K . Recommended
and C
EN
are respectively 100 K and 5.6 nF that allow obtaining 200 s
Figure 9. Overcurrent protection simplified schematic
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L6206
I
OUT
I
SOVER
Figure 10. Overcurrent protection waveforms
Circuit description
V
EN
V
DD
V th(ON)
V th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF t
DELAY t
OCD(ON) t
EN(FALL) t
D(OFF)EN t
OCD(OFF) t
DISABLE t
EN(RISE) t
D(ON)EN
D02IN1400
Figure 11. Output current protection threshold versus R
CL
value
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Circuit description
Figure 12. t
DISABLE
versus C
EN
and R
EN
(V
DD
= 5 V)
L6206
&
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Figure 13. t
DELAY
versus C
EN
(V
DD
= 5 V)
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In addition to the overcurrent detection, the L6206 device integrates a thermal protection for preventing the device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switchesoff when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).
DocID07617 Rev 4
L6206 Application information
A typical application using the L6206 device is shown in Figure 14
. Typical component
values for the application are shown in Table 8 . A high quality ceramic capacitor in the range
of 100 to 200 nF should be placed between the power pins (VS
A
and VS
B
) and ground near the L6206 device to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the
EN
A
/OCD
A
and EN
B
/OCD
B
nodes to ground set the shutdown time for the bridge A and bridge B respectively when an overcurrent is detected (see
A
SENSE
B
and
) should be connected to power ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see
Table 4: Pin description on page 6 ). It is
recommended to keep power ground and signal ground separated on the PCB.
Table 8. Component values for typical application
Component Value Component Value
C
1
C
2
C
BOOT
C
P
C
ENA
C
ENB
100 F
100 nF
220 nF
10 nF
5.6 nF
5.6 nF
D
1
D
2
R
CLA
R
CLB
R
ENA
R
ENB
1N4148
1N4148
5 K
5 K
100 k
100 k
Figure 14. Typical application (with reference to 24-pin packages)
DocID07617 Rev 4
*/7
17/29
29
Application information L6206
18/29
The outputs of the L6206 device can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half-bridges. When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition the overcurrent detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the overcurrent detection threshold.
For most applications the recommended configuration is half-bridge 1 of bridge A paralleled with the half-bridge 1 of the bridge B, and the same for the half-bridges 2 as shown in
. The current in the two devices connected in parallel will share very well since the
R
DS(ON)
of the devices on the same die is well matched.
When connected in this configuration the overcurrent detection circuit, which senses the current in each bridge (A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. With the enables connected in parallel, the first detection of an overcurrent in either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current equally, the resulting overcurrent detection threshold will be twice the minimum threshold set by the resistors R
CLA
or R
CLB
in
. It is recommended to use R
CLA
= R
CLB
.
In this configuration the resulting bridge has the following characteristics:
Equivalent device: full bridge
R
DS(ON)
0.15 typ. value at T
J
= 25 °C
5.6 A max. RMS load current
11.2 A max. OCD threshold
Figure 15. Parallel connection for higher current (with reference to 24-pin packages)
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DocID07617 Rev 4
L6206 Application information
To operate the device in parallel and maintain a lower overcurrent threshold, half-bridge 1 and the half-bridge 2 of the bridge A can be connected in parallel and the same done for the bridge B as shown in
Figure 16 . In this configuration, the peak current for each half-bridge is
still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased.
When connected in this configuration the overcurrent detection circuit, senses the sum of the current in upper devices connected in parallel. With the enables connected in parallel, an overcurrent will turn of both bridges. Since the circuit senses the total current in the upper devices, the overcurrent threshold is equal to the threshold set the resistor R
CLA
. R
CLA
R
CLB
sets the threshold when outputs OUT1
sets the threshold when outputs OUT1
It is recommended to use R
CLA
= R
CLB
.
B
A
and OUT2
and OUT2
B
are high.
or R
CLB
in
A
are high and resistor
In this configuration, the resulting bridge has the following characteristics:
Equivalent device: full bridge
R
DS(ON)
0.15 typ. value at T
2.8 A max. RMS load current
J
= 25 °C
5.6 A max. OCD threshold
Figure 16. Parallel connection with lower overcurrent threshold
(with reference to 24-pin packages)
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DocID07617 Rev 4 19/29
29
Application information L6206
It is also possible to parallel the four half-bridges to obtain a simple half-bridge as shown in
. In this configuration the overcurrent threshold is equal to twice the minimum threshold set by the resistors R
CLA
R
CLA
= R
CLB
.
or R
CLB
in
Figure 17 . It is recommended to use
The resulting half-bridge has the following characteristics:
Equivalent device: half-bridge
R
DS(ON)
0.075.
typ. value at T
J
= 25 °C
5.6 A max. RMS load current
11.2 A max. OCD threshold
Figure 17. Paralleling the four half-bridges (with reference to 24-pin packages)
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20/29 DocID07617 Rev 4
L6206
6.2
Application information
Output current capability and IC power dissipation
In
Figure 18 and Figure 19 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different driving types:
One full bridge ON at a time (
) in which only one load at a time is energized.
Two full bridges ON at the same time (
) in which two loads at the same time are energized.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 18. IC power dissipation versus output current with one full bridge ON at a time
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Figure 19. IC power dissipation versus output current with two full bridges ON at the same time
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DocID07617 Rev 4 21/29
29
Application information L6206
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heatsinking can be achieved
using copper on the PCB with proper area and thickness. Figure 21
and
show the junction to ambient thermal resistance values for the PowerSO36 and SO24 packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with a 6 cm
2
dissipating footprint (copper thickness of 35 µm), the
R th j-amb
is about 35 °C/W. Figure 20 shows mounting methods for this package. Using
a multilayer board with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W.
Figure 20. Mounting the PowerSO package
Slug soldered to PCB with dissipating area
Slug soldered to PCB with dissipating area plus ground layer
Slug soldered to PCB with dissipating area plus ground layer contacted through via holes
Figure 21. PowerSO36 junction ambient thermal resistance versus on-board copper area
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22/29 DocID07617 Rev 4
L6206 Application information
Figure 22. SO24 junction ambient thermal resistance versus on-board copper area
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DocID07617 Rev 4 23/29
29
Application information L6206
Figure 23. Typical quiescent current vs. supply voltage
Iq [m A]
5.6
f sw
= 1 kHz T j
= 25 °C
Figure 24. Typical high-side R voltage
DS(ON)
vs. supply
R
DS(ON)
[ ]
5.4
5.2
5.0
4.8
4.6
T j
= 85 °C
T j
= 125 °C
0.380
0.376
0.372
0.368
0.364
0.360
0.356
0.352
0.348
0.344
0.340
0.336
T j
= 25 °C
0 10 20 30
V
S
[V]
40 50 60 0 5 10 15
V
S
[V]
20 25 30
Figure 25. Normalized typical quiescent current vs. switching frequency
Iq / (Iq @ 1 kHz)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0 20 40 f
SW
[kHz]
60 80 100
Figure 26. Normalized R
DS(ON)
vs.junction temperature (typical value)
R
DS(ON)
/ (R
DS(ON)
@ 25 °C)
1.8
1.6
1.4
1.2
1.0
0.8
0 20 40 60
Tj [°C]
80 100 120 140
Figure 27. Typical low-side R
DS(ON)
vs. supply voltage
R
DS(ON)
[ ]
0.300
0.296
T j
= 25 °C
Figure 28. Typical drain-source diode forward
ON characteristic
I
SD
[A]
3.0
T j
= 25 °C
2.5
0.292
2.0
0.288
1.5
0.284
1.0
0.280
0.5
0.276
0 5 10
V
S
15
[V]
20 25 30
0.0
700 800 900 1000
V
SD
[mV]
1100 1200 1300
24/29 DocID07617 Rev 4
L6206 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
Figure 29. PowerSO36 package outline
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DocID07617 Rev 4 25/29
29
Package information L6206
Table 9. PowerSO36 package mechanical data
Dimensions (mm) Dimensions (inch)
Symbol
Min. Typ. Max. Min. Typ. Max.
A a1 0.10 a2 a3 0 b 0.22 c 0.23 -
D (1) 15.80 -
3.60 -
0.30 0.004 -
3.30 -
-
0.10 0 -
D1 9.40 -
E 13.90 -
9.80 0.370 -
14.50 0.547 e e3
E1
(1)
-
0.65 -
11.05
10.90 -
-
E2 -
E3 5.80 -
-
-
-
2.90 -
0.0256
0.435
-
6.20 0.228 -
E4 2.90 -
G 0 -
H 15.50
h -
L 0.80 -
-
-
3.20 0.114 -
0.10 0 -
1.10 -
0.385
0.570
-
-
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
0.141
0.012
0.130
0.004
0.015
0.012
0.630
1. “D” and “E1” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch).
- Critical dimensions are “a3”, “E” and “G”.
26/29 DocID07617 Rev 4
L6206
7.2 SO24 package information
Figure 30. SO24 package outline
Package information
&
Table 10. SO24 package mechanical data
Dimensions (mm) Dimensions (inch)
Symbol
Min. Typ. Max. Min. Typ. Max.
A 2.35 -
A1 0.10 -
B 0.33 -
C 0.23 -
D (1) 15.20 -
E 7.40 e -
H 10.0 h 0.25 -
L 0.40 k ddd -
-
0° (min.), 8° (max.)
0.10 -
0.050
0.004
1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
0.299
-
0.419
0.030
0.050
0.104
0.012
0.020
0.013
0.614
DocID07617 Rev 4 27/29
29
Revision history L6206
Date
03-Sep-2003
24-Feb-2014
13-Mar-2017
03-Oct-2018
Revision
Table 11. Document revision history
Changes
1
2
3
4
Initial release.
Updated Section : Description on page 1 (removed “MultiPower-” from “MultiPower-BCD technology”).
Added Contents on page 2 .
Updated Section 1: Block diagram (added section title, numbered and moved Figure 1: Block diagram from page 1 to page 3).
Added title to Section 2: Maximum ratings on page 4 , added numbers and titles from Table 1: Absolute maximum ratings to
Table 3: Thermal data .
Added title to Section 3: Pin connections on page 6 , added number and title to Figure 2: Pin connections (top view) , renumbered note 1 below Figure 2 , added title to Table 4: Pin description .
Added title to Section 4: Electrical characteristics on page 8 , added title and number to Table 5 , renumbered notes 1 to 3 below Table 5 .
Renumbered Figure 3 and Figure 4 .
Added section numbers to Section 5: Circuit description on page 11 ,
Section 5.1
to Section 5.4
. Removed “and uC” from first sentence in
Section 5.2
. Renumbered Table 6 and Table 7 , added header to
Table 6 . Renumbered Figure 5 to Figure 13 . .
Added section numbers to Section 6: Application information on page 17 , Section 6.1
to Section 6.3
. Renumbered Table 8 , added header to Table 8 . Renumbered Figure 14 to Figure 29 .
Updated Section 7: Package information on page 26 (added main title and ECOPACK text. Added titles from Table 9: PowerSO36 package mechanical data to Table 11: SO24 package mechanical data and from Figure 30: PowerSO36 package outline to Figure 32:
SO24 package outline , reversed order of named tables and figures.
Removed 3D figures of packages, replaced 0.200 by 0.020 inch of max. B value in Table 11 ).
Added cross-references throughout document.
Added Section 8: Revision history and Table 12 .
Minor modifications throughout document.
Updated Table 8 on page 17 (removed C
REF row).
Updated Figure 14 on page 17 (replaced by new figure and title).
Updated Figure 15 on page 18 , Figure 16 on page 19 , and Figure 17 on page 20 [added “(with reference to 24-pin packages)” to titles].
Minor modifications throughout document.
Removed PowerDIP24 package from the whole document.
Removed “T j
“ from
.
Minor modifications throughout document.
28/29 DocID07617 Rev 4
L6206
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DocID07617 Rev 4 29/29
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