STMicroelectronics L6226 Datasheet

L6226

DMOS dual full bridge driver

Datasheet - production data

 Undervoltage lockout

 Integrated fast free wheeling diodes

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Features

 Operating supply voltage from 8 to 52 V

 2.8 A output peak current (1.4 A DC)

 R

DS(on)

0.73  typ. value at T

J

= 25 °C

 Operating frequency up to 100 kHz

 Programmable high side overcurrent detection and protection

 Diagnostic output

 Paralleled operation

 Cross conduction protection

 Thermal shutdown

Applications

 Bipolar stepper motor

 Dual or quad DC motor

Description

The L6226 is a DMOS dual full bridge designed for motor control applications, realized in multipower-BCD technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. Available in

PowerSO36 and SO24 (20+2+2) packages, the

L6226 features thermal shutdown and a nondissipative overcurrent detection on the high side power MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection.

Figure 1. Block diagram

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October 2018

This is information on a product in full production.

DocID9452 Rev 5 1/29 www.st.com

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Contents

Contents

11

L6226

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2

Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3

Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 12

4.4

Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output current capability and IC power dissipation. . . . . . . . . . . . . . . . . . . . . . . . 21

Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1

PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2

SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/29 DocID9452 Rev 5

L6226 Maximum ratings

1.1

1.2

Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter

V

V

S

OD

Supply voltage V

SA

= V

SB

= V

S

Differen tial voltage between

VS

A

, OUT1 and VS

SENSE

A

, OUT2

B

, OUT1

B

B

A

, SENSE

, OUT2

B

,

A

V

SA

= V

SB

V

SENSEA

= V

S

= 60 V;

= V

SENSEB

= GND

OCD

A

,

OCD

B

OCD pins voltage range

PROGCL

A

,

PROGCL

B

PROGCL pins voltage range -

-

V

BOOT

V

IN

,V

EN

Input and enable voltage range -

V

SA

= V

SB

= V

S

V

SENSEA

,

V

SENSEB

I

S(peak)

Voltage range at pins SENSE and SENSE

B

A

Pulsed supply current (for each

VS pin), internally limited by the overcurrent protection

-

V

SA

= V

SB

= V

S

; t

PULSE

< 1 ms

I

S

RMS supply current

(for each VS pin)

V

SA

= V

SB

= V

S

T stg

, T

OP

Storage and operating temperature range

-

60 V

-0.3 to +10 V

-0.3 to +7 V

V S + 10 V

-0.3 to +7 V

-1 to +4

3.55

V

A

-40 to 150 ° C

Recommended operating conditions

Table 2. Recommended operating conditions

Symbol Parameter conditions Max. Unit

V

V

S

OD

V

SENSEA

,

V

SENSEB

I

OUT f sw

Supply voltage

Differential voltage between

VS

A

, OUT1 and VS

SENSE

B

B

, OUT1

B

A

, OUT2

A

, SENSE

, OUT2

B

,

A

VS

A

= VS

B

= V

S

;

VSENSE

A

= VSENSE

B

Vo ltage range at pins SENSE and SENSE

B

RMS output current

A

V

SA

= V

SB

= V

S

8

(pulsed t

W

< t rr

)

(DC)

-

-

-6

-1

-

52

6

1

1.4

V

V

V

A

Switching frequency 100 kHz

DocID9452 Rev 5 3/29

29

Maximum ratings L6226

Symbol

Table 3. Thermal data

Description

Rth-j-pins Maximum thermal resistance junction-pins

Rth-j-amb1 Maximum thermal resistance junction-ambient 1

Rth-j-amb1 Maximum thermal resistance junction-ambient 2

Rth-j-amb1 Maximum thermal resistance junction-ambient 3

Rth-j-amb2 Maximum thermal resistance junction-ambient 4

SO24 PowerSO36

15

-

52

-

-

78

-

2

-

36

16

63

Unit

° C/W

° C/W

° C/W

° C/W

° C/W

° C/W

4/29 DocID9452 Rev 5

L6226 Pin connections

Figure 2. Pin connections

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1. The slug is internally connected to pins 1,18,19 and 36 (GND pins).

Table 4. Pin description

Pin no.

Name Type

SO24

1

2

PowerSO36

10

11

IN1A

IN2A

3

4

5

12

13

15

6, 7, 18, 19 1, 18, 19, 36

8 22

SENSEA

OCDA

OUT1A

GND

OUT1B

Function

Logic input Bridge A logic input 1.

Logic input Bridge A logic input 2.

Power supply

Bridge A source pin. This pin must be connected to power ground directly or through a sensing power resistor.

Open drain output

Bridge A overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection.

Power output

Bridge A output 1.

GND

Signal ground terminals. In SO packages, these pins are also used for heat dissipation toward the PCB.

Power output

Bridge B output 1.

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Pin connections L6226

SO24

Pin no.

PowerSO36

Table 4. Pin description (continued)

Name Type

9

10

11

12

13

14

15

16

17

20

21

22

23

24

24

25

26

27

28

29

30

32

33

4

5

7

8

9

Function

OCDB

SENSEB

IN1B

IN2B

PROGCLB

ENB

VBOOT

OUT2B

VSB

VSA

OUT2A

VCP

ENA

PROGCLA

Open drain output

Bridge B overcurrent detection and thermal protection pin.An internal open drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection.

Power supply

Bridge B source pin. This pin must be connected to power ground directly or through a sensing power resistor.

Logic input Bridge B input 1

Logic input Bridge B input 2

R pin

Bridge B overcurrent level programming.

A resistor connected between this pin and

Ground sets the programmable current limiting value for the bridge B. By connecting this pin to Ground the maximum current is set.This pin cannot be left non-connected.

Logic input

Supply voltage

Bridge B enable. LOW logic level switches

OFF all power MOSFETs of bridge B. If not used, it has to be connected to +5 V.

Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B.

Power output

Bridge B output 2.

Power supply

Power supply

Bridge B power supply voltage. it must be connected to the supply voltage together with pin VSA.

Bridge A power supply voltage. it must be connected to the supply voltage together with pin VSB.

Power output

Output

Bridge A output 2.

Logic input

R pin

Charge pump oscillator output.

Bridge A enable. LOW logic level switches

OFF all power MOSFETs of bridge A. If not used, it has to be connected to +5 V.

Bridge A overcurrent level programming.

A resistor connected between this pin and

Ground sets the programmable current limiting value for the bridge A. By connecting this pin to ground the maximum current is set.This pin cannot be left nonconnected.

6/29 DocID9452 Rev 5

L6226 Electrical characteristics

T

A

= 25 °C, V

S

= 48 V, unless otherwise specified

Symbol Parameter

Table 5. Electrical characteristics conditions Typ.

V

Sth(ON)

V

Sth(OFF)

Turn-on threshold

Turn-off threshold

I

S

Quiescent supply current

T j(OFF)

Thermal shutdown temperature

Output DMOS transistors

-

-

-

All bridges OFF;

T

J

= -25 °C to 125 °C

(1)

5.8 6.3 6.8

5 5.5 6

-

-

5

165

10

-

V

V m

° C

R

DS(ON)

High-side + low-side switch ON resistance

I

DSS

Leakage current

T

J

= 25 °C

T

J

= 125 °C

(1)

EN = Low; OUT = V

S

EN = Low; OUT = GND

-

-

-

-0.3

1.47 1.69

2.35 2.70

-

-

-

 mA

Source drain diodes

V

SD

Forward ON voltage t rr t fr

Reverse recovery time

Forward recovery time

Logic input

V

IL

V

IH

I

IL

Low level logic input voltage

High level logic input voltage

Low level logic input current

I

IH

High level logic input current

V th(ON)

Turn-on input threshold

V th(OFF)

Turn-off input threshold

V th(HYS)

Input threshold hysteresis

Switching characteristics t

D(on)EN

Enable to out turn ON delay time

(2) t

D(on)IN

Input to out turn ON delay time t

RISE

Output rise time

(2) t

D(off)EN

Enable to out turn OFF delay time (2) t

D(off)IN

Input to out turn OFF delay time t

FALL time

(2)

I

SD

= 2.8 A, EN = LOW

-

I f

= 1.4 A

-

-

-

-

-

GND logic input voltage

7 V logic input voltage

I

LOAD

= 1.4 A, resistive load

I

LOAD

= 1.4 A, resistive load

(dead time included)

I

LOAD

= 1.4 A, resistive load

I

LOAD

= 1.4 A, resistive load

I

LOAD

= 1.4 A, resistive load

I

LOAD

= 1.4 A, resistive load

-

-

-

-0.3

2

-10

-

-

-

-

-

1.8 2.0

0.8 1.3 -

0.25 0.5 -

0.8

7

-

V

V

µA

10 µA

V

V

V

500

-

1.15 1.3

300

200

-

-

-

1.9

800 ns

-

40 250 ns

500 800 1000 ns

500 800 1000 ns

40 250 ns

V ns ns

µs

DocID9452 Rev 5 7/29

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Electrical characteristics L6226

Symbol

Table 5. Electrical characteristics (continued)

Parameter t dt f

CP

Charge pump frequency

Overcurrent detection

Test conditions

-

-25 °C < Tj < 125 °C

Min.

Typ . Max.

Unit

0.5 1 -

0.6 1

µs

MHz

Is over

Input supply overcurrent detection threshold

-25 °C <Tj < 125 °C; R

-25 °C <Tj < 125 °C; R

CL

CL

-25 °C <Tj < 125 °C; R

CL

= 39 k 

= 5 k 

= GND

ROPDR Open drain ON resistance t

OCD(ON)

OCD turn-on delay time

(3) t

OCD(OFF)

OCD turn-off delay time

(3)

I = 4 mA

I = 4 mA; C

I = 4 mA; C

EN

EN

< 100 pF

< 100 pF

1. Tested at 25 °C in a restricted range and guaranteed by characterization.

2. See Figure 3

.

3. See Figure 4

.

-10%

-10%

-30%

-

-

-

0.29

2.21

2.8

40

200

100

+10%

+10%

+30%

60

-

-

A

 ns ns

Figure 3. Switching characteristic definition

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L6226 Electrical characteristics

Figure 4. Overcurrent detection timing definition

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Circuit description L6226

4.1 Power stages and charge pump

The L6226 integrates two independent Power MOS full bridges. Each Power MOS has an

R

DSon

= 0.73  (typical value at 25 °C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1  s typical) between the switch off and switch on of two Power MOS in one leg of a bridge. Using N

channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (VBOOT) supply is obtained through an internal oscillator and

few external components to realize a charge pump circuit as shown in Figure 5

. The oscillator output (VCP) is a square wave at 600 kHz (typical) with 10 V amplitude.

Recommended values/part numbers for the charge pump circuit are shown in Table 6 .

Table 6. Charge pump external components values

Component Value

C

BOOT

220 nF

C

P

10

D1 1N4148

D2 1N4148

Figure 5. Charge pump circuit

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Pins IN1 A , IN2 A , IN1 B , IN2 B , EN A and EN B are TTL/ CMOS and microcontroller compatible

logic inputs. The internal structure is shown in Figure 4

. Typical value for turn-on and turn-off thresholds are respectively Vthon = 1.8 V and Vthoff = 1.3 V. Pins EN A and EN B are commonly used to implement Overcurrent and Thermal protection by connecting them respectively to the outputs OCD A and OCD B , which are open-drain outputs. If that type of connection is chosen, some care needs to be taken in driving these pins. Two configurations are shown in

Figure 7 and Figure 8

. If driven by an open drain (collector) structure, a pull-up resistor R EN and a capacitor C EN are connected as shown in

Figure 7 . If the driver is

a standard Push-Pull structure the resistor R EN and the capacitor C EN are connected as

shown in Figure 8

. The resistor R EN should be chosen in the range from 2.2 k  to 180 k  .

Recommended values for R EN and C EN are respectively 100 k  and 5.6 nF. More information on selecting the values is found in the overcurrent protection section.

DocID9452 Rev 5

L6226

Figure 6. Logic inputs internal structure

9

Circuit description

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Figure 8. ENA and ENB pins push-pull driving

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Table 7. Truth table

Inputs Outputs

L X

(1)

High Z

1. Don't care.

2. High impedance output.

DocID9452 Rev 5 11/29

29

Circuit description L6226

An overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides protection against a short-circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated.

Figure 9 shows a simplified schematic of the overcurrent detection circuit for the Bridge A.

Bridge B is provided of an analogous circuit.

To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the out-put current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference cur-rent IREF. When the output current reaches the detection threshold Isover the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4 mA connected to OCD pin is turned on.

Figure 10

shows the OCD operation.

This signal can be used to regulate the output current simply by connecting the OCD pin to

EN pin and adding an external R-C as shown in

Figure 9 . The off time before recovering

normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.

I

REF

and, therefore, the output current detection threshold are selectable by RCL value, following the equations:

 Isover = 2.8 A ± 30% at -25 °C < Tj < 125 °C if R

CL

(PROGCL connected to GND)

= 0 

 Isover = 11050 / R

CL

± 10% at -25 °C < T j

< 125 °C if 5 k  < R

C

< 40 k 

Figure 11

shows the output current protection threshold versus R

CL to 40 k  .

value in the range 5 k 

The disable time t

DISABLE means of the accurate

before recovering normal operation can be easily programmed by thresholds of the logic inputs. It is affected whether by C

EN magnitude is reported in

Figure 12

. The delay time t

DELAY an overcurrent has been detected depends only by C

EN

Figure 13

.

and R

EN

values and its

before turning off the bridge when

value. Its magnitude is reported in

C

EN

is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C

EN

should be chosen as big as possible according to the maximum tolerable delay time and the R

EN

value should be chosen according to the desired disable time.

The resistor R values for R

EN disable time.

EN

should be chosen in the range from 2.2 k  to 180 k  . Recommended

and C

EN

are respectively 100 k  and 5.6 nF that allow obtaining 200 µs

12/29 DocID9452 Rev 5

L6226 Circuit description

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Figure 10. Overcurrent protection waveforms

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Circuit description

Figure 11. Output current protection threshold versus R

CL

value

,

6 2 9 ( 5

>$ @

N N N N

5

& /

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N N N

Figure 12. t

DISABLE

versus C

EN

and R

EN

(V

DD

= 5 V)

N : N :

5

(1

N :

5

(1

N :

5

(1

N :

N

L6226

14/29 DocID9452 Rev 5

L6226

Figure 13. t

DELAY

versus C

EN

(V

DD

= 5 V)

Circuit description

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In addition to the overcurrent detection, the L6226 integrates a thermal protection for preventing the device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).

DocID9452 Rev 5 15/29

29

Application information L6226

A typical application using L6226 is shown in

Figure 14 . Typical component values for the

application are shown in

Figure 8 . A high quality ceramic capacitor in the range of 100 to

200 nF should be placed between the power pins (VS

A

and VS

B

) and ground near the

L6226 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the

EN

A

/OCD

A

and EN

B

/OCD

B

nodes to ground set the shut down time for the Bridge A and

Bridge B respectively when an over current is detected (see overcurrent protection). The two current sources (SENSE

A

and SENSE

B

) should be connected to power ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see pin description).

It is recommended to keep power ground and signal ground separated on PCB.

Component

C

1

C

2

C

BOOT

C

P

C

ENA

C

ENB

C

REF

Table 8. Component values for typical application

Value Component Value

 F D

1

1N4148 nF D

2

1N4148

220 nF R

CLA nF R

CLB nF R

ENA nF R

ENB

68 nF -

16/29 DocID9452 Rev 5

L6226

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Application information

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Figure 14. Typical application

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DocID9452 Rev 5 17/29

29

Paralleled operation L6226

The outputs of the L6226 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. When the two halves of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition the overcurrent detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold.

For most applications the recommended configuration is half bridge 1 of bridge A paralleled with the half bridge 1 of the bridge B, and the same for the half bridges 2 as shown in

Figure 15

. The current in the two devices connected in parallel will share very well since the

R

DS(ON)

of the devices on the same die is well matched.

When connected in this configuration the over current detection circuit, which senses the current in each bridge (A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. With the enables connected in parallel, the first detection of an over current in either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors R

CLA

or R

CLB

in

Figure 15

. It is recommended to use R

CLA

= R

CLB

.

In this configuration the resulting Bridge has the following characteristics.

 Equivalent device: full bridge

 R

DS(ON)

0.37  typ. value at TJ = 25°C

 2.8 A max. RMS load current

 5.6 A max. OCD threshold

18/29 DocID9452 Rev 5

L6226 Paralleled operation

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Figure 15. Parallel connection for higher current

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To operate the device in parallel and maintain a lower overcurrent threshold, half bridge 1 and the half bridge 2 of the bridge A can be connected in parallel and the same done for the bridge B as shown in

Figure 16

. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased.

When connected in this configuration the overcurrent detection circuit, senses the sum of the current in upper devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges.

Since the circuit senses the total current in the upper devices, the overcurrent threshold is equal to the threshold set the resistor R

CLA outputs OUT1B and OUT2B are high.

or R

CLB

in

Figure 16

when outputs OUT1A and OUT2A are high and resistor R

CLB

. R

CLA

sets the threshold

sets the threshold when

It is recommended to use R

CLA

= R

CLB

.

In this configuration, the resulting bridge has the following characteristics.

 Equivalent device: full bridge

 R

DS(ON)

0.37  typ. value at T

J

= 25 °C

 1.4 A max. RMS load current

 2.8 A max. OCD threshold

DocID9452 Rev 5 19/29

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Paralleled operation L6226

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Figure 16. Parallel connection with lower overcurrent threshold

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It is also possible to parallel the four half bridges to obtain a simple half bridge as shown in

Figure 17

. In this configuration the, the overcurrent threshold is equal to twice the minimum threshold set by the resistors R

CLA

R

CLA

= R

CLB

.

or R

CLB

in

Figure 17 . It is recommended to use

The resulting half bridge has the following characteristics.

 Equivalent device: half bridge

 R

DS(ON)

0.18  typ. value at T

J

= 25 °C

 2.8 A max RMS load current

 5.6 A max OCD threshold

20/29 DocID9452 Rev 5

L6226

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Figure 17. Paralleling the four half bridges

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Output current capability and IC power dissipation

In

Figure 18 and Figure 19 are shown the approximate relation between the output current

and the IC power dissipation using PWM current control driving two loads, for two different driving types:

 One full bridge ON at a time (

Figure 18

) in which only one load at a time is energized.

 Two full bridges ON at the same time (

Figure 19

) in which two loads at the same time are energized.

For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature

(125 °C maximum).

DocID9452 Rev 5 21/29

29

Paralleled operation

Figure 18. IC power dissipation versus output current with one full bridge ON at a time

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Figure 19. IC power dissipation versus output current with two full bridges ON at the same time

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L6226 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using

copper on the PCB with proper area and thickness. Figure 21

and

22 show the junction-to-

ambient thermal resistance values for the PowerSO36 and SO24 packages.

For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6 cm 2 dissipating footprint (copper thickness of 35 µm), the R thJA is about 35 °C/W.

Figure 20

shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W.

Figure 20. Mounting the PowerSO package

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DocID9452 Rev 5 23/29

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Package information L6226

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

Figure 23. PowerSO36 package outline

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24/29 DocID9452 Rev 5

L6226 Package information

Table 9. PowerSO36 package mechanical data

Dimensions (mm)

Symbol

Min.

Typ.

Max.

A

a1 a2 a3 b c

D (1)

D1

-

0.10

3.60

0.30

3.30

0 0.10

0.22

0.23

0.38

0.32

15.80

9.40

16.00

9.80

H h

L

N

S

E 13.90 14.50 e 0.65 e3 11.05

E1 (1) 10.90 11.10

E2

E3

E4

G

-

5.80

2.90

0

2.90

6.20

3.20

0.10

15.50

-

0.80

15.90

1.10

1.10

10°(max.)

8 °(max.)

-

-

-

-

DocID9452 Rev 5 25/29

29

Package information

8.2 SO24 package information

Figure 24. SO24 package outline

L6226

26/29

&

Table 10. SO24 package mechanical data

Dimensions mm inch Symbol

Min. Typ. Max. Min. Typ. Max.

A 2.35 -

A1 0.10 -

B 0.33 -

C 0.23 -

D 15.20 -

E 7.40 e -

H 10.0 h 0.25 -

L 0.40 k ddd -

-

0° (min.), 8° (max.)

0.10 -

0.050

0.004

0.104

0.012

0.020

0.013

0.614

0.299

-

0.419

0.030

0.050

DocID9452 Rev 5

L6226 Ordering codes

Order codes

L6226PD

L6226D

Table 11. Ordering information

Package

PowerSO36

SO24

Packing

Tube

DocID9452 Rev 5 27/29

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Revision history

Date

Sep-2003

04-Mar-2008

29-Sep-2009

21-Oct-2009

03-Oct-2018

Table 12. Document revision history

Revision Changes

3

4

1

2

5

Initial release

Minor revision due to revalidation process, no content change

Updated Table 1 on page 3

Updated Figure 4 on page 9

Removed PowerDIP24 package from the whole document.

Removed “T j

“ from

Table 2 on page 3

.

Minor modifications throughout document.

L6226

28/29 DocID9452 Rev 5

L6226

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

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