STMicroelectronics VNS3NV04DP-E Datasheet

VNS3NV04DP-E

OMNIFET II fully autoprotected Power MOSFET

Features

Max on-state resistance (per ch.)

Current limitation (typ)

Drain-source clamp voltage

R

ON

I

LIMH

V

CLAMP

120 m

Ω

3.5 A

40 V

■

■

■

■

■

■

■

■

■

■

■

ECOPACK

®

: lead free and RoHS compliant

Automotive Grade: compliance with AEC guidelines

Linear current limitation

Thermal shutdown

Short circuit protection

Integrated clamp

Low current drawn from input pin

Diagnostic feedback through input pin

ESD protection

Direct access to the gate of the Power

MOSFET (analog driving)

Compatible with standard Power MOSFET

SO-8

Description

The VNS3NV04DP-E device is made up of two monolithic chips (OMNIFET II) housed in a standard SO-8 package. The OMNIFET II is designed using STMicroelectronics™ VIPower™

M0-3 technology and is intended for replacement of standard Power MOSFETs in up to 50 kHz DC applications.

Built-in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments.

Fault feedback can be detected by monitoring voltage at the input pin

Table 1.

Device summary

Package

SO-8

September 2013

Tube

VNS3NV04DP-E

Order codes

Tape and reel

VNS3NV04DPTR-E

Doc ID 018529 Rev 2 1/21

www.st.com

1

1

2

Contents

Contents

3

4

5

VNS3NV04DP-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

Overvoltage clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2

Linear current limiter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3

Overtemperature and short circuit protection . . . . . . . . . . . . . . . . . . . . . . 16

3.4

Status feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3

SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 9.

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 10.

SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Doc ID 018529 Rev 2 3/21

List of figures

List of figures

VNS3NV04DP-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4.

Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5.

Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6.

Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7.

Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8.

Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9.

Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10.

Static drain-source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.

Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12.

Static drain-source on resistance vs input voltage (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13.

Static drain-source on resistance vs input voltage (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14.

Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 15.

Static drain-source on resistance vs Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 16.

Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 17.

Turn-on current slope (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 18.

Turn-on current slope (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 19.

Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 20.

Turn-off drain source voltage slope (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 21.

Turn-off drain-source voltage slope (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 22.

Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 23.

Switching time resistive load (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 24.

Switching time resistive load (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 25.

Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 26.

Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 27.

Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 28.

Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 29.

Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 30.

SO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 31.

SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 32.

Tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

INPUT1

OVERVOLTAGE

CLAMP

GATE

CONTROL

OVER

TEMPERATURE

LINEAR

CURRENT

LIMITER

DRAIN1

DRAIN2

OVERVOLTAGE

CLAMP

LINEAR

CURRENT

LIMITER

SOURCE1

SOURCE2

GATE

CONTROL

OVER

TEMPERATURE

INPUT2

Figure 2.

Configuration diagram (top view)

SOURCE 1

INPUT 1

SOURCE 2

INPUT 2

1

4

8

5

DRAIN 1

DRAIN 1

DRAIN 2

DRAIN 2

Doc ID 018529 Rev 2 5/21

Electrical specifications VNS3NV04DP-E

Figure 3.

Current and voltage conventions

I

IN1

V

IN1

V

IN2

I

IN2

R

IN1

R

IN2

INPUT 1

INPUT 2

SOURCE 1

DRAIN 1

DRAIN 2

SOURCE 2

I

D2

I

D1

V

DS1

V

DS1

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document.

Table 2.

Symbol

Absolute maximum ratings

Parameter

V

DSn

V

INn

I

INn

R

IN MINn

I

Dn

I

Rn

V

ESD1

V

ESD2

P

T tot j

T c

T stg

Drain-Source Voltage (V

INn

Input voltage

Input current

Minimum input series impedance

Drain current

Reverse DC output current

Case operating temperature

Storage temperature

= 0 V)

Electrostatic discharge (R = 1.5 K

Ω, C = 100 pF)

Electrostatic discharge on output pins only (R = 330

Ω,

C = 150 pF)

Total dissipation at T c

= 25 °C

Operating junction temperature

Value

Internally clamped

Internally clamped

+/- 20

220

Internally limited

-5.5

4000

16500

4

Internally limited

Internally limited

-55 to 150

Unit

V

V mA

Ω

A

A

V

V

Ω

°C

°C

°C

6/21 Doc ID 018529 Rev 2

VNS3NV04DP-E Electrical specifications

Table 3.

Symbol

Thermal data

Parameter Max value Unit

R thj-lead

Thermal resistance junction-lead (per channel) 30 °C/W

R thj-amb

Thermal resistance junction-ambient 80

(1)

°C/W

1.

When mounted on a standard single-sided FR4 board with 50mm

2

of Cu (at least 35

μm thick) connected to all DRAIN pins of the relative channel

Values specified in this section are for -40 °C < T j

< 150 °C, unless otherwise stated.

Table 4.

Symbol

Off

Parameter

V

CLAMP

V

V

I

CLTH

INTH

ISS

Drain-source clamp voltage

Drain-source clamp threshold voltage

Input threshold voltage

Supply current from input pin

Test conditions

V

IN

= 0 V; I

D

= 1.5 A 40

V

IN

= 0 V; I

D

= 2 mA 36

V

DS

= V

IN

; I

D

= 1 mA

Min Typ Max Unit

0.5

45 55

2.5

V

DS

= 0 V; V

IN

= 5 V 100 150

V

V

V

µA

V

INCL

I

DSS

Input-source clamp voltage

Zero input voltage drain current

(V

IN

= 0 V)

I

IN

= 1 mA

I

IN

= -1 mA

V

DS

= 13 V; V

IN

= 0 V; T j

= 25 °C

V

DS

= 25 V; V

IN

= 0 V

6

-1

6.8

8

-0.3

30

75

V

V

µA

µA

Table 5.

Symbol

R

DS(on)

On

Parameter Test conditions

Static drain-source on resistance

V

IN

= 5 V; I

D

= 1.5 A; T j

= 25 °C

V

IN

= 5 V; I

D

= 1.5 A

Min Typ Max Unit

—

—

—

—

120

240 m

Ω m

Ω

T j

= 25 °C, unless otherwise specified

Table 6.

Symbol

g fs

(1)

C

OSS

Dynamic

Parameter

Forward transconductance

Output capacitance

Test conditions

V

DD

= 13 V; I

D

= 1.5 A

Min Typ Max Unit

—

V

DS

= 13 V; f = 1 MHz; V

IN

= 0 V —

5.0

150

—

—

S pF

Doc ID 018529 Rev 2 7/21

Electrical specifications VNS3NV04DP-E

Table 7.

Symbol

t d(on) t r t d(off) t f t d(on) t r t d(off) t f

Switching

Parameter

Turn-on delay time

Rise time

Turn-off delay time

Fall time

Turn-on delay time

Rise time

Turn-off delay time

Fall time

Test conditions

V

DD

= 15 V; I

D

= 1.5 A;

V gen

MIN

= 5 V; R gen

= R

IN

= 220

Ω (see

Figure 4

)

V

DD

V gen

= 15 V; I

= 5 V; R

D

(see

Figure 4

)

= 1.5 A; gen

= 2.2 K

Ω

(dI/dt) on

Turn-on current slope

Q i

Total input charge

V

DD

V gen

R gen

= 15 V; I

D

= 5 V;

= R

IN MIN

= 1.5 A;

= 220

Ω

V

DD

I gen

= 12 V; I

D

= 1.5 A; V

IN

= 5 V;

= 2.13 mA (see

Figure 7

)

Min Typ Max Unit

90 300

250 750

450 1350

250 750

0.45

1.35

2.5

7.5

3.3

10.0

2.0

6.0

ns

µs

µs

µs

µs ns ns ns

4.7

8.5

A/µs nC

Table 8.

Symbol

V

SD

(1) t rr

Source drain diode

Parameter Test conditions

Forward on voltage

Reverse recovery time

I

SD

= 1.5 A; V

IN

= 0 V

Q rr

Reverse recovery charge

I

SD

V

DD

= 1.5 A; dI/dt = 12 A/µs;

= 30 V; L = 200 µH

(see

Figure 5

)

I

RRM

Reverse recovery current

1.

Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

Min Typ Max Unit

0.8

107

V ns

37 µC

0.7

A

-40 °C < T j

< 150 °C, unless otherwise specified

Table 9.

Symbol

Protections

Parameter Test conditions

V

IN

= 5 V; V

DS

Min Typ Max Unit

= 13 V 3.5

5 7 A I lim

Drain current limit t dlim

T jsh

Step response current limit

Overtemperature shutdown

T jrs reset

I gf

Fault sink current

E as

Single pulse avalanche energy

V

IN

= 5 V; V

DS

= 13 V

V

IN

= 5 V; V

DS

= 13 V; T j

= T jsh

Starting T

V

IN j

= 25 °C; V

= 5 V; R gen

DD

= R

IN MIN

= 24 V;

= 220

Ω;

L = 24 mH (see

Figure 6

and

Figure 8

)

10 µs

150 175 200 °C

135 °C

10 15 20 mA

100 mJ

8/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

Figure 4.

Switching time test circuit for resistive load

Electrical specifications

V

D

V gen

R gen

I

D

90%

V gen t d(on) t r

10% t d(off) t f

t t

Figure 5.

Test circuit for diode recovery times

220

Ω

D

I

OMNIFET

S

B

A

FAST

DIODE

R gen

A

B

I

OMNIFET

D

L=100uH

V

DD

V gen

S

8.5

Ω

Doc ID 018529 Rev 2 9/21

Electrical specifications

Figure 6.

Unclamped inductive load test circuits

VNS3NV04DP-E

V

IN

P

W

R

GEN

Figure 7.

Input charge test circuit

V

IN

GEN

ND8003

10/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

Figure 8.

Unclamped inductive waveforms

Electrical specifications

Doc ID 018529 Rev 2 11/21

Electrical specifications VNS3NV04DP-E

12/21

Figure 9.

Source-drain diode forward characteristics

800

750

700

650

600

0

Vsd (mV)

1100

1050

1000

950

900

850

1

Vin=0V

2 3 4 5 6

Id (A)

7

Figure 11. Derating curve

8 9 10 11 12

Figure 10. Static drain-source on resistance

Rds(on) (mohms)

1000

900

800

Tj=-40ºC

Vin=2.5V

700

600

500

400

300

Tj=25ºC

Tj=150ºC

200

100

0

0.05

0.1 0.15

0.2

0.25

0.3

Id(A)

0.35

0.4

0.45

0.5

0.55

Figure 12. Static drain-source on resistance vs input voltage

(part 1)

Rds(on) (mohms)

300

175

150

125

100

75

50

25

0

275

250

225

200

Tj=150ºC

Tj=25ºC

Tj=-40ºC

3 3.5

4 4.5

Vin(V)

5 5.5

6

Id=3.5A

Id=1A

Id=3.5A

Id=1A

Id=3.5A

Id=1A

6.5

Figure 14. Transconductance Figure 13. Static drain-source on resistance vs input voltage

(part 2)

Rds(on) (mohms)

250

225

200

175

150

125

100

75

50

25

0

3 3.5

4 4.5

Vin(V)

5

Id=1.5A

Tj=150ºC

Tj=25ºC

Tj=-40ºC

5.5

6 6.5

Gfs (S)

11

5

4

3

2

1

0

0

10

9

8

7

6

Vds=13V

0.5

1 1.5

2 2.5

Id (A)

3

Tj=-40ºC

Tj=25ºC

Tj=150ºC

3.5

4 4.5

5 5.5

Doc ID 018529 Rev 2

VNS3NV04DP-E Electrical specifications

Figure 15. Static drain-source on resistance vs Id

Figure 16. Transfer characteristics

Rds(on) (mohms)

250

225

200

Vin=5V

175

150

125

100

75

50

25

0

0 0.5

1 1.5

2

Id (A)

2.5

Tj=150ºC

Tj=25ºC

Tj= - 40ºC

3 3.5

4

Idon (A)

6

5.5

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

1.5

2

Vds=13.5V

Tj=150ºC

Tj=25ºC

2.5

3

Tj=-40ºC

3.5

Vin (V)

4 4.5

5 5.5

6

Figure 17. Turn-on current slope (part 1) Figure 18. Turn-on current slope (part 2)

di/dt(A/us)

5

3

2.5

2

1.5

4.5

4

3.5

0.5

1

0

0

Vin=5V

Vdd=15V

Id=1.5A

250

500

750 1000 1250 1500 1750 2000 2250 2500

Rg(ohm) di/dt(A/usec)

1.75

1.5

1.25

1

Vin=3.5V

Vdd=15V

Id=1.5A

0.75

0.5

0.25

0

0 250 500 750 1000 1250 1500 1750 2000 2250 2500

Rg(ohm)

Figure 19. Input voltage vs input charge Figure 20. Turn-off drain source voltage slope (part 1)

Vin (V)

9

3

2

5

4

1

0

0

8

7

6

1

Vds=1V

Id=1.5A

2 3 4 5 6

Qg (nC)

7 8 9 10 11 dv/dt(V/usec)

300

275

250

225

200

175

150

125

100

75

50

25

0

0

250

500

Vin=5V

Vdd=15V

Id=1.5A

750

1000

1250

1500

1750

2000

2250

Rg(ohm)

2500

Doc ID 018529 Rev 2 13/21

Electrical specifications VNS3NV04DP-E

Figure 21. Turn-off drain-source voltage slope (part 2)

Figure 22. Capacitance variations

dv/dt(V/usec)

300

275

250

225

200

175

150

125

100

75

50

25

0

0

250

500

Vin=3.5V

Vdd=15V

Id=1.5A

750

1000 1500

1250

Rg(ohm)

1750

2000

2250

2500

C(pF)

350

300

250

200

150

100

50

0 5 10 15

Vds(V)

20

f=1MHz

Vin=0V

25 30 35

Figure 23. Switching time resistive load

(part 1)

Figure 24. Switching time resistive load

(part 1)

t(usec)

4

3.5

3

2.5

2

1.5

Vdd=15V

Id=1.5A

Vin=5V td(off) tr tf

1

0.5

0

0

td(on)

250

500

750

1000

1250

1500

Rg(ohm)

1750

2000

2250

2500

Figure 25. Output characteristics

t(nsec)

900

800

tr

700

600

500

400

300

200

100

tf td(off) td(on)

0

3.25

3.5

3.75

Vdd=15V

Id=1.5A

Rg=220ohm

4 4.25

Vin(V)

4.5

4.75

Figure 26. Normalized on resistance vs temperature

5 5.25

Id (A)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

0 1 2 3 4 5

Vds (V)

6

Vin=5V

Vin=4V

Vin=3V

7 8 9 10

Rds(on) (mOhm)

4

3.5

3

2.5

2

1.5

1

Vin=5V

Id=1.5A

0.5

-50 -25 0 25 50 75

Tc )ºC)

100 125 150 175

14/21 Doc ID 018529 Rev 2

VNS3NV04DP-E Electrical specifications

Figure 27. Normalized input threshold voltage vs temperature

Figure 28. Normalized current limit vs junction temperature

Vinth (V)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25

Vds=Vin

Id=1mA

0 25 50 75

Tc (ºC)

100 125 150 175

Figure 29. Step response current limit

Tdlim(usec)

13

12.5

12

11.5

11

10.5

10

9.5

9

8.5

8

7.5

Vin=5V

Rg=220ohm

5 7.5

10 12.5 15 17.5 20 22.5 25 27.5 30 32.5

Vdd(V)

Ilim (A)

10

9

8

7

6

5

4

3

2

1

0

-50 -25

Vin=5V

Vds=13V

0 25 50 75

Tc (ºC)

100 125 150 175

Doc ID 018529 Rev 2 15/21

Protection features VNS3NV04DP-E

3.1

During normal operation, the INPUT pin is electrically connected to the gate of the internal power MOSFET through a low impedance path.

The device then behaves like a standard power MOSFET and can be used as a switch from

DC up to 50 KHz. The only difference from the user’s standpoint is that a small DC current

I

ISS

(typ. 100 µA) flows into the INPUT pin in order to supply the internal circuitry.

The following sections describe the device features.

Overvoltage clamp protection

Internally set at 45 V, along with the rugged avalanche characteristics of the Power

MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.

3.2 Linear current limiter circuit

Limits the drain current I

D

to I lim

whatever the INPUT pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh.

3.3 Overtemperature short circuit protection

These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15 °C below shutdown temperature.

In the case of an overtemperature fault condition (T j

> T jsh

), the device tries to sink a diagnostic current I gf

through the INPUT pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current I gf

, the INPUT pin falls to 0 V. This however not affects the device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current I

ISS

.

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit.

16/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

4

Package and packing information

Package and packing information

4.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at:

www.st.com

.

ECOPACK

®

is an ST trademark.

4.2 SO-8 mechanical data

Table 10.

SO-8 mechanical data

Dim. mm

Min. Typ. Max.

A

A1 0.10

A2 1.25

b 0.28

c 0.17

D

(1)

4.80

E 5.80

E1

(2)

3.80

4.90

6.00

3.90

1.75

0.25

0.48

0.23

5.00

6.20

4.00 h 0.25

L 0.40

L1 k 0° ccc

1.04

0.50

1.27

8°

0.10

1.

Dimension “D” does not include mold Flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side).

2.

Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Doc ID 018529 Rev 2 17/21

Package and packing information

Figure 30. SO-8 package dimension

VNS3NV04DP-E

0016023 D

18/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

4.3 SO-8 packing information

Figure 31. SO-8 tube shipment (no suffix)

B

C

A

Package and packing information

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

100

2000

532

3.2

6

0.6

Figure 32. Tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

2500

2500

330

1.5

13

20.2

12.4

60

18.4

All dimensions are in mm.

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

12

4

P

8

D (± 0.1/-0)

1.5

D1 (min)

F (± 0.05)

K (max)

P1 (± 0.1)

1.5

5.5

4.5

2

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

Doc ID 018529 Rev 2 19/21

Revision history

Table 11.

Document revision history

Date Revision

09-Mar-2011

18-Sep-2013

1

2

Initial release.

Updated Disclaimer

Changes

VNS3NV04DP-E

20/21 Doc ID 018529 Rev 2

VNS3NV04DP-E

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Doc ID 018529 Rev 2 21/21