STMicroelectronics VNP8T Datasheet

VNP8T

Features

Type

VNP8T

R

DS(on)

120 m Ω

I lim

3.5 A

V clamp

43 V

• Linear current limitation

• Thermal shutdown

• Short circuit protection

• Integrated clamp

• Low current drawn from input pin

• Diagnostic feedback through input pin

• ESD protection

• Direct access to the gate of the Power

MOSFET (analog driving)

• Compatible with standard Power MOSFETs

Omnifet II fully autoprotected Power MOSFET

Datasheet

-

production data

Description

The VNP8T is a monolithic device designed in

STMicroelectronics

®

VIPower

®

M0-3 technology, intended for the replacement of standard Power

MOSFETs from DC up to 50 kHz applications.

Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments.

Fault feedback can be detected by monitoring the voltage at the input pin.

Table 1. Device summary

DIE delivery package Order code

D1 (Uncut inked wafer)

D8 (Tape & Reel)

VNP8TD1

VNP8TD8

September 2013

This is information on a product in full production.

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www.st.com

6

7

3

4

1

2

Contents

Contents

5

VNP8T

Block diagram and pad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

Overvoltage clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2

Linear current limiter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3

Overtemperature and short circuit protections . . . . . . . . . . . . . . . . . . . . . 10

4.4

Status feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DIE package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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VNP8T

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pad location (axes origin: center of DIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5.

Table 6.

Table 7.

Table 8.

Off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

On-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9.

Source drain diode (T j

= 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 10.

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11.

DIE delivery package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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List of figures

List of figures

VNP8T

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Pad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3.

Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.

Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6.

Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7.

Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8.

DIE delivery package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

Carrier tape information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Reel 7 INCH information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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VNP8T

1

Block diagram and pad configuration

Block diagram and pad configuration

Figure 1. Block diagram

'UDLQ

/VERVOLTAG E

FODPS

,QSXW

*DWH

FRQWURO

2YHU

WHPSHUDWXUH

/LQHDU

FXUUHQW

OLPLWHU

6RXUFH

("1($'5

Figure 2. Pad configuration

Y

Output

Tempsens

0

Input 150 Gate

X ai13314

Table 2. Pad location (axes origin: center of DIE)

Center pad coordinates Pad dimensions

Pad description

X (µm) Y (µm)

Input

Output

Gate

(1)

Drain

-613.5

730

427.5

1.

This pad is intended for testing purposes only.

-390.2

29.7

-301.2

Back

X (µm)

432

250

102

Y (µm)

432

1379.4

102

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18

Block diagram and pad configuration

Parameter

Die size

Back metallization

Front metallization

Passivation layer

Die thickness

Scribe street width

Table 3. Physical characteristics

Description Value

2.21 x 1.72

Ti - Ni - Au

Al - Si

Silicon - Nitride

3

1.5

280 ±20

100

VNP8T

Unit mm

µm

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DocID022888 Rev 5

VNP8T Absolute maximum ratings

Stressing the device above the ratings listed in Table 4: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability.

Symbol

Table 4. Absolute maximum ratings

Parameter

V

DS

V

IN

I

IN

R

IN MIN

I

D

I

R

V

ESD1

V

ESD2

Drain-source voltage (V

IN

= 0 V)

Input voltage

Input current

Minimum input series impedance

Drain current

Reverse DC output current

Electrostatic discharge (R = 1.5 K Ω ; C = 100 pF)

Electrostatic discharge on output pin only

(R = 330

Ω

; C = 150 pF)

Operating junction temperature T j

T stg

Storage temperature

E

MAX

Single pulse avalanche energy

(L = 8 mH; I out

= 3.5 A; T j

= 175 °C)

Value

Internally clamped V

± 20

220

Internally limited

-5.5

4000 mA

Ω

A

V

16500

Internally limited

-55 to 150

95

Unit

°C mJ

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18

Electrical characteristics VNP8T

Values specified in this section are for -40 °C < T j

< 175 °C, unless otherwise specified.

Symbol Parameter

Table 5. Off-state

Test conditions Min.

Typ.

Max.

Unit

V

CLAMP

Drain-source clamp voltage

V

CLTH

Drain-source clamp threshold voltage

V

INTH

I

ISS

V

I

INCL

DSS

Input threshold voltage

Supply current from input pin

Input-source clamp voltage

Zero input voltage drain current

(V

IN

= 0 V)

V

V

IN

IN

= 0 V; I

= 0 V; I

D

D

= 200 mA

= 2 mA

43

36

45 55 V

V

V

DS

= V

IN

; I

D

= 1 mA 0.6

2.5

V

V

DS

= 0 V; V

IN

= 5 V

I

IN

= 1 mA;

I

IN

= -1 mA

6

-1.0

100

6.8

6.8

150

8

-0.3

V

DS

T j

= 13 V; V

= 25 °C;

IN

= 0 V;

30

V

DS

= 4 V; V

IN

= 0 V; 50

µA

V

V

µA

µA

V

DS

T j

= 4 V; V

IN

= 0 V;

= -40 °C to 150 °C

V

DS

= 25 V; V

IN

= 0 V

30

90

µA

µA

Symbol Parameter

R

DS(on)

Static drain-source on resistance

Table 6. On-state

Test conditions

V

IN

= 5 V; I

D

= 1.5 A; T j

= 25 °C

V

IN

= 5 V; I

D

= 1.5 A

Min. Typ. Max.

Unit

—

—

— 120 m Ω

— 280 m

Ω

Table 7. Dynamic

Symbol Parameter Test conditions Min Typ Max Unit g fs

(1)

C

OSS

(1)

Forward transconductance V

DD

Output capacitance V

DS

= 13 V; I

D

= 1.5 A

= 13 V; f = 1 MHz; V

IN

1.

Guaranteed by design/characterization on final product.

— 5.0

—

= 0 V — 150 —

S pF

8/19

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VNP8T Electrical characteristics

Symbol Parameter

Table 8. Switching

Test conditions t d(on) t r t d(off) t f t d(on) t r t d(off) t f

Turn-on delay time

Rise time

Turn-off delay time

Fall time

Turn-on delay time

Rise time

Turn-off delay time

Fall time

V

V

V

V

DD gen

DD gen

= 15 V; I

= 5 V; R

(see Figure 3

)

= 15 V; I

= 5 V; R

(see Figure 3

)

D

D

= 1.5 A gen gen

= R

IN MIN

= 1.5 A

= 2.2 K Ω

= 220 Ω

(dI/dt)

Q on

(1) i

(1)

Turn-on current slope

Total input charge

V

DD

V gen

= 15 V; I

D

= 1.5 A

= 5 V; R gen

= R

IN MIN

= 220 Ω

V

DD

I gen

= 12 V; I

D

= 1.5 A; V

IN

= 5 V

= 2.13 mA (see Figure 6

)

1.

Guaranteed by design/characterization on final product.

Min Typ Max Unit

—

—

—

— 148

— 473

— 804

— 484

— 627

3.1

3.7

2.3

— 1.89

— 10

—

—

—

—

—

—

—

—

—

—

A/µs nC ns ns ns ns ns

µs

µs

µs

Table 9. Source drain diode (T j

= 25 °C)

(1)

Parameter Test conditions Min Typ Max Unit Symbol

V

SD

(2)

Forward on voltage I

SD

= 1.5 A; V

IN

= 0 V t

Q rr rr

Reverse recovery time

Reverse recovery charge

I

SD

V

DD

= 1.5 A; dI/dt = 12 A/µs;

= 30 V; L = 200 µH

(see Figure 4 )

I

RRM

Reverse recovery current

1.

Guaranteed by design/characterization on final product.

2.

Pulsed: Pulse duration = 300ms, duty cycle 1.5%

— 0.8

—

— 107 —

— 37 —

— 0.7

—

V ns

µC

A

Symbol Parameter

Table 10. Protections

Test conditions Min Typ Max Unit

T jrs

(1)

E t

I

I lim dlim

T jsh gf as

(2)

Drain current limit

Step response current limit

Overtemperature shutdown

Overtemperature reset

Fault sink current

Single pulse avalanche energy

V

IN

= 5 V; V

DS

= 13 V 3.5

5

V

IN

= 5 V; V

DS

= 13 V 10

7

175 200 225

V

IN

= 5 V; V

DS

= 13 V; T j

= T jsh

Starting T

V

IN j

= 25°C; V

= 5 V; R

DD gen

= R

IN MIN

= 24 V;

= 220 Ω ;

L = 24 mH (see

Figure 5

and

Figure 7 )

°C

160

10 15 20 mA

100

A

µs mJ

1.

Guaranteed by design.

2.

Energy capability not tested; its maximum value is guaranteed by design on package products.

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18

Protection features VNP8T

During normal operation, the INPUT pin is electrically connected to the gate of the internal

Power MOSFET through a low impedance path.

The device then behaves like a standard Power MOSFET and can be used as a switch from

DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current

I

ISS

(typ. 100 µA) flows into the INPUT pin in order to supply the internal circuitry.

4.2

4.3

The device integrates overvoltage clamp protection that is internally set at 45 V. This feature together with the rugged avalanche characteristics of the Power MOSFET stage gives this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.

Linear current limiter circuit

A linear current limiter circuit limits the drain current I

D

to I lim

whatever the INPUT pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh

.

Overtemperature and short circuit protections

These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 175 to 225 °C, a typical value being 200 °C. The device is automatically restarted when the chip temperature falls to about 10 °C below shutdown temperature.

Note:

In the case of an overtemperature fault condition (T j

> T jsh

), the device tries to sink a diagnostic current I gf

through the INPUT pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current I gf

, the INPUT pin falls to 0V.

However this does not affect the device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current I

ISS

.

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit.

10/19

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VNP8T Protection features

Figure 3. Switching time test circuit for resistive load

Vgen

RL

VD

Rgen D

OMNIFET

S

2200

μ F

3.3

μ

F

VDD

ID

90%

Vgen td(on) tr

10% td(off) tf t t

Figure 4. Test circuit for diode recovery times

$

$

:

,

'

/-.)&%4

6

%

)DVW

'LRGH

%

'

, —(

5

JHQ

9

''

,

/- .)&%4

9

JHQ

6

:

("1($'5 ai13315

DocID022888 Rev 5

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18

Protection features

VIN

Figure 5. Unclamped inductive load test circuits

L

VD

2200

μ F

3.3

μ F VDD

ID

Rgen

D

OMNIFET

S

PW

ai13316

Figure 6. Input charge test circuit

VNP8T

V

IN

GEN

ND8003

12/19

DocID022888 Rev 5

VNP8T

Figure 7. Unclamped inductive waveforms

VCLAMP

VD

Protection features

VDD

ID

IAR

VDD ai13317

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18

Package information VNP8T

5.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

14/19

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VNP8T

6 DIE package options

DIE package options

Package option

D1

D7

D8

Table 11. DIE delivery package options

Description Details

Wafer tested, inked, uncut;

see Figure 8: DIE delivery package options

Saw pickup and place subcontract required;

Wafer is between a double plastic shell, inside a plastic envelope sealed under vacuum;

Minimum number of wafers per box is approximately 5, weight is 1.5 kg.

Wafer tested, inked, cut on sticky foil on 7.5" plastic

ring; see Figure 8: DIE delivery package options

Suitable for automatic pickup and place machine for sticky foil. Wafer is held by a plastic ring protected by two carton shells, inside a plastic envelope sealed under vacuum.

Minimum number of wafers per box is approximately 5, weight is 2 kg.

Wafer tested, inked, cut and packaged in tape and

reel.See Figure 9: Carrier tape information and

Figure 10: Reel 7 INCH information .

Suitable for automatic pickup.

Figure 8. DIE delivery package options

Figure 9. Carrier tape information

'!0'2)

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18

DIE package options

GAPGRI00339

VNP8T

16/19

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VNP8T

Figure 10. Reel 7 INCH information

DIE package options

Tape Width (mm) A max N min W1 max. W2 max W3 Min/Max

60 7.9/10.9

16 180 60 16.4 22.4 15.9/19.4

GAPGRI00340

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Revision history

Date

14-Mar-2012

11-Sep-2012

14-Dec-2012

24-Jun-2013

18-Sep-2013

Revision

Table 12. Document revision history

Changes

1

2

3

4

5

Initial release

Updated test conditions in Table 8.

Updated Table 11 and added Figure 9 and 10.

Updated Figure 2: Pad configuration

Table 10: Protections :

– T jrs

: added footnote

Features :

– V clamp

: updated value

Table 4: Absolute maximum ratings :

– E

MAX

: added row

Table 5: Off-state :

– I

DSS

: added test conditions and value

Updated disclaimer.

VNP8T

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VNP8T

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