VNW100N04
"OMNIFET":
FULLY AUTOPROTECTED POWER MOSFET
Table 1. General Features
Type V clamp
VNW100N04 42 V
R
DS(on)
0.012
Ω
I lim
100 A
■ LINEAR CURRENT LIMITATION
■ THERMAL SHUT DOWN
■ SHORT CIRCUIT PROTECTION
■ INTEGRATED CLAMP
■ LOW CURRENT DRAWN FROM INPUT PIN
■ DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN
■ ESD PROTECTION
■ DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
■ COMPATIBLE WITH STANDARD POWER
MOSFET
■ STANDARD TO-247 PACKAGE
Figure 1. Package
TO-247
1
2
3
DESCRIPTION
The VNW100N04, is a monolithic device made using STMicroelectronics VIPower M0
Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications.
Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments.
Fault feedback can be detected by monitoring the voltage at the input pin.
Obsolete Product(s) - Obsolete Product(s)
Tube Tape and Reel
TO-247 VNW100N04 –
REV. 2
1/12 June 2004
VNW100N04
Figure 2. Block Diagram
Table 3. Absolute Maximum Ratings
Symbol Parameter
V
DS
V
IN
I
D
I
R
V esd
P tot
T j
T c
T stg
Drain-Source Voltage (V in
= 0)
Input Voltage
Drain Current
Reverse DC Output Current
Electrostatic Discharge (C = 100 pF, R =1.5 K
Ω
)
Total Dissipation at T c
= 25 °C
Operating Junction Temperature
Case Operating Temperature
Storage Temperature
Value
Internally Clamped
18
Internally Limited
–100
2000
208
Internally Limited
Internally Limited
-55 to 150
Table 4. Thermal Data
Symbol Parameter Value
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Unit
R thj-case
R thj-amb
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Max
Max
0.6
30
°C/W
°C/W
Unit
V
V
A
A
V
W
°C
°C
°C
2/12
VNW100N04
ELECTRICAL CHARACTERISTICS (T case
= 25°C unless otherwise specified)
Table 5. Off
Symbol
V
CLAMP
V
CLTH
Parameter
Drain-source Clamp Voltage
Drain-source Clamp Threshold
Voltage
V
INCL
I
DSS
I
ISS
Input-Source Reverse Clamp
Voltage
Zero Input Voltage
Drain Current (V in
= 0)
Supply Current from Input Pin
Test Conditions
I
D
= 50 A; V in
= 0
I
D
= 2 mA; V in
= 0
I in
= –1 mA
V
DS
= 13 V; V in
= 0
V
DS
= 25 V; V in
= 0
V
DS
= 0 V; V in
= 10 V
Min.
Typ.
Max.
36 42 48
35
–1
250
–0.3
50
200
500
Unit
V
V
V
µA
µA
µA
Table 6. On
(1)
Symbol Parameter Test Conditions
V
R
IN(th)
DS(on)
Input Threshold Voltage
Static Drain-source On
Resistance
V
DS
= V in
; I
D
+ I in
= 1 mA
V in
= 10 V; I
D
= 50 A
V in
= 5 V; I
D
= 50 A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Table 7. Dynamic
Symbol g fs
(2)
Parameter
Forward
Transconductance
Test Conditions
V
DS
= 13 V; I
D
= 50 A
C oss
Output Capacitance V
DS
Note: 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
= 13 V; f = 1 MHz; V in
= 0
Table 8. Switching
(3)
Symbol Parameter
Turn-on Delay Time t d(on) t r t d(off) t f
Rise Time
Turn-off Delay Time
Fall Time
Test Conditions
V
DD
= 15 V; I d
= 50 A;
V gen
= 10V; R gen
= 10
Ω
(see Figure 27)
Min.
Typ.
Max.
0.8
3
0.012
0.015
Unit
V
Ω
Ω
Min.
Typ.
Max.
40 60
Unit
S
2000 3000 pF
Min.
Typ.
Max.
110 250
500 900
1000 1800
600 1000
2.2
3.5
Unit ns ns ns ns
µs t d(off) t f
(di/dt) on
Fall Time
(see Figure 27)
Turn-on Current Slope V
DD
= 15 V; I
D
= 50 A
V in
= 10 V; R gen
= 10
Ω
Q i
Total Input Charge V
DD
= 15 V; I
Note: 3. Parameters guaranteed by design/characterization.
D
= 50 A; V in
= 10 V
22
12
55
190
30
18
µs
µs
A/µS nC
3/12
VNW100N04
ELECTRICAL CHARACTERISTICS (cont’d)
Table 9. Source Drain Diode
Symbol
V
SD
(4) t rr
(5)
Q rr
(5)
I
RRM
(5)
Parameter
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
I
SD
Test Conditions
= 50 A; V in
= 0
= 50 A; di/dt = 100 A/µs
V
DD
= 30 V; T j
= 25 °C
(see test circuit, Figure 29)
Note: 4. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
5. Parameters guaranteed by design/characterization.
Min.
Typ.
Max.
1.6
800
5
15
Unit
V ns
µC
A
Table 10. Protection
Symbol t
I lim dlim
(6)
Parameter
Drain Current Limit
Step Response Current Limit
Test Conditions
V in
= 10 V; V
DS
= 13 V
V in
= 5 V; V
DS
= 13 V
V in
= 10 V
V in
= 5 V
T jsh
(6)
T jrs
(6)
I gf
(6)
Overtemperature Shutdown
Overtemperature Reset
E as
(6)
Fault Sink Current
Single Pulse
Avalanche Energy
V in
= 10 V; V
DS
= 13 V
V in
= 5 V; V
DS
= 13 V starting T j
V in
= 25 °C; V
= 10 V; R
DD
= 20 V gen
= 1 K
Ω
; L = 10 mH
Note: 6. Parameters guaranteed by design/characterization.
Min.
Typ.
Max.
35
35
50
50
65
65
50
130
80
200
170
155
50
20
4
PROTECTION FEATURES
During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a
– OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (I iss
) flows into the Input pin in order to supply the internal circuitry.
element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 170°C. The device is automatically
The device integrates:
– OVERVOLTAGE CLAMP PROTECTION:
– STATUS FEEDBACK: In the case of an internally set at 42V, along with the rugged overtemperature fault condition, a Status avalanche characteristics of the Power
Feedback is provided through the Input pin. The
MOSFET stage give this device unrivalled ruggedness and energy handling capability.
Obsolete Product(s) - Obsolete Product(s) inductive loads.
internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω . The failure can be detected by monitoring the
– LINEAR CURRENT LIMITER CIRCUIT: limits voltage at the Input pin, which will be close to the drain current Id to Ilim whatever the Input pin ground potential.
voltage. When the current limiter is active, the
Additional features of this device are ESD device operates in the linear region, so power dissipation may exceed the capability of the restarted when the chip temperature falls below
155°C.
Obsolete Product(s) - Obsolete Product(s) heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, protection according to the Human Body model and the ability to be driven from a TTL Logic circuit
(with a small increase in R
DS(on)
).
junction temperature may reach the overtemperature threshold T jsh
.
Unit
A
A
µs
µs
°C
°C mA mA
J
4/12
Figure 3. Thermal Impedance Figure 4. Derating Curve
VNW100N04
Figure 5. Output Characteristics Figure 6. Transconductance
Figure 7. Static Drain-Source On Resistance vs
Input Voltage
Figure 8. Static Drain-Source On Resistance
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VNW100N04
Figure 9. Static Drain-Source On Resistance Figure 10. Input Charge vs Input Voltage
Figure 11. Capacitance Variations Figure 12. Normalized Input Threshold Voltage vs Temperature
Figure 13. Normalized On Resistance vs
Temperature
Figure 14. Normalized On Resistance vs
Temperature
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Figure 15. Turn-on Current Slope Figure 16. Turn-on Current Slope
VNW100N04
Figure 17. Turn-off Drain-Source Voltage Slope Figure 18. Turn-off Drain-Source Voltage Slope
Figure 19. Switching Time Resistive Load Figure 20. Switching Time Resistive Load
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VNW100N04
Figure 21. Switching Time Resistive Load Figure 22. Current Limit vs Junction
Temperature
Figure 23. Step Response Current Limit Figure 24. Source Drain Diode Forward
Characteristics
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Figure 25. Unclamped Inductive Load Test
Circuits
VNW100N04
Figure 26. Unclamped Inductive Waveforms
Figure 27. Switching Times Test Circuits For
Resistive Load
Figure 28. Input Charge Test Circuit
Figure 29. Test Circuit For Inductive Load
Switching And Diode Recovery Times
Figure 30. Waveforms
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VNW100N04
PACKAGE MECHANICAL
Table 11. TO-247 Mechanical Data
Symbol b2 c
D
E
A
A1 b b1 e
L
L1
L2
∅
P
∅
R
S
Package Weight
Min
4.85
2.20
1.0
2.0
3.0
0.40
19.85
15.45
14.20
3.70
3.55
4.50
Figure 31. TO-247 Package Dimensions millimeters
Typ
5.45
18.50
5.50
Gr. 4.43
Max
5.15
2.60
1.40
2.40
3.40
0.80
20.15
15.75
14.80
4.30
3.65
5.50
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P025P
Note: Drawing is not to scale.
10/12
REVISION HISTORY
Table 12. Revision History
Date Revision
September-1996
18-June-2004
1
2
Description of Changes
First Issue
Stylesheet update. No content change.
VNW100N04
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11/12
VNW100N04
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted Obsolete Product(s) - Obsolete Product(s) to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not Obsolete Product(s) - Obsolete Product(s)
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All other names are the property of their respective owners
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