SECTION 7 GENERAL-PURPOSE TIMER. NXP MC68331

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SECTION 7GENERAL-PURPOSE TIMER

This section is an overview of GPT function. Refer to the

GPT Reference Manual (GP-

TRM/AD) for complete information about the GPT module.

7.1 General

The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. A bus interface unit connects the GPT to the intermodule bus (IMB).

The capture/compare unit features three input capture channels, four output compare channels, and one channel that can be selected as an input capture or output compare channel. These channels share a 16-bit free-running counter which derives its clock from a nine-stage prescaler or from the external clock input signal, PCLK.

Pulse accumulator channel logic includes an 8-bit counter; the pulse accumulator can operate in either event counting mode or gated time accumulation mode.

Pulse-width modulator outputs are periodic waveforms whose duty cycles can be independently selected and modified by user software. The PWM circuits share a 16-bit free-running counter that can be clocked by the same nine-stage prescaler used by the capture/compare unit or by the PCLK input.

All GPT pins can also be used for general-purpose input/output. The input capture and output compare pins form a bidirectional 8-bit parallel port (PORTGP). PWM pins are outputs only. PAI and PCLK pins are inputs only.

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IC1/PGP0

IC2/PGP1

IC3/PGP2

CAPTURE/COMPARE UNIT

PULSE ACCUMULATOR

OC1/PGP3

OC2/OC1/PGP4

OC3/OC1/PGP5

OC4/OC1/PGP6

IC4/OC5/OC1/PGP7

PAI

PRESCALER PCLK

PWMA

PWMB

PWM UNIT

BUS INTERFACE

7

IMB

GPT BLOCK

Figure 7-1 GPT Block Diagram

7.2 GPT Registers and Address Map

The GPT programming model consists of a configuration register (GPTMCR), parallel

I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2,

TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL), pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,

PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1,

TMSK2). Functions of the module configuration register are discussed in 7.3 Special

Modes of Operation and 7.4 Polled and Interrupt-Driven Operation. Other register

functions are discussed in the appropriate sections.

All registers can be accessed using byte or word operations. Certain capture/compare registers and pulse-width modulation registers must be accessed by word operations to ensure coherency. If byte accesses are used to read a register such as the timer counter register (TCNT), there is a possibility that data in the byte not being accessed will change while the other byte is read. Both bytes must be accessed at the same time.

The modmap (MM) bit in the system integration module configuration register (SIM-

CR) defines the most significant bit (ADDR23) of the IMB address for each register in the MCU.

Refer to APPENDIX D REGISTER SUMMARY for a GPT address map and register

bit/field descriptions. SECTION 4 SYSTEM INTEGRATION MODULE contains more

information about how the state of MM affects the system.

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7.3 Special Modes of Operation

The GPT module configuration register (GPTMCR) module configuration register

(GPTMCR) is used to control special GPT operating modes. These include low-power stop mode, freeze mode, single-step mode, and test mode. Normal GPT operation can

be polled or interrupt-driven. Refer to 7.4 Polled and Interrupt-Driven Operation for

more information.

7.3.1 Low-Power Stop Mode

Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop mode the system clock to the module is turned off. The clock remains off until STOP is negated or a reset occurs. All counters and prescalers within the timer stop counting while the STOP bit is set. Only the module configuration register (GPTMCR) and the interrupt configuration register (ICR) should be accessed while in the stop mode. Accesses to other GPT registers cause unpredictable behavior. Low-power stop can also be used to disable module operation during debugging.

7.3.2 Freeze Mode

The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the

CPU enters background debugging mode. At the present time, FRZ1 has no effect;

setting FRZ0 causes the GPT to enter freeze mode. Refer to SECTION 5 CENTRAL

PROCESSING UNIT for more information on background debugging mode.

Freeze mode freezes the current state of the timer. The prescaler and the pulse accumulator do not increment and changes to the pins are ignored (input pin synchronizers are not clocked). All of the other timer functions that are controlled by the CPU will operate normally; for example, registers can be written to change pin directions, force output compares, and read or write I/O pins.

While the FREEZE signal is asserted, the CPU has write access to registers and bits that are normally read-only, or write-once. The write-once bits can be written to as often as needed. The prescaler and the pulse accumulator remain stopped and the input pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM), the FRZ0 bit is cleared, or the MCU is reset.

Activities that are in progress prior to FREEZE assertion are completed. For example, if an input edge on an input capture pin is detected just as the FREEZE signal is asserted, the capture occurs and the corresponding interrupt flag is set.

7.3.3 Single-Step Mode

Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP bit is asserted, the prescaler and the pulse accumulator stop counting and changes at input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP was set. After STOPP is set, the INCP bit can be set to increment the prescaler and clock the input synchronizers once. The INCP bit is self-negating after the prescaler is incremented. INCP can be set repeatedly. The INCP bit has no effect when the

STOPP bit is not set.

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7.3.4 Test Mode

Test mode is used during Freescale factory testing. The GPT has no dedicated testmode control register; all GPT testing is done under control of the system integration module.

7.4 Polled and Interrupt-Driven Operation

Normal GPT function can be polled or interrupt-driven. All GPT functions have an associated status flag and an associated interrupt. The timer interrupt flag registers

(TFLG1 and TFLG2) contain status flags used for polled and interrupt-driven operation. The timer mask registers (TMSK1 and TMSK2) contain interrupt control bits. Control routines can monitor GPT operation by polling the status registers. When an event occurs, the control routine transfers control to a service routine that handles that event.

If interrupts are enabled for an event, the GPT requests interrupt service when the event occurs. Using interrupts does not require continuously polling the status flags to see if an event has taken place. However, status flags must be cleared after an interrupt is serviced, in order to disable the interrupt request.

7.4.1 Polled Operation

When an event occurs in the GPT, that event sets a status flag in TFLG1 or TFLG2.

The GPT sets the flags; they cannot be set by the CPU. TFLG1 and TFLG2 are 8-bit registers that can be accessed individually or as one 16-bit register. The registers are

initialized to zero at reset. Table 7-1 shows status flag assignment.

Table 7-1 GPT Status Flags

Flag

Mnemonic

IC1F

IC2F

IC3F

OC1F

OC2F

OC3F

OC4F

I4/O5F

TOF

PAOVF

PAIF

Register

Assignment

TFLG1

TFLG1

TFLG1

TFLG1

TFLG1

TFLG1

TFLG1

TFLG1

TFLG2

TFLG2

TFLG2

Source

Input Capture 1

Input Capture 2

Input Capture 3

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Input Capture 4/Output Compare 5

Timer Overflow

Pulse Accumulator Overflow

Pulse Accumulator Input

For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2 in the same bit position. If a mask bit is set and an associated event occurs, a hardware interrupt request is generated.

To re-enable a status flag after an event occurs, the status flags must be cleared. Status registers are cleared in a particular sequence. The register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared.

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7.4.2 GPT Interrupts

The GPT has 11 internal sources that can cause it to request interrupt service (refer

to Table 7-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources.

TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one

16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and

TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position.

TMSK2 also controls the operation of the timer prescaler. Refer to 7.7 Prescaler for

more information.

The value of the interrupt level (IRL) field in the interrupt control register (ICR) determines the priority of GPT interrupt requests. IRL values correspond to MCU interrupt request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request signal; IRQ1 is the lowest-priority signal. A value of %111 causes IRQ7 to be asserted when a GPT interrupt request is made; lower field values cause corresponding lower-priority interrupt request signals to be asserted. Setting field value to %000 disables interrupts.

Table 7-2 GPT Interrupt Sources

Name

—

IC1

IC2

IC3

OC1

OC2

OC3

OC4

IC4/OC5

TO

PAOV

PAI

Source

Number

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

Source

Adjusted Channel

Input Capture 1

Input Capture 2

Input Capture 3

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Input Capture 4/Output Compare 5

Timer Overflow

Pulse Accumulator Overflow

Pulse Accumulator Input

Vector

Number

IVBA : 0000

IVBA : 0001

IVBA : 0010

IVBA : 0011

IVBA : 0100

IVBA : 0101

IVBA : 0110

IVBA : 0111

IVBA : 1000

IVBA : 1001

IVBA : 1010

IVBA : 1011

The CPU32 recognizes only interrupt request signals of a priority greater than the status register interrupt priority (IP) mask value. When the CPU acknowledges an interrupt request, the priority of the acknowledged request is written to the IP mask and driven out on the IMB address lines.

When the IP mask value driven out on the address lines is the same as the IRL value, the GPT contends for arbitration priority. GPT arbitration priority is determined by the value of the IARB field in GPTMCR. Each MCU module that can make interrupt requests must be assigned a nonzero IARB value in order to implement an arbitration scheme. Arbitration is performed by means of serial assertion of IARB field bit values.

When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge cycle by placing an interrupt vector number on the data bus. The vector number is used to calculate displacement into the CPU32 exception vector table. Vector numbers are formed by concatenating the value in the ICR IVBA field with a 4-bit value supplied by the GPT when an interrupt request is made. Hardware prevents the vector number from changing while it is being driven out on the IMB. Vector number assign-

ment is shown in Table 7-2.

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At reset, IVBA is initialized to $0. To enable interrupt-driven timer operation, the upper nibble ($4–$F) of a user-defined vector number ($40–$FF) must be written to IVBA, and interrupt handler routines must be located at the addresses pointed to by the corresponding vector. Note that IVBA must be written before GPT interrupts are enabled, or the GPT could supply a vector number ($00 to $0F) that corresponds to an assigned or reserved exception vector.

The internal GPT interrupt priority hierarchy is shown in Table 7-2. The lower the in-

terrupt source number, the higher the priority. A single GPT interrupt source can be given priority over all other GPT interrupt sources by assigning the priority adjust field

(PAB) in the ICR a value equal to its source number.

Interrupt requests are asserted until associated status flags are cleared. Status flags must be cleared in a particular sequence. The status register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared.

Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-

TEGRATION MODULE for more information about exceptions and interrupts.

7.5 Pin Descriptions

The GPT uses 12 pins. Each pin can perform more than one function. Descriptions of

GPT pins divided into functional groups follow.

7.5.1 Input Capture Pins (IC[1:3])

Each of these pins is associated with a single GPT input capture function. Each pin has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. Each pin has an associated 16-bit capture register that holds the captured counter value. These pins can also be used

for general-purpose I/O. Refer to 7.8.2 Input Capture Functions for more informa-

tion.

7.5.2 Input Capture/Output Compare Pin (IC4/OC5)

This pin can be configured for use by either an input capture or an output compare function. It has an associated 16-bit register that is used for holding either the input capture value or the output match value. When used for input capture the pin has the same hysteresis as other input capture pins. The pin can be used for general-purpose

I/O. Refer to 7.8.2 Input Capture Functions and 7.8.3 Output Compare Functions

for more information.

7.5.3 Output Compare Pins (OC[1:4])

These pins are used for GPT output compare functions. Each pin has an associated

16-bit compare register and a 16-bit comparator. Pins OC2, OC3, and OC4 are associated with a specific output compare function. The OC1 function can affect the output of all compare pins. If the OC1 pin is not needed for an output compare function it can

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be used to output the clock selected for the timer counter register. Any of these pins

can also be used for general-purpose I/O. Refer to 7.8.3 Output Compare Functions

for more information.

7.5.4 Pulse Accumulator Input Pin (PAI)

The PAI pin connects a discrete signal to the pulse accumulator for timed or gated pulse accumulation. PAI has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. It can

be used as a general-purpose input pin. Refer to 7.10 Pulse Accumulator for more

information.

7.5.5 Pulse-Width Modulation (PWMA, PWMB)

PWMA and PWMB pins carry pulse-width modulator outputs. The modulators can be programmed to generate a periodic waveform of variable frequency and duty cycle.

PWMA can be used to output the clock selected as the input to the PWM counter.

These pins can also be used for general-purpose output. Refer to 7.11 Pulse-Width

Modulation Unit for more information.

7.5.6 Auxiliary Timer Clock Input (PCLK)

PCLK connects an external clock to the GPT. The external clock can be used as the clock source for the capture/compare unit or the PWM unit in place of one of the prescaler outputs. PCLK has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. This pin

can also be used as a general-purpose input pin. Refer to 7.7 Prescaler for more in-

formation.

7.6 General-Purpose I/O

Any GPT pin can be used for general-purpose I/O when it is not used for another purpose. Capture/compare pins are bidirectional, others can be used only for output or input. I/O direction is controlled by a data direction bit in the port GP data direction register (DDRGP).

Parallel data is read from and written to the port GP data register (PORTGP). Pin data can be read even when pins are configured for a timer function. Data read from PORT-

GP always reflects the state of the external pin, while data written to PORTGP may not always affect the external pin.

Data written to PORTGP does not immediately affect pins used for output compare functions, but the data is latched. When an output compare function is disabled, the last data written to PORTGP is driven out on the associated pin if it is configured as an output. Data written to PORTGP can cause input captures if the corresponding pin is configured for input capture function.

The pulse accumulator input (PAI and the external clock input (PCLK) pins provide general-purpose input. The state of these pins can be read by accessing the PAIS and

PCLKS bits in the pulse accumulator control register (PACTL).

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Pulse-width modulation A and B (PWMA/PWMB) output pins can serve as generalpurpose outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in the compare force (CFORC) and PWM control (PWMC) registers, respectively, control their operation.

7.7 Prescaler

Capture/compare and PWM units have independent 16-bit free-running counters as a main timing component. These counters derive their clocks from the prescaler or from

the PCLK input. Figure 7-2 is a prescaler block diagram.

In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are provided. Connected to these outputs are two multiplexers, one for the capture/compare unit, the other for the PWM unit.

Multiplexers can each select one of seven prescaler taps or an external input from the

PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0] in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter

(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC).

After reset, the GPT is configured to use system clock divided by four for TCNT and system clock divided by two for PWMCNT. Initialization software can change the division factor. The PPR bits can be written at any time but the CPR bits can only be written once after reset unless the GPT is in test or freeze mode.

The prescaler can be read at any time. In freeze mode the prescaler can also be written. Word accesses must be used to ensure coherency. If coherency is not needed byte accesses can be used. The prescaler value is contained in bits [8:0] while bits

[15:9] are unimplemented and are read as zeros.

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SYSTEM CLOCK

DIVIDER

÷

512

EXT.

TO PULSE ACCUMULATOR

TO PULSE ACCUMULATOR

TO PULSE ACCUMULATOR

CPR2 CPR1 CPR0

÷

256

÷

128

÷

64

÷

32

÷

16

÷

8

÷

4

EXT.

SELECT

TO CAPTURE/

COMPARE

TIMER

PCLK

PIN

÷

128

÷

64

÷

32

÷

16

÷

8

÷

4

÷

2

EXT.

SELECT

TO

PWM UNIT

SYNCHRONIZER AND

DIGITAL FILTER

PPR2 PPR1 PPR0

Figure 7-2 Prescaler Block Diagram

GPT PRESCALER BLOCK

Multiplexer outputs (including the PCLK signal) can be connected to external pins) can be connected to external pins. The CPROUT bit in the TMSK2 register configures the

OC1 pin to output the TCNT clock and the PPROUT bit in the PWMC register configures the PWMA pin to output the PWMC clock. CPROUT and PPROUT can be written at any time. Clock signals on OC1 and PWMA do not have a 50% duty cycle. They have the period of the selected clock but are high for only one system clock time.

The prescaler also supplies three clock signals to the pulse accumulator clock select mux. These are the system clock divided by 512, the external clock signal from the

PCLK pin and the capture/compare clock signal.

7.8 Capture/Compare Unit

The capture/compare unit contains the timer counter (TCNT), the input capture (IC)

functions and the output compare (OC) functions. Figure 7-3 is a block diagram of the

capture/compare unit.

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PCLK

SYSTEM

CLOCK

7-10

PRESCALER–DIVIDE BY

4, 8, 16, 32, 64, 128, OR 256

1 OF 8 SELECT

CPR2 CPR1 CPR0

16-BIT TIMER BUS

TFLG1

IC1F

TCNT (HI) TCNT (LO)

16-BIT FREE-RUNNING

COUNTER

TOI

TOF

TMSK1

IC1I

9

INTERRUPT

REQUESTS

1

BIT-0

PIN

FUNCTIONS

PGP0

IC1

16-BIT LATCH CLK

TIC1 (HI) TIC1 (LO)

IC2I

2

16-BIT LATCH CLK

TIC2 (HI) TIC2 (LO)

IC2F

BIT-1

PGP1

IC2

IC3I

3

16-BIT LATCH CLK

TIC3 (HI) TIC3 (LO)

IC3F

BIT-2

PGP2

IC3

OC1I

4

CFORC

16-BIT COMPARATOR =

TOC1 (HI) TOC1 (LO)

OC1F

FOC1

BIT-3

PGP3

OC1

OC2I

5

16-BIT COMPARATOR =

TOC2 (HI) TOC2 (LO)

OC2F

FOC2

BIT-4

PGP4

OC2/

OC1

OC3I

6

16-BIT COMPARATOR =

TOC3 (HI) TOC3 (LO)

OC3F

FOC3

BIT-5

PGP5

OC3/

OC1

OC4I

7

16-BIT COMPARATOR =

TOC4 (HI) TOC4 (LO)

OC4F

FOC4

BIT-6

PGP6

OC4/

OC1

I4/O5I

8

16-BIT COMPARATOR =

TI4/O5 (HI) TI4/O5 (LO)

16-BIT LATCH CLK

OC5

I4/O5F

IC4

I4/O5

STATUS

FLAGS

FOC5

FORCE

OUTPUT

COMPARE

INTERRUPT

ENABLES

BIT-7

PGP7

IC4/

OC5/

OC1

PARALLEL

PORT PIN

CONTROL

16/32 CC BLOCK

Figure 7-3 Capture/Compare Unit Block Diagram

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7.8.1 Timer Counter

The timer counter (TCNT) is the key timing component in the capture/compare unit.

The timer counter is a 16-bit free-running counter that starts counting after the processor comes out of reset. The counter cannot be stopped during normal operation. After reset, the GPT is configured to use the system clock divided by four as the input to the counter. The prescaler divides the system clock and provides selectable input frequencies. User software can configure the system to use one of seven prescaler outputs or an external clock.

The counter can be read any time without affecting its value. Because the GPT is interfaced to the IMB and the IMB supports a 16-bit bus, a word read gives a coherent value. If coherency is not needed, byte accesses can be made. The counter is set to

$0000 during reset and is normally a read-only register. In test mode and freeze mode, any value can be written to the timer counter.

When the counter rolls over from $FFFF to $0000, the timer overflow flag (TOF) in timer interrupt flag register 2 (TFLG2) is set. An interrupt can be enabled by setting the corresponding interrupt enable bit (TOI) in timer interrupt mask register 2 (TMSK2).

Refer to 7.4.2 GPT Interrupts for more information.

7.8.2 Input Capture Functions

All GPT input capture functions use the same 16-bit timer counter (TCNT). Each input capture pin has a dedicated 16-bit latch and input edge-detection/selection logic. Each input capture function has an associated status flag, and can cause the GPT to make an interrupt service request.

When a selected edge transition occurs on an input capture pin, the associated 16-bit latch captures the content of TCNT and sets the appropriate status flag. An interrupt request can be generated when the transition is detected.

Edge-detection logic consists of control bits that enable edge detection and select a transition to detect. The EDGxA and EDGxB bits in timer control register 2 (TCTL2) determine whether the input capture functions detect rising edges only, falling edges only, or both rising and falling edges. Clearing both bits disables the input capture function. Input capture functions operate independently of each other and can capture the same TCNT value if individual input edges are detected within the same timer count cycle.

Input capture interrupt logic includes a status flag, which indicates that an edge has been detected, and an interrupt enable bit. An input capture event sets the ICxF bit in the timer interrupt flag register 1 (TFLG1) and causes the GPT to make an interrupt request if the corresponding ICxI bit is set in the timer interrupt mask register 1

(TMSK1). If the ICxI bit cleared, software must poll the status flag to determine that an

event has occurred. Refer to 7.4 Polled and Interrupt-Driven Operation for more in-

formation.

Input capture events are generally asynchronous to the timer counter. Because of this, input capture signals are conditioned by a synchronizer and digital filter. Events are

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synchronized with the system clock so that latching of TCNT content and counter incrementation occur on opposite half-cycles of the system clock. Inputs have hysteresis. Capture of any transition longer than two system clocks is guaranteed; any transition shorter than one system clock has no effect.

Figure 7-4 shows the relationship of system clock to synchronizer output. The value

latched into the capture register is the value of the counter several system clock cycles after the transition that triggers the edge detection logic. There can be up to one clock cycle of uncertainty in latching of the input transition. Maximum time is determined by the system clock frequency.

The input capture register is a 16-bit register. A word access is required to ensure coherency. If coherency is not required, byte accesses can be used to read the register.

Input capture registers can be read at any time without affecting their values.

7

F

SYS

(PH1)

CAPTURE/COMPARE

CLOCK

TCNT

EXTERNAL PIN

SYNCHRONIZER

OUTPUT

CAPTURE REGISTER

$0101 $0102

$0102

ICF FLAG

1153A

Figure 7-4 Input Capture Timing Example

7-12

An input capture occurs every time a selected edge is detected, even when the input capture status flag is set. This means that the value read from the input capture register corresponds to the most recent edge detected, which may not be the edge that caused the status flag to be set.

7.8.3 Output Compare Functions

Each GPT output compare pin has an associated 16-bit compare register and a 16-bit comparator. Each output compare function has an associated status flag, and can cause the GPT to make an interrupt service request. Output compare logic is designed to prevent false compares during data transition times.

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When the programmed content of an output compare register matches the value in

TCNT, an output compare status flag (OCxF) bit in TFLG1 is set. If the appropriate interrupt enable bit (OCxI) in TMSK1 is set, an interrupt request is made when a match

occurs. Refer to 7.4.2 GPT Interrupts for more information.

Operation of output compare 1 differs from that of the other output compare functions.

OC1 control logic can be programmed to make state changes on other OC pins when an OC1 match occurs. Control bits in the timer compare force register (CFORC) allow for early forced compares.

7.8.3.1 Output Compare 1

Output compare 1 can affect any or all of OC[1:5] when an output match occurs. In addition to allowing generation of multiple control signals from a single comparison operation, this function makes it possible for two or more output compare functions to control the state of a single OC pin. Output pulses as short as one timer count can be generated in this way.

The OC1 action mask register (OC1M) and the OC1 action data register (OC1D) control OC1 function. Setting a bit in OC1M selects a corresponding bit in the GPT parallel data port. Bits in OC1D determine whether selected bits are to be set or cleared when an OC1 match occurs. Pins must be configured as outputs in order for the data in the register to be driven out on the corresponding pin. If an OC1 match and another output match occur at the same time and both attempt to alter the same pin, the OC1 function controls the state of the pin.

7.8.3.2 Forced Output Compare

Timer compare force register (CFORC) is used to make forced compares. The action taken as a result of a forced compare is the same as when an output compare match occurs, except that status flags are not set. Forced channels take programmed actions immediately after the write to CFORC.

The CFORC register is implemented as the upper byte of a 16-bit register which also contains the PWM control register C (PWMC). It can be accessed as eight bits or a word access can be used. Reads of force compare bits (FOC) have no meaning and always return zeros. These bits are self-negating.

7.9 Input Capture 4/Output Compare 5

The IC4/OC5 pin can be used for input capture, output compare, or general-purpose

I/O. A function enable bit (I4/O5) in the pulse accumulator control register (PACTL) configures the pin for input capture (IC4) or output compare function (OC5). Both bits are cleared during reset, configuring the pin as an input, but also enabling the OC5 function. IC4/OC5 I/O functions are controlled by the I4/O5 bit in the port GP data direction register (DDRGP).

The 16-bit register (TI4/O5) used with the IC4/OC5 function acts as an input capture register or as an output compare register depending on which function is selected.

When used as the input capture 4 register, it cannot be written except in test or freeze mode.

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7.10 Pulse Accumulator

The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can

operate in external event counting or gated time accumulation modes. Figure 7-5 is a

block diagram of the pulse accumulator.

In event counting mode, the counter increments each time a selected transition of the pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the system clock divided by four.

In gated time accumulation mode a clock increments PACNT while the PAI pin is in the active state. There are four possible clock sources.

Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has rolled over from $FF to $00. This can be used to extend the range of the counter beyond eight bits.

An interrupt request can be made when each of the status flags is set. However, operation of the PAI interrupt depends on operating mode. In event counting mode, an interrupt is requested when the edge being counted is detected. In gated mode, the request is made when the PAI input changes from active to inactive state. Interrupt requests are enabled by the PAOVI and PAII bits in the TMSK2 register.

Bits in the pulse accumulator control register (PACTL) control the operation of PACNT.

The PAMOD bit selects event counting or gated operation. In event counting mode, the PEDGE control bit determines whether a rising or falling edge is detected; in gated mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the clock source used in gated mode.

PACTL and PACNT are implemented as one 16-bit register, but can be accessed with byte or word access cycles. Both registers are cleared at reset, but the PAIS and

PCLKS bits show the state of the PAI and PCLK pins.

The PAI pin can also be used for general-purpose input. The logic state of the PAIS bit in PACTL shows the state of the pin.

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10

INTERRUPT

REQUESTS

11

TMSK2 TFLG2

PAI

SYNCHRONIZER

&

DIGITAL FILTER

EDGE

DETECT

LOGIC

2:1

MUX

OVERFLOW

PACNT

8-BIT COUNTER

ENABLE

PACTL

INTERNAL

DATA BUS

PCLK

TCNT OVERFLOW

CAPTURE/COMPARE CLK

PRESCALER

÷

512

MUX

16/32 PLS ACC BLOCK

Figure 7-5 Pulse Accumulator Block Diagram

7.11 Pulse-Width Modulation Unit

The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB.

A single clock output from the prescaler multiplexer drives a 16-bit counter that is used

to control both channels. Figure 7-6 is a block diagram of the pulse-width modulation

unit.

The PWM unit has two operational modes. Fast mode uses a clocking rate equal to 1/

256 of the prescaler output rate; slow mode uses a rate equal to 1/32768 of the prescaler output rate. The duty cycle ratios of the two PWM channels can be individually controlled by software. The PWMA pin can also output the clock that drives the PWM counter. PWM pins can also be used as output pins.

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16-BIT DATA BUS

PWMA REGISTER PWMB REGISTER

7

PWMA

PIN

F1A

BIT

R

LATCH

S

ZERO DETECTOR

PWMBUFA REGISTER PWMBUFB REGISTER

COMPARATOR A COMPARATOR B

R

LATCH

S

ZERO DETECTOR

PWMB

PIN

F1B

BIT

SFA

BIT

MULTIPLEXER A MULTIPLEXER B

SFB

BIT

16-BIT COUNTER

16-BIT TIMER BUS

FROM

PRESCALER

16/32 PWM BLOCK

Figure 7-6 PWM Block Diagram

7.11.1 PWM Counter

The 16-bit counter in the PWM unit is similar to the timer counter in the capture/compare unit. During reset, the GPT is configured to use the system clock divided by two to drive the counter. Initialization software can reconfigure the counter to use one of seven prescaler outputs or an external clock input from the PCLK pin.

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The PWM count register (PWMCNT) can be read at any time without affecting its value. A read must be a word access to ensure coherence, but byte accesses can be made if coherence is not needed. The counter is cleared to $0000 during reset and is a read-only register except in freeze or test mode.

Fifteen of the sixteen counter bits are output to multiplexers A and B. The multiplexers provide the fast and slow modes of the PWM unit. Mode for PWMA is selected by the

SFA bit in the PWM control register C (PWMC). Mode for PWMB is selected by the

SFB bit in the same register.

PWMA, PWMB, and PPR[2:0] bits in PWMC control PWM output frequency. In fast mode, bits [7:0] of PWMCNT are used to clock the PWM logic; in slow mode, bits [14:7] are used. The period of a PWM output in is 128 times longer than the fast mode period.

Table 7-3 shows a range of PWM output frequencies using a 16.78-MHz system clock

and 20.97-MHz system clock.

Table 7-3 PWM Frequency Ranges

Using 16.78-MHz/20.97-MHz System Clocks

PPR Prescaler Tap

[2:0] 16.78 MHz

20.97 MHz

000 Div 2 = 8.39 MHz Div 2 = 10.5 MHz

001 Div 4 = 4.19 MHz Div 4 = 5.25 MHz

SFA/B = 0

16.78 MHz

32.8 kHz

16.4 kHz

20.97 MHz

41 kHz

20.5 kHz

010 Div 8 = 2.10 MHz Div 8 = 2.62 MHz 8.19 kHz

011 Div 16 = 1.05 MHz Div 16 = 1.31 MHz 4.09 kHz

100 Div 32 = 524 kHz Div 32 = 655 kHz

101 Div 64 = 262 kHz Div 64 = 328 kHz

2.05 kHz

1.02 kHz

110 Div 128 = 131 kHz Div 128 = 164 kHz

111 PCLK PCLK

512 Hz

PCLK/256

10.2 kHz

5.15 kHz

2.56 kHz

1.28 kHz

SFA/B = 1

16.78 MHz 20.97 MHz

256 Hz 320 Hz

128 Hz

64.0 Hz

32.0 Hz

16.0 Hz

8.0 Hz

160 Hz

80.0 Hz

40.0 Hz

20.0 Hz

10.0 Hz

641 Hz 4.0 Hz 5.0 Hz

PCLK/256 PCLK/32768 PCLK/32768

7.11.2 PWM Function

The pulse width values of the PWM outputs are determined by control registers PWMA and PWMB. PWMA and PWMB are 8-bit registers implemented as two bytes of a 16bit register. PWMA and PWMB can be accessed as separate bytes or as one 16-bit register. A value of $00 loaded into either register causes the corresponding output pin to output a continuous logic level zero signal. A value of $80 causes the corresponding output signal to have a 50% duty cycle, and so on, to the maximum value of $FF, which corresponds to an output which is at logic level one for 255/256 of the cycle.

Setting the F1A (for PWMA) or F1B (for PWMB) bits in the register causes the corresponding pin to output a continuous logic level one signal. The logic level of the associated pin does not change until the end of the current cycle. F1A and F1B are the lower two bits of CFORC, but can be accessed at the same word address as PWMC.

Data written to PWMA and PWMB is not used until the end of a complete cycle. This prevents spurious short or long pulses when register values are changed. The current duty cycle value is stored in the appropriate PWM buffer register (PWMBUFA or PW-

MBUFB). The new value is transferred from the PWM register to the buffer register at the end of the current cycle.

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Registers PWMA, PWMB, and PWMC are reset to $00 during reset. These registers may be written or read at any time. PWMC is implemented as the lower byte of a 16bit register. The upper byte is the CFORC register. The buffer registers, PWMBUFA and PWMBUFB, are read-only at all times and may be accessed as separate bytes or as one 16-bit register.

Pins PWMA and PWMB can also be used for general-purpose output. The values of the F1A and F1B bits in PWMC are driven out on the corresponding PWM pins when normal PWM operation is disabled. When read, the F1A and F1B bits reflect the states of the PWMA and PWMB pins.

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