APPENDIX D REGISTER SUMMARY. NXP MC68331

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APPENDIX D REGISTER SUMMARY

This appendix contains address maps, register diagrams, and bit/field definitions for the MCU. More detailed information about register function is provided in the appropriate sections of the manual.

Except for central processing unit resources, information is presented in the intermod-

ule bus address order shown in Table D-1.

Table D-1 Module Address Map

Module

GPT

SIM

QSM

Size (Bytes)

128

512

Base Address

$YFF900

$YFFA00

$YFFC00

Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM configuration register

(SIMCR) determines where the control registers block is located in the system memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when

MM = 1, register addresses range from $FFF000 to $FFFFFF.

In the module memory maps in this appendix, the “Access” column specifies which registers are accessible at the supervisor privilege level only and which registers can be assigned to either the supervisor or user privilege level.

D.1 Central Processing Unit

CPU32 registers are not part of the module address map. The following diagram is a functional representation of CPU resources.

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D.1.1 CPU32 Register Model

16 15

8 7

DATA REGISTERS

ADDRESS REGISTERS

A7 (USP) USER STACK POINTER

PC PROGRAM COUNTER

CCR CONDITION CODE REGISTER

Figure D-1 User Programming Model

D-2

16 15

15 8 7

(CCR)

A7 (SSP) SUPERVISOR STACK POINTER

SR STATUS REGISTER

VBR VECTOR BASE REGISTER

2 0

SFC

DFC

ALTERNATE FUNCTION

CODE REGISTERS

Figure D-2 Supervisor Programming Model Supplement

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D.1.2 — Status Register

T[1:0]

RESET:

0 0

The status register (SR) contains condition codes, an interrupt priority mask, and three control bits. The condition codes are contained in the condition code register (CCR), the lower byte of the SR. (The lower and upper bytes of the status register are also referred to as the user and system bytes, respectively.) At the user privilege level, only the CCR is available. At the supervisor level, software can access the full status register.

T[1:0] — Trace Enable

00 = No tracing

01 = Trace on change of flow

10 = Trace on instruction execution

11 = Undefined; reserved

S — Supervisor/User State

0 = CPU operates at user privilege level

1 = CPU operates at supervisor privilege level

IP[2:0] — Interrupt Priority Mask

The priority value in this field (0 to 7) is used to mask interrupts.

X — Extend Flag

Used in multiple-precision arithmetic operations. In many instructions it is set to the same value as the C bit.

N — Negative Flag

Set when the MSB of a result register is set.

Z — Zero Flag

Set when all bits of a result register are zero.

V — Overflow Flag

Set when two's complement overflow occurs as the result of an operation.

C — Carry Flag

Set when a carry or borrow occurs during an arithmetic operation. Also used during shift and rotate instructions to facilitate multiple word operations.

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D.2 General-Purpose Timer

Table D-2 displays the GPT address map. The column labeled “Access” indicates the

privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required: a designation of “S/U” indicates that the register can be programmed to the desired privilege level.

Table D-2 GPT Address Map

S/U

Access

S/U

Address 15 8 7

$YFF900 GPT MODULE CONFIGURATION (GPTMCR)

$YFF902

$YFF904

(RESERVED FOR TEST)

INTERRUPT CONFIGURATION (ICR)

$YFF906 PGP DATA DIRECTION (DDRGP)

$YFF908 OC1 ACTION MASK (OC1M)

$YFF90A

$YFF90C

PGP DATA (PORTGP)

OC1 ACTION DATA (OC1D)

TIMER COUNTER (TCNT)

PA CONTROL (PACTL) PA COUNTER (PACNT)

$YFF90E

$YFF910

$YFF912

$YFF914

$YFF916

$YFF918

$YFF91A

$YFF91C

INPUT CAPTURE 1 (TIC1)

INPUT CAPTURE 2 (TIC2)

INPUT CAPTURE 3 (TIC3)

OUTPUT COMPARE 1 (TOC1)

OUTPUT COMPARE 2 (TOC2)

OUTPUT COMPARE 3 (TOC3)

OUTPUT COMPARE 4 (TOC4)

INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)

$YFF91E

$YFF920

$YFF922

$YFF924

$YFF926

$YFF928

$YFF92A

$YFF92C

$YFF92E –

$YFF93F

TIMER CONTROL 1 (TCTL1)

TIMER MASK 1 (TMSK1)

TIMER FLAG 1 (TFLG1)

FORCE COMPARE (CFORC)

TIMER CONTROL 2 (TCTL2)

TIMER MASK 2 (TMSK2)

TIMER FLAG 2 (TFLG2)

PWM CONTROL C (PWMC)

PWM CONTROL A (PWMA) PWM CONTROL B (PWMB)

PWM COUNT (PWMCNT)

PWMA BUFFER (PWMBUFA) PWMB BUFFER (PWMBUFB)

GPT PRESCALER (PRESCL)

NOT USED

Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.

D.2.1 GPTMCR — GPT Module Configuration Register

$YFF900

15 14 13 12 11

STOP FRZ1 FRZ0 STOPP INCP

RESET:

0 0 0 0 0

SUPV

GPTMCR bits control freeze, low-power stop, and single-step modes.

STOP — Stop Clocks

0 = Internal clocks not shut down

1 = Internal clocks shut down

IARB

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FRZ[1:0] — FREEZE Response

FRZ1 is not used; FRZ0 encoding determines response to the IMB FREEZE signal.

0 = Ignore IMB FREEZE signal

1 = Freeze the current state of the GPT

STOPP — Stop Prescaler

0 =Normal operation

1 =Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins.

INCP — Increment Prescaler

0 =Has no meaning

1 =If STOPP is asserted, increment prescaler once and clock input synchronizers once.

SUPV — Supervisor/Unrestricted Data Space

0 =Registers with access controlled by the SUPV bit are accessible from either the user or supervisor privilege level.

1 =Registers with access controlled by the SUPV bit are restricted to supervisor access only.

IARB[3:0] — Interrupt Arbitration

Each module that generates interrupts must have an IARB value. IARB values are used to arbitrate between interrupt requests of the same priority.

D.2.2 GPTMTR — GPT Module Test Register (Reserved)

$YFF902

This address is currently unused and returns zeros when read. It is reserved for GPT factory test.

D.2.3 ICR — GPT Interrupt Configuration Register

$YFF904

RESET:

IPA

IPL

0 0

IVBA

ICR fields determine internal and external interrupt priority, and provide the upper nibble of the interrupt vector number supplied to the CPU when an interrupt is acknowledged.

IPA — Interrupt Priority Adjust

Specifies which of the 11 internal GPT interrupt sources is assigned highest priority.

IPL — Interrupt Priority Level

Specifies the priority level of GPT interrupt requests.

IVBA — Interrupt Vector Base Address

Contains the most significant nibble of interrupt vector numbers supplied by the GPT.

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D.2.4 DDRGP — Port GP Data Direction Register

PORTGP — Port GP Data Register

$YFF906

$YFF907

15 8 7 0

DDRGP PORTGP

RESET:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and PORTGP holds the 8-bit data.

DDRGP[7:0] — Parallel Data Direction Register

0 = Input only

1 = Output

PORTGP[7:0] — Parallel Data Register

D.2.5 OC1M— OC1 Action Mask Register

OC1D — OC1 Action Data Register

$YFF908

$YFF909

OC1M

11 10

OC1D

3 2

RESET:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which pins are affected. OC1D determines what outputs are affected.

OC1M[5:1] — OC1 Mask

0 = Corresponding output compare pin is not affected by OC1 compare.

1 = Corresponding output compare pin is affected by OC1 compare.

OC1M[5:1] correspond to OC[5:1].

OC1D[5:1] — OC1 Data

0 =If OC1 mask bit is set, clear corresponding output compare pin on OC1 match.

1 =If OC1 mask bit is set, set corresponding output compare pin on OC1 match.

OC1D[5:1] correspond to OC[5:1].

D.2.6 TCNT — Timer Counter Register $YFF90A

TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the GPT module.

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D.2.7 PACTL — Pulse Accumulator Control Register

PACNT — Pulse Accumulator Counter

$YFF90C

$YFF90D

PAIS

RESET:

14 13 12 11 10

PAEN PAMOD PEDGE PCLKS I4/O5

0 0 0 U 0

PACLK

0 0

0 0 0 0

PACNT

0 0 0

PACTL enables the pulse accumulator and selects either event counting or gated mode. In event counting mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an internal clock.

PAIS — PAI Pin State (Read Only)

PAEN — Pulse Accumulator Enable

0 = Pulse accumulator disabled

1 = Pulse accumulator enabled

PAMOD — Pulse Accumulator Mode

0 = External event counting

1 = Gated time accumulation

PEDGE — Pulse Accumulator Edge Control

The effects of PEDGE and PAMOD are shown in the following table.

PAMOD

PCLKS — PCLK Pin State (Read Only)

PEDGE

Effect

PAI Falling Edge Increments Counter

PAI Rising Edge Increments Counter

Zero on PAI Inhibits Counting

One on PAI Inhibits Counting

I4/O5 — Input Capture 4/Output Compare 5

0 = Output compare 5 enabled

1 = Input capture 4 enabled

PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)

PACLK[1:0]

Pulse Accumulator Clock Selected

System Clock Divided by 512

Same Clock Used to Increment TCNT

TOF Flag from TCNT

External Clock, PCLK

PACNT — Pulse Accumulator Counter

Eight-bit read/write counter used for external event counting or gated time accumulation.

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D.2.8 TIC[1:3] — Input Capture Registers 1–3

$YFF90E–$YFF912

The input capture registers are 16-bit read-only registers used to latch the value of

TCNT when a specified transition is detected on the corresponding input capture pin.

They are reset to $FFFF.

D.2.9 TOC[1:4] — Output Compare Registers 1–4 $YFF914–$YFF91A

The 16-bit read/write output compare registers can be used as output waveform controls or as elapsed time indicators. For output compare functions, they are written to a desired match value and compared against TCNT to control specified pin actions.

They are reset to $FFFF.

D.2.10 TI4/O5 — Input Capture 4/Output Compare 5 Register

$YFF91C

This register serves either as input capture register 4 or output compare register 5, depending on the state of I4/O5 in PACTL.

$YFF91E

D.2.11 TCTL1/TCTL2 — Timer Control Registers 1 and 2

OM5

RESET:

OL5

0 0

OM4

OL4

OM3

OL3

OM2

OL2

EDGE4

6 5

EDGE3

4 3

EDGE2

2 1

EDGE1

0 0 0 0 0 0 0 0 0 0 0 0 0

TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input capture to be performed.

OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits

Each pair of bits specifies an action to be taken when output comparison is successful.

OM/OL[5:2]

Action Taken

Timer Disconnected from Output Logic

Toggle OCx Output Line

Clear OCx Output Line to zero

Set OCx Output Line to one

EDGE[4:1] — Input Capture Edge Control

Each pair of bits configures input sensing logic for the corresponding input capture.

EDGE[4:1]

Configuration

Capture Disabled

Capture on Rising Edge Only

Capture on Falling Edge Only

Capture on Any (Rising or Falling) Edge

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D.2.12 TMSK1/TMSK2 — Timer Interrupt Mask Registers 1 and 2

$YFF920

I4/O5I

RESET:

0 0 0

OCI

ICI

TOI

5 4 3

PAOVI PAII CPROUT

0 0 0 0

CPR

TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT functions.

I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable

0 = IC4/OC5 interrupt disabled

1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set

OCI[4:1] — Output Compare Interrupt Enable

0 = OC interrupt disabled

1 = OC interrupt requested when OC flag set

OCI[4:1] correspond to OC[4:1].

ICI[3:1] — Input Capture Interrupt Enable

0 = IC interrupt disabled

1 = IC interrupt requested when IC flag set

ICI[3:1] correspond to IC[3:1].

TOI — Timer Overflow Interrupt Enable

0 = Timer overflow interrupt disabled

1 = Interrupt requested when TOF flag is set

PAOVI — Pulse Accumulator Overflow Interrupt Enable

0 = Pulse accumulator overflow interrupt disabled

1 = Interrupt requested when PAOVF flag is set

PAII — Pulse Accumulator Input Interrupt Enable

0 = Pulse accumulator interrupt disabled

1 = Interrupt requested when PAIF flag is set

CPROUT — Capture/Compare Unit Clock Output Enable

0 = Normal operation for OC1 pin

1 = TCNT clock driven out OC1 pin

CPR[2:0] — Timer Prescaler/PCLK Select Field

This field selects one of seven prescaler taps or PCLK to be TCNT input.

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D.2.13 TFLG1/TFLG2 — Timer Interrupt Flag Registers 1 and 2

$YFF922

I4/O5F

RESET:

0 0

OCF

ICF

TOF

5 4

PAOVF PAIF

0 0

These registers show condition flags that correspond to GPT events. If the corresponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs.

I4/O5F — Input Capture 4/Output Compare 5 Flag

When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the TOC5 value in TI4/O5. When I4/O5 in PACTL is one, the flag is set each time a selected edge is detected at the I4/O5 pin.

OCF[4:1] — Output Compare Flags

An output compare flag is set each time TCNT matches the corresponding TOC register. OCF[4:1] correspond to OC[4:1].

ICF[3:1] — Input Capture Flags

A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] correspond to IC[3:1].

TOF — Timer Overflow Flag

This flag is set each time TCNT advances from a value of $FFFF to $0000.

PAOVF — Pulse Accumulator Overflow Flag

This flag is set each time the pulse accumulator counter advances from a value of $FF to $00.

PAIF — Pulse Accumulator Flag

In event counting mode, this flag is set when an active edge is detected on the PAI pin.

In gated time accumulation mode, it is set at the end of the timed period.

D.2.14 CFORC — Compare Force Register

PWMC — PWM Control Register C

$YFF924

$YFF925

FOC

11 10

9 8 7

FPWMA FPWMB PPROUT

PPR

4 3

SFA

SFB

F1A

F1B

RESET:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets

PWM operating conditions.

FOC[5:1] — Force Output Compare

0 = Has no meaning.

1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set.

FOC[5:1] correspond to OC[5:1].

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FPWMA — Force PWMA Value

0 = Normal PWMA operation.

1 = The value of F1A is driven out on the PWMA pin, regardless of the state of

PPROUT.

FPWMB — Force PWMB Value

0 = Normal PWMB operation.

1 = The value of F1B is driven out on the PWMB pin.

PPROUT — PWM Clock Output Enable

0 = Normal PWM operation on PWMA.

1 = TCNT clock driven out PWMA pin.

PPR[2:0] — PWM Prescaler/PCLK Select

This field selects one of seven prescaler taps or PCLK to be PWMCNT input.

PPR[2:0]

000

001

010

011

100

101

110

111

System Clock

Divide-by Factor

128

PCLK

SFA — PWMA Slow/Fast Select

0 = PWMA period is 256 PWMCNT increments long.

1 = PWMA period is 32768 PWMCNT increments long.

SFB — PWMB Slow/Fast Select

0 = PWMB period is 256 PWMCNT increments long.

1 = PWMB period is 32768 PWMCNT increments long.

The following table shows a range of PWM output frequencies using a 16.78-MHz system clock and 20.97 system clock.

PPR

[2:0]

000

001

010

011

100

101

110

111

Prescaler Tap

16.78 MHz 20.97 MHz

Div 2 = 8.39 MHz Div 2 = 10.5 MHz

Div 4 = 4.19 MHz Div 4 = 5.25 MHz

Div 8 = 2.10 MHz Div 8 = 2.62 MHz

Div 16 = 1.05 MHz Div 16 = 1.31 MHz

Div 32 = 524 kHz Div 32 = 655 kHz

Div 64 = 262 kHz Div 64 = 328 kHz

Div 128 = 131 kHz Div 128 = 164 kHz

PCLK PCLK

SFA/B = 0

16.78 MHz

32.8 kHz

20.97 MHz

41 kHz

16.4 kHz

8.19 kHz

4.09 kHz

2.05 kHz

20.5 kHz

10.2 kHz

5.15 kHz

2.56 kHz

1.02 kHz

512 Hz

PCLK/256

SFA/B = 1

16.78 MHz

256 Hz

128 Hz

64.0 Hz

32.0 Hz

16.0 Hz

20.97 MHz

320 Hz

160 Hz

80.0 Hz

40.0 Hz

20.0 Hz

1.28 kHz

641 Hz

8.0 Hz

4.0 Hz

10.0 Hz

5.0 Hz

PCLK/256 PCLK/32768 PCLK/32768

F1A — Force Logic Level One on PWMA

0 = Force logic level zero output on PWMA pin.

1 = Force logic level one output on PWMA pin.

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F1B — Force Logic Level One on PWMB

0 = Force logic level zero output on PWMB pin.

1 = Force logic level one output on PWMB pin.

The value in these registers determines pulse width of the corresponding PWM output.

A value of $00 corresponds to continuously low output; a value of $80 to 50% duty cycle. Maximum value ($FF) selects an output that is high for 255/256 of the period.

Writes to these registers are buffered by PWMBUFA and PWMBUFB.

D.2.16 PWMCNT — PWM Count Register $YFF928

PWMCNT is the 16-bit free-running counter used for GPT PWM functions.

D.2.17 PWMBUFA — PWM Buffer Register A $YFF92A

$YFF92B

To prevent glitches when PWM duty cycle is changed, the contents of PWMA and

PWMB are transferred to these read-only registers at the end of each duty cycle. Reset state is $0000.

D.2.18 PRESCL — GPT Prescaler $YFF92C

The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000.

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D.3 System Integration Module

Table D-3 displays the SIM address map. The column labeled “Access” indicates the

privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required. A designation of “S/U” indicates that the register can be programmed to the desired privilege level.

S/U

Access

S/U

Table D-3 SIM Address Map

Address 15 8 7 0

$YFFA00

$YFFA02

SIM CONFIGURATION (SIMCR)

FACTORY TEST (SIMTR)

$YFFA04

$YFFA06

$YFFA08

$YFFA0A

CLOCK SYNTHESIZER CONTROL (SYNCR)

NOT USED RESET STATUS REGISTER (RSR)

MODULE TEST E (SIMTRE)

NOT USED NOT USED

$YFFA0C

$YFFA0E

$YFFA10

$YFFA12

$YFFA14

$YFFA16

$YFFA18

$YFFA1A

$YFFA1C

$YFFA1E

$YFFA20

NOT USED

PORT E DATA (PORTE0)

PORT E DATA (PORTE1)

PORT E DATA DIRECTION (DDRE)

PORT E PIN ASSIGNMENT (PEPAR)

PORT F DATA (PORTF0)

PORT F DATA (PORTF1)

PORT F DATA DIRECTION (DDRF)

PORT F PIN ASSIGNMENT (PFPAR)

NOT USED SYSTEM PROTECTION CONTROL

(SYPCR)

PERIODIC INTERRUPT CONTROL (PICR) $YFFA22

$YFFA24

$YFFA26

$YFFA28

$YFFA2A

$YFFA2C

$YFFA2E

PERIODIC INTERRUPT TIMING (PITR)

NOT USED

SOFTWARE SERVICE (SWSR)

NOT USED

TEST MODULE MASTER SHIFT A (TSTMSRA)

TEST MODULE MASTER SHIFT B (TSTMSRB)

$YFFA30

$YFFA32

$YFFA34

$YFFA36

$YFFA38

$YFFA3A

$YFFA3C

$YFFA3E

TEST MODULE SHIFT COUNT (TSTSC)

TEST MODULE REPETITION COUNTER (TSTRC)

TEST MODULE CONTROL (CREG)

TEST MODULE DISTRIBUTED REGISTER (DREG)

NOT USED

PORT C DATA (PORTC)

NOT USED

$YFFA40

$YFFA42

$YFFA44

$YFFA46

$YFFA48

$YFFA4A

$YFFA4C

$YFFA4E

CHIP-SELECT PIN ASSIGNMENT (CSPAR0)

CHIP-SELECT PIN ASSIGNMENT (CSPAR1)

CHIP-SELECT BASE BOOT (CSBARBT)

CHIP-SELECT OPTION BOOT (CSORBT)

CHIP-SELECT BASE 0 (CSBAR0)

CHIP-SELECT OPTION 0 (CSOR0)

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Table D-3 SIM Address Map

Access

$YFFA6A

$YFFA6C

$YFFA6E

$YFFA70

$YFFA72

$YFFA74

$YFFA76

$YFFA78

$YFFA7A

$YFFA7C

$YFFA7E

Address 15 8 7 0

$YFFA50 CHIP-SELECT BASE 1 (CSBAR1)

$YFFA52

$YFFA54

$YFFA56

$YFFA58

CHIP-SELECT OPTION 1 (CSOR1)

CHIP-SELECT BASE 2 (CSBAR2)

CHIP-SELECT OPTION 2 (CSOR2)

CHIP-SELECT BASE 3 (CSBAR3)

$YFFA5A

$YFFA5C

$YFFA5E

$YFFA60

$YFFA62

$YFFA64

$YFFA66

$YFFA68

CHIP-SELECT OPTION 3 (CSOR3)

CHIP-SELECT BASE 4 (CSBAR4)

CHIP-SELECT OPTION 4 (CSOR4)

CHIP-SELECT BASE 5 (CSBAR5)

CHIP-SELECT OPTION 5 (CSOR5)

CHIP-SELECT BASE 6 (CSBAR6)

CHIP-SELECT OPTION 6 (CSOR6)

CHIP-SELECT BASE 7 (CSBAR7)

CHIP-SELECT OPTION 7 (CSOR7)

NOT USED

CHIP-SELECT BASE 8 (CSBAR8)

CHIP-SELECT OPTION 8 (CSOR8)

CHIP-SELECT BASE 9 (CSBAR9)

CHIP-SELECT OPTION 9 (CSOR9)

CHIP-SELECT BASE 10 (CSBAR10)

CHIP-SELECT OPTION 10 (CSOR10)

NOT USED NOT USED

NOT USED

Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR

D.3.1 SIMCR — Module Configuration Register

$YFFA00

15 14 13

EXOFF FRZSW FRZBM

RESET:

0 0 0

SLVEN

DATA11

SHEN

0 0

7 6

SUPV MM

1 1

IARB

SIMCR controls system configuration. SIMCR can be read or written at any time, except for the module mapping (MM) bit, which can only be written once.

EXOFF — External Clock Off

0 = The CLKOUT pin is driven from an internal clock source.

1 = The CLKOUT pin is placed in a high-impedance state.

FRZSW — Freeze Software Enable

0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run.

1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts during software debug.

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FRZBM — Freeze Bus Monitor Enable

0 = When FREEZE is asserted, the bus monitor continues to operate.

1 = When FREEZE is asserted, the bus monitor is disabled.

SLVEN — Factory Test Mode Enabled

0 = IMB is not available to an external master.

1 = An external bus master has direct access to the IMB.

SHEN[1:0] — Show Cycle Enable

This field determines what the EBI does with the external bus during internal transfer operations.

SUPV — Supervisor/Unrestricted Data Space

The SUPV bit places the SIM global registers in either supervisor or user data space.

0 = Registers with access controlled by the SUPV bit are accessible from either the user or supervisor privilege level.

1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.

MM — Module Mapping

0 = Internal modules are addressed from $7FF000 – $7FFFFF.

1 = Internal modules are addressed from $FFF000 – $FFFFFF.

IARB[3:0] — Interrupt Arbitration Field

Determines SIM interrupt arbitration priority. The reset value is $F (highest priority), to prevent SIM interrupts from being discarded during initialization.

$YFFA02

D.3.2 SIMTR — System Integration Test Register

SIMTR is used for factory test only.

D.3.3 SYNCR — Clock Synthesizer Control Register

$YFFA04

RESET:

0 0

1 1 1

1 1

EDIV

4 3 2

SLIMP SLOCK RSTEN

STSIM

STEXT

U U 0 0 0

SYNCR determines system clock operating frequency and mode of operation.

Clock frequency is determined by SYNCR bit settings as follows: .

W — Frequency Control (VCO)

0 = Base VCO frequency

1 = VCO frequency multiplied by four

X — Frequency Control Bit (Prescale)

0 = VCO frequency divided by four (base system clock frequency)

1 = VCO frequency divided by two (system clock frequency doubles)

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Y[5:0] — Frequency Control (Counter)

The Y field is the initial value for the modulus 64 down counter in the synthesizer feedback loop. Values range from 0 to 63.

EDIV — ECLK Divide Rate

0 = ECLK is system clock divided by 8

1 = ECLK is system clock divided by 16

SLIMP — Limp Mode

0 = External crystal is VCO reference

1 = Loss of crystal reference

SLOCK — Synthesizer Lock

0 = VCO is enabled, but has not locked.

1 = VCO has locked on the desired frequency or system clock is external.

RSTEN — Reset Enable

0 = Loss of reference causes the MCU to operate in limp mode.

1 = Loss of reference causes system reset.

STSIM — Stop Mode System Integration Clock

0 = SIM clock driven by an external source and VCO off during low-power stop.

1 = SIM clock driven by VCO during low-power stop.

STEXT — Stop Mode External Clock

0 = CLKOUT held low during low-power stop.

1 = CLKOUT driven from SIM clock during low-power stop.

D.3.4 RSR — Reset Status Register

$YFFA07

NOT USED

8 7 6

EXT POW

HLT

LOC

SYS

TST

RSR contains a status bit for each reset source in the MCU. RSR is updated when the

MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple sources assert reset signals at the same time, more than one bit in RSR may be set.

This register can be read at any time; a write has no effect.

EXT — External Reset

Reset caused by an external signal.

POW — Power-Up Reset

Reset caused by the power-up reset circuit.

SW — Software Watchdog Reset

Reset caused by the software watchdog circuit.

HLT — Halt Monitor Reset

Reset caused by the halt monitor.

D-16

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LOC — Loss of Clock Reset

Reset caused by loss of clock frequency reference.

SYS — System Reset

Reset caused by a RESET instruction.

TST — Test Submodule Reset

Reset caused by the test submodule. Used during system test only.

D.3.5 SIMTRE — System Integration Test Register (ECLK)

D.3.6 PORTE0/PORTE1 — Port E Data Register

$YFFA08

$YFFA11, $YFFA13

NOT USED

8 7

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

RESET:

U U U U U U U U

PORTE is an internal data latch that can be accessed at two locations. PORTE can be read or written at any time. If a pin in I/O port E is configured as an output, the corresponding bit value is driven out on the pin. When a pin is configured for output, a read of PORTE returns the latched bit value; when a pin is configured for input, a read returns the pin logic level.

D.3.7 DDRE — Port E Data Direction Register

$YFFA15

NOT USED

8 7 6 5 4 3 2 1 0

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0

RESET:

0 0 0 0 0 0 0 0

Bits in this register control the direction of the port E pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time.

D.3.8 PEPAR — Port E Pin Assignment Register

$YFFA17

NOT USED

8 7 6 5 4 3 2 1 0

PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0

RESET:

DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8

Bits in this register determine the function of port E pins. Setting a bit assigns the corresponding pin to a bus control signal; clearing a bit assigns the pin to I/O port E.

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Table D-4 Port E Pin Assignments

PEPAR Bit

PEPA7

PEPA6

PEPA5

PEPA4

PEPA3

PEPA2

PEPA1

PEPA0

Port E Signal

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Bus Control Signal

SIZ1

SIZ0

RMC

AVEC

DSACK1

DSACK0

D.3.9 PORTF0/PORTF1 — Port F Data Register

$YFFA19, $YFFA1B

NOT USED

8 7

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

RESET:

U U U U U U U U

PORTF is an internal data latch that can be accessed at two locations. It can be read or written at any time. If a pin in I/O port F is configured as an output, the corresponding bit value is driven out on the pin. When a pin is configured for output, a read of PORTF returns the latched bit value; when a pin is configured for input, a read returns the pin logic level.

D.3.10 DDRF — Port F Data Direction Register

$YFFA1D

NOT USED

8 7 6 5 4 3 2 1 0

DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0

RESET:

0 0 0 0 0 0 0 0

Bits in this register control the direction of the port F pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time.

D.3.11 PFPAR — Port F Pin Assignment Register

$YFFA1F

NOT USED

8 7

PFPA7

PFPA6

PFPA5

PFPA4

PFPA3

PFPA2

PFPA1

PFPA0

RESET:

DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9

Bits in this register determine the function of port F pins. Setting a bit assigns the corresponding pin to a control signal; clearing a bit assigns the pin to port F.

D-18

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Table D-5 Port F Pin Assignments

PFPAR Field Port F Signal Control Signal

PFPA7 PF7 IRQ7

PFPA6

PFPA5

PF6

PF5

IRQ6

IRQ5

PFPA4

PFPA3

PFPA2

PFPA1

PFPA0

PF4

PF3

PF2

PF1

PF0

IRQ4

IRQ3

IRQ2

IRQ1

MODCLK

D.3.12 SYPCR — System Protection Control Register

$YFFA21

NOT USED

8 7

SWE

SWP

SWT

4 3 2

HME BME

BMT

RESET:

1 MODCLK 0 0 0 0 0 0

SYPCR controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written once following power-on or reset.

SWE — Software Watchdog Enable

0 = Software watchdog disabled

1 = Software watchdog enabled

SWP — Software Watchdog Prescale

0 = Software watchdog clock not prescaled

1 = Software watchdog clock prescaled by 512

SWT[1:0] — Software Watchdog Timing

This field selects software watchdog time-out period.

Table D-6 Software Watchdog Ratio

SWP

SWT Ratio

00 2

HME — Halt Monitor Enable

0 = Disable halt monitor function

1 = Enable halt monitor function

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BME — Bus Monitor External Enable

0 = Disable bus monitor function for an internal to external bus cycle.

1 = Enable bus monitor function for an internal to external bus cycle.

BMT[1:0] — Bus Monitor Timing

This field selects bus monitor time-out period.

Table D-7 Bus Monitor Period

BMT

Bus Monitor Time-out Period

64 System Clocks

32 System Clocks

16 System Clocks

8 System Clocks

D.3.13 PICR — Periodic Interrupt Control Register

$YFFA22

RESET:

0 0

PIRQL

0 0 0 0

PIV

1 1 1

Contains information concerning periodic interrupt priority and vectoring. PICR[10:0] can be read or written at any time. PICR[15:11] are unimplemented and always return zero.

PIRQL[2:0] — Periodic Interrupt Request Level

This field determines the priority of periodic interrupt requests.

PIV[7:0] — Periodic Interrupt Vector

The bits of this field contain the periodic interrupt vector number supplied by the SIM when the CPU acknowledges an interrupt request.

D.3.14 PITR — Periodic Interrupt Timer Register $YFFA24

RESET:

0 0

PTP

MODCLK

0 0 0 0

PITM

0 0 0

Contains the count value for the periodic timer. This register can be read or written at any time.

PTP — Periodic Timer Prescaler Control

0 = Periodic timer clock not prescaled

1 = Periodic timer clock prescaled by a value of 512

PITM[7:0] — Periodic Interrupt Timing Modulus

This is the 8-bit timing modulus used to determine periodic interrupt rate. Use the following expression to calculate timer period.

D-20

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D.3.15 SWSR — Software Service Register

$YFFA27

NOT USED

8 7

RESET:

0 0 0 0 0 0 0 0

When the software watchdog is enabled, a service sequence must be written to this register within a specific interval. When read, SWSR always returns $00. Register shown with read value.

$YFFA30

D.3.16 TSTMSRA — Master Shift Register A

D.3.17 TSTMSRB — Master Shift Register B

D.3.18 TSTSC — Test Module Shift Count

D.3.19 TSTRC — Test Module Repetition Count

$YFFA32

$YFFA34

$YFFA36

D.3.20 CREG — Test Submodule Control Register $YFFA38

D.3.21 DREG — Distributed Register

$YFFA3A

D.3.22 PORTC — Port C Data Register

$YFFA41

NOT USED

8 7

PC6

PC5

PC4

PC3

PC2

RESET:

0 1 1 1 1 1

PORTC latches data for chip-select pins that are used for discrete output.

PC1

PC0

D.3.23 CSPAR0 — Chip Select Pin Assignment Register 0

$YFFA44

RESET:

0 0

CSPA0[6]

12 11

CSPA0[5]

10 9

CSPA0[4]

8 7

CSPA0[3]

6 5

CSPA0[2]

4 3

CSPA0[1]

DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1

1 0

CSBOOT

1 DATA0

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Table D-8 CSPAR0 Pin Assignments

CSPAR0 Field

CSPA0[6]

CSPA0[5]

CSPA0[4]

CSPA0[3]

CSPA0[2]

CSPA0[1]

CSBOOT

CSPAR0 Signal

CS5

CS4

CS3

CS2

CS1

CS0

CSBOOT

Alternate Signal

FC2

FC1

FC0

BGACK

—

Discrete Output

PC2

PC1

PC0

—

Contains seven 2-bit fields, CSPA0[6:1] and CSBOOT, that determine the functions of corresponding chip-select pins. CSPAR0[15:14] are not used. These bits always read zero; write has no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have no effect. The alternate functions can be enabled by data bus mode selection during reset.

$YFFA46

D.3.24 CSPAR1 — Chip Select Pin Assignment Register 1

RESET:

14 13 12 11 10

0 0 0 0 0

0 0 0 0

CSPA1[4]

DATA7

CSPA1[3]

6 5

CSPA1[2]

DATA6 1 DATA5 1

CSPA1[1]

DATA4 1

CSPA1[0]

DATA3 1

Table D-9 CSPAR1 Pin Assignments

CSPAR1 Field

CSPA1[4]

CSPA1[3]

CSPA1[2]

CSPA1[1]

CSPA1[0]

CSPAR1 Signal

CS10

CS9

CS8

CS7

CS6

Alternate Signal Discrete Output

ADDR23 ECLK

ADDR22

ADDR21

PC6

PC5

ADDR20

ADDR19

PC4

PC3

Contains five 2-bit fields (CSPA1[4:0]) that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; write has no effect. The CSPAR1 pin assignments table shows alternate functions that can be enabled by data bus mode selection during reset.

Table D-10 CSPAR0 and CSPAR1 Pin Assignment Field Encoding

Bit Field

Description

Discrete Output*

Alternate Function*

Chip Select (8-Bit Port)

Chip Select (16-Bit Port)

*Does not apply to the CSBOOT field

D-22

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D.3.25 CSBARBT — Chip Select Base Address Register Boot ROM $YFFA48

ADDR

RESET:

ADDR

0 0

ADDR

0 0

ADDR

0 0

ADDR

0 0 0 0 0 0 0

BLKSZ

Each chip-select pin has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip select. CSBARBT contains the base address for selection of a bootstrap peripheral memory device. Bit and field definition for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.

ADDR[23:11] — Base Address

This field sets the starting address of a particular address space.

BLKSZ — Block Size

This field determines the size of the block above the base address that is enabled by the chip select.

Table D-11 Block Size Encoding

BLKSZ[2:0]

000

001

010

011

100

101

110

111

Block Size

2 K

8 K

16 K

64 K

128 K

256 K

512 K

1 M

Address Lines Compared

ADDR[23:11]

ADDR[23:13]

ADDR[23:14]

ADDR[23:16]

ADDR[23:17]

ADDR[23:18]

ADDR[23:19]

ADDR[23:20]

D.3.26 CSORBT — Chip Select Option Register Boot ROM

CSOR[0:10] — Chip Select Option Registers

$YFFA4A

$YFFA4E–$YFFA76

MODE

RESET:

BYTE

0 0 0

R/W

11 10

STRB

DSACK

6 5

SPACE

4 3

IPL

1 0

AVEC

0 0 0 0 0 0 0 0 0 0 0 0 0

Contain parameters that support bootstrap operations from peripheral memory devices. Bit and field definitions for CSORBT and CSOR[0:10] are the same.

MODE — Asynchronous Bus/Synchronous E-clock Mode

Synchronous mode cannot be used with internally generated autovectors.

0 = Asynchronous mode selected

1 = Synchronous mode selected

BYTE — Upper/Lower Byte Option

The value in this field determines whether a select signal can be asserted.

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R/W — Read/Write

This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.

STRB — Address Strobe/Data Strobe

0 = Address strobe

1 = Data strobe

DSACK — Data Strobe Acknowledge

This field specifies the source of DSACK in asynchronous bus mode and controls wait state insertion.

SPACE — Address Space Select

This field selects an address space to be used by the chip-select logic.

IPL — Interrupt Priority Level

This field determines interrupt priority level when a chip select is used for interrupt acknowledge. It does not affect CPU interrupt recognition.

AVEC — Autovector Enable

Do not enable autovector support when in synchronous mode.

0 = External interrupt vector enabled

1 = Autovector enabled

Table D-12 Option Register Function Summary

MODE BYTE R/W STRB DSACK SPACE

0 = ASYNC 00 = Disable 00 = Rsvd 0 = AS 0000 = 0 WAIT 00 = CPU SP

IPL

000 = All

1 = SYNC 01 = Lower 01 = Read 1 = DS 0001 = 1 WAIT 01 = User SP 001 = Priority 1 1 = On

10 = Upper 10 = Write 0010 = 2 WAIT 10 = Supv SP 010 = Priority 2

11 = Both 11 = Both 0011 = 3 WAIT

0100 = 4 WAIT

11 = S/U SP 011 = Priority 3

100 = Priority 4

AVEC

0 = Off

0101 = 5 WAIT

0110 = 6 WAIT

0111 = 7 WAIT

1000 = 8 WAIT

101 = Priority 5

110 = Priority 6

111 = Priority 7

1001 = 9 WAIT

1010 = 10 WAIT

1011 = 11 WAIT

1100 = 12 WAIT

1101 = 13 WAIT

1110 = F term

1111 = External

D-24

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D.4 Queued Serial Module

Table D-13 displays the QSM address map. The column labeled “Access” indicates

the privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required: a designation of “S/U” indicates that the register can be programmed to the desired privilege level.

Table D-13 QSM Address Map

S/U

Access

S/U

QUEUE RAM

S/U

QUEUE RAM

S/U

QUEUE RAM

Address

$YFFC00

$YFFC02

$YFFC04

$YFFC06

$YFFC08

$YFFC0A

$YFFC0C

$YFFC0E

$YFFC10

$YFFC12

$YFFC14

$YFFC16

$YFFC18

$YFFC1A

$YFFC1C

$YFFC1E

$YFFC20–

$YFFCFF

$YFFD00–

$YFFD1F

$YFFD20–

$YFFD3F

$YFFD40–

$YFFD4F

15 8 7

QSM MODULE CONFIGURATION (QSMCR)

QSM TEST (QTEST)

QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)

NOT USED

SPI CONTROL 3 (SPCR3)

NOT USED

SCI CONTROL 0 (SCCR0)

SCI CONTROL 1 (SCCR1)

SCI STATUS (SCSR)

SCI DATA (SCDR)

NOT USED

Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.

PQS DATA (PORTQS)

PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)

SPI CONTROL 0 (SPCR0)

SPI CONTROL 1 (SPCR1)

SPI CONTROL 2 (SPCR2)

SPI STATUS (SPSR)

RECEIVE RAM (RR[0:F])

TRANSMIT RAM (TR[0:F])

COMMAND RAM (CR[0:F])

D.4.1 QSMCR — QSM Configuration Register

$YFFC00

15 14 13

STOP FRZ1 FRZ0

RESET:

0 0 0

SUPV

0 0

IARB

QSMCR bits enable stop and freeze modes, and determine the arbitration priority of

QSM interrupt requests.

STOP — Stop Enable

0 = Normal QSM clock operation

1 = QSM clock operation stopped

When STOP is set, the QSM enters low-power stop mode. System clock input to the module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be

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valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during reset. The SCI receiver and transmitter must be disabled before STOP is set. To stop the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.

FRZ[1:0] — Freeze Control

0 = Ignore the FREEZE signal on the IMB

1 = Halt the QSPI (on a transfer boundary)

FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the

IMB is asserted. FREEZE is asserted whenever the CPU enters background mode.

FRZ0 is reserved for future use.

SUPV — Supervisor/Unrestricted

0 = Supervisor access

1 = User access

IARB — Interrupt Arbitration

Each module that generates interrupts must have an IARB value. IARB values are used to arbitrate between interrupt requests of the same priority.

$YFFC02

D.4.2 QTEST — QSM Test Register

Used for factory test only.

D.4.3 QILR — QSM Interrupt Level Register

QIVR — QSM Interrupt Vector Register

$YFFC04

$YFFC05

RESET:

0 0

ILQSPI

ILSCI

0 0 0 0

INTV

1 1 1

The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and

SCI interrupt requests. QIVR determines the value of the interrupt vector number the

QSM supplies when it responds to an interrupt acknowledge cycle. At reset, QIVR is initialized to vector number $0F, the uninitialized interrupt vector number. To use interrupt-driven serial communication, a user-defined vector number must be written to

QIVR.

ILQSPI — Interrupt Level for QSPI

When an interrupt request is made, ILQSPI value determines which of the interrupt request signals is asserted; when a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU32 to determine whether to respond. ILQS-

PI must have a value in the range $0 (lowest priority) to $7 (highest priority).

ILSCI — Interrupt Level for SCI

When an interrupt request is made, ILSCI value determines which of the interrupt request signals is asserted. When a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU32 to determine whether to respond. The field must have a value in the range $0 (lowest priority) to $7 (highest priority).

If ILQSPI and ILSCI have the same nonzero value, and both submodules simultaneously request interrupt service, the QSPI has priority.

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INTV[7:0] — Interrupt Vector Number

The values of INTV[7:1] are the same for both QSPI and SCI interrupt requests; the value of INTV0 used during an interrupt acknowledge cycle is supplied by the QSM.

INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI interrupt. A write to INTV0 has no effect. Reads of INTV0 return a value of one.

D.4.4 SCCR0 — SCI Control Register 0 $YFFC08

RESET:

0 0

0 0 0 0 0 0

SCBR

0 0 0 0 1 0

SCCR0 contains the SCI baud rate selection field. Baud rate must be set before the

SCI is enabled. The CPU32 can read and write SCCR0 at any time. Changing the value of SCCR0 bits during a transfer operation can disrupt operation.

SCBR — SCI Baud Rate

SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of zero to SCBR disables the baud rate generator. Baud clock rate is calculated as follows:

D.4.5 SCCR1 — SCI Control Register 1

$YFFC0A

14 13

LOOPS WOMS

RESET:

0 0 0

ILT

11 10 9

PT PE M

0 0 0

WAKE

TIE

TCIE

RIE

ILIE

RWU

SBK

0 0

SCCR1 contains SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU can read and write SCCR0 at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCCR1 bits during a transfer operation can disrupt operation.

LOOPS — Loop Mode

0 = Normal SCI operation, no looping, feedback path disabled

1 = Test SCI operation, looping, feedback path enabled

WOMS — Wired-OR Mode for SCI Pins

0 = If configured as an output, TXD is a normal CMOS output.

1 = If configured as an output, TXD is an open-drain output.

ILT — Idle-Line Detect Type

0 = Short idle-line detect (start count on first one)

1 = Long idle-line detect (start count on first one after stop bit(s))

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PT — Parity Type

0 = Even parity

1 = Odd parity

PE — Parity Enable

0 = SCI parity disabled

1 = SCI parity enabled

M — Mode Select

0 = 10-bit SCI frame

1 = 11-bit SCI frame

WAKE — Wakeup by Address Mark

0 = SCI receiver awakened by idle-line detection

1 = SCI receiver awakened by address mark (last bit set)

TIE — Transmit Interrupt Enable

0 = SCI TDRE interrupts inhibited

1 = SCI TDRE interrupts enabled

TCIE — Transmit Complete Interrupt Enable

0 = SCI TC interrupts inhibited

1 = SCI TC interrupts enabled

RIE — Receiver Interrupt Enable

0 = SCI RDRF and OR interrupts inhibited

1 = SCI RDRF and OR interrupts enabled

ILIE — Idle-Line Interrupt Enable

0 = SCI IDLE interrupts inhibited

1 = SCI IDLE interrupts enabled

TE — Transmitter Enable

0 = SCI transmitter disabled (TXD pin can be used as I/O)

1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)

RE — Receiver Enable

0 = SCI receiver disabled (status bits inhibited)

1 = SCI receiver enabled

RWU — Receiver Wakeup

0 = Normal receiver operation (received data recognized)

1 = Wakeup mode enabled (received data ignored until awakened)

SBK — Send Break

0 = Normal operation

1 = Break frame(s) transmitted after completion of current frame

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D.4.6 SCSR — SCI Status Register

$YFFC0C

NOT USED

9 8

TDRE

6 5 4

RDRF RAF IDLE

RESET:

1 1 0 0 0 0 0 0 0

SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by a CPU32 read/write sequence. The sequence consists of reading SCSR, then reading or writing SCDR.

If an internal SCI signal for setting a status bit comes after the CPU32 has read the asserted status bits, but before the CPU has written or read SCDR, the newly set status bit is not cleared. SCSR must be read again with the bit set and SCDR must be written or read before the status bit is cleared.

A long-word read can consecutively access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either byte are cleared on a subsequent read or write of register SCDR.

TDRE — Transmit Data Register Empty

0 = Register TDR still contains data to be sent to the transmit serial shifter.

1 = A new character can now be written to register TDR.

TC — Transmit Complete

0 = SCI transmitter is busy.

1 = SCI transmitter is idle.

RDRF — Receive Data Register Full

0 = Register RDR is empty or contains previously read data.

1 = Register RDR contains new data.

RAF — Receiver Active

0 = SCI receiver is idle.

1 = SCI receiver is busy.

IDLE — Idle-Line Detected

0 = SCI receiver did not detect an idle-line condition.

1 = SCI receiver detected an idle-line condition.

OR — Overrun Error

0 = RDRF is cleared before new data arrives.

1 = RDRF is not cleared before new data arrives.

NF — Noise Error Flag

0 = No noise detected on the received data

1 = Noise occurred on the received data.

MC68331

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FE — Framing Error

0 = No framing error on the received data

1 = Framing error or break occurred on the received data.

PF — Parity Error

0 = No parity error on the received data

1 = Parity error occurred on the received data.

D.4.7 SCDR — SCI Data Register

$YFFC0E

RESET:

0 0

8 7 6 5 4 3 2 1 0

R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0

0 0 0 0 0 U U U U U U U U U

SCDR consists of two data registers located at the same address. RDR is a read-only register that contains data received by the SCI serial interface. Data comes into the receive serial shifter and is transferred to RDR. TDR is a write-only register that contains data to be transmitted. Data is first written to TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When the SCI is configured for 8-bit operation, R8/T8 have no meaning or effect.

D.4.8 PORTQS — Port QS Data Register

$YFFC15

NOT USED

8 7 6 5 4 3 2 1 0

PQS7 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0

RESET:

0 0 0 0 0 0 0

PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS.

D.4.9 PQSPAR — PORT QS Pin Assignment Register

DDRQS — PORT QS Data Direction Register

$YFFC16

$YFFC17

RESET:

14 13 12 11

PQSPA6 PQSPA5 PQSPA4 PQSPA3

0 0 0 0 0

9 8 7 6 5 4 3 2 1 0

PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0

0 0 0 0 0 0 0 0 0 0 0

Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.

D-30

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Table D-14 PQSPAR Pin Assignments

PQSPAR Field

PQSPA0

PQSPA1

PQSPA2

PQSPA3

PQSPA4

PQSPA5

PQSPA6

PQSPA7

PQSPAR Bit

Pin Function

PQS0

MISO

PQS1

MOSI

PQS2

SCK

PQS3

PCS0/SS

PQS4

PCS1

PQS5

PCS2

PQS6

PCS3

PQS7

TXD

1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK.

2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it becomes SCI serial output TXD.

DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both

QSPI function and I/O function.

Table D-15 Effect of DDRQS on PORTQS Pins

Pin

PQS0

PQS1

PQS2

PQS3

PQS4

PQS5

PQS6

PQS7

DDRQS Bit

Pin Function

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Digital Output

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Table D-16 Effect of DDRQS on QSM Pin Function

QSM Pin

MISO

MOSI

SCK

PCS0/SS

PCS[3:1]

TXD

RXD

Mode

Master

Slave

Master

Slave

Master

Slave

Master

Slave

Master

Slave

DDRQS

Bit

DDQS0

DDQS1

DDQS2

DDQS3

DDQS

[4:6]

Transmit DDQS7

Receive None

Bit

State

0 Inactive

Inactive

Pin Function

Serial Data Input to QSPI

Disables Data Input

Disables Data Output

Serial Data Output from QSPI

Disables Data Output

Serial Data Output from QSPI

Serial Data Input to QSPI

Disables Data Input

Disables Clock Output

Clock Output from QSPI

Clock Input to QSPI

Disables Clock Input

Assertion Causes Mode Fault

Chip-Select Output

QSPI Slave Select Input

Disables Select Input

Disables Chip-Select Output

Chip-Select Output

Serial Data Output from SCI

NA Serial Data Input to SCI

1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK.

2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 =1), in which case it becomes SCI serial output TXD.

DDRQS determines the direction of the TXD pin only when the SCI transmitter is disabled. When the SCI transmitter is enabled, the TXD pin is an output.

D.4.10 SPCR0 — QSPI Control Register 0

$YFFC18

MSTR

RESET:

WOMQ

BITS

10 9 8

CPOL CPHA

0 0 0 0 0 1 0 0 0 0 0 1 0 0

SPCR0 contains parameters for configuring the QSPI and enabling various modes of operation. The CPU has read/write access to SPCR0, but the QSM has read access only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to

SPCR0 while the QSPI is enabled disrupts operation.

MSTR — Master/Slave Mode Select

0 = QSPI is a slave device.

1 = QSPI is system master.

D-32

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WOMQ — Wired-OR Mode for QSPI Pins

0 = Outputs have normal MOS drivers.

1 = Pins designated for output by DDRQS have open-drain drivers.

BITS — Bits Per Transfer

The BITS field determines the number of serial data bits transferred.

CPOL — Clock Polarity

0 = The inactive state value of SCK is logic level zero.

1 = The inactive state value of SCK is logic level one.

CPHA — Clock Phase

0 =Data captured on the leading edge of SCK and changed on the following edge of SCK.

1 =Data is changed on the leading edge of SCK and captured on the following edge of SCK.

SPBR — Serial Clock Baud Rate

QSPI baud rate is selected by writing a value from 2 to 255 into SPBR. Giving BR a value of zero or one disables SCK (disable state determined by CPOL).

$YFFC1A

D.4.11 SPCR1 — QSPI Control Register 1

SPE

RESET:

0 0 0 0

DSCKL

0 1 0

0 0 0 0

DTL

0 1 0

SPCR1 enables the QSPI and specified transfer delays. The CPU32 has read/write access to SPCR1, but the QSM has read access only to all bits but enable bit SPE.

SPCR1 must be written last during initialization because it contains SPE. Writing a new value to SPCR1 while the QSPI is enabled disrupts operation.

SPE — QSPI Enable

0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.

1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.

DSCKL — Delay before SCK

When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip-select pins.

DTL — Length of Delay after Transfer

When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.

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Freescale Semiconductor, Inc.

D.4.12 SPCR2 — QSPI Control Register 2

$YFFC1C

SPIFIE

RESET:

WREN

0 0

WRTO

0 0

ENDQP

0 0

NEWQP

SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read access only. SPCR2 is buffered. New SPCR2 values become effective only after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. SPCR2 reads return the value of the register, not the buffer.

SPIFIE — SPI Finished Interrupt Enable

0 = QSPI interrupts disabled

1 = QSPI interrupts enabled

WREN — Wrap Enable

0 = Wraparound mode disabled

1 = Wraparound mode enabled

WRTO — Wrap To

0 = Wrap to pointer address $0

1 = Wrap to address in NEWQP

ENDQP — Ending Queue Pointer

This field contains the last QSPI queue address.

NEWQP — New Queue Pointer Value

This field contains the first QSPI queue address.

D.4.13 SPCR3 — QSPI Control Register 3

SPSR — QSPI Status Register

$YFFC1E

$YFFC1F

RESET:

0 0

10 9 8 7

LOOPQ HMIE HALT SPIF

MODF

HALTA

CPTQP

0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enables, and the halt control bit. The CPU has read/write access to SPCR3, but the QSM has read access only. SPCR3 must be initialized before QSPI operation begins. Writing a new value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains information concerning the current serial transmission. Only the QSPI can set bits in SPSR.

The CPU reads SPSR to obtain QSPI status information and writes it to clear status flags.

D-34

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LOOPQ — QSPI Loop Mode

0 = Feedback path disabled

1 = Feedback path enabled

HMIE — HALTA and MODF Interrupt Enable

0 = HALTA and MODF interrupts disabled

1 = HALTA and MODF interrupts enabled

HALT — Halt

0 = Halt not enabled

1 = Halt enabled

SPIF — QSPI Finished Flag

0 = QSPI not finished

1 = QSPI finished

MODF — Mode Fault Flag

0 =Normal operation

1 =Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode (SS input taken low).

HALTA — Halt Acknowledge Flag

0 = QSPI not halted

1 = QSPI halted

CPTQP — Completed Queue Pointer

CPTQP points to the last command executed. It is updated when the current command is complete. When the first command in a queue is executing, CPTQP contains either the reset value ($0) or a pointer to the last command completed in the previous queue.

D.4.14 RR[0:F] — Receive Data RAM

$YFFD00–$YFFD0E

Data received by the QSPI is stored in this segment. The CPU32 reads this segment to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, word, or long-word addressing.

D.4.15 TR[0:F] — Transmit Data RAM $YFFD20–$YFFD3E

Data that is to be transmitted by the QSPI is stored in this segment. The CPU32 normally writes one word of data into this segment for each queue command to be executed.

Information to be transmitted must be written to transmit data RAM in a right-justified format. The QSPI cannot modify information in the transmit data RAM. The QSPI copies the information to its data serializer for transmission. Information remains in transmit RAM until overwritten.

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D.4.16 CR[0:F] — Command RAM

$YFFD40–$YFFD4F

CONT

—

CONT

BITSE

—

BITSE

—

DSCK

—

DSCK

PCS3

—

PCS3

PCS2

—

PCS2

PCS1

—

PCS1

PCS0*

—

PCS0*

COMMAND CONTROL PERIPHERAL CHIP SELECT

*The PCS0 bit represents the dual-function PCS0/SS.

Command RAM is used by the QSPI when in master mode. The CPU32 writes one byte of control information to this segment for each QSPI command to be executed.

The QSPI cannot modify information in command RAM.

Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options.

A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in NEWQP through the address in ENDQP (both of these fields are in

SPCR2).

CONT — Continue

0 = Control of chip selects returned to PORTQS after transfer is complete.

1 = Peripheral chip selects remain asserted after transfer is complete.

BITSE — Bits per Transfer Enable

0 = Eight bits

1 = Number of bits set in BITS field of SPCR0

DT — Delay after Transfer

The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. The delay between transfers is determined by the SPCR1 DTL field.

DSCK — PCS to SCK Delay

0 = PCS valid to SCK transition is one-half SCK.

1 = SPCR1 DSCKL field specifies delay from PCS valid to SCK.

PCS[3:0] — Peripheral Chip Select

Peripheral chip-select bits are used to select an external device for serial data transfer.

More than one peripheral chip select may be activated at a time, and more than one peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs.

D-36

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S/U

Access

S/U

Access

S/U

Table D-17 MC68331 Module Address Map

(Assumes SIMCR MM = 1)

$FFFA0A

$FFFA0C

$FFFA0E

$FFFA10

$FFFA12

$FFFA14

$FFFA16

$FFFA18

$FFFA1A

$FFFA1C

$FFFA1E

$FFFA20

GPT

Address 15 8 7 0

$FFF900 GPT MODULE CONFIGURATION (GPTMCR)

$FFF902

$FFF904

$FFF906

$FFF908

(RESERVED FOR TEST)

INTERRUPT CONFIGURATION (ICR)

PGP DATA DIRECTION (DDRGP)

OC1 ACTION MASK (OC1M)

PGP DATA (PORTGP)

OC1 ACTION DATA (OC1D)

$FFF90A

$FFF90C

$FFF90E

$FFF910

$FFF912

$FFF914

$FFF916

$FFF918

TIMER COUNTER (TCNT)

PA CONTROL (PACTL) PA COUNTER (PACNT)

INPUT CAPTURE 1 (TIC1)

INPUT CAPTURE 2 (TIC2)

INPUT CAPTURE 3 (TIC3)

OUTPUT COMPARE 1 (TOC1)

OUTPUT COMPARE 2 (TOC2)

OUTPUT COMPARE 3 (TOC3)

$FFF91A

$FFF91C

$FFF91E

$FFF920

$FFF922

$FFF924

$FFF926

$FFF928

OUTPUT COMPARE 4 (TOC4)

INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)

TIMER CONTROL 1 (TCTL1)

TIMER MASK 1 (TMSK1)

TIMER CONTROL 2 (TCTL2)

TIMER MASK 2 (TMSK2)

TIMER FLAG 1 (TFLG1)

FORCE COMPARE (CFORC)

TIMER FLAG 2 (TFLG2)

PWM CONTROL C (PWMC)

PWM CONTROL A (PWMA) PWM CONTROL B (PWMB)

PWM COUNT (PWMCNT)

$FFF92A

$FFF92C

$FFF92E –

$FFF93F

PWMA BUFFER (PWMBUFA) PWMB BUFFER (PWMBUFB)

GPT PRESCALER (PRESCL)

NOT USED

SIM

Address 15 8 7 0

$FFFA00 MODULE CONFIGURATION (SIMCR)

$FFFA02

$FFFA04

$FFFA06

$FFFA08

FACTORY TEST (SIMTR)

CLOCK SYNTHESIZER CONTROL (SYNCR)

NOT USED RESET STATUS (RSR)

MODULE TEST E (SIMTRE)

$FFFA22

NOT USED

PORTE DATA (PORTE0)

PORTE DATA (PORTE1)

PORTE DATA DIRECTION (DDRE)

PORTE PIN ASSIGNMENT (PEPAR)

PORTF DATA (PORTF0)

NOT USED

PORTF DATA (PORTF1)

PORTF DATA DIRECTION (DDRF)

PORTF PIN ASSIGNMENT (PFPAR)

SYSTEM PROTECTION CONTROL

(SYPCR)

PERIODIC INTERRUPT CONTROL (PICR)

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S/U

Access

S/U

Table D-17 MC68331 Module Address Map, (Continued)

(Assumes SIMCR MM = 1)

$FFFA5E

$FFFA60

$FFFA62

$FFFA64

$FFFA66

$FFFA68

$FFFA6A

$FFFA6C

$FFFA6E

$FFFA70

$FFFA72

$FFFA74

$FFFA76

$FFFA78

$FFFA7A

$FFFA7C

$FFFA7E

$FFFA3E

$FFFA40

$FFFA42

$FFFA44

$FFFA46

$FFFA48

$FFFA4A

$FFFA4C

$FFFA4E

$FFFA50

$FFFA52

$FFFA54

$FFFA56

$FFFA58

$FFFA5A

$FFFA5C

SIM (Continued)

Address 15 8 7 0

$FFFA24 PERIODIC INTERRUPT TIMING (PITR)

$FFFA26

$FFFA28

$FFFA2A

$FFFA2C

NOT USED

SOFTWARE SERVICE (SWSR)

NOT USED

$FFFA2E

$FFFA30

$FFFA32

$FFFA34

$FFFA36

$FFFA38

$FFFA3A

$FFFA3C

NOT USED NOT USED

TEST MODULE MASTER SHIFT A (TSTMSRA)

TEST MODULE MASTER SHIFT B (TSTMSRB)

TEST MODULE SHIFT COUNT (TSTSC)

TEST MODULE REPETITION COUNTER (TSTRC)

TEST MODULE CONTROL (CREG)

TEST MODULE DISTRIBUTED (DREG)

NOT USED NOT USED

NOT USED

PORT C DATA (PORTC)

NOT USED

CHIP-SELECT PIN ASSIGNMENT (CSPAR0)

CHIP-SELECT PIN ASSIGNMENT (CSPAR1)

CHIP-SELECT BASE BOOT (CSBARBT)

CHIP-SELECT OPTION BOOT (CSORBT)

CHIP-SELECT BASE 0 (CSBAR0)

CHIP-SELECT OPTION 0 (CSOR0)

CHIP-SELECT BASE 1 (CSBAR1)

CHIP-SELECT OPTION 1 (CSOR1)

CHIP-SELECT BASE 2 (CSBAR2)

CHIP-SELECT OPTION 2 (CSOR2)

CHIP-SELECT BASE 3 (CSBAR3)

CHIP-SELECT OPTION 3 (CSOR3)

CHIP-SELECT BASE 4 (CSBAR4)

CHIP-SELECT OPTION 4 (CSOR4)

CHIP-SELECT BASE 5 (CSBAR5)

CHIP-SELECT OPTION 5 (CSOR5)

CHIP-SELECT BASE 6 (CSBAR6)

CHIP-SELECT OPTION 6 (CSOR6)

CHIP-SELECT BASE 7 (CSBAR7)

CHIP-SELECT OPTION 7 (CSOR7)

CHIP-SELECT BASE 8 (CSBAR8)

CHIP-SELECT OPTION 8 (CSOR8)

CHIP-SELECT BASE 9 (CSBAR9)

CHIP-SELECT OPTION 9 (CSOR9)

CHIP-SELECT BASE 10 (CSBAR10)

CHIP-SELECT OPTION 10 (CSOR10)

NOT USED NOT USED

NOT USED

D-38

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S/U

Access

S/U

Table D-17 MC68331 Module Address Map, (Continued)

(Assumes SIMCR MM = 1)

QSM

Address 15 8 7 0

$FFFC00 QSM MODULE CONFIGURATION (QSMCR)

$FFFC02

$FFFC04

$FFFC06

$FFFC08

QSM TEST (QTEST)

QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)

NOT USED

SCI CONTROL 0 (SCCR0)

$FFFC0A

$FFFC0C

$FFFC0E

$FFFC10

$FFFC12

$FFFC14

$FFFC16

$FFFC18

$FFFC1A

$FFFC1C

$FFFC1E

$FFFC20–

$FFFCFF

$FFFD00–

$FFFD1F

NOT USED

SCI CONTROL 1 (SCCR1)

SCI STATUS (SCSR)

SCI DATA (SCDR)

NOT USED

PQS PIN ASSIGNMENT (PQSPAR)

NOT USED

PQS DATA (PORTQS)

PQS DATA DIRECTION (DDRQS)

SPI CONTROL 0 (SPCR0)

SPI CONTROL 1 (SPCR1)

SPI CONTROL 2 (SPCR2)

SPI CONTROL 3 (SPCR3) SPI STATUS (SPSR)

RECEIVE RAM (RR[0:F]) S/U

QUEUE

RAM

S/U

QUEUE

RAM

S/U

QUEUE

RAM

$FFFD20–

$FFFD3F

$FFFD40–

$FFFD4F

TRANSMIT RAM (TR[0:F])

COMMAND RAM (CR[0:F])

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D-39

D-40

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Table D-18 Register Bit and Field Mnemonics

CSPA0[6:1]

CSPA1[4:0]

CSBOOT

DDE[7:0]

DDF[7:0]

DDRGP[7:0]

DDQS[7:0]

DSACK

DSCK

DSCKL

DTL

EDGE[4:1]

EDIV

ENDQP

EXOFF

Mnemonic

ADDR[23:11]

AVEC

BITS

BITSE

BLKSZ

BME

BMT[1:0]

BYTE

CONT

CPHA

CPOL

CPROUT

CPR[2:0]

CPTQP

EXT

F1A

F1B

FOC[5:1]

FPWMA

FPWMB

FRZBM

FRZSW

FRZ[1:0]

HALT

HALTA

HLT

HME

HMIE

Name

Base Address

Autovector Enable

Bits Per Transfer

Bits Per Transfer Enable

Block Size

Bus Monitor External Enable

Bus Monitor Timing

Upper/Lower Byte Option

Carry Flag

Continue

Clock Phase

Clock Polarity

Capture/Compare Clock Output Enable

Timer Prescaler/PCLK Select Field

Completed Queue Pointer

Chip-Select [6:1]

Chip-Select [4:0]

Boot ROM Chip Select

Port E Data Direction

Port F Data Direction

Port GP Data Direction

Port QS Data Direction

Data Strobe Acknowledge

PCS to SCK Delay

Delay Before SCK

Delay After Transfer

Length of Delay After Transfer

Input Capture Edge Control

ECLK Divide Rate

Ending Queue Pointer

External Clock Off

External Reset

Force Logic Level One on PWMA

Force Logic Level One on PWMB

Framing Error

Force Output Compare

Force PWMA Value

Force PWMB Value

Freeze Bus Monitor Enable

Freeze Software Enable

Freeze Response

Freeze1

Halt

Halt Acknowledge Flag

Halt Monitor Reset

Halt Monitor Enable

HALTA and MODF Interrupt Enable

Register Location

CSBAR[0:10], CSBARBT

CSOR[0:10], CSORBT

SPCR0

CR[0:F]

CSBAR[0:10], CSBARBT

SYPCR

CSOR[0:10], CSORBT

CCR

CR[0:F]

SPCR0

TMSK2

SPSR

CSPAR0

CSPAR1

CSPAR0

DDRE

DDRF

DDRGP

DDRQS

CSOR[0:10], CSORBT

CR[0:F]

SPCR1

CR[0:F]

SPCR1

TCTL2

SYNCR

SPCR2

SIMCR

RSR

PWMC

SCSR

CFORC

SIMCR

GPTMCR

QSMCR

SPCR3

SPSR

RSR

SYPCR

SPCR3

REGISTER SUMMARY

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LOC

LOOPQ

LOOPS

MODE

MODF

MSTR

NEWQP

OC1D[5:1]

OC1M[5:1]

OCF[4:1]

OCI[4:1]

OM[5:2]

OL[5:2]

PACLK[1:0]

I4/O5I

IARB[3:0]

ICF[3:1]

ICI[3:1]

IDLE

ILIE

ILQSPI

ILSCI

ILT

INCP

INTV[7:0]

IP[2:0]

IPA

IPL

IVBA

Table D-18 Register Bit and Field Mnemonics, (Continued)

Mnemonic

I4/O5

I4/O5F

PACNT

PAEN

PAIF

PAII

PAIS

PAMOD

PAOVF

PAOVI

PC[6:0]

Name

Input Capture 4/Output Compare 5

Flag

I4/O5 Interrupt Enable

Interrupt Arbitration

Input Capture Flags

Input Capture Interrupt Enable

Idle-Line Detected

Idle-Line Interrupt Enable

Interrupt Level for QSPI

Interrupt Level for SCI

Idle-Line Detect Type

Increment Prescaler

Interrupt Vector Number

Interrupt Priority Mask

Interrupt Priority Adjust

Interrupt Priority Level

Interrupt Vector Base Address

Loss of Clock Reset

QSPI Loop Mode

Loop Mode

Mode Select

Module Mapping

Asynchronous/Synchronous Mode

Mode Fault Flag

Master/Slave Mode Select

Negative Flag

New Queue Pointer Value

Noise Error

OC1 Data

OC1 Mask

Output Compare Flags

Output Compare Interrupt Enable

Output Compare Mode Bits

Output Compare Level Bits

Overrun Error

Pulse Accumulator Clock Select

(Gated Mode)

Pulse Accumulator Counter

Pulse Accumulator Enable

Pulse Accumulator Flag

Pulse Accumulator Input Interrupt

Enable

PAI Pin State (Read Only)

Pulse Accumulator Mode

Pulse Accumulator Overflow Flag

Pulse Accumulator Overflow Interrupt

Enable

Port C Data

Register Location

PACNT

TFLG1

PACNT

TFLG2

TMSK2

PACNT

TFLG2

TMSK2

PORTC

TMSK1

GPTMCR, QSMCR, SIMCR

TFLG1

TMSK1

SCSR

SCCR1

QILR

SCCR1

GPTMCR

QIVR

ICR

CSOR[0:10], CSORBT, ICR

ICR

RSR

SPCR3

SCCR1

SIMCR

CSOR[0:10], CSORBT

SPSR

SPCR0

CCR

SPCR2

SCSR

OC1D

OC1M

TFLG1

TMSK1

TCTL1

SCSR

PACNT

MC68331

USER’S MANUAL

REGISTER SUMMARY

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D-41

D-42

Freescale Semiconductor, Inc.

Table D-18 Register Bit and Field Mnemonics, (Continued)

POW

PPROUT

PPR[2:0]

PQS[7:0]

PQSPA[6:0]

PTP

RAF

RDRF

RIE

RR[0:F]

RSTEN

R/W

RWU

R[8:0]/T[8:0]

Mnemonic

PCLKS

PCS[3:0]

PE[7:0]

PEDGE

PEPA[7:0]

PF[7:0]

PFPA[7:0]

PORTGP[7:0]

PIRQL[2:0]

PITM[7:0]

PIV[7:0]

SBK

SCBR

SFA

SFB

SHEN[1:0]

SLIMP

SLOCK

SLVEN

SPACE

SPBR

SPE

SPIF

SPIFIE

STEXT

STOP

STOPP

STRB

Name

PCLK Pin State (Read Only)

Peripheral Chip Select

Parity Enable

Port E Data

Pulse Accumulator Edge Control

Port E Pin Assignment

Parity Error

Port F Data

Port F Pin Assignment

Port GP Data

Periodic Interrupt Request Level

Periodic Interrupt Timing Modulus

Periodic Interrupt Vector

Power-Up Reset

PWM Clock Output Enable

PWM Prescaler/PCLK Select

Port QS Data

Port QS Pin Assignment

Parity Type

Periodic Timer Prescaler Control

Receiver Active

Receive Data Register Full

Receiver Enable

Receiver Interrupt Enable

Receive Data RAM

Reset Enable

Read/Write

Receiver Wakeup

SCI Receive/Transmit Data

Supervisor/User State

Send Break

SCI Baud Rate

PWMA Slow/Fast Select

PWMB Slow/Fast Select

Show Cycle Enable

LIMP Mode

Synthesizer Lock

Factory Test Mode Enabled

Address Space Select

Serial Clock Baud Rate

QSPI Enable

QSPI Finished Flag

SPI Finished Interrupt Enable

Stop Mode External Clock

Stop Clocks

Stop Enable

Stop Prescaler

Address Strobe/Data Strobe

Register Location

PACNT

CR[0:F]

SCCR1

PORTE

PACNT

PEPAR

SCSR

PORTF

PFPAR

PORTGP

PICR

PITR

PICR

RSR

PWMC

PORTQS

PQSPAR

SCCR1

PITR

SCSR

SCCR1

QSPI RAM

SYNCR

CSOR[0:10], CSORBT

SCCR1

SCDR

SCCR1

SCCR0

PWMC

SIMCR

SYNCR

SIMCR

CSOR[0:10], CSORBT

SPCR0

SPCR1

SPSR

SPCR2

SYNCR

GPTMCR

QSMCR

GPTMCR

CSOR[0:10], CSORBT

REGISTER SUMMARY

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MC68331

USER’S MANUAL

Freescale Semiconductor, Inc.

Table D-18 Register Bit and Field Mnemonics, (Continued)

TOF

TOI

TR[0:F]

TST

WAKE

WOMQ

WOMS

WREN

WRTO

Y[5:0]

Mnemonic

STSIM

SUPV

SWE

SWP

SWT[1:0]

SYS

T[1:0]

TCIE

TDRE

TIE

Name

Stop Mode System Integration Clock

Supervisor/Unrestricted

Software Watchdog Reset

Software Watchdog Enable

Software Watchdog Prescale

Software Watchdog Timing

System Reset

Trace Enable

Transmit Complete

Transmit Complete Interrupt Enable

Transmit Data Register Empty

Transmitter Enable

Transmit Interrupt Enable

Timer Overflow Flag

Timer Overflow Interrupt Enable

Transmit Data RAM

Test Submodule Reset

Overflow Flag

Frequency Control (VCO)

Wakeup by Address Mark

Wired-OR Mode for QSPI Pins

Wired-OR Mode for SCI Pins

Wrap Enable

Wrap To

Extend

Frequency Control Bit (Prescale)

Frequency Control (Counter)

Zero Flag

Register Location

SYNCR

GPTMCR, QSMCR, SIMCR

RSR

SYPCR

RSR

SCSR

SCCR1

SCSR

SCCR1

TFLG2

TMSK2

QSPI RAM

RSR

CCR

SYNCR

SCCR1

SPCR0

SCCR1

SPCR2

CCR

SYNCR

CCR

MC68331

USER’S MANUAL

REGISTER SUMMARY

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D-43

Freescale Semiconductor, Inc.

D-44

REGISTER SUMMARY

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MC68331

USER’S MANUAL

Freescale Semiconductor, Inc.

INDEX

MC68331

USER’S MANUAL

INDEX

For More Information On This Product,

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I-1

Freescale Semiconductor, Inc.

I-2

INDEX

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MC68331

USER’S MANUAL