Intel® Server Board S2600IP and Intel® Workstation Board

Intel

®

Intel

®

Workstation Board W2600CR

Technical Product Specification

Intel order number G34153-003

Revision 1.2

October, 2013

Enterprise Platforms and Services Division - Marketing

ii

Revision History

Revision History

Date

February, 2012

June, 2012

October, 2013

Revision

Number

1.0

1.1

1.2

Modifications

Initial release.



Updated thermal management and environmental summary.



Updated onboard power connectors information.



Added support for Intel

®

Xeon

®

processor E5-2600 v2 product family



Updated memory support tables

Disclaimers

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WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR

INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature .

Intel order number G34153-003 Revision 1.2

Table of Contents

Table of Contents

1.

Introduction .......................................................................................................................... 1

1.1

Chapter Outline ........................................................................................................ 1

1.2

Server Board Use Disclaimer .................................................................................. 1

2.

Product Overview ................................................................................................................. 2

2.1

Product Feature Set ................................................................................................. 3

2.1.1

Main Board Connector and Component Layout ...................................................... 5

2.1.2

Main Board Rear I/O Layout .................................................................................... 8

2.1.3

Server Board Mechanical Drawings ...................................................................... 10

3.

Functional Architecture ..................................................................................................... 19

3.1

Processor Support ................................................................................................. 20

3.1.1

Processor Socket Assembly .................................................................................. 20

3.1.2

Processor Population Rules .................................................................................. 21

3.1.3

Processor Initialization Error Summary ................................................................. 22

3.2

Processor Functions Overview .............................................................................. 25

3.2.1

Intel

®

QuickPath Interconnect ................................................................................ 26

3.2.2

Integrated Memory Controller (IMC) and Memory Subsystem .............................. 26

3.2.3

Processor Integrated I/O Module (IIO) ................................................................... 32

3.3

Intel

®

C600-A Chipset Functional overview ........................................................... 34

3.3.1

Digital Media Interface (DMI) ................................................................................. 34

3.3.2

PCI Express* Interface .......................................................................................... 34

3.3.3

Serial ATA (SATA) Controller ................................................................................ 34

3.3.4

Serial Attached SCSI (SAS)/SATA (SCU) Controller ............................................. 35

3.3.5

AHCI ...................................................................................................................... 35

3.3.6

Rapid Storage Technology .................................................................................... 35

3.3.7

PCI Interface .......................................................................................................... 36

3.3.8

Low Pin Count (LPC) Interface .............................................................................. 36

3.3.9

Serial Peripheral Interface (SPI) ............................................................................ 36

3.3.10

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 36

3.3.11

Advanced Programmable Interrupt Controller (APIC) ........................................... 36

3.3.12

Universal Serial Bus (USB) Controllers ................................................................. 36

3.3.13

Gigabit Ethernet Controller .................................................................................... 36

3.3.14

RTC ....................................................................................................................... 37

3.3.15

GPIO ...................................................................................................................... 37

3.3.16

Enhanced Power Management ............................................................................. 37

3.3.17

Manageability ......................................................................................................... 37

3.3.18

System Management Bus (SMBus* 2.0) ............................................................... 37

3.3.19

Integrated NVSRAM controller .............................................................................. 37

3.3.20

Virtualization Technology for Directed I/O (Intel® VT-d) ........................................ 38

3.3.21

JTAG Boundary-Scan ............................................................................................ 38

Revision 1.2 Intel order number G34153-003 iii

Table of Contents

3.3.22

KVM/Serial Over Lan (SOL) Function .................................................................... 38

3.3.23

On-board SAS/SATA Support and Options ........................................................... 38

3.4

PCI Subsystem ...................................................................................................... 39

3.5

Network Interface Controller .................................................................................. 40

3.5.1

Network Interface ................................................................................................... 40

3.6

I/O Module Support (not avaiable for Intel

®

Server Board S2600IP4L and Intel

®

Workstation Board W2600CR2L) ............................................................................................ 41

3.7

3.8

3.9

3.10

SAS ROC Module Support .................................................................................... 42

HD Audio Support (Intel

®

Workstation Board W2600CR Only) ............................. 43

USB3.0 Support (Intel

®

Workstation Board W2600CR Only) ................................ 44

IEEE1394b Support (Intel

®

Workstation Board W2600CR Only) ........................... 45

4.

Platform Management Overview ....................................................................................... 46

4.1

Server Management Function Architecture ........................................................... 46

4.1.1

Feature Support ..................................................................................................... 46

4.1.2

Basic and Advanced Features ............................................................................... 48

4.1.3

Integrated BMC Hardware: Emulex* Pilot III .......................................................... 49

4.2

Server Management Functional Specifications ..................................................... 51

4.2.1

BMC Internal Timestamp Clock ............................................................................. 51

4.2.2

System Event Log (SEL) ....................................................................................... 52

4.2.3

Sensor Data Record (SDR) Repository ................................................................. 52

4.2.4

Field Replaceable Unit (FRU) Inventory Device .................................................... 52

4.2.5

BMC Beep Codes .................................................................................................. 52

4.2.6

Diagnostic Interrupt (NMI) Button .......................................................................... 53

4.2.7

BMC Watchdog ...................................................................................................... 53

4.3

Sensor Monitoring .................................................................................................. 54

4.3.1

Overview ................................................................................................................ 54

4.3.2

Core Sensor List for EPSD Platforms Based on Intel

®

Xeon

®

Processor E5

4600/2600/2400/1600/1400 Product Families ...................................................................... 54

4.3.3

BMC System Management Health Monitoring ....................................................... 55

4.3.4

Processor Sensors ................................................................................................ 56

4.4

Thermal and Acoustic Management ...................................................................... 59

4.4.1

Set Throttling Mode ............................................................................................... 60

4.4.2

Altitude ................................................................................................................... 60

4.4.3

Set Fan Profile ....................................................................................................... 60

4.4.4

Fan PWM Offset .................................................................................................... 60

4.4.5

Quiet Fan Idle Mode .............................................................................................. 60

4.4.6

Thermal Sensor Input for Fan Speed Control ........................................................ 61

4.4.7

Power Supply Status\Health Sensors .................................................................... 62

4.4.8

System Event Sensor ............................................................................................ 63

4.5

Platform Management Interface ............................................................................ 64

4.5.1

Channel Management ........................................................................................... 65

iv Intel order number G34153-003 Revision 1.2

Table of Contents

4.5.2

User Model ............................................................................................................ 65

4.5.3

LAN Interface ......................................................................................................... 65

4.6

BMC Firmware Update .......................................................................................... 75

4.6.1

The BMC firmware release Number ...................................................................... 75

4.6.2

Boot Recovery Mode ............................................................................................. 75

4.6.3

Force Firmware Update Jumper ............................................................................ 76

4.6.4

Fast Firmware Update over USB ........................................................................... 76

4.7

Advanced Management Feature Support .............................................................. 77

4.7.1

Enabling Advanced Management Features ........................................................... 77

4.7.2

Keyboard, Video, Mouse (KVM) Redirection ......................................................... 77

4.7.3

Media Redirection .................................................................................................. 78

4.8

Intel

®

Intelligent Power Node Manager (NM) ......................................................... 80

4.8.1

Overview ................................................................................................................ 80

4.9

EU Lot 6 Mode ....................................................................................................... 81

5.

System Security ................................................................................................................. 82

5.1

5.2

BIOS Password Protection .................................................................................... 82

Trusted Platform Module (TPM) Support ............................................................... 84

5.2.1

TPM security BIOS ................................................................................................ 84

5.2.2

Physical Presence ................................................................................................. 85

5.2.3

TPM Security Setup Options ................................................................................. 85

5.3

Intel

®

Trusted Execution Technology ..................................................................... 87

6.

Connector/Header Locations and Pin-outs ..................................................................... 88

6.1

Power Connectors ................................................................................................. 88

6.1.1

Main Power Connector .......................................................................................... 88

6.1.2

CPU Power Connectors ......................................................................................... 88

6.1.3

Add-in Card Power Connectors ............................................................................. 88

6.2

Front Panel Header and Connectors ..................................................................... 89

6.2.1

Front Panel Header ............................................................................................... 89

6.2.2

Front Panel USB Connector .................................................................................. 90

6.2.3

Local Control Panel Connector .............................................................................. 90

6.3

On Board Storage Connectors .............................................................................. 90

6.3.1

SATA Connectors: 6Gbps ..................................................................................... 90

6.3.2

Multiport Mini-SAS/SATA Connectors ................................................................... 91

6.3.3

Intel

®

RAID C600 Upgrade Key Connector ............................................................ 92

6.3.4

HSBP_I2C Header ................................................................................................. 92

6.3.5

HDD LED Header .................................................................................................. 92

6.3.6

Internal Type- A USB Connector ........................................................................... 92

6.3.7

Internal eUSB SSD Header ................................................................................... 93

6.4

Management and Security Connectors ................................................................. 93

6.4.1

RMM4_Lite Connector ........................................................................................... 93

6.4.2

RMM4_NIC Connector .......................................................................................... 93

Revision 1.2 Intel order number G34153-003 v

Table of Contents

6.4.3

TPM Connector ...................................................................................................... 94

6.4.4

PMBus* Connector ................................................................................................ 94

6.4.5

Chassis Intrusion Header ...................................................................................... 94

6.4.6

IPMB Connector .................................................................................................... 94

6.5

FAN Connectors .................................................................................................... 94

6.5.1

System FAN Connectors ....................................................................................... 95

6.5.2

CPU FAN Connector ............................................................................................. 95

6.6

Serial Port and Video Connectors ......................................................................... 95

6.6.1

Serial Port A Connector (DB9, for Intel

®

Server Board S2600IP only) .................. 95

6.6.2

Serial Port B Connector ......................................................................................... 96

6.6.3

Video Connector (For Intel

®

Server Board S2600IP only) ..................................... 96

6.6.4

Internal Video header (For Intel

®

Workstation Board W2600CR only) .................. 97

7.

Jumper Blocks .................................................................................................................... 98

7.1

BIOS Default and Password Reset Usage Procedure ........................................... 99

7.1.1

Set BIOS to default (Clearing the CMOS) ............................................................. 99

7.1.2

Clearing the Password ........................................................................................... 99

7.2

Force BMC Update Procedure ............................................................................ 100

7.3

BIOS Recovery Jumper ....................................................................................... 100

7.4

ME Force Update Jumper .................................................................................... 101

8.

Intel

®

Light Guided Diagnostics ...................................................................................... 102

8.1

8.2

5-volt Stand-by LED ............................................................................................. 102

Fan Fault LED ...................................................................................................... 102

8.3

8.4

CPU Fault LED .................................................................................................... 102

DIMM Fault LEDs ................................................................................................ 104

8.5

System ID LED, System Status LED and POST Code Diagnostic LEDs ............ 104

8.5.1

System ID LED .................................................................................................... 105

8.5.2

System Status LED .............................................................................................. 106

8.5.3

POST Code Diagnostic LEDs .............................................................................. 107

9.

Design and Environmental Specifications ..................................................................... 108

9.1

Products Design Specifications ........................................................................... 108

9.2

9.3

MTBF ................................................................................................................... 108

Server Board Power Requirements ..................................................................... 111

9.3.1

Processor Power Support .................................................................................... 112

9.4

Power Supply Output Requirements ................................................................... 112

9.4.1

Output Power/Currents ........................................................................................ 112

9.4.2

Cross Loading ...................................................................................................... 112

9.4.3

Standby Output .................................................................................................... 113

9.4.4

Voltage Regulation .............................................................................................. 113

9.4.5

Dynamic Loading ................................................................................................. 113

9.4.6

Capacitive Loading .............................................................................................. 114

9.4.7

Grounding ............................................................................................................ 114

vi Intel order number G34153-003 Revision 1.2

Table of Contents

9.4.8

Closed loop stability ............................................................................................. 114

9.4.9

Residual Voltage Immunity in Standby mode ...................................................... 114

9.4.10

Common Mode Noise .......................................................................................... 114

9.4.11

Soft Starting ......................................................................................................... 115

9.4.12

Zero Load Stability Requirements ....................................................................... 115

9.4.13

Ripple/Noise ........................................................................................................ 115

9.4.14

Timing Requirements ........................................................................................... 115

Appendix A: Integration and Usage Tips .............................................................................. 118

Appendix B: BMC Sensor Tables .......................................................................................... 119

Appendix C: Platform Specific BMC Appendix .................................................................... 140

Introduction ......................................................................................................................... 140

Product ID .......................................................................................................................... 140

IPMI Channel ID Assignments ........................................................................................... 140

ACPI S3 Sleep State Support ............................................................................................ 140

Processor Support for Intel

®

Server Board S2600IP .......................................................... 140

Supported Chassis ............................................................................................................. 140

Chassis-specific sensors .................................................................................................... 141

Hot-plug fan support ........................................................................................................... 141

Fan redundancy support .................................................................................................... 141

Fan domain definition ......................................................................................................... 142

HSC Availability .................................................................................................................. 144

Power unit support ............................................................................................................. 145

Redundant Fans only for Intel

®

Server Chassis ................................................................. 145

Fan Fault LED support ....................................................................................................... 145

Memory Throttling support ................................................................................................. 146

Introduction ......................................................................................................................... 146

Product ID .......................................................................................................................... 146

IPMI Channel ID Assignments ........................................................................................... 146

ACPI S3 Sleep State Support ............................................................................................ 146


®

Server Board W2600CR ....................................................... 147

Supported Chassis ............................................................................................................. 147

Chassis-specific sensors .................................................................................................... 147

Hot-plug fan support ........................................................................................................... 147

Fan redundancy support .................................................................................................... 147

Board specific feature ......................................................................................................... 147

Fan domain definition ......................................................................................................... 147

HSC Availability .................................................................................................................. 148

Revision 1.2 Intel order number G34153-003 vii

Table of Contents

Power unit support ............................................................................................................. 148


®

Server Chassis ................................................................. 148

Fan Fault LED support ....................................................................................................... 148

Memory Throttling support ................................................................................................. 148

Appendix D: POST Code Diagnostic LED Decoder ............................................................. 149

Appendix E: POST Error Messages and Handling .............................................................. 155

Glossary ................................................................................................................................... 162

Reference Documents ............................................................................................................ 165

viii Intel order number G34153-003 Revision 1.2

List of Figures

List of Figures

Figure 1. Intel

®

Server Board S2600IP ......................................................................................... 2

Figure 2. Intel

®

Workstation Board W2600CR .............................................................................. 2

Figure 3. Intel

®

Server Board S2600IP Major Components .......................................................... 6

Figure 4. Intel

®

Server Board S2600IP Rear I/O Layout ............................................................... 8

Figure 5. Intel

®

Workstation Board W2600CR Rear I/O Layout .................................................... 9

Figure 6. Mounting Hole Locations (1 of 2) ................................................................................. 10

Figure 7. Mounting Hole Locations (2 of 2) ................................................................................. 11

Figure 8. Major Connector Pin-1 Locations (1 of 3) .................................................................... 12

Figure 9. Major Connector Pin-1 Locations (2 of 3) .................................................................... 13

Figure 10. Major Connector Pin-1 Locations (3 of 3) .................................................................. 14

Figure 11. Primary Side Keep-out Zone ..................................................................................... 16

Figure 12. Primary Side Card-Side Keep-out Zone .................................................................... 17

Figure 13. Second Side Keep-out Zone ...................................................................................... 18

Figure 14. Intel

®

Server Board S2600IP Functional Block Diagram ........................................... 19

Figure 15. Intel

®

Workstation Board W2600CR Functional Block Diagram ................................ 20

Figure 16. Processor Socket Assembly ...................................................................................... 21

Figure 17. Processor Socket ILM ................................................................................................ 21

Figure 18. Integrated Memory Controller Functional Block Diagram .......................................... 26

Figure 19. DIMM Slot Layout ...................................................................................................... 30

Figure 20. External RJ45 NIC Port LED Definition ..................................................................... 41

Figure 21. Supported I/O Module Options .................................................................................. 42

Figure 22. USB3.0 Discrete Host Controller Block Diagram ....................................................... 44

Figure 23. IEEE 1394b Discrete Host Controller Block Diagram ................................................ 45

Figure 24. Integrated BMC Hardware ......................................................................................... 51

Figure 25. High-level Fan Speed Control Process ...................................................................... 61

Figure 26. Setup Utility

– TPM Configuration Screen ................................................................. 86

Figure 27. Video Connector Pin-out ............................................................................................ 96

Figure 28. Jumper Blocks (J1C3, J1F1, J1F2, J2F3, J2F2) ....................................................... 98

Figure 29. Stand by LED, Fan Fault LED and CPU Fault LED Location .................................. 103

Figure 30. DIMM Fault LED’s Location ..................................................................................... 104

Figure 31. Location of System Status, System ID and POST Code Diagnostic LEDs .............. 105

Figure 32. Power Distribution Block Diagram ........................................................................... 111

Figure 33. Differential Noise test setup ..................................................................................... 115

Figure 34. Output Voltage Timing ............................................................................................. 116

Figure 35. Turn On/Off Timing (Power Supply Signals) ............................................................ 117

Figure 36. POST Code Diagnostic LED Decoder ..................................................................... 149

Revision 1.2 Intel order number G34153-003 ix

x

List of Tables

List of Tables

Table 1. Product Feature Set ........................................................................................................ 3

Table 2. Mixed Processor Configurations Error Summary. ......................................................... 23

Table 3. UDIMM Support Guidelines .......................................................................................... 27

Table 4. RDIMM Support Guidelines .......................................................................................... 28

Table 5. LRDIMM Support Guidelines ........................................................................................ 29

Table 6. DIMM Nomenclature ..................................................................................................... 30

Table 7. Intel

®

RAID C600 Upgrade Key Options ....................................................................... 35

Table 8. Intel

®

Server Board S2600IP/Workstation Board W2600CR PCI Bus Segment

Characteristics ...................................................................................................................... 39

Table 9. Supported Intel

®

Integrated RAID Modules ................................................................... 43

Table 10. Standard Speaker Channels ....................................................................................... 44

Table 11. Basic and Advanced Features .................................................................................... 48

Table 12. BMC Beep Codes ....................................................................................................... 52

Table 13. NMI Signal Generation and Event Logging ................................................................. 53

Table 14. Supported BMC FW Health Sensor Offsets ................................................................ 56

Table 15. Processor Sensors ...................................................................................................... 56

Table 16. Processor Status Sensor Implementation ................................................................... 56

Table 17. Supported ERR2 Timeout Sensor Offsets .................................................................. 58

Table 18. Supported CATERR Sensor Offsets ........................................................................... 59

Table 19. Support MSID Mismatch Sensor Offsets .................................................................... 59

Table 20. Supported Power Supply Status Sensor Offsets ........................................................ 62

Table 21. Support System Event Sensor Offsets ....................................................................... 63

Table 22. Supported Firmware Update Status Sensor Offsets ................................................... 64

Table 23. Standard Channel Assignments ................................................................................. 65

Table 24. Supported RMCP+ Cipher Suites ............................................................................... 66

Table 25. Supported RMCP+ Payload Types ............................................................................. 66

Table 26. Factory Configured PEF Table Entries ....................................................................... 71

Table 27. Enabling Advanced Management Features ................................................................ 77

Table 28. TSetup Utility

– Security Configuration Screen Fields ................................................ 86

Table 29. Main Power Connector Pin-out ................................................................................... 88

Table 30. CPU_1 Power Connector Pin-out ............................................................................... 88

Table 31. CPU_2 Power Connector Pin-out ............................................................................... 88

Table 32. Add-in Slot Power Pin-input ("OPT_12V_PWR") ........................................................ 89

Table 33. Front Panel Header Pin-out ........................................................................................ 89

Table 34. Front Panel USB Connector Pin-out ........................................................................... 90

Table 35. Local Front Panel Connector Pin-out .......................................................................... 90

Table 36. SATA 6Gbps Connector Pin-out ................................................................................. 90


List of Tables

Table 37. Multiport SAS/SATA Connector Pin-out ("SCU_0 (0-3)") ............................................ 91

Table 38. Multiport SAS/SATA Connector Pin-out ("SCU_1 (4-7)") ............................................ 91

Table 39. Intel

®

RAID C600 Upgrade Key Connector Pin-out .................................................... 92

Table 40. HSBP_I2C Header Pin-out ......................................................................................... 92

Table 41. HDD LED Header Pin-out ........................................................................................... 92

Table 42. Type-A USB Connector Pin-out .................................................................................. 92

Table 43. eUSB SSD Header Pin-out ......................................................................................... 93

Table 44. RMM4_Lite Connector Pin-out .................................................................................... 93

Table 45. RMM4_NIC Connector Pin-out ................................................................................... 93

Table 46. TPM Connector Pin-out .............................................................................................. 94

Table 47. PMBus* Connector Pin-out ......................................................................................... 94

Table 48. Chassis Intrusion Header Pin-out ............................................................................... 94

Table 49. IPMB Connector Pin-out ............................................................................................. 94

Table 50. 6-pin System FAN Connector Pin-out ......................................................................... 95

Table 51. 4-pin System FAN Connector Pin-out ......................................................................... 95

Table 52. CPU FAN Connector Pin-out ...................................................................................... 95

Table 53. Serial Port A Connector Pin-out .................................................................................. 95

Table 54. Serial Port B Connector Pin-out .................................................................................. 96

Table 55. Video Connector Pin-out details ................................................................................. 96

Table 56. Server Board Jumpers (J1C3, J1F1, J1F2, J2F3, J2F2) ............................................ 98

Table 57. System Status LED ................................................................................................... 106

Table 58. POST Code Diagnostic LEDs ................................................................................... 107

Table 59. Server Board Design Specifications ......................................................................... 108

Table 60. Intel

®

Server Board S2600IP MTBF Estimate ........................................................... 109

Table 61. Intel

®

Workstation Board W2600CR MTBF Estimate ................................................ 109

Table 62. Intel

®

Xeon

®

Processor Dual Processor TDP profile ................................................. 112

Table 63. Minimum Load Ratings ............................................................................................. 112

Table 64. Loading Conditions ................................................................................................... 113

Table 65.Voltage Regulation Limits .......................................................................................... 113

Table 66. Transient Load Requirements ................................................................................... 113

Table 67. Capacitive Loading Conditions ................................................................................. 114

Table 68. Ripples and Noise ..................................................................................................... 115

Table 69. Output Voltage Timing .............................................................................................. 116

Table 70. Turn On/Off Timing ................................................................................................... 116

Table 71. Integrated BMC Core Sensors .................................................................................. 121

Table 72. Intel

®

Server Board S2600IP - BMC Channel Assignments ..................................... 140

Table 73. Intel

®

Server Board S2600IP - Chassis-specific Sensors ......................................... 141

Table 74. Intel

®

Server Board S2600IP - Fan Domain Definition .............................................. 142

Table 75. Intel

®

Server Chassis P4208/P4216/P4224/P4308 (UPL) Power support ................ 145

Table 76. Intel

®

Server Chassis R2208/R2216/R2224/R2308/R2312 (BHP) Power support ... 145

Table 77. Intel

®

Workstation Board W2600CR - BMC Channel Assignments .......................... 146

Revision 1.2 Intel order number G34153-003 xi

List of Tables

Table 78. Intel

®

Workstation Board W2600CR - Chassis-specific sensors ............................... 147

Table 79. Intel

®

Workstation Board W2600CR - Fan domain definition .................................... 147

Table 80. Intel

®

Server Chassis P4304 (UPL) Power support .................................................. 148

Table 81. POST Progress Code LED Example ........................................................................ 150

Table 82. POST Progress Codes ............................................................................................. 150

Table 83. MRC Progress Codes ............................................................................................... 152

Table 84. MRC Fatal Error Codes ............................................................................................ 153

Table 85. POST Error Codes and Messages ........................................................................... 155

Table 86. POST Error Beep Codes .......................................................................................... 160

Table 87. Integrated BMC Beep Codes .................................................................................... 161

xii Intel order number G34153-003 Revision 1.2

<This page is intentionally left blank.>

List of Tables

Revision 1.2 Intel order number G34153-003 xiii

Introduction

1. Introduction

This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel

®

Server Board S2600IP and Intel

®

Workstation Board

W2600CR.

In addition, you can obtain design-level information for a given subsystem by ordering the External

Product Specifications (EPS) for the specific subsystem. EPS documents are not publicly available and you must order them through your local Intel representative.

1.1 Chapter Outline

This document is divided into the following chapters:

































Chapter 1

– Introduction

Chapter 2

– Product Overview

Chapter 3

– Functional Architecture

Chapter 4

– Platform Management Overview

Chapter 5

– System Security

Chapter 6

– Connector/Header Locations and Pin-outs

Chapter 7

– Jumper Blocks

Chapter 8

– Intel ®

Light Guided Diagnostics

Chapter 9

– Design and Environmental Specifications

Appendix A: Integration and Usage Tips

Appendix B: BMC Sensor Tables

Appendix C: Platform Specific BMC Appendix

Appendix D: POST Code Diagnostic LED Decoder

Appendix E: POST Error Messages and Handling

Glossary

Reference Documents

1.2 Server Board Use Disclaimer

Intel

®

Server Boards contain a number of high-density VLSI (Very-large-scale integration) and power delivery components that require adequate airflow for cooling. Intel ensures through its own chassis development and testing that when Intel

®

server building blocks are used together, the fully integrated system meets the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of the published operating or nonoperating limits.

Revision 1.2 Intel order number G34153-003 1

Product Overview

2. Product Overview

The Intel

®


®

Workstation Board W2600CR are Enterprise I/O Rich platforms for Pedestal and Rack Server and workstation market.

Figure 1. Intel

®

Server Board S2600IP

Figure 2. Intel

®

Workstation Board W2600CR

2 Intel order number G34153-003 Revision 1.2

Product Overview

2.1 Product Feature Set

Board Name

Processors

Chipset

Table 1. Product Feature Set

Intel

®



Support for one or two Intel

2600 Processor(s) and Intel

®

®

Xeon

®

E5-

Xeon

®

E5-

2600 v2 Processor(s)



8 GT/s Intel

®

Quick Path Interconnect

(Intel

®

QPI)

Intel

®



Support for one or two Intel

®

Xeon

®

2600 Processor(s) and Intel

®

Xeon

®

E5-

E5-

2600 v2 Processor(s)



8 GT/s Intel

®

Quick Path Interconnect (Intel

®

QPI)



LGA 2011 Socket



Thermal Design Power up to 135 W





LGA 2011 Socket

Thermal Design Power up to 150 W

Intel

®

C600-A chipset with support for optional Intel

®

C600 RAID Upgrade Keys

Memory

Slots

 16 DDR3 DIMMs with 800MT/s, 1067MT/s, 1333MT/s,1600MT/s, *1866MT/s

 Eight memory channels (four channels for each processor socket)

 Channels A, B, C, D, E, F, G and H

 Support for Registered DDR3 Memory (RDIMM), Unbuffered DDR3 memory ((UDIMM) and

Load Reduced DDR3 memory (LRDIMM)

 DDR3 standard I/O voltage of 1.5V and DDR3 Low Voltage of 1.35V

 Slot 1: PCIe Gen3 x16, connector from first processor.



 Slot 4: PCIe Gen3 x8, connector from second processor.

 Slot 5: PCIe Gen3 x16, connector from second processor.

 Slot 6: PCIe Gen3 x8, connector, from second processor

 Slot 7: PCIe Gen3 x16,connector, from second processor

 Slot 8: PCIe Gen2 x4 electrical with x8 physical connector, from second processor

IOM Connector: I/O Module (optional with Flex Cable*)

Notes: The IOM connector is not available for all boards and only supports PCIe Gen1 Speed

SM Conn: SAS Module (optional)

 6Gbps or 12Gbps SAS ROC module Options

Ethernet

On-board storage controllers and options

Video

Intel

®

I350 Quad 1GbE fully integrated GbE

MAC and PHY Network Controller

Intel

®

I350 Dual 1GbE fully integrated GbE MAC and PHY Controller

 One eUSB 2x5 pin connector to support 2mm low-profile eUSB solid state devices

 Two 7-pin single port AHCI SATA connectors capable of supporting up to 6 GB/sec

 Two SCU 4-port mini-SAS connectors capable of supporting up to 3 GB/sec SAS/SATA

 Intel

®

Integrated RAID module support (Optional)

 Intel

®

RAID C600 Upgrade Key support providing optional expanded SATA/SAS RAID capabilities



Integrated Matrox* G200 2D Video

Graphics controller



1 Rear VGA port





Integrated Matrox* G200 2D Video

Graphics controller

1 Internal VGA connector


Product Overview

Board Name

Audio

I/O

Server

Management

Security

None

Intel

®

Intel

®

ALC889 HD Audio (7.1 + S/PDIF Out)



4 Rear USB2.0 1 Rear Serial A



4 Rear USB2.0 2 Rear USB3.0



2 Type A USB2.0 Connectors



1 Internal Serial B



2 Type A USB2.0 Connector



1 1394b Connector



1 Internal Serial B



Onboard Server Engines* LLC Pilot III* Controller



Support for Intel

®

Remote Management Module 4 solutions



Intel

®

Light-Guided Diagnostics on field replaceable units



Support for Intel

®

System Management Software



Support for Intel

®

Intelligent Power Node Manager (Need PMBus*-compliant power supply)

Intel

®

Trusted Platform Module (TPM) - AXXTPME5 (accessory option)

Power-Supply 750W/1200W/1600W Common Redundant Power-Supply with PMBus* Support

Supported Suspend to RAM

(S3)

Form Factor

Chassis

None

Custom 14.2'' W x 15.0'' D

Pedestal: P4000L chassis

2U Rack: R2000 chassis

Pedestal: P4000L WS chassis

*1866MT/s is only for

Intel

®

Xeon

®



Product Overview

2.1.1 Main Board Connector and Component Layout

The following figure shows the layout of the server board. Each connector and major component is identified by a number or letter, and a description is given below the figure.

Callout

A

B

C

D

E

F

G

H

I

J

K

Description

Slot 1, PCI Express* Gen3

RMM4 lite module connector


TPM



RMM4 Connector


Battery



Revision 1.2 Intel order number G34153-003

Callout

AD

AE

AF

AG

AH

AI

AJ

AK

AL

AM

AN

Description

DIMM C1/C2/D1/D2

System Fan connector 1/2/3/4/5/6

Type A USB connector


ROC Module connector

LCP connector

Front Panel connector

Front Panel USB connector

Main Power 4-pin connector

MinISAS Port B(4-7)

MiniSAS Port A(0-3)

5

Product Overview

W

X

Y

Z

S

T

U

V

Callout

L

M

N

O

P

Q

R

Description


DIMM E1/E2/F1/F2

Status LED

ID LED

Diagnostic LED

NIC 3/4 (S2600IP only)

USB 2/3, NIC 2

USB 0/1, NIC 1

VGA Port (S2600IP only)

Serial Port A (S2600IP only)

Processor 2 Power connector

Processor 2 Fan connector

DIMM H2/H1/G2/G1

PMBus* connector

Main Power connector

AA Processor 1 Power connector

AB DIMM B2/B1/A2/A1

AC Processor 1 Fan connector

AV

AW

AX

AY

AZ

BA

BB

BC

Callout

AO

AP

AQ

AR

AS

AT

AU

BD

BE

SATA Port 1

SATA Port 0

CPLD Update

Description

IPMB

HDD LED

ME FRC UPDT

CMOS CLR

BIOS RCVRY

PASSWD CLR

Storage Upgrade Key eUSB SSD

HSBP connector

Chassis intrusion

Serial B connector

BMC Force Update

I/O Module connector (not available for S2600IP4L)

System Fan connector 7

Figure 3. Intel

®

Server Board S2600IP Major Components


Product Overview

G

H

I

J

K

L

M

Callout

A

B

C

D

E

F

N

O

P

Description


RMM4 Lite module


TPM



RMM4 Connector


Battery




DIMM E1/E2/F1/F2

Status LED

ID LED

Diagnostic LED


AK

AL

AM

AN

AO

AP

AQ

Callout

AE

AF

AG

AH

AI

AJ

AR

AS

AT

Description

DIMM C1/C2/D1/D2

System Fan connector 1/2/3/4/5/6



ROC Module connector

LCP connector

Front Panel connector

Front Panel USB connector

Main Power 4-pin connector

1394b connector(W2600CR only)

MiniSAS Port B(4-7)

MiniSAS Port A(0-3)

SATA Port 1

SATA Port 0

CPLD Update

IPMB

7

Product Overview

Callout

Q

R

S

T

U

V

W

SPDIF connector

USB 2/3, NIC 2

USB 0/1, NIC 1

Description

USB3.0 0/1(W2600CR only)

HD Audio (W2600CR only)

Processor 2 Power connector

Front Audio connector

X

Y

Processor 2 Fan connector

DIMM H2/H1/G2/G1

Z PMBus* connector

AA Main Power connector

AB Processor 1 Power connector

AC DIMM B2/B1/A2/A1

AD Processor 1 Fan connector

Callout

AU

AV

AW

AX

AY

AZ

BA

BB

BC

BD

BE

BF

BG

BH

Description

HDD LED

ME FRC UPDT

CMOS CLR

BIOS RCVRY

PASSWD CLR

Storage Upgrade Key eUSB SSD

HSBP connector

Chassis intrusion

Serial B connector

BMC Force Update

I/O Module connector (not available for W2600CR2L)

Internal video connector

System Fan connector 7

Figure 3. Intel

®

Workstation Board W2600CR Major Components

2.1.2 Main Board Rear I/O Layout

The following drawing shows the layout of the rear I/O components for the server boards.

Callout

A

B

C

D

Description

Serial Port A

Video Port

NIC Port 1, USB Port 0 (bottom) and 1

(top)


(top)

Callout

E

F

G

H

Description

NIC Port 3(top) and 4(bottom)

Diagnostics LED’s

ID LED

Status LED

Figure 4. Intel

®

Server Board S2600IP Rear I/O Layout


Callout

A

B

C

D

Description

7.1 Channel HD Audio Jack Connector

USB3.0 Port 0(bottom) and 1(top)


(top)


(top)

Callout

E

F

Description

Diagnostics LED’s

ID LED

G Status LED

Figure 5. Intel

®

Workstation Board W2600CR Rear I/O Layout

Product Overview


Product Overview

2.1.3 Server Board Mechanical Drawings

10

Figure 6. Mounting Hole Locations (1 of 2)


Product Overview

Figure 7. Mounting Hole Locations (2 of 2)


Product Overview

12

Figure 8. Major Connector Pin-1 Locations (1 of 3)


Product Overview



Product Overview

14



Product Overview


Product Overview

Figure 11. Primary Side Keep-out Zone


Product Overview

Figure 12. Primary Side Card-Side Keep-out Zone


Product Overview

Figure 13. Second Side Keep-out Zone


Functional Architecture

3. Functional Architecture

The architecture and design of the Intel

®

Server Board S2600IP and Intel is based on the Intel

®

Sandy Bridge-EP Processor series in an LGA 2011 Socket with Intel

®

®


C600-A chipset. The chipset is designed for systems based on the Intel

®

Xeon

®

Quick Path Interconnect (Intel

®

QPI) speed at 8GT/s.

This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards.

Revision 1.2

Figure 14. Intel

®

Server Board S2600IP Functional Block Diagram

Intel order number G34153-003 19


Figure 15. Intel

®

Workstation Board W2600CR Functional Block Diagram

3.1 Processor Support

The server board includes two Socket-R (LGA2011) processor sockets and can support one or two of the following processors - Intel

®

Xeon

®

processor E5-2600 and E5-2600 v2 product family with a Thermal

Design Power (TDP) of up to 150W.

Note: The 150w TDP processor is only supported on Intel

®

Workstation Board W2600CR and Intel

®

Server Board S2600IP only supports up to 135W TDP processors. Previous generation Intel

®

Xeon

® processors are not supported on the Intel server boards described in this document.

For a complete updated list of supported processors, please visit the support website.

3.1.1 Processor Socket Assembly

Each processor socket of the server board is pre-assembled with an Independent Latching Mechanism

(ILM) and Back Plate which allow for secure placement of the processor and processor heat to the server board. The illustration below identifies each sub-assembly component.



Heat Sink

Server Board

Independent Latching

Mechanism (ILM)

Back Plate

Figure 16. Processor Socket Assembly

80mm

80mm

Figure 17. Processor Socket ILM

The square ILM has an 80x80mm heat sink mounting hole pattern and is used on the Intel

®

Server Board

S2600IP and Intel

®

Workstation Board W2600CR.

Note: Processor Thermal solutions for the Intel

®

Workstation Board W2600CR are NOT the same with

Intel

®

Server Board S2600IP when install 150W TDP Processors.

3.1.2 Processor Population Rules

Note: Although the server board does support dual-processor configurations consisting of different processors that meet the defined criteria below, Intel does not perform validation testing of this configuration.

For optimal system performance in dual-processor configurations, Intel recommends that identical processors be installed.



When using a single processor configuration, the processor must be installed into the processor socket labeled

“CPU_1”.

When two processors are installed, the following population rules apply:













Both processors must be of the same processor family.

Both processors must have the same number of cores.

Both processors must have the same cache sizes for all levels of processor cache memory.

Processors with different core frequencies can be mixed in a system, given the prior rules are met. If this condition is detected, all processor core frequencies are set to the lowest common denominator (highest common speed) and an error is reported.

Processors which have different QPI link frequencies may operate together if they are otherwise compatible and if a common link frequency can be selected. The common link frequency would be the highest link frequency that all installed processors can achieve.

Processor stepping within a common processor family can be mixed as long as it is listed in the processor specification updates published by Intel Corporation.

3.1.3 Processor Initialization Error Summary

The following table describes mixed processor conditions and recommended actions for all Intel

® server boards and Intel server systems designed around the Intel

®

Xeon

® processor E5-2600 and E5-

2600 v2 product family and Intel

®

C600 chipset product family architecture. The errors fall into one of the following three categories:



Fatal: If the system can boot, it pauses at a blank screen with the text

“Unrecoverable

fatal error found. System will not boot until the error is resolved” and “Press <F2>

to enter setup”, regardless of whether the “Post Error Pause” setup option is enabled or disabled.

When the operator presses the <F2> key on the keyboard, the error message is displayed on the Error Manager screen, and an error is logged to the System Event Log

(SEL) with the POST Error Code.

The system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.

For Fatal Errors during processor initialization, the System Status LED will be set to a steady Amber color, indicating an unrecoverable system failure condition.



Major:

If the “Post Error Pause” setup option is enabled, the system goes directly to the

Error Manager to display the error, and logs the POST Error Code to SEL. Operator intervention is required to continue booting the system.

Otherwise, if “POST Error Pause” is disabled, the system continues to boot and no prompt is given for the error, although the Post Error Code is logged to the Error

Manager and in a SEL message.





Minor: The message is displayed on the screen or on the Error Manager screen, and the POST Error Code is logged to the SEL. The system continues booting in a degraded state. The user may want to replace the erroneous unit. The POST Error Pause option setting in the BIOS setup does not have any effect on this error.

Table 2. Mixed Processor Configurations Error Summary.

Error

Processor family not Identical

Processor model not Identical

Processor cores/threads not identical Fatal

Processor cache not identical

Severity

Fatal

Fatal

Fatal

System Action

The BIOS detects the error condition and responds as follows:

 Logs the POST Error Code into the System Event Log (SEL).

 Alerts the BMC to set the System Status LED to steady Amber.

 Displays “0194: Processor family mismatch detected” message in the Error Manager.

 Takes Fatal Error action (see above) and will not boot until the fault condition is remedied.


 Logs the POST Error Code into the System Event Log (SEL).


 Displays “0196: Processor model mismatch detected” message in the Error Manager.



 Logs the POST Error Code into the SEL.


 Displays “0191: Processor core/thread count mismatch

detected

” message in the Error Manager.

Takes Fatal Error action (see above) and will not boot until the fault condition is remedied.






Displays “0192: Processor cache size mismatch detected message in the Error Manager.




Processor Intel QuickPath

Interconnect link frequencies not identical

®

Error

Processor frequency (speed) not identical

Processor microcode update missing

Processor microcode update failed

Severity

Fatal

Fatal

Minor

Major

System Action

The BIOS detects the processor frequency difference, and responds as follows:

 Adjusts all processor frequencies to the highest common frequency.

 No error is generated – this is not an error condition.

 Continues to boot the system successfully.

If the frequencies for all processors cannot be adjusted to be the

same, then this is an error, and the BIOS responds as follows:



 Does not disable the processor.

 Displays “0197: Processor speeds unable to synchronize” message in the Error Manager.


The BIOS detects the QPI link frequencies and responds as follows:

 Adjusts all QPI interconnect link frequencies to highest common frequency.

 No error is generated

– this is not an error condition.

 Continues to boot the system successfully.

If the link frequencies for all QPI links cannot be adjusted to be the

same, then this is an error, and the BIOS responds as follows:



 Displays “0195: Processor Intel(R) QPI link frequencies

unable to synchronize

” message in the Error Manager.

 Does not disable the processor.




 Displays “818x: Processor 0x microcode update not found” message in the Error Manager or on the screen.

 The system continues to boot in a degraded state, regardless of the setting of POST Error Pause in the Setup.





Displays “816x: Processor 0x unable to apply microcode

update

” message in the Error Manager or on the screen.

Takes Major Error action. The system may continue to boot in a degraded state, depending on the setting of POST Error Pause in

Setup, or may halt with the POST Error Code in the Error Manager waiting for operator intervention.



3.2 Processor Functions Overview

With the release of the Intel

®

Xeon

®

processor E5-2600 and E5-2600 v2 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and

Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; two Intel

®

QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to

40 lanes of Gen 3 PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express*

Gen 2 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space.

The following sections will provide an overview of the key processor features and functions that help to define the performance and architecture of the server board. For more comprehensive processor specific information, refer to the Intel

®

Xeon

®

processor E5-2600 and E5-2600 v2 product family documents listed in the Reference Document list.

Processor Feature Details:



Up to 8 execution cores for Intel

®

Xeon

®

processor E5-2600 product family





Up to 12 execution cores for Intel

®

Xeon

®


Each core supports two threads (Intel

®

Hyper-Threading Technology), up to 16 threads per socket for E5-2600 and 24 threads per socket for E5-2600 v2











46-bit physical addressing and 48-bit virtual addressing

1 GB large page support for server applications

A 32-KB instruction and 32-KB data first-level cache (L1) for each core

A 256-KB shared instruction/data mid-level (L2) cache for each core

Up to 20 MB last level cache (LLC) for E5-2600: up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores



Up to 30 MB last level cache (LLC) for E5-2600 v2: up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores

Supported Technologies:



Intel

®

Virtualization Technology (Intel

®

VT)





Intel

®

Virtualization Technology for Directed I/O (Intel

®

VT-d)

Intel

®

Virtualization Technology

“Sandy Bridge” Processor Extensions









Intel

®

Trusted Execution Technology (Intel

®

TXT)

Intel

®

64 Architecture

Intel

®

Streaming SIMD Extensions 4.1 (Intel

®

SSE4.1)

Intel

®

Streaming SIMD Extensions 4.2 (Intel

®

SSE4.2)





Intel

®

Advanced Vector Extensions (Intel

®

AVX)

Intel

®

Hyper-Threading Technology









Execute Disable Bit

Intel

®

Turbo Boost Technology

Intel

®

Intelligent Power Technology

Enhanced Intel

®

SpeedStep Technology



3.2.1 Intel

®

QuickPath Interconnect

The Intel

®

QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency. The Intel

®

QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture.

The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock. Each port supports a link pair consisting of two unidirectional links to complete the connection between two components. This supports traffic in both directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and Protocol.

The Intel

®

QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation. It supports both low-latency source snooping and a scalable home snoop behavior. The coherency protocol provides for direct cache-to-cache transfers for optimal latency.

3.2.2 Integrated Memory Controller (IMC) and Memory Subsystem

CPU 1

CPU 2

Integrated into the processor is a memory controller. Each processor provides four DDR3 channels that support the following:

Figure 18. Integrated Memory Controller Functional Block Diagram

















Unbuffered DDR3 and registered DDR3 DIMMs

LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher capacity memory subsystems

Independent channel mode or lockstep mode

Data burst length of eight cycles for all memory organization modes

Memory DDR3 data transfer rates of 800, 1066, 1333, 1600 and 1866* MT/s

64-bit wide channels plus 8-bits of ECC support for each channel

DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V

1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices: o UDIMM DDR3

– SR x8 and x16 data widths, DR – x8 data width o RDIMM DDR3

– SR,DR, and QR – x4 and x8 data widths o LRDIMM DDR3

– QR – x4 and x8 data widths with direct map or with rank multiplication























3.2.2.1

Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM

Open with adaptive idle page close timer or closed page policy

Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern

Isochronous access support for Quality of Service (QoS)

Minimum memory configuration: independent channel support with 1 DIMM populated

Integrated dual SMBus* master controllers

Command launch modes of 1n/2n

RAS Support: o Rank Level Sparing and Device Tagging o Demand and Patrol Scrubbing o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device.

Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in lockstep mode o Data scrambling with address to ease detection of write errors to an incorrect address. o Error reporting from Machine Check Architecture o Read Retry during CRC error handling checks by iMC o Channel mirroring within a socket



CPU1 Channel Mirror Pairs (A,B) and (C,D)



CPU2 Channel Mirror Pairs (E,F) and (G,H) o Error Containment Recovery

Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)

Memory thermal monitoring support for DIMM temperature

*1866MT/s is only supported for E5-2600 v2 product family

Supported Memory

Table 3. UDIMM Support Guidelines

Ranks Per

DIMM and

Data Width

Memory Capacity Per

DIMM

1

Speed (MT/s) and Voltage Validated by

Slot per Channel (SPC) and DIMM Per Channel (DPC)

2,3

2 Slots per Channel

1DPC

1.35V 1.5V

Intel

®

Xeon

®


1.35V

2DPC

1.5V

SRx8

ECC

DRx8

ECC

1GB

2GB

2GB

4GB

4GB

8GB

1066,1333

1066,1333

1066, 1333

1066, 1333

1066

1066

1066, 1333

1066, 1333

SRx8

ECC

1GB 2GB

Intel

®

Xeon

®


4GB 1066,1333

1066, 1333,

1600, 1866

1066, 1333 1066, 1333, 1600

DRx8

ECC

2GB 4GB 8GB 1066,1333

1066, 1333,

1066, 1333 1066, 1333, 1600

1600,1866

Notes:

1. Supported DRAM Densities are 1Gb, 2Gb and 4Gb. Only 2Gb and 4Gb are validated by Intel.

2. Command Address Timing is 1N for 1DPC and 2N for 2DPC.



Supported and Validated

Supported but not Validate

Table 4. RDIMM Support Guidelines

Ranks Per DIMM and Data Width

SRx8

DRx8

Memory Capacity Per DIMM

1



2

2 Slots per Channel

1DPC

1.35V 1.5V

Intel

®

Xeon

®


1.35V

2DPC

1GB 2GB 4GB 1066, 1333

1.5V

1066, 1333, 1600

1066, 1333

1066, 1333, 1600

2GB 4GB 8GB 1066, 1333 1066, 1333, 1600

1066, 1333

1066, 1333, 1600

SRx4

DRx4

QRx4

QRx8

2GB

4GB

8GB

4GB

4GB

8GB

16GB

8GB

8GB

16GB

32GB

16GB

1066, 1333

1066, 1333

800

800

1066, 1333, 1600 1066, 1333 1066, 1333, 1600

1066, 1333, 1600

1066, 1333

1066, 1333, 1600

1066

800 800

1066

800 800

Intel

®

Xeon

®


SRx8

DRx8

SRx4

DRx4

1GB

2GB

2GB

4GB

2GB

4GB

4GB

8GB

4GB

8GB

8GB

16GB

1066, 1333

1066, 1333

1066, 1333

1066, 1333

1066, 1333, 1600,

1866

1066, 1333, 1600,

1866

1066, 1333, 1600,

1866

1066, 1333, 1600,

1866

1066 1333 1066, 1333, 1600

1066 1333

1066, 1333, 1600

1066 1333

1066, 1333, 1600

1066 1333 1066, 1333, 1600

QRx4

8GB 16GB 32GB 800

1066

800 800

QRx8

4GB 8GB 16GB 800

1066

800 800

Notes:

1. Supported DRAM Densities are 1Gb, 2Gb and 4Gb. Only 2Gb and 4Gb are validated by Intel

®

.

2. Command Address Timing is 1N.

3. QR RDIMM are supported but only validated by Intel/PMO in a homogenous environment. The coverage will have limited system level testing, no signal integrity testing, and no interoperability testing the passing QR

RDIMMs will be web posted.


Supported but not Validate

Supported w/Limited Validation

4



Table 5. LRDIMM Support Guidelines

Ranks

Per

DIMM and

Data

Width

1

Memory Capacity

Per DIMM

2

1.35V



3,4

2 Slots per Channel

1DPC 2DPC

1.5V 1.35V 1.5V

Intel

®

Xeon

®


QRx4

(DDP)

5

QRx8

(P)

5

16GB 32GB

8GB 16GB

1066

1066

1066, 1333

1066, 1333

1066

1066

Intel

®

Xeon

®


QRx4

(DDP)

5

16GB 32GB


1066, 1333 1066, 1333 1066, 1333

QRx8

(P)

5

32GB

Notes:

64GB 1066 1066

1. Physical Rank is used to calculate DIMM Capacity.

2. Supported and validated DRAM Densities are 2Gb and 4Gb.

1066

3. Command Address Timing is 1N.

4. The speeds are estimated targets and will be verified through simulation.

5. DDP - Dual Die Package DRAM stacking. P

– Planer monolithic DRAM Die.

1066, 1333

1066, 1333

1066, 1333

1066

3.2.2.2 Memory Population Rules

Note: Although mixed DIMM configurations are supported, Intel only performs platform validation on systems that are configured with identical DIMMs installed.

Each processor provides four banks of memory, each capable of supporting up to 2 DIMMs.

 DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets.

 The memory channels from processor socket 1 are identified as Channel A, B, C and D. The memory channels from processor socket 2 are identified as Channel E, F, G, and H.

 The silk screened DIMM slot identifiers on the board provide information about the channel, and therefore the processor to which they belong. For example, DIMM_A1 is the first slot on Channel

A on processor 1; DIMM_E1 is the first DIMM socket on Channel E on processor 2.

 The memory slots associated with a given processor are unavailable if the corresponding processor socket is not populated.

 A processor may be installed without populating the associated memory slots provided a second processor is installed with associated memory.

In this case, the memory is shared by the processors.

However, the platform suffers performance degradation and latency due to the remote memory.

 Processor sockets are self-contained and autonomous. However, all memory subsystem support

(such as Memory RAS, Error Management,) in the BIOS setup are applied commonly across processor sockets.



On the Intel

®


®

Workstation Board W2600CR a total of 16 DIMM slots is provided (2 CPUs

– 4 Channels/CPU, 2 DIMMs/Channel). The nomenclature for DIMM sockets is detailed in the following table:

Table 6. DIMM Nomenclature

(0)

Channel A

Processor Socket 1

(1)

Channel B

(2)

Channel C

(3)

Channel D

A1 A2 B1 B2 C1 C2 D1 D2 E1

(0)

Channel E

E2 F1

Processor Socket 2

(1)

Channel F

(2)

Channel G

(3)

Channel H

F2 G1 G2 H1 H2

Figure 19. DIMM Slot Layout

The following are generic DIMM population requirements that generally apply to both the Intel

®

Server

Board S2600IP and Intel

®

Workstation Board W2600CR.



DIMM slots on any memory channel must be filled following the “farthest fill first” rule.

 A maximum of 8 ranks can be installed on any one channel, counting all ranks in each DIMM on the channel.

 DIMM types (UDIMM, RDIMM, LRDIMM) must not be mixed within or across processor sockets.



 Mixing ECC with non-ECC DIMMs (UDIMMs) is not supported within or across processor sockets.

 Mixing Low Voltage (1.35V) DIMMs with Standard Voltage (1.5V) DIMMs is not supported within or across processor sockets.

 Mixing DIMMs of different frequencies and latencies is not supported within or across processor sockets.

 LRDIMM Rank Multiplication Mode and Direct Map Mode must not be mixed within or across processor sockets.

 Only ECC UDIMMs support Low Voltage 1.35V operation.

 QR RDIMMs may only be installed in DIMM Slot 1 or 2 on a channel.

 2 DPC QR Low Voltage RDIMMs are not supported.

 In order to install 3 QR LRDIMMs on the same channel, they must be operated with Rank

Multiplication as RM = 2.

 RAS Modes Lockstep, Rank Sparing, and Mirroring are mutually exclusive in this BIOS. Only one operating mode may be selected, and it will be applied to the entire system.

 If a RAS Mode has been configured, and the memory population will not support it during boot, the system will fall back to Independent Channel Mode and log and display errors

 Rank Sparing Mode is only possible when all channels that are populated with memory meet the requirement of having at least 2 SR or DR DIMM installed, or at least one QR DIMM installed, on each populated channel.

 Lockstep or Mirroring Modes require that for any channel pair that is populated with memory, the memory population on both channels of the pair must be identically sized.

DIMM population rules require that DIMMs within a channel be populated starting with the BLUE

DIMM slot or DIMM farthest from the processor in a “fill-farthest” approach. In addition, when populating a Quad-rank DIMM with a Single- or Dual-rank DIMM in the same channel, the

Quad-rank DIMM must be populated farthest from the processor. Note that Quad-rand DIMMs and UDIMMs are not allowed in three slots populated configurations. Intel MRC will check for correct DIMM placement.

3.2.2.3 Publishing System Memory

 The BIOS displays the “Total Memory” of the system during POST if Display Logo is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system.

 The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term Effective

Memory refers to the total size of all DDR3 DIMMs that are active (not disabled) and not used as redundant units.

 The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the same as the amount described by the first bullet above.

If Quite Boot is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST. This total is the same as the amount described by the first bullet above.

3.2.2.4 RAS Features

The server board supports the following memory RAS modes:

 Independent Channel Mode

 Rank Sparing Mode



 Mirrored Channel Mode

 Lockstep Channel Mode

Regardless of RAS mode, the requirements for populating within a channel given in the section 3.2.2.2

must be met at all times. Note that support of RAS modes that require matching DIMM population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated. Independent Channel

Mode is the only mode that supports non-ECC DIMMs in addition to ECC DIMMs.

For RAS modes that require matching populations, the same slot positions across channels must hold the same DIMM type with regards to size and organization. DIMM timings do not have to match but timings will be set to support all DIMMs populated (that is, DIMMs with slower timings will force faster DIMMs to the slower common timing modes).

3.2.2.4.1 Independent Channel Mode

Channels can be populated in any order in Independent Channel Mode. All four channels may be populated in any order and have no matching requirements. All channels must run at the same interface frequency but individual channels may run at different DIMM timings (RAS latency, CAS Latency, and so forth).

3.2.2.4.2 Rank Sparing Mode

In Rank Sparing Mode, one rank is a spare of the other ranks on the same channel. The spare rank is held in reserve and is not available as system memory. The spare rank must have identical or larger memory capacity than all the other ranks (sparing source ranks) on the same channel. After sparing, the sparing source rank will be lost.

3.2.2.4.3 Mirrored Channel Mode

In Mirrored Channel Mode, the memory contents are mirrored between Channel 0 and Channel 2 and also between Channel 1 and Channel 3. As a result of the mirroring, the total physical memory available to the system is half of what is populated. Mirrored Channel Mode requires that Channel 0 and Channel 2, and Channel 1 and Channel 3 must be populated identically with regards to size and organization. DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel 2 and across Channel

1 and Channel 3 must be populated the same.

3.2.2.4.4 Lockstep Channel Mode

In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 0 and Channel 1, and Channel 2 and Channel 3. Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices. Lockstep Channel Mode requires that Channel 0 and Channel

1, and Channel 2 and Channel 3 must be populated identically with regards to size and organization. DIMM slot populations within a channel do not have to be identical but the same

DIMM slot location across Channel 0 and Channel 1 and across Channel 2 and Channel 3 must be populated the same.

3.2.3 Processor Integrated I/O Module (IIO)

The processor’s integrated I/O module provides features traditionally supported through chipset components. The integrated I/O module provides the following features:



3.2.3.1 PCI Express* Interfaces

The integrated I/O module incorporates the PCI Express* interface and supports up to 40 lanes of

PCI Express*. Following are key attributes of the PCI Express* interface:

Intel

®


®

Workstation Board W2600CR supports PCI-e slots from two processors:

From first processor:

 Slot 1: PCIe Gen3 x16 connector



From second processor:





 Slot 8: PCIe Gen2 x4 electrical with x8 physical connector.

Note: System will have video output on PCIe slots from first processor by default. If need add-in video card output on slots from second processor, please refer System Service guide to change Bios setup.

3.2.3.2 DMI2 Interface to the PCH

The platform requires an interface to the legacy Southbridge (PCH) which provides basic legacy functions required for the server platform and operating systems. Since only one PCH is required and allowed for the system, any sockets which do not connect to PCH would use this port as a standard x4 PCI Express* 2.0 interface.

3.2.3.3 Integrated IOAPIC

Provides support for PCI Express* devices implementing legacy interrupt messages without interrupt sharing.

3.2.3.4 Non Transparent Bridge

PCI Express* non-transparent bridge (NTB) acts as a gateway that enables high performance, low overhead communication between two intelligent subsystems; the local and the remote subsystems.

The NTB allows a local processor to independently configure and control the local subsystem, provides isolation of the local host memory domain from the remote host memory domain while enabling status and data exchange between the two domains.

3.2.3.5 4.2.3.1.5 Intel

®

Used for efficient, high bandwidth data movement between two locations in memory or from memory to I/O.



3.3 Intel

®

The Intel

®

C600-A Chipset in the Intel

®

Server Board S2600IP and Intel provide a connection point between various I/O components and Intel

®

®


Xeon Sandy Bridge-EP processors, which includes the following core platform functions:















































Digital Media Interface (DMI)

PCI Express* Interface

Serial ATA (SATA) Controller

Serial Attached SCSI (SAS)/SATA Controller

AHCI

Rapid Storage Technology

PCI Interface

Low Pin Count (LPC) Interface

Serial Peripheral Interface (SPI)

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

Advanced Programmable Interrupt Controller (APIC)

Universal Serial Bus (USB) Controllers

Gigabit Ethernet Controller

RTC

GPIO

Enhanced Power Management

Intel

®

Active Management Technology (Intel

®

AMT)

Manageability

System Management Bus (SMBus* 2.0)

Integrated NVSRAM controller

Virtualization Technology for Directed I/O (Intel

®

VT-d)

JTAG Boundary-Scan

KVM/Serial Over LAN (SOL) Function

3.3.1 Digital Media Interface (DMI)

Digital Media Interface (DMI) is the chip-to-chip connection between the processor and The Intel

®

C600-A

Chipset. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally.

3.3.2 PCI Express* Interface

The Intel

®

C600-A Chipset provides up to 8 PCI Express* Root Ports, supporting the PCI Express* Base

Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in each direction (10

Gb/s concurrent). PCI Express* Root Ports 1-4 or Ports 5-8 can independently be configured to support four x1s, two x2s, one x2 and two x1s, or one x4 port widths.

3.3.3 Serial ATA (SATA) Controller

The Intel

®

C600-A Chipset has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s (600 MB/s) on up to two


Functional Architecture ports (Port 0 and 1 Only) while all ports support rates up to 3.0 Gb/s (300 MB/s) and up to 1.5 Gb/s (150

MB/s). The SATA controller contains two modes of operation

– a legacy mode using I/O space, and an

AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities.

The Intel

®

C600-A Chipset supports the Serial ATA Specification, Revision 3.0. The Intel

®

C600-A

Chipset also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0

Specification, Revision 1.0 (AHCI support is required for some elements).

3.3.4 Serial Attached SCSI (SAS)/SATA (SCU) Controller

The Intel

®

C600-A Chipset supports up to 8 SAS ports that are compliant with SAS 2.0 Specification and all ports support rates up to 3.0 Gb/s. All 8 ports are also independently configurable and compliant with

SATA Gen2 and support data transfer rates of up to 3.0 Gb/s.

SAS/SATA controller is only available on specific Intel

®

C600-A Chipset SKUs with optional RAID C600

Upgrade key. Certain SKUs are also limited to support 4 of 8 SAS/SATA ports only. Please refer details below:

Note: SAS/SATA (SCU) port 0-3 is by default enabled while port 4-7 is disabled.

Table 7. Intel

®

RAID C600 Upgrade Key Options

Intel RAID C600 Upgrade Key Options

(Product Codes)

Default

– No option key installed

RKSATA4R5

RKSATA8

RKSATA8R5

RKSAS4

RKSAS4R5

RKSAS8

RKSAS8R5

Key Color

N/A

Black

Blue

White

Green

Yellow

Orange

Purple

Description

4 Port SATA with Intel

®

ESRT RAID 0,1,10 and Intel

®

RSTe RAID 0,1,5,10


®

ESRT2 RAID 0,1, 5, 10 and Intel

®

RSTe RAID 0,1,5,10


®

ESRT2 RAID 0,1, 10 and Intel

®

RSTe RAID 0,1,5,10


®


®

RSTe RAID 0,1,5,10

4 Port SAS with Intel

®


®

RSTe RAID 0,1,10


®


®

RSTe RAID 0,1,10


®


®

RSTe RAID 0,1,10


®


®

RSTe RAID 0,1,10

Additional information for the on-board RAID features and functionality can be found in the Intel

®

RAID Software User

’s Guide (Intel Document Number D29305-019).

3.3.5 AHCI

The Intel

®

C600-A Chipset provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (for example, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware.

3.3.6 Rapid Storage Technology

The Intel

®

C600-A Chipset provides support for Intel

®

Rapid Storage Technology, providing both AHCI and integrated RAID functionality. The RAID capability provides high-performance RAID 0, 1, 5 and 10 functionality on the Intel

®

C600-A chipset. Matrix RAID support is provided to allow multiple RAID levels to


Functional Architecture be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot-spare support, SMART alerting, and RAID 0 auto replace.

3.3.7 PCI Interface

The Intel

®

C600-A chipset PCI interface provides a 33 MHz, Revision 2.3 implementation. The Intel

®

C600-A chipset integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal Intel

®

C600-A chipset requests. This allows for combinations of up to four PCI down devices and PCI slots.

3.3.8 Low Pin Count (LPC) Interface

The Intel

®

C600-A chipset implements an LPC Interface as described in the LPC 1.1 Specification. The

Low Pin Count (LPC) bridge function of the Intel

®

C600-A resides in PCI Device 31: Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.

3.3.9 Serial Peripheral Interface (SPI)

The Intel

®

C600-A chipset implements an SPI Interface as an alternative interface for the BIOS flash device. The SPI flash is required to support Gigabit Ethernet and Intel

®

Active Management Technology.

The Intel

®

C600-A chipset supports up to two SPI flash devices with speeds up to 50 MHz.

3.3.10 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. The Intel

®

C600-A chipset’s DMA controller.

C600-A chipset supports LPC DMA through the Intel

®

The timer/counter block contains three counters that are equivalent in function to those found in one

82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone.

The Intel

®

C600-A chipset provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two 82C59 interrupt controllers. In addition, the Intel

®

C600-A chipset supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform.

3.3.11 Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the Intel

®

C600-A incorporates the Advanced Programmable Interrupt Controller (APIC).

3.3.12 Universal Serial Bus (USB) Controllers

The Intel

®

C600-A chipset has up to two Enhanced Host Controller Interface (EHCI) host controllers that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The Intel

®

C600-A chipset supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full-speed, and low-speed capable.

3.3.13 Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface using a PCI function. The controller provides a full memory-mapped or IO mapped interface along with a 64 bit address master support for systems using more than 4 GB of physical memory and DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its bus master capabilities enable the component to process high-level


Functional Architecture commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control

Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism.

3.3.14 RTC

The Intel

®

C600-A chipset contains a real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data. The RTC operates on a 32.768 KHz crystal and a 3 V battery.

3.3.15 GPIO

Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on the Intel

®

C600-A chipset configuration.

3.3.16 Enhanced Power Management

The Intel

®

C600-A chipset’s power management functions include enhanced clock control and various low-power (suspend) states (for example, Suspend-to-RAM and Suspend-to-Disk). A hardware-based thermal management circuit permits software-independent entrance to low-power states. The Intel

®

C600-

A chipset contains full support for the Advanced Configuration and Power Interface (ACPI) Specification,

Revision 4.0a.

3.3.17 Manageability

In addition to Intel AMT the Intel

®

C600-A chipset integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.

3.3.18 System Management Bus (SMBus* 2.0)

The Intel

®

C600-A chipset contains a SMBus* Host interface that allows the processor to communicate with SMBus* slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.

The Intel

®

C600-A chipset’s SMBus* host controller provides a mechanism for the processor to initiate communications with SMBus* peripherals (slaves). Also, the Intel

®

C600-A chipset supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus* interface (see System Management Bus (SMBus*) Specification, Version 2.0):

Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block

Read/Write, and Host Notify.

The Intel

®

C600-A chipset’s SMBus* also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus* devices.

3.3.19 Integrated NVSRAM controller

The Intel

®

C600-A chipset has an integrated NVSRAM controller that supports up to 32KB external device.

The host processor can read and write data to the NVSRAM component.



3.3.20

The Intel

®

C600-A chipset provides hardware support for implementation of Intel

Technology with Directed I/O (Intel

®

®

Virtualization

VT-d). Intel VT-d consists of technology components that support the virtualization of platforms based on Intel

®

Architecture Processors. Intel VT-d Technology enables multiple operating systems and applications to run in independent partitions. A partition behaves like a virtual machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset of host physical memory.

3.3.21 JTAG Boundary-Scan

The Intel

®

C600-A chipset adds the industry standard JTAG interface and enables Boundary-Scan in place of the XOR chains used in previous generations of chipsets. Boundary-Scan can be used to ensure device connectivity during the board manufacturing process. The JTAG interface allows system manufacturers to improve efficiency by using industry available tools to test the Intel

®

C600-A chipset on an assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface between the system and a bed-of-nails tester.

3.3.22 KVM/Serial Over Lan (SOL) Function

These functions support redirection of keyboard, mouse, and text screen to a terminal window on a remote console. The keyboard, mouse, and text redirection enables the control of the client machine through the network. Text, mouse, and keyboard redirection allows the remote machine to control and configure the client by entering BIOS setup. The KVM/SOL function emulates a standard PCI serial port and redirects the data from the serial port to the management console using LAN. KVM has additional requirements of internal graphics and SOL may be used when KVM is not supported.

3.3.23 On-board SAS/SATA Support and Options

The Intel

®

C600 chipset provides storage support by two integrated controllers: AHCI and SCU. By default the server board will support up to 10 SATA ports: Two white 6Gb/sec SATA ports from the

AHCI controller labeled as “SATA_0” and “SATA_1” and two MINISAS 3Gb/sec SATA/SAS ports routed from the SCU controller labeled as “SCU0 (PORT0-3) and “SCU1(PORT4-7).

The SCU Port can be configured with the two embedded software RAID options:

Intel

®

Embedded Server RAID Technology 2 (ESRT2) based on LSI* MegaRAID SW

RAID technology supporting RAID levels 0,1, and 10.



Intel

®

Rapid Storage Technology (RSTe) supporting RAID levels 0, 1, 5, and 10.

3.3.23.1 Intel

®

Features of the embedded software RAID option Intel

®

Embedded Server RAID Technology 2

(ESRT2) include the following:



Based on LSI* MegaRAID Software Stack





Software RAID with system providing memory and CPU utilization

Supported RAID Levels

– 0,1,5,10



4 and 8 Port SATA RAID 5 support provided with appropriate Intel

®

RAID C600



Upgrade Key

4 and 8 Port SAS RAID 5 support provided with appropriate Intel

®

RAID C600

Upgrade Key





Maximum drive support = 8

Open Source Compliance = Binary Driver (includes Partial Source files) or Open Source





 using MDRAID layer in Linux.

OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL*, SLES, other Linux* variants using partial source builds.

Utilities = Windows* GUI and CLI, Linux GUI and CLI, DOS CLI, and EFI CLI

3.3.23.2 Intel

®

Features of the embedded software RAID option Intel

®

Rapid Storage Technology (RSTe) include the following:



Software RAID with system providing memory and CPU utilization



Supported RAID Levels

– 0,1,5,10 o 4 Port SATA RAID 5 available standard (no option key required) o 8 Port SATA RAID 5 support provided with appropriate Intel

®

RAID C600 Upgrade

Key o No SAS RAID 5 support



Maximum drive support = 32 (in arrays with 8 port SAS), 16 (in arrays with 4 port SAS),





128 (JBOD)

Open Source Compliance = Yes (uses MDRAID)

OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL* 6.2 and later,

SLES* 11 w/SP2 and later, VMWare* 5.x.







Utilities = Windows* GUI and CLI, Linux CLI, DOS CLI, and EFI CLI

Uses Matrix Storage Manager for Windows*

MDRAID supported in Linux* (does not require a driver)

Note: No boot drive support to targets attached through SAS expander card

3.4 PCI Subsystem

The primary I/O buses for the Intel

®


®

Workstation Board W2600CR are

PCI Express* Gen3 with six independent PCI bus segments. The following tables list the characteristics of the PCI bus segments.

Table 8. Intel

®

Server Board S2600IP/Workstation Board W2600CR PCI Bus Segment

Characteristics

Voltage

3.3 V x16

Width

3.3 V

3.3 V

X8 or none

(with mux) x16 or x8(with mux)

Speed

32 GB/S PCI

Type

Express*

Gen3

16 GB/S or none

PCI

Express*

Gen3

32 GB/S or

16 GB/S

PCI

Express*

Gen3

PCI I/O Card Slots

X16 PCI Express* Gen3 throughput to Slot1 (x16 mechanically) x8 PCI Express* Gen3 throughput to Slot 2 (x8 mechanically) x16 PCI Express* Gen3 throughput to Slot 3 (x16 mechanically)



3.3 V

3.3 V

3.3 V

3.3 V

X8 or none


X8 or none


16 GB/S or none

PCI

Express*

Gen3

32 GB/S or

16 GB/S

PCI

Express*

Gen3

16 GB/S or none

PCI

Express*

Gen3

32 GB/S or

16 GB/S

PCI

Express*

Gen3 x8 PCI Express* Gen3 throughput to Slot 4 (x8 mechanically, Non-

Persistent)

X16 PCI Express* Gen3 throughput to Slot 5 (x16 mechanically, Non-

Persistent) x8 PCI Express* Gen3 throughput to Slot 6 (x8 mechanically, Non-

Persistent)


Persistent)

3.3 V X4 4 GB/S PCI

Express*

Gen2


Persistent)

3.5 Network Interface Controller

The Intel

®

Server Board S2600IP and Workstation Board S2600CR has a Intel

®

Ethernet Controller I350

GbE Controller. The controller supports PCI Express* PCIe v2.0 (5GT/s and 2.5GT/s). The controller enables four-port or two-port 1000BASE-T implementations using integrated PHY’s. The controller supports VMDq, SR-IOV, EEE, and DMA Coalescing.

3.5.1 Network Interface

Network connectivity is provided by means of an onboard Intel

®

Ethernet Controller 1350-AM4 providing up to four 10/100/1000 Mb Ethernet ports.

On the Intel

®

Server Board S2600IP, four external 10/100/1000 Mb RJ45 Ethernet ports are provided. On the Intel

®

Workstation Board W2600CR, two external 10/100/1000 Mb RJ45 Ethernet ports are provided.

Each Ethernet port drives two LEDs located on each network interface connector. The LED at the right of the connector is the link/activity LED and indicates network connection when on, and transmit/receive activity when blinking. The LED at the left of the connector indicates link speed as defined in the following table.



LED Color

Green/Amber (Right)

Green (Left)

Off

Amber

Green

On

Blinking

LED State NIC State

10 Mbps

100 Mbps

1000 Mbps

Active Connection

Transmit/Receive activity

Figure 20. External RJ45 NIC Port LED Definition

3.6 I/O Module Support (not avaiable for Intel

®

Server Board S2600IP4L and

Intel

®

Workstation Board W2600CR2L)

To broaden the standard on-board feature set, the server board supports the option of adding a single I/O module providing external ports for a variety of networking interfaces. The I/O module attaches to a high density 80pin connector on the server board labeled “IO_Module”.

Supported I/O modules include:



Product Code and iPN

AXX10GBNIAIOM

MM# 917905

AXX10GBTWLIOM

MM# 917907

AXX1FDRIBIOM

MM# 918607

AXX4P1GBPWLIOM

MM# 917911

AXXIOMKIT

MM# 920852

Description

Dual SFP+ port 10GbE IO Module based on Intel

®

82599 10GbE Ethernet Controller

Dual RJ45 Port, 10GBASE-T IO Module, based on Intel

®

I350 Ethernet chipset

Single Port, FDR speed Infiniband* module, with QSFP connector.

Quad Port 1GbE 1o Module based on Intel

I/O Module Cable and Brackets

®

Ethernet Controller I350

Figure 21. Supported I/O Module Options

Notes:

1. I/O Module cable and Brackets accessory is necessary to support I/O module on Intel

®

Server Board

S2600IP.

2. IOM connector only supports PCIe Gen1 Speed

3.7 SAS ROC Module Support

The system provides support for Intel

®

Integrated RAID mezzanine modules that utilize a high density 80pin connector (labeled “SAS_MOD”) on the server board.


Features of this option include:

 Does not utilize a PCIe slot

 SKU options to support full or entry level hardware RAID

 4 or 8 port and SAS/SATA or SATA –only ROC options


 SKU options to support 512MB or 1GB embedded memory

 Intel designed flash + optional support for super-cap backup (Maintenance Free Back Up) or improved Lithium Polymer battery

Table 9. Supported Intel

®

Integrated RAID Modules

External Name Description Product Code

Intel

®

Integrated RAID Module

RMS25CB080

Intel

®


RMS25CB040

8 Port SAS-2.1, Full HW RAID, 1GB, Mezz Slot

RAID Levels 0,1,10, 5, 50, 6, 60

4 Port SAS-2.1, Full HW RAID, 1GB, Mezz Slot

RAID Levels 0,1,10, 5, 50, 6, 60

RMS25CB080

RMS25CB040

Intel

®


RMT3CB080

Intel

®


RMS25KB080

8 Port SATA-3, Full HW RAID, 512MB, Mezz

Slot

RAID Levels 0,1,10, 5, 50, 6, 60

RMT3CB080

8 Port SAS-2.1, Entry-level HW RAID, Mezz Slot RMS25KB080

RAID Levels 0,1,1E

Intel

®


RMS25KB040

4 Port SAS-2.1, Entry-level HW RAID, Mezz Slot RMS25KB040

RAID Levels 0,1,1E

For additional product information, please refer the following Intel

®

document:

Intel

®

Integrated RAID Module RMS25PB080, RMS25PB040, RMS25CB080, and

RMS25CB040 Hardware User’s Guide – Intel Order Number G37519-003.

3.8 HD Audio Support (Intel

®

Workstation Board W2600CR Only)

The Intel

®

Workstation Board W2600CR support 7.1 HD Audio through the High Definition Audio Codec

Realtek* ALC889. The ALC889 provides ten DAC channels that simultaneously support 7.1 sound playback, plus two channels of independent stereo sound output (multiple streaming) through the front panel stereo outputs. Also supports two channels of S/PDIF In/Out (W2600CR only supports 1 S/PDIF

Out port) and two channels of Microphone In (Front/Rear). The ALC889 is driven by the Intel

®

HD Audio

Interface (Azalia) from Intel

®

C600-A chipset.



Table 10. Standard Speaker Channels

Channel name Identifier

Front Left

Front Right

SPEAKER_FRONT_LEFT

SPEAKER_FRONT_RIGHT

Front Center SPEAKER_FRONT_CENTER

Low Frequency (Subwoofer) SPEAKER_LOW_FREQUENCY

Back Left

Back Right

Side Left

Side Right

SPEAKER_BACK_LEFT

SPEAKER_BACK_RIGHT

SPEAKER_SIDE_LEFT

SPEAKER_SIDE_RIGHT

1.0

Mono

No

No

Yes

No

No

No

No

No

2.0

Stereo

Yes

Yes

No

No

No

No

No

No

5.1

Surround

Yes

Yes

Yes

Yes

Yes

Yes

No

No

3.9 USB3.0 Support (Intel

®


The Intel

®

Workstation Board W2600CR supports two USB3.0 SuperSpeed* ports, which is required as a standard Workstation feature. The TI 2 port USB3.0 discrete host controller TUSB7320 is used to meet this requirement. The TUSB7320 USB3.0 host controller complies with Universal Serial Bus 3.0

Specification and Intel’s eXtensible Host Controller Interface (xHCI).

7.1

Surround

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

44

Figure 22. USB3.0 Discrete Host Controller Block Diagram



3.10 IEEE1394b Support (Intel

®


Intel

®

Workstation Board W2600CR offers one front panel IEEE 1394b port from a discrete controller

(Texas Instruments XIO2221).The XIO2221 uses a PCIe x1 Gen 1 upstream interface from Intel

®

C600-A chipset. When connected to 1394b compliant devices, the XIO2221 can transfer data at speeds of up to

800 Mbps. The Intel

®

Workstation Board W2600CR includes an internal 1394b connector that allows for a front panel 1394b cable attach.

Revision 1.2

Figure 23. IEEE 1394b Discrete Host Controller Block Diagram


Platform Management Overview

4. Platform Management Overview

4.1 Server Management Function Architecture

4.1.1 Feature Support

4.1.1.1 IPMI 2.0 Features

The IPMI 2.0 features are as follows:

1. Baseboard management controller (BMC)

2. IPMI Watchdog timer

3. Messaging support, including command bridging and user/session support

4. Chassis device functionality, including power/reset control and BIOS boot flags support

5. Event receiver device: The BMC receives and processes events from other platform subsystems.

6. Field Replaceable Unit (FRU) inventory device functionality: The BMC supports access to system

FRU devices using IPMI FRU commands.

7. System Event Log (SEL) device functionality: The BMC supports and provides access to a SEL.

8. Sensor Data Record (SDR) repository device functionality: The BMC supports storage and access of system SDRs.

9. Sensor device and sensor scanning/monitoring: The BMC provides IPMI management of sensors. It polls sensors to monitor and report system health.

10. IPMI interfaces

11. Host interfaces include system management software (SMS) with receive message queue support, and server management mode (SMM)

12. IPMB interface

13. LAN interface that supports the IPMI-over-LAN protocol Remote Management Control Protocol

(RMCP, RMCP+)

14. Serial-over-LAN (SOL)

15. ACPI state synchronization: The BMC tracks ACPI state changes that are provided by the BIOS.

16. BMC self test: The BMC performs initialization and run-time self-tests and makes results available to external entities.

See also the Intelligent Platform Management Interface Specification Second Generation, Version 2.0.

4.1.1.2 Non IPMI features

The BMC supports the following non-IPMI features. This list does not preclude support for future enhancements or additions.

 In-circuit BMC firmware update

 Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality.

 Chassis intrusion detection (dependent on platform support)

 Basic fan control using Control version 2 SDRs

 Fan redundancy monitoring and support

 Power supply redundancy monitoring and support

 Hot-swap fan support

 Acoustic management: Support for multiple fan profiles



 Signal testing support: The BMC provides test commands for setting and getting platform signal states.

 The BMC generates diagnostic beep codes for fault conditions.

 System GUID storage and retrieval

 Front panel management: The BMC controls the system status LED and chassis ID LED. It supports secure lockout of certain front panel functionality and monitors button presses. The chassis ID LED is turned on using a front panel button or a command.

 Power state retention

 Power fault analysis

 Intel

®

Light-Guided Diagnostics

 Power unit management: Support for power unit sensor. The BMC handles power-good dropout conditions.

 DIMM temperature monitoring: New sensors and improved acoustic management using closedloop fan control algorithm taking into account DIMM temperature readings.

 Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs).

 Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs).

 Platform environment control interface (PECI) thermal management support

 E-mail alerting

 Embedded web server

 Integrated KVM.

 Integrated Remote Media Redirection

 Lightweight Directory Access Protocol (LDAP) support

 Intel

®

Intelligent Power Node Manager support

4.1.1.3 New Manageability Features

Intel

®

S1400/S1600/S2400/S2600 Server Platforms offer a number of changes and additions to the manageability features that are supported on the previous generation of servers. The following is a list of the more significant changes that are common to this generation Integrated BMC based Intel

®

Server boards:

 Sensor and SEL logging additions/enhancements (for example, additional thermal monitoring capability)

 SEL Severity Tracking and the Extended SEL

 Embedded platform debug feature which allows capture of detailed data for later analysis.

 Provisioning and inventory enhancements: o Inventory data/system information export (partial SMBIOS table)

 Enhancements to fan speed control.

 DCMI 1.1 compliance (product-specific).

 Support for embedded web server UI in Basic Manageability feature set.

 Enhancements to embedded web server o Human-readable SEL o Additional system configurability o Additional system monitoring capability


Platform Management Overview o Enhanced on-line help

 Enhancements to KVM redirection o Support for higher resolution

 Support for EU Lot6 compliance

 Management support for PMBus* rev1.2 compliant power supplies

 BMC Data Repository (Managed Data Region Feature)

 Local Control Display Panel

 System Airflow Monitoring

 Exit Air Temperature Monitoring

 Ethernet Controller Thermal Monitoring

 Global Aggregate Temperature Margin Sensor

 Memory Thermal Management

 Power Supply Fan Sensors

 Energy Star Server Support

 Smart Ride Through (SmaRT)/ Closed Loop System Throttling (CLST)

 Power Supply Cold Redundancy

 Power Supply FW Update

 Power Supply Compatibility Check

 BMC FW reliability enhancements: o Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the BMC. o BMC System Management Health Monitoring

4.1.2 Basic and Advanced Features

The bellowing table lists basic and advanced feature support. Individual features may vary by platform.

See the appropriate Platform Specific EPS addendum for more information.

Table 11. Basic and Advanced Features

Feature

IPMI 2.0 Feature Support

In-circuit BMC Firmware Update

FRB 2

Chassis Intrusion Detection

Fan Redundancy Monitoring

Hot-Swap Fan Support

Acoustic Management

Diagnostic Beep Code Support

Power State Retention

ARP/DHCP Support

X

X

X

X

Basic

X

X

X

X

X

X

Advanced

X

X

X

X

X

X

X

X

X

X



Feature

PECI Thermal Management Support

E-mail Alerting

Embedded Web Server

SSH Support

Integrated KVM

Integrated Remote Media Redirection

Lightweight Directory Access Protocol (LDAP)

Intel

®

Intelligent Power Node Manager Support

SMASH CLP

X

X

X

Basic

X

X

X

X

Advanced

X

X

X

X

X

X

X

X

X

4.1.3

4.1.3.1

Integrated BMC Hardware: Emulex* Pilot III

Emulex* Pilot III Baseboard Management Controller Functionality

The Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management. Firmware usage of these hardware features is platform dependent.

The following is a summary of the Integrated BMC management hardware features that comprise the

BMC:

 400MHz 32-bit ARM9 processor with memory management unit (MMU)

 Two independent10/100/1000 Ethernet Controllers with Reduced Media Independent Interface

(RMII)/ Reduced Gigabit Media Independent Interface (RGMII) support

 DDR2/3 16-bit interface with up to 800 MHz operation

 16 10-bit ADCs

 Sixteen fan tachometers

 Eight Pulse Width Modulators (PWM)

 Chassis intrusion logic

 JTAG Master

 Eight I

2

C interfaces with master-slave and SMBus* timeout support. All interfaces are SMBus* 2.0 compliant.

 Parallel general-purpose I/O Ports (16 direct, 32 shared)

 Serial general-purpose I/O Ports (80 in and 80 out)

 Three UARTs

 Platform Environmental Control Interface (PECI)

 Six general-purpose timers

 Interrupt controller

 Multiple Serial Peripheral Interface (SPI) flash interfaces

 NAND/Memory interface

 Sixteen mailbox registers for communication between the BMC and host

 LPC ROM interface

 BMC watchdog timer capability

 SD/MMC card controller with DMA support

 LED support with programmable blink rate controls on GPIOs

 Port 80h snooping capability

 Secondary Service Processor (SSP), which provides the HW capability of offloading time critical processing tasks from the main ARM core.

Emulex* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller with the following features:



4.1.3.1.1 Super I/O (SIO)

The BMC integrates a super I/O module with the following features:

 Keyboard Style/BT interface for BMC support

 Two Fully Functional Serial Ports, compatible with the 16C550

 Serial IRQ Support

 Up to 16 Shared GPIO available for host processor

 Programmable Wake-up Event Support

 Plug and Play Register Set

 Power Supply Control

4.1.3.1.2 Graphics Controller

The graphics controller provides the following features:

 Integrated Graphics Core with 2D Hardware accelerator

 High speed Integrated 24-bit RAMDAC

DDR-2/3 memory interface with 16Mbytes of memory allocated and reported for graphics memory.

4.1.3.1.3 Remote Keyboard, Video, Mouse, and Storage (KVMS )

The Integrated BMC contains a remote KVMS subsystem with the following features:

 USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and floppy

 USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse

 Hardware Based Video Compression and Redirection Logic

 Supports both text and Graphics redirection

 Hardware assisted Video redirection using the Frame Processing Engine

 Direct interface to the Integrated Graphics Controller registers and Frame buffer

 Hardware-based encryption engine



Figure 24. Integrated BMC Hardware

4.2 Server Management Functional Specifications

4.2.1 BMC Internal Timestamp Clock

The BMC maintains an internal timestamp clock that is used by various BMC subsystems, for example, time stamping SEL entries. As part of BMC initialization after AC power is applied or the BMC is reset, the

BMC initializes this internal clock to the value retrieved from the SSB component’s RTC from a SMBus* slave read operation. This is the system RTC and is on the battery power well so it maintains the current time even when there is no AC supplied to the system.

4.2.1.1 System Clock Synchronization

The BIOS must send the Set SEL Time command with the current system time to the BMC during system Power-on Self Test (POST). Synchronization during very early POST is preferred, so that any

SEL entries recorded during system boot can be accurately time stamped. Additionally, during sleep state transitions other than S0 the BIOS will synchronize the time.

If the time is modified through an OS interface, then the BMC’s time is not synchronized until the next system reboot.



4.2.2 System Event Log (SEL)

The BMC implements the system event log as specified in the Intelligent Platform Management Interface

Specification, Version 2.0. The SEL is accessible regardless of the system power state through the

BMC's in-band and out-of-band interfaces.

The BMC allocates 95231 bytes (approximately 93 KB) of non-volatile storage space to store system events. The SEL timestamps may not be in order. Up to 3,639 SEL records can be stored at a time. Any comma nd that results in an overflow of the SEL beyond the allocated space is rejected with an “Out of

Space” IPMI completion code (C4h).

4.2.3 Sensor Data Record (SDR) Repository

The BMC implements the sensor data record (SDR) repository as specified in the Intelligent Platform

Management Interface Specification, Version 2.0.

The SDR is accessible through the BMC’s in-band and out-of-band interfaces regardless of the system power state The BMC allocates 65,519 bytes of nonvolatile storage space for the SDR.

4.2.4 Field Replaceable Unit (FRU) Inventory Device

The BMC implements the interface for logical FRU inventory devices as specified in the Intelligent

Platform Management Interface Specification, Version 2.0. This functionality provides commands used for accessing and managing the FRU inventory information. These commands can be delivered through all interfaces.

The BMC provides FRU device command access to its own FRU device and to the FRU devices throughout the server. The FRU device ID mapping is defined in the Platform Specific Information. The

BMC controls the mapping of the FRU device ID to the physical device.

4.2.5 BMC Beep Codes

The BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered (for example, on each power-up attempt), but are not sounded continuously. Common supported codes are listed in below Table

Additional platform-specific beep codes can be found in the appropriate Platform Specific

Information. Each digit in the code is represented by a sequence of beeps whose count is equal to the digit.

Table 12. BMC Beep Codes

Code Reason for Beep

1-5-2-1 No CPUs installed or first CPU socket is empty.

1-5-2-4 MSID Mismatch.

1-5-4-2 Power fault: DC power is unexpectedly lost (power good dropout).

1-5-4-4 Power control fault (power good assertion timeout).

1-5-1-2 VR Watchdog Timer sensor assertion

Associated Sensors

CPU Missing Sensor

MSID Mismatch Sensor.

Power unit

– power unit failure offset.

Power unit

– soft power control failure offset.

VR Watchdog Timer



4.2.6


1-5-1-4 The system does not power on or unexpectedly powers off and a power supply unit (PSU) is present that is an incompatible model with one or more other PSUs in the system

Diagnostic Interrupt (NMI) Button

Associated Sensors

PS Status

The BMC generates an NMI pulse under certain conditions. The BMC-generated NMI pulse duration is at least 30 ms. Once an NMI has been generated by the BMC, the BMC does not generate another NMI until the system has been reset or powered down.

The following actions cause the BMC to generate an NMI pulse:

1. Receiving a Chassis Control command to pulse the diagnostic interrupt. This command does not cause an event to be logged in the SEL.

2. Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout action enabled.

The following table shows the behavior regarding NMI signal generation and event logging by the

BMC.

Table 13. NMI Signal Generation and Event Logging

Causal Event NMI

Signal Generation Front Panel Diag Interrupt Sensor Event Logging

Support

Chassis Control command (pulse diagnostic interrupt)

Front panel diagnostic interrupt button pressed

Watchdog Timer pre-timeout expiration with

NMI/diagnostic interrupt action

X

X

X

–

X

X

4.2.7 BMC Watchdog

The BMC FW is increasingly called upon to perform system functions that are time-critical in that failure to provide these functions in a timely manner can result in system or component damage. Intel

®

S1400/S1600/S2400/S2600 Server Platforms introduce a BMC watchdog feature to provide a safe-guard against this scenario by providing an automatic recovery mechanism. It also can provide automatic recovery of functionality that has failed due to a fatal FW defect triggered by a rare sequence of events or a BMC hang due to some type of HW glitch (for example, power).

This feature is comprised of a set of capabilities whose purpose is to detect misbehaving subsections of

BMC firmware, the BMC CPU itself, or HW subsystems of the BMC component, and to take appropriate action to restore proper operation. The action taken is dependent on the nature of the detected failure and may result in a restart of the BMC CPU, one or more BMC HW subsystems, or a restart of malfunctioning

FW subsystems.

The BMC watchdog feature will only allow up to three resets of the BMC CPU (such as HW reset) or entire FW stack (such as a SW reset) before giving up and remaining in the uBOOT code. This count is cleared upon cycling of power to the BMC or upon continuous operation of the BMC without a watchdog-generated reset occurring for a period of > 30 minutes. The BMC

FW logs a SEL event indicating that a watchdog-generated BMC reset (either soft or hard reset) has occurred. This event may be logged after the actual reset has occurred. Refer sensor


Platform Management Overview section for details for the related sensor definition. The BMC will also indicate a degraded system status on the Front Panel Status LED after an BMC HW reset or FW stack reset. This state (which follows the state of the associated sensor) will be cleared upon system reset or (AC or DC) power cycle.

Note: A reset of the BMC may result in the following system degradations that will require a system reset or power cycle to correct:

1. Timeout value for the rotation period can be set using this parameter; potentially incorrect

ACPI Power State reported by the BMC.

2. Reversion of temporary test modes for the BMC (for example, as set through Set SM Signal command) back to normal operational modes.

3. FP status LED and DIMM fault LEDs may not reflect BIOS detected errors.

4.3 Sensor Monitoring

4.3.1 Overview

The BMC monitors system hardware and reports system health. The information gathered from physical sensors is translated into IPMI sensors as part of the “IPMI Sensor Model”. The BMC also reports various system state changes by maintaining virtual sensors that are not specifically tied to physical hardware.

This section describes the BMC sensors as well as describing how specific sensor types are modeled.

Unless otherwise specified, the term “sensor” refers to the IPMI sensor-model definition of a sensor.

4.3.2 Core Sensor List for EPSD Platforms Based on Intel

®

Processor E5

4600/2600/2400/1600/1400 Product Families

Specific server boards may only implement a sub-set of sensors and/or may include additional sensors.

The system-specific details of supported sensors and events are described in the Appendix of this document. The actual sensor name associated with a sensor number may vary between server boards or systems.

Sensor Type Codes

Sensor table given below lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. Refer to the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.

 Sensor Type

The sensor type references the values in the Sensor Type Codes table in the Intelligent Platform

Management Interface Specification Second Generation v2.0. It provides a context to interpret the sensor.

 Event/Reading Type

The event/reading type references values from the Event/Reading Type Code Ranges and the

Generic Event/Reading Type Code tables in the Intelligent Platform Management Interface

Specification Second Generation v2.0. Digital sensors are specific type of discrete sensors that only have two states.

 Event Thresholds/Triggers

The following event thresholds are supported for threshold type sensors:

- [u,l][nr,c,nc] upper non-recoverable, upper critical, upper non-critical, lower non-recoverable, lower critical, lower non-critical uc, lc upper critical, lower critical

Event triggers are supported event-generating offsets for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Code or Sensor Type Code tables in the Intelligent



Platform Management Interface Specification Second Generation, Version 2.0, depending on whether the sensor event/reading type is generic or a sensor-specific response.

 Assertion/Deassertion

Assertion and de-assertion indicators reveal the type of events this sensor generates:

-

As: Assertion

- De: De-assertion

 Readable Value/Offsets

-

Readable value indicates the type of value returned for threshold and other nondiscrete type sensors.

- Readable offsets indicate the offsets for discrete sensors that are readable by means of the Get Sensor Reading command. Unless otherwise indicated, event triggers are readable. Readable offsets consist of the reading type offsets that do not generate events.

 Event Data

Event data is the data that is included in an event message generated by the associated sensor.

For threshold-based sensors, these abbreviations are used:

-

R: Reading value

-

T: Threshold value

 Rearm Sensors

The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used in the comment column to describe a sensor:

-

A: Auto-rearm

- M: Manual rearm

-

I: Rearm by init agent

 Default Hysteresis

The hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which can be 1 or 2 (positive or negative hysteresis).

 Criticality

Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the front panel status LED.

 Standby

Some sensors operate on standby power. These sensors may be accessed and/or generate events when the main (system) power is off, but AC power is present.

4.3.3 BMC System Management Health Monitoring

The BMC tracks the health of each of its IPMI sensors and report failures by providing a “BMC FW

Health” sensor of the IPMI 2.0 sensor type Management Subsystem Health with support for the Sensor

Failure offset. Only assertions should be logged into the SEL for the Sensor Failure offset. The sensor number of the failed sensor is provided in event data byte 2, as per the IPMI 2.0 Specification. The BMC

Firmware Health sensor asserts for any sensor when 10 consecutive sensor errors are read. These are not standard sensor events (that is, threshold crossings or discrete assertions). These are BMC Hardware

Access Layer (HAL) errors like I2C NAKs or internal errors while attempting to read a register. If a successful sensor read is completed, the counter resets to zero.

IPMI Sensor Characteristics



1. Event reading type code: 6Fh (Sensor specific)

2. Sensor type code: 28h (Management Subsystem Health)

3. Rearm type: Auto

If this sensor is implemented, then the following sensor-specific offsets are supported.

Table 14. Supported BMC FW Health Sensor Offsets

Offset

04h

Description

Sensor failure

Event Logging

Assertion and deassertion

4.3.4 Processor Sensors

The BMC provides IPMI sensors for processors and associated components, such as voltage regulators and fans. The sensors are implemented on a per-processor basis.

Table 15. Processor Sensors

Sensor Name

Processor Status

Digital Thermal Sensor

Processor VRD Over-Temperature

Indication

Processor Voltage

Per-Processor

Socket

Yes

Yes

Yes

Yes

Processor Thermal Control (Prochot) Yes

Description

Processor presence and fault state

Relative temperature reading by means of PECI

Discrete sensor that indicates a processor VRD has crossed an upper operating temperature threshold

Threshold sensor that indicates a processor power-good state

Percentage of time a processor is throttling due to thermal conditions

4.3.4.1 Processor Status Sensors

The BMC provides an IPMI sensor of type processor for monitoring status information for each processor slot. If an event state (sensor offset) has been asserted, it remains asserted until one of the following happens:

1. A Rearm Sensor Events command is executed for the processor status sensor.

2. AC or DC power cycle, system reset, or system boot occurs.

The BMC provides system status indication to the front panel LEDs for processor fault conditions shown

in Table 16.

CPU Presence status is not saved across AC power cycles and therefore will not generate a de-assertion after cycling AC power.

Table 16. Processor Status Sensor Implementation

3

4

5

Offset

0

1

2

Internal error (IERR)

Thermal trip

Processor Status Detected By

Not Supported

BMC

FRB1/BIST failure

FRB2/Hang in POST failure

Not Supported

BIOS

1

FRB3/Processor startup/initialization failure (CPU fails to start) Not Supported

Configuration error (for DMI) BIOS

1



4.3.4.1.1

Offset

6

7

8

Processor presence detected

Processor disabled

Processor Status

SM BIOS uncorrectable CPU-complex error

9 Terminator presence detected

Note: Fault is not reflected in the processor status sensor.

Processor Presence

Detected By

Not Supported

BMC

Not Supported

Not Supported

Upon BMC initialization, which occurs when AC power is applied or the BMC is reset, the processor presence offset is initialized to the deasserted state and then the BMC checks to see if the processor is present and sets the presence offset accordingly.

This state is updated at each DC power-on and at system resets. The net effect of this is that there should be one event logged at BMC startup for processor presence for each installed processor, assuming the SDR is configured to generate the event. No additional events for processor presence are expected unless the sensor is manually re-armed using an IPMI command or a processor is removed or inserted. Note that removal and insertion should only occur when AC power is removed from the system so it is not expected that a SEL entry will be seen for this specific occurrence.

4.3.4.2 Processor Population Fault (CPU Missing) Sensor

The BMC supports a Processor Population Fault sensor for monitoring for the condition in which processor slots are not populated as required by the platform HW to allow power-on of the system.

At BMC startup, the BMC will check for the fault condition and set the sensor state accordingly.

The BMC also checks for this fault condition at each attempt to DC power-on the system. At each DC power-on attempt, a beep code is generated if this fault is detected. Please refer Table

9 (BMC Beep Codes) for beep code details.

The following steps are used to correct the fault condition and clear the sensor state:

1. AC power down the server.

2. Install the missing processor into the correct slot.

3. AC power on the server.

Refer to the applicable platform BMC EPS as to the details of what population rules must be followed.

4.3.4.3 ERR2 Timeout Monitoring

The BMC supports an ERR2 Timeout Sensor (1 per CPU) that asserts if a CPU’s ERR2 signal has been asserted for longer than a fixed time period (> 90 seconds). ERR[2] is a processor signal that indicates when the IIO (Integrated IO module in the processor) has a fatal error which could not be communicated to the core to trigger SMI. ERR[2] events are fatal error conditions, where the BIOS and OS will attempt to gracefully handle error, but may not be always do so reliably. A continuously asserted ERR2 signal is an indication that the BIOS cannot service the condition that caused the error. This is usually because that condition prevents the BIOS from running.

When an ERR2 timeout occurs, the BMC asserts/deasserts the ERR2 Timeout Sensor, and logs a SEL event for that sensor. The default behavior for BMC core firmware is to initiate a system reset upon detection of an ERR2 timeout. The BIOS setup utility provides an option to disable or enable system reset by the BMC for detection of this condition.




1. Event reading type code: 03h (Generic

– digital discrete)

2. Sensor type code: 07h (Processor)

3. Rearm type: Auto

Table 17. Supported ERR2 Timeout Sensor Offsets

Offset

01h

Description

State asserted

Event Logging


4.3.4.4 CATERR Sensor and Market Segment ID (MSID) Mismatch

The BMC supports a CATERR sensor for monitoring the system CATERR signal.

The CATERR signal is defined as having 3 states; high (no event), pulsed low (possibly fatal may be able to recover), and low (fatal). All processors in a system have their CATERR pins tied together. The pin is used as a communication path to signal a catastrophic system event to all CPUs. The BMC has direct access to this aggregate CATERR signal.

The BMC only monitors for the “CATERR held low” condition. A pulsed low condition is ignored by the

BMC.

If a CATERR-low condition is detected, the BMC logs an error message to the SEL against the

CATERR sensor and then queries each CPU to determine if it was due to an MSID mismatch condition. An MSID mismatch occurs if a processor is installed into a system board that has incompatible power capabilities. The MSID mismatch condition is indicated in a processor machine check MSR. If PECI is nonfunctional (it isn’t guaranteed in this situation), then MSID mismatch can’t be detected in that case.

If the CATERR is due to an MSID mismatch, then the BMC will log an additional SEL log against the MSID Mismatch sensor, light the CPU fault LED, emit a beep code, and let the system hang. Please refer Table 9 (BMC Beep Codes) for beep code details. If no MSID mismatch is detected, then the default action after logging the SEL entry is to reset the system.

The BIOS setup utility provides an option to disable or enable system reset by the BMC for detection of this condition.

4.3.4.5 CATERR Sensor

The BMC supports a CATERR sensor for monitoring the system CATERR signal.

The sensor is rearmed on power-on (AC or DC power on transitions). It is not rearmed on system resets in order to avoid multiple SEL events that could occur due to a potential reset loop if the CATERR keeps recurring, which would be the case if the CATERR was due to an MSID mismatch condition.

On EPSD boards, the CATERR signal from each CPU are tied together and routed to the BMC as one signal. When the BMC detects that this aggregate CATERR signal has asserted, it can then go through

PECI to query each CPU to determine which one was the source of the error and write an OEM code identifying the CPU slot into an event data byte in the SEL entry. If PECI is nonfunctional (it isn’t guaranteed in this situation), then the OEM code should indicate that the source is unknown.

Event data byte 2 and byte 3 for CATERR sensor SEL events

ED2 - CATERR type.

0: Unknown

1: CATERR



2: CPU Core Error (not supported on EPSD Platforms Based on Intel

®

Xeon

®

Processor E5

4600/2600/2400/1600 Product Families)

3: MSID Mismatch

ED3 - CPU bitmap that causes the system CATERR.

[0]: CPU0

[1]: CPU1

[2]: CPU2

[3]: CPU3


1. Event reading type code: 03h (Digital discrete)

2. Sensor type code: 07h (Processor)

3. Rearm type: Manual

The following sensor-specific offsets are supported:

Table 18. Supported CATERR Sensor Offsets

Offset

01h

Description

State asserted

Event Logging


4.3.4.6 MSID Mismatch Sensor

The BMC supports a MSID Mismatch sensor for monitoring for the fault condition that will occur if there is a power rating incompatibility between a baseboard and an a processor

The sensor is rearmed on power-on (AC or DC power on transitions).


1. Event reading type code: 03h (Digital discrete)

2. Sensor type code:

3. Rearm type:

07h (Processor)

Manual

The following sensor-specific offsets are supported:

Offset

Table 19. Support MSID Mismatch Sensor Offsets

Description Event Logging

01h State asserted Assertion and deassertion

4.4 Thermal and Acoustic Management

The Intel

®


®

Workstation Board W2600CR offers multiple thermal and acoustic management features to maintain comprehensive thermal protection as well as intelligent fan speed control. The features can be adjusted in BIOS interface with path BIOS > Advanced > System

Acoustic and Performance Configuration.



4.4.1 Set Throttling Mode

Select the most appropriate memory thermal throttling mechanism for memory sub-system from

[Auto], [DCLTT], [SCLTT] and [SOLTT].

[Auto]

– BIOS automatically detect and identify the appropriate thermal throttling mechanism based on DIMM type, airflow input, DIMM sensor availability.

[DCLTT]

– Dynamic Closed Loop Thermal Throttling: for the SOD DIMM with system airflow input

[SCLTT]

– Static Close Loop Thermal Throttling: for the SOD DIMM without system airflow input

[SOLTT]

– Static Open Loop Thermal Throttling: for the DIMMs without sensor on dimm (SOD)

The default setting is [Auto].

4.4.2 Altitude

Select the proper altitude that the system is distributed from [300m or less], [301m-900m], [901m-1500m],

[Above 1500m] options. Lower altitude selection can lead to potential thermal risk. And higher altitude selection provides better cooling but with undesired acoustic and fan power consumption. If the altitude is known, higher altitude is recommended in order to provide sufficient cooling. The default setting is [301m

– 900m].

4.4.3 Set Fan Profile

[Performance] and [Acoustic] fan profiles are available to select. The Acoustic mode offers best acoustic experience and appropriate cooling capability covering mainstream and majority of the add-in cards.

Performance mode is designed to provide sufficient cooling capability covering all kinds of add-in cards on the market. The default setting is [Performance]

4.4.4 Fan PWM Offset

This feature is reserved for manual adjustment to the minimum fan speed curves. The valid range is from [0 to 100] which stands for 0% to 100% PWM adding to the minimum fan speed.

This feature is valid when Quiet Fan Idle Mode is at Enabled state. The default setting is [0].

4.4.5 Quiet Fan Idle Mode

This feature can be [Enabled] or [Disabled]. If enabled, the fan will either stopped or shift to a lower speed when the aggregate sensor temperatures are satisfied indicating the system is at ideal thermal/light loading conditions. When the aggregate sensor temperatures not satisfied, the fan will shift back to normal control curves. If disabled, the fan will never stopped or shift into lower fan speed whatever the aggregate sensor temperatures are satisfied or not. The default setting is [Disabled]

Note:

1. The above features may or may not be in effective depends on the actual thermal characters of a specific system.

2. Refer to System TPS for the board in Intel chassis thermal and acoustic management

3. Refer to Fan Control Whitepaper for the board in third party chassis fan speed control customization.



4.4.6 Thermal Sensor Input for Fan Speed Control

The BMC uses various IPMI sensors as inputs to FSC. Some of the sensors are actual physical sensor and some are

“virtual” sensors derived from calculation.

The following IPMI thermal sensors are used as input to the fan speed control:



Front Panel Temperature Sensor

1



Baseboard Temperature Sensor

2



CPU Margin Sensors

3,5,6



DIMM Thermal Margin Sensors

3,5



Exit Air Temperature Sensor

1, 4, 8





PCH Temperature Sensor

4,6

On-board Ethernet Controller Temperature Sensors

4, 6



Add-In Intel SAS/IO Module Temperature Sensors

4, 6





PSU Thermal Sensor

4, 9

CPU VR Temperature Sensors

4, 7



DIMM VR Temperature Sensors

4, 7

 iBMC Temperature Sensor

4, 7



Global Aggregate Thermal Margin Sensors

3, 8

Note:

1. For fan speed control in Intel chassis

2. For fan speed control in 3rd party chassis

3. Temperature margin from throttling threshold

4. Absolute temperature

5. PECI value

6. On-die sensor

7. On-board sensor

8. Virtual sensor

9. Available only when PSU has PMBus*

A simplified model is shown as below which gives a high level concept of the fan speed control structure.

Revision 1.2

Figure 25. High-level Fan Speed Control Process



4.4.7 Power Supply Status\Health Sensors

The BMC supports one Power Supply Status sensor for each system power supply module. In order to track problems in which the PSU firmware is not operating to full capacity, an additional case (degraded condition if the PSU firmware is not operating to full capacity) is added to the existing Power Supply Status sensor offset definitions. This is handled by assertion of the

“configuration error” offset of the PSU status sensor. These sensors are only supported for systems that use PMBus*-compliant power supplies.


1. Event reading type code: 6Fh (Sensor Specific)

2. Event sensor type code: 08h (Power Supply)

3. Rearm type: Auto

The following sensor-specific offsets are supported.

Table 20. Supported Power Supply Status Sensor Offsets

Offset

00h

01h

Description

Presence detected

– Asserted if power supply module is present. Events are only logged for power supply presence upon changes in the presence state after AC power is applied (no events logged for initial state).

Power supply failure detected

– Asserted if power supply module has failed.

The following codes for failure modes are put into the SEL Event Data 2 byte:



01h - Output voltage fault



02h - Output power fault



03h - Output over-current fault



04h - Over-temperature fault



05h

– Fan fault

The SEL Event Data 3 byte will have the contents of the associated

PMBus* Status register to allow for showing multiple conditions for the event. For example, Data 3 will have the contents of the

VOLTAGE_STATUS register at the time an Output Voltage fault was detected. Refer to the PMBus Specification for details on specific resister contents

Event Logging

Assertion and

Deassertion

Assertion and

Deassertion



Offset

02h

03h

06h

Description

Predictive failure

– Asserted if some condition, such as failing fan, has been detected that is likely to lead to a power supply module failure.

The following codes for warning modes are put into the SEL Event Data 2 byte:



01h - Output voltage warning



02h - Output power warning



03h - Output over-current warning



04h - Over-temperature warning



05h - Fan warning



06h - Under-voltage warning



07h - Input over-current warning



08h - Input over-power warning

The SEL Event Data 3 byte will have the contents of the associated

PMBus* Status register to allow for showing multiple conditions for the event. For example, Data 3 will have the contents of the

VOLTAGE_STATUS register at the time an Output Voltage Warning was detected. Refer to the PMBus Specification for details on specific resister contents.

Power supply AC lost

– Asserted if there is no AC power input to power supply module.

Configuration error

– The following codes for configuration errors are put into the SEL Event Data 2 byte:



01h - The BMC cannot access the PMBus* device on the PSU but its

FRU device is responding.



02h - The PMBUS_REVISION command returns a version number that is not supported (only version 1.1 and 1.2 are supported for platforms covered under this FW EAS).



03h - The PMBus* device does not successfully respond to the

PMBUS_REVISION command.



04h

– The PSU is incompatible with one or more PSUs that are present in the system.

05h

–The PSU FW is operating in a degraded mode (likely due to a failed firmware update).

Event Logging

Assertion and

Deassertion

Assertion and

Deassertion

Assertion and

Deassertion

4.4.8 System Event Sensor

The BMC supports a System Event sensor and logs SEL event for following events.

04h

Table 21. Support System Event Sensor Offsets

Offset

02h

Description

OEM code (Undetermined system HW failure)

PEF action

Event Logging

Assertion and

Deassertion

Assertion only

For offset 2, OEM code will be logged in event data byte 2 to indicate the type of failure. Only one value will be supported at this time, but others may be added in the future. The code for this particular fault will be 0x00 (PECI access failure) and all other values reserved. Upon detection of the CPU PECI fault condition, the offset shall assert. It shall deassert upon system power cycle or system reset. Assertion of offset 02h shall contribute a “fatal” condition to the system status as reflected in the Front Panel system status LED.



4.4.8.1 Update Related SEL Logging

BMC FW will support a single FW Update Status sensor. This sensor is used to generate SEL events related to update of embedded firmware on the platform. This includes updates to the BMC, BIOS, and

ME FW.


1. Event reading type code: 70h (OEM defined)

2. Sensor type code: 2Bh (Version Change)

3. Rearm type: Auto

This sensor is an event-only sensor that is not readable. Event generation is only enabled for assertion events. Since this is an event-only sensor it should be defined by a type-3 SDR as defined in the IPMI 2.0 Specification.

Offset

00h

01h

02h

Table 22. Supported Firmware Update Status Sensor Offsets

Description

Update started

Update completed successfully

Update failure

Event

Logging

Contribution to system health

Assertion OK

Assertion OK

Assertion OK

Event Data Bytes

Byte 2: [Bits 7:4] Target of update

0000b = BMC

0001b = BIOS

0010b = ME

0011b = EWS (Embedded Web server)

All other values reserved

[Bits 3:1] Target instance (zero-based)

Byte 3:

[Bits 0:0] Reserved

Reserved

Note: All reserved bits must be set to zero.

4.5 Platform Management Interface

This chapter describes the supported BMC communication interfaces:

1. Host SMS interface by means of low pin count (LPC)/keyboard controller style (KCS) interface

2. Host SMM interface by means of low pin count (LPC)/keyboard controller style (KCS) interface

3. Intelligent Platform Management Bus (IPMB) I2C interface

4. LAN interface using the IPMI-over-LAN protocols



4.5.1 Channel Management

Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. Commands are provided to

configure each channel for privilege levels and access modes. Table 23 shows the standard channel

assignments:

Table 23. Standard Channel Assignments

Channel ID

0

1

2

3

4

5

6

Interface

Primary IPMB

LAN 1

LAN 2

LAN3

1

(Provided by the Intel

®

Dedicated Server Management NIC)

Reserved

USB

Secondary IPMB

No

Yes

Supports

Sessions

Yes

Yes

Yes

No

No

7 SMM

8

– 0Dh

Reserved

0Eh Self

2

0Fh SMS/Receive Message Queue

Notes:

1. Optional hardware supported by the server system.

No

–

–

No

2. Refers to the actual channel used to send the request.

4.5.2 User Model

The BMC supports the IPMI 2.0 user model. 15 user IDs are supported. These 15 users can be assigned to any channel. The following restrictions are placed on user-related operations:

1. User names for User IDs 1 and 2 cannot be changed. These are always “” (Null/blank) and “root” respectively.

2.

User 2 (“root”) always has the administrator privilege level.

3. All user passwords (including passwords for 1 and 2) may be modified.

4. User IDs 3-15 may be used freely, with the condition that user names are unique. Therefore, no other users can be named “” (Null), “root,” or any other existing user name.

4.5.3 LAN Interface

The BMC implements both the IPMI 1.5 and IPMI 2.0 messaging models. These provide out-of-band local area network (LAN) communication between the BMC and the network.

Run-time determination of LAN channel capabilities can be determined by both standard IPMI defined mechanisms.



4.5.3.1 IPMI 1.5 Messaging

The communication protocol packet format consists of IPMI requests and responses encapsulated in an

IPMI session wrapper for authentication, and wrapped in an RMCP packet, which is wrapped in an

IP/UDP packet. Although authentication is provided, no encryption is provided, so administrating some settings, such as user passwords, through this interface is not advised. Session establishment commands are IPMI commands that do not require authentication or an associated session.

The BMC supports the following authentication types over the LAN interface.

1. None (no authentication)

2. Straight password/key

3. MD5

4.5.3.2 IPMI 2.0 Messaging

IPMI 2.0 messaging is built over RMCP+ and has a different session establishment protocol. The session commands are defined by RMCP+ and implemented at the RMCP+ level, not IPMI commands.

Authentication is implemented at the RMCP+ level. RMCP+ provides link payload encryption, so it is possible to communicate private/sensitive data (confidentiality).

The BMC supports the cipher suites identified in Table 24.

Table 24. Supported RMCP+ Cipher Suites

ID Authentication Algorithm

0

1

RAKP-none

1

2

RAKP-HMAC-SHA1

RAKP-HMAC-SHA1

Integrity Algorithm(s)

None

None

HMAC-SHA1-96

Confidentiality Algorithm(s)

None

None

None

3

6

7

8

RAKP-HMAC-SHA1

RAKP-HMAC-MD5

RAKP-HMAC-MD5

RAKP-HMAC-MD5

11 RAKP-HMAC-MD5

HMAC-SHA1-96

None

HMAC-MD5-128

HMAC-MD5-128

MD5-128

AES-CBC-128

None

None

AES-CBC-128

None

12 RAKP-HMAC-MD5 MD5-128 AES-CBC-128

Note: Cipher suite 0 defaults to callback privilege for security purposes. This may be changed by any administrator.

For user authentication, the BMC can be configured with ‘null’ user names, whereby password/key lookup is done based on ‘privilege level only’, or with non-null user names, where the key lookup for the session is determined by user name.

IPMI 2.0 messaging introduces payload types and payload IDs to allow data types other than IPMI commands to be transferred. IPMI 2.0 serial-over-LAN is implemented as a payload type.

Table 25. Supported RMCP+ Payload Types

Payload Type

00h

01h

02h

10h

– 15h

Feature

IPMI message N/A

IANA

Serial-over-LAN N/A

OEM explicit Intel (343)

Session setup N/A



4.5.3.3 RMCP/ASF Messaging

The BMC supports RMCP ping discovery in which the BMC responds with a pong message to an

RMCP/ASF ping request. This is implemented per the Intelligent Platform Management Interface

Specification Second Generation v2.0.

4.5.3.4 BMC LAN Channels

The BMC supports three RMII/RGMII ports that can be used for communicating with Ethernet devices.

Two ports are used for communication with the on-board NICs and one is used for communication with an

Ethernet PHY located on an optional add-in card (or equivalent on-board circuitry).

4.5.3.4.1 Baseboard NICs

The specific Ethernet controller (NIC) used on a server is platform-specific but all baseboard device options provide support for an NC-SI manageability interface. This provides a sideband high-speed connection for manageability traffic to the BMC while still allowing for a simultaneous host access to the

OS if desired.

The Network Controller Sideband Interface (NC-SI) is a DMTF industry standard protocol for the side band management LAN interface. This protocol provides a fast multi-drop interface for management traffic.

The baseboard NIC(s) are connected to a single BMC RMII/RGMII port that is configured for RMII operation. The NC-SI protocol is used for this connection and provides a 100 Mb/s full-duplex multi-drop interface which allows multiple NICs to be connected to the BMC. The physical layer is based upon RMII, however RMII is a point-to-point bus whereas NC-SI allows 1 master and up to 4 slaves. The logical layer

(configuration commands) is incompatible with RMII.

Multi-port baseboard NICs on some products will provide support for a dedicated management channel than can be configured to be hidden from the host and only used by the BMC. This mode of operation is configured by a BIOS setup option.

4.5.3.4.2 Dedicated Management Channel

An additional LAN channel dedicated to BMC usage and not available to host SW is supported by an optional add-in card. There is only a PHY device present on the add-in card. The BMC has a builtin MAC module that uses the RGMII interface to link with the card’s PHY. Therefore, for this dedicated management interface, the PHY and MAC are located in different devices.

The PHY on the card connects to the BMC’s other RMII/RGMII interface (that is, the one that is not connected to the baseboard NICs). This BMC port is configured for RGMII usage.

In addition to the use of an add-in card for a dedicated management channel, on systems that support multiple Ethernet ports on the baseboard, the system BIOS provides a setup option to allow one of these baseboard ports to be dedicated to the BMC for manageability purposes.

When this is enabled, that port is hidden from the OS.

4.5.3.4.3 Concurrent Server Management Use of Multiple Ethernet Controllers

Provided the HW supports a management link between the BMC and a NIC port, the BMC FW supports concurrent OOB LAN management sessions for the following combination:

 Two on-board NIC ports

 One on-board NIC and the optional dedicated add-in management NIC.

 Two on-board NICs and optional dedicated add-in management NIC.



All NIC ports must be on different subnets for the above concurrent usage models.

MAC addresses are assigned for management NICs from a pool of up to 3 MAC addresses allocated specifically for manageability. The total number of MAC addresses in the pool is dependent on the product HW constraints (for example,a board with 2 NIC ports available for manageability would have a

MAC allocation pool of 2 addresses).For these channels, support can be enabled for IPMI-over-LAN and

DHCP.

For security reasons, embedded LAN channels have the following default settings:

IP Address: Static

All users disabled

IPMI-enabled network interfaces may not be placed on the same subnet. This includes the Intel

®

Dedicated Server Management NIC and either of the BMC’s embedded network interfaces.

Host-BMC communication over the same physical LAN connection

– also known as “loopback” – is not supported. This includes “ping” operations.

On baseboards with more than two onboard NIC ports, only the first two ports can be used as BMC LAN channels. The remaining ports have no BMC connectivity.

 Maximum bandwidth supported by BMC LAN channels are as follows:

 BMC LAN1 (Baseboard NIC port) ----- 100M (10M in DC off state)

 BMC LAN 2 (Baseboard NIC port) ----- 100M (10M in DC off state)

 BMC LAN 3 (Dedicated NIC) ----- 1000M

4.5.3.5 Dedicated Management NIC MAC Address

For EPSD Platforms Based on Intel

®

Xeon

®

Processor E5 4600/2600/2400/1600/1400 Product Families each server board has either five or seven MAC addresses assigned to it at the Intel factory. The printed

MAC address is assigned to NIC1 on the server board.

If the platform has two NIC built into the main board then there will be five MAC addresses assigned as follows:

 NIC 1 MAC address (for OS usage)

 NIC 2 MAC address = NIC 1 MAC address + 1 (for OS usage)

 BMC LAN channel 1 MAC address = NIC1 MAC address + 2


 BMC LAN channel 3 (RMM) MAC address = NIC1 MAC address + 4

If the platform has four NIC built into the main board then there will be seven MAC addresses assigned as follows:

 NIC 1 MAC address (for OS usage)






 BMC LAN channel 3 (RMM) MAC address = NIC1 MAC address + 6.



4.5.3.6 IPV6 Support

In addition to IPv4, Intel

®

S1400/S1600/S2400/S2600 Server Platforms support IPv6 for manageability channels. Configuration of IPv6 is provided by extensions to the IPMI Set and Get LAN Configuration

Parameters commands as well as through a Web Console IPv6 configuration web page.

The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and completely independently. For example, IPv4 can be DHCP configured while IPv6 is statically configured or vice versa.

4.5.3.6.1 LAN Failover

The BMC FW provides a LAN failover capability such that the failure of the system HW associated with one LAN link will result in traffic being rerouted to an alternate link. This functionality is configurable by IPMI methods as well as by the BMC’s Embedded UI, allowing for user to specify the physical LAN links constitute the redundant network paths or physical

LAN links constitute different network paths. BMC will support only a all or nothin g” approach – that is, all interfaces bonded together, or none are bonded together.

The LAN Failover feature applies only to BMC LAN traffic. It bonds all available Ethernet devices but only one is active at a time. When enabled, If the active connection’s leash is lost, one of the secondary connections is automatically configured so that it has the same IP address

(the next active LAN link will be chosen randomly from the pool of backup LAN links with link status as “UP”). Traffic immediately resumes on the new active connection.

The LAN Failover enable/disable command may be sent at any time. After it has been enabled, standard IPMI commands for setting channel configuration that specify a LAN channel other than the first will return an error code.

Standard IPMI commands for getting channel configuration will return the cached settings for the inactive channels.

4.5.3.7 BMC IP Address Configuration

Enabling the BMC’s network interfaces requires using the Set LAN Configuration Parameter command to configure LAN configuration parameter 4, IP Address Source.

4.5.3.8 DHCP BMC Hostname

The BMC allows setting a DHCP Hostname. DHCP Hostname can be set regardless of the IP Address source configured on the BMC. But this parameter is only used if the IP Address source is set to DHCP.

4.5.3.9 Address Resolution Protocol (ARP)

The BMC can receive and respond to ARP requests on BMC NICs. Gratuitous ARPs are supported, and disabled by default.

4.5.3.10 Virtual Local Area Network (VLAN)

The BMC supports VLAN as defined by IPMI 2.0 specifications. VLAN is supported internally by the BMC, not through switches. VLAN provides a way of grouping a set of systems together so that they form a logical network. This feature can be used to set up a management VLAN where only devices which are members of the VLAN will receive packets related to management and members of the VLAN will be isolated from any other network traffic. Please note that VLAN does not change the behavior of the host network setting, it only affects the BMC LAN communication.



LAN configuration options are now supported (by means of the Set LAN Config Parameters command, parameters 20 and 21) that allow support for 802.1Q VLAN (Layer 2). This allows VLAN headers/packets to be used for IPMI LAN sessions. VLAN ID’s are entered and enabled by means of parameter 20 of the

Set LAN Config Parameters IPMI command. When a VLAN ID is configured and enabled, the BMC only accepts packets with that VLAN tag/ID. Conversely, all BMC generated LAN packets on the channel include the given VLAN tag/ID. Valid VLAN ID

’s are 1 through 4094, VLAN ID’s of 0 and 4095 are reserved, per the 802.1Q VLAN specification. Only one VLAN can be enabled at any point in time on a

LAN channel. If an existing VLAN is enabled, it must first be disabled prior to configuring a new VLAN on the same LAN channel.

Parameter 21 (VLAN Priority) of the Set LAN Config Parameters IPMI command is now implemented and a range from 0-7 will be allowed for VLAN Priorities. Please note that bits 3 and 4 of Parameter 21 are considered Reserved bits.

Parameter 25 (VLAN Destination Address) of the Set LAN Config Parameters IPMI command is not supported and returns a completion code of 0x80 (parameter not supported) for any read/write of parameter 25.

If the BMC IP address source is DHCP, then the following behavior is seen:

 If the BMC is first configured for DHCP (prior to enabling VLAN), when VLAN is enabled, the BMC performs a discovery on the new VLAN in order to obtain a new BMC IP address.

 If the BMC is configured for DHCP (before disabling VLAN), when VLAN is disabled, the

BMC performs a discovery on the LAN in order to obtain a new BMC IP address.

If the BMC IP address source is Static, then the following behavior is seen:

 If the BMC is first configured for static (prior to enabling VLAN), when VLAN is enabled, the BMC has the same IP address that was configured before. It is left to the management application to configure a different IP address if that is not suitable for VLAN.

 If the BMC is configure for static (prior to disabling VLAN), when VLAN is disabled, the

BMC has the same IP address that was configured before. It is left to the management application to configure a different IP address if that is not suitable for LAN.

4.5.3.11 Secure Shell (SSH)

Secure Shell (SSH) connections are supported for one SMASH-CLP session to the BMC.

4.5.3.12 Serial-over-LAN (SOL 2.0)

The BMC supports IPMI 2.0 SOL.

IPMI 2.0 introduced a standard serial-over-LAN feature. This is implemented as a standard payload type

(01h) over RMCP+.

Three commands are implemented for SOL 2.0 configuration.

1.

“Get SOL 2.0 Configuration Parameters” and “Set SOL 2.0 Configuration Parameters”: These commands are used to get and set the values of the SOL configuration parameters. The parameters are implemented on a per-channel basis.

2.

“Activating SOL”: This command is not accepted by the BMC. It is sent by the BMC when SOL is activated to notify a remote client of the switch to SOL.

3. Activating a SOL session requires an existing IPMI-over-LAN session. If encryption is used, it should be negotiated when the IPMI-over LAN session is established. Intel

®

Server Board S2600IP SOL



2

3

7

8

9

4

5

6

10

11

12 sessions are supported on serial port A (COM1). Intel

®

Workstation Board S2600IP SOL sessions are supported on serial port B (COM2).

4.5.3.13 Platform Event Filter (PEF)

The BMC includes the ability to generate a selectable action, such as a system power-off or reset, when a match occurs to one of a configurable set of events. This capability is called Platform Event Filtering, or

PEF. One of the available PEF actions is to trigger the BMC to send a LAN alert to one or more destinations.

The BMC supports 20 PEF filters. The first twelve entries in the PEF filter table are pre-configured (but may be changed by the user). The remaining entries are left blank, and may be configured by the user.

Event Filter

Number

1

Table 26. Factory Configured PEF Table Entries

Offset Mask Events

Temperature sensor out of range Non-critical, critical and nonrecoverable

Non-critical, critical and nonrecoverable

Non-critical, critical and nonrecoverable

General chassis intrusion

Failure and predictive failure

Uncorrectable ECC

POST error

FRB2

Policy Correction Time

Power down, power cycle, and reset

OEM system boot event

Drive Failure, Predicted Failure

Voltage sensor out of range

Fan failure

Chassis intrusion (security violation)

Power supply failure

BIOS

BIOS: POST code error

Watchdog Timer expiration for FRB2

Node Manager

Watchdog timer

System restart (reboot)

Hot Swap Controller

Additionally, the BMC supports the following PEF actions:



Power off



Power cycle





Reset

OEM action



Alerts

The “Diagnostic interrupt” action is not supported.

4.5.3.14 LAN Alerting

The BMC supports sending embedded LAN alerts, called SNMP PET (Platform Event traps), and SMTP email alerts.

The BMC supports a minimum of four LAN alert destinations.



4.5.3.14.1 SNMP Platform Event Traps (PETs)

This feature enables a target system to send SNMP traps to a designated IP address by means of LAN.

These alerts are formatted per the Intelligent Platform Management Interface Specification Second

Generation v2.0. A MIB file associated with the traps is provided with the BMC firmware to facilitate interpretation of the traps by external software.

The format of the MIB file is covered under RFC 2578.

4.5.3.15 Alert Policy Table

Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is to be sent. There is a maximum of 20 alert policy entries. There are no pre-configured entries in the alert policy table because the destination types and alerts may vary by user. Each entry in the alert policy table contains four bytes for a maximum table size of 80 bytes.

4.5.3.15.1 E-mail Alerting

The Embedded Email Alerting feature allows the user to receive e-mails alerts indicating issues with the server. This allows e-mail alerting in an OS-absent (for example, Pre-OS and OS-Hung) situation. This feature provides support for sending e-mail by means of SMTP, the Simple Mail Transport Protocol as defined in Internet RC 821. The e-mail alert provides a text string that describes a simple description of the event. SMTP alerting is configured using the embedded web server.

4.5.3.16 SM-CLP (SM-CLP Lite)

SMASH refers to Systems Management Architecture for Server Hardware. SMASH is defined by a suite of specifications, managed by the DMTF, that standardize the manageability interfaces for server hardware. CLP refers to Command Line Protocol. SM-CLP is defined by the Server Management Command Line Protocol Specification (SM-CLP) ver1.0, which is part of the SMASH suite of specifications. The specifications and further information on SMASH can be found at the DMTF website ( http://www.dmtf.org/ ).

The BMC provides an embedded “lite” version of SM-CLP that is syntax-compatible but not considered fully compliant with the DMTF standards.

4.5.3.17 Embedded Web Server

BMC Base manageability provides an embedded web server and an OEM-customizable web

GUI which exposes the manageability features of the BMC base feature set. It is supported over all on-board NICs that have management connectivity to the BMC as well as an optional dedicated add-in management NIC. At least two concurrent web sessions from up to two different users is supported. The embedded web user interface shall support the following client web browsers:

 Microsoft Internet Explorer 7.0*



 Mozilla Firefox 3.0*



The embedded web user interface supports strong security (authentication, encryption, and firewall support) since it enables remote server configuration and control. Embedded web server uses ports #80 and #443. The user interface presented by the embedded web user interface


Platform Management Overview shall authenticate the user before allowing a web session to be initiated. Encryption using 128bit SSL is supported. User authentication is based on user id and password.

The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated. It presents all functions to all users but grays-out those functions that the user does not have privilege to execute. (For example, if a user does not have privilege to power control, then the item shall be displayed in greyout font in that user’s UI display). The web GUI also provides a launch point for some of the advanced features, such as KVM and media redirection. These features are grayed out in the GUI unless the system has been updated to support these advanced features.

Additional features supported by the web GUI includes:

 Presents all the Basic features to the users.

 Power on/off/reset the server and view current power state.

 Displays BIOS, BMC, ME and SDR version information.

 Display overall system health.

 Configuration of various IPMI over LAN parameters for both IPV4 and IPV6

 Configuration of alerting (SNMP and SMTP).

 Display system asset information for the product, board, and chassis.

 Display of BMC-owned sensors (name, status, current reading, enabled thresholds), including color-code status of sensors.

 Provides ability to filter sensors based on sensor type (Voltage, Temperature, Fan and

Power supply related)

 Automatic refresh of sensor data with a configurable refresh rate.

 On-line help.

 Display/clear SEL (display is in easily understandable human readable format).

 Supports major industry-standard browsers (Microsoft Internet Explorer* and Mozilla

Firefox*).

 The GUI session automatically times-out after a user-configurable inactivity period. By default, this inactivity period is 30 minutes.

 Embedded Platform Debug feature - Allow the user to initiate a “diagnostic dump” to a file that can be sent to Intel for debug purposes.

 Virtual Front Panel. The Virtual Front Panel provides the same functionality as the local front panel. The displayed LEDs match the current state of the local panel LEDs. The displayed buttons (for example,power button) can be used in the same manner as the local buttons.

 Display of ME sensor data. Only sensors that have associated SDRs loaded will be displayed.

 Ability to save the SEL to a file.

 Ability to force HTTPS connectivity for greater security. This is provided through a configuration option in the UI.

 Display of processor and memory information as is available over IPMI over LAN.

 Ability to get and set Node Manager (NM) power policies.

 Display of power consumed by the server.

 Ability to view and configure VLAN settings.

 Warn user the reconfiguration of IP address will cause disconnect.

 Capability to block logins for a period of time after several consecutive failed login attempts. The lock-out period and the number of failed logins that initiates the lock-out period are configurable by the user.

 Server Power Control - Ability to force into Setup on a reset.



4.5.3.18 Virtual Front Panel

 Virtual Front Panel is the module present as “Virtual Front Panel” on the left side in the embedded web server when "remote Control" tab is clicked.

 Main Purpose of the Virtual Front Panel is to provide the front panel functionality virtually.

 Virutal Front Panel (VFP) will mimic the status LED and Power LED status and Chassis ID alone. It is automatically in sync with BMC every 40 seconds.

 For any abnormal status LED state, Virtual Front Panel will get the reason behind the abnormal or status LED changes and displayed in VFP side.

 As Virtual Front Panel uses the chass is control command for power actions. It won’t log the Front button press event since Logging the front panel press event for Virtual Front

Panel press will mislead the administrator.

 For Reset from Virtual Front Panel , the reset will be done by a “Chassis control” command.

 For Reset from Virtual Front Panel, the restart cause will be because of “Chassis control” command.

 During Power action, Power button/Reset button should not accept the next action until current Power action is complete and the acknowledgment from BMC is received.

 EWS will provide a valid message during Power action until it completes the current Power action.

 The VFP does not have any effect on whether the front panel is locked by “Set Front Panel

Enables” command.

 The chassis ID LED provides a visual indication of a system being serviced. The state of the chassis ID LED is affected by the following actions:

 Toggled by turning the chassis ID button on or off.

 There is no precedence or lock-out mechanism for the control sources. When a new request arrives, previous requests are terminated. For example, if the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is pressed again, then the chassis ID LED turns off.

 Note that the chassis ID will turn on because of the original chassis ID button press and will reflect in the Virtual Front Panel after VFP sync with BMC. Virtual Front Panel won’t reflect the chassis LED software blinking by the software command as there is no mechanism to get the chassis ID Led status.

 Only Infinite chassis ID ON/OFF by the software command will reflect in EWS during automatic /manual EWS sync up with BMC.

 Virtual Front Panel help should available for virtual panel module.

 At present, NMI button in VFP is disabled in Intel ®

S1400/S1600/S2400/S2600 Server

Platforms. It can be used in future.

4.5.3.19 Embedded Platform Debug

The Embedded Platform Debug feature supports capturing low-level diagnostic data (applicable MSRs,

PCI config-space registers, and so on). This feature allows a user to export this data into a file that is retrievable from the embedded web GUI, as well as through host and remote IPMI methods, for the purpose of sending to an Intel engineer for an enhanced debugging capability. The files are compressed, encrypted, and password protected. The file is not meant to be viewable by the end user but rather to provide additional debugging capability to an Intel support engineer.

4.5.3.20 Data Center Management Interface (DCMI)

The DCMI Specification is an emerging standard that is targeted to provide a simplified management interface for Internet Portal Data Center (IPDC) customers. It is expected to become a requirement for


Platform Management Overview server platforms which are targeted for IPDCs. DCMI is an IPMI-based standard that builds upon a set of required IPMI standard commands by adding a set of DCMI-specific IPMI OEM commands. Intel

®

S1400/S1600/S2400/S2600 Server Platforms will be implementing the mandatory DCMI features in the

BMC firmware (DCMI 1.1 Errata 1 compliance). Please refer to DCMI 1.1 errata 1 spec for details. Only mandatory commands will be supported. No support for optional DCMI commands. Optional power management and SEL roll over feature is not supported. DCMI Asset tag will be independent of baseboard FRU asset Tag. Please refer table DCMI Group Extension Commands for more details on

DCMI commands.

4.5.3.21 Lightweight Directory Authentication Protocol (LDAP)

The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the BMC for the purpose of authentication and authorization. The BMC user connects with an LDAP server for login authentication. This is only supported for non-IPMI logins including the embedded web UI and SM-CLP.

IPMI users/passwords and sessions are not supported over LDAP.

LDAP can be configured (IP address of LDAP server, port, and so on) from the BMC’s Embedded Web UI.

LDAP authentication and authorization is supported over the any NIC configured for system management.

The BMC uses a standard Open LDAP implementation for Linux.

Only open LDAP is supported by BMC. Windows and Novel LDAP are not supported.

4.6 BMC Firmware Update

4.6.1 The BMC firmware release Number

The BMC firmware releases are numbered as follows:

AB.CD.XXX

Where:

CD is a two digit number starting with 00 for the first release. This is the number returned in minor ID in

Get Device ID response.

B is major release number (1 for the first major release typically at first production shipment).

A is point release indicator (A=0 means this is a regular official release, A=1 means this is a point release for limited distribution). A hex representation of “AB” is returned in major ID in Get Device ID response.

XXX is the build number for internal tracking. This number is returned in OEM bytes of Get Device ID response.

4.6.2 Boot Recovery Mode

The BMC’s boot block supports firmware transfer updates. The Operational Firmware Transfer mode preserves several files in the PIA Linux file system. Boot Recovery mode cannot preserve the files because it does not understand Linux file systems, and treats it as a large binary data section. This means a Boot Recovery update completely replaces the PIA with the factory default version: an empty

SEL, a default SDR, and default IPMI configuration and user settings.

Boot Recovery mode can successfully complete an update in some situations where the Operational

Firmware Transfer mode will fail. If there is an incompatibility or bug in the operational code causing it to crash or hang, only a Boot Recovery Mode Update works. Another example is if the flash layout of the sections changes across an update. Because the operational Firmware Transfer mode tries to preserve


Platform Management Overview the contents of the PIA section, in this case, it will corrupt the flash where the old PIA section was.

Because the Boot Recovery mode is blindly writing binary data to flash, in this case, it will succeed.

There are two ways to enter Boot Recovery mode:

 The Force Firmware Update jumper is asserted when A/C power is applied.

 The operational code is corrupt and the boot loader cannot boot.

In the Boot Recovery mode, the BMC only responds to the small set of commands listed above. Only the

KCS SMS interface is supported; USB-based Fast Firmware Update is not supported.

4.6.3 Force Firmware Update Jumper

The Force Firmware Update jumper can be used to put the BMC in Boot Recovery mode for a low-level update. It causes the BMC to abort its normal boot process and stay in the boot loader without executing any Linux code.

The jumper is normally in the de-asserted position. The system must be completely powered off (A/C power removed) before the jumper is moved. After power is re-applied and the firmware update is complete, the system must be powered off again and the jumper must be returned to the de-asserted position before normal operation can begin.

There is no boot

–block-write protection jumper.

4.6.4 Fast Firmware Update over USB

The BMC supports a Fast Firmware Update mode in addition to the standard KCS SMS interface. This is a special protocol that goes over the USB connection between the host and the BMC.



4.7 Advanced Management Feature Support

This section explains the advanced management features supported by the BMC firmware.

4.7.1 Enabling Advanced Management Features

The Advanced management features are to be delivered as part of the BMC FW image. The

BMC’s baseboard SPI flash contains code/data for both the Basic and Advanced features. An optional add-in card Intel

®

RMM4 lite is used as the activation mechanism. When the BMC FW initializes, it attempts to access the Intel

®

RMM4 lite. If the attempt to access Intel

®

RMM4 lite is successful, then the BMC activates the Advanced features.

Advanced manageability features are supported over all NIC ports enabled for server manageability. This includes baseboard NICs as well as the LAN channel provided by the optional Dedicated NIC add-in card.

RMM4 is comprised of two boards

– RMM4 lite and the optional Dedicated Server Management NIC

(DMN). If the optional Dedicated Server Management NIC is not used then the traffic can only go through the onboard Integrated BMC-shared NIC and share network bandwidth with the host system.

Table 27. Enabling Advanced Management Features

Manageability Hardware

Intel

®

Integrated BMC

Benefits

Comprehensive IPMI based base manageability features

Intel

®

Remote Management Module 4

– Lite

Package contains one module

–

1- Key for advance Manageability features.

Intel

®

Remote Management Module 4

Package includes 2 modules

–

1 - key for advance features

2 - Dedicated NIC (1Gbe) for management

No dedicated NIC for management

Enables KVM and media redirection from the onboard

NIC

Dedicated NIC for management traffic. Higher bandwidth connectivity for KVM and media

Redirection with 1Gbe NIC.

4.7.2 Keyboard, Video, Mouse (KVM) Redirection

The BMC firmware supports keyboard, video, and mouse redirection (KVM) over LAN. This feature is available remotely from the embedded web server as a Java applet. This feature is only enabled when the Intel

®

RMM4 lite is present. The client system must have a Java Runtime Environment (JRE) version

6.0 or later to run the KVM or media redirection applets.

The BMC supports an embedded KVM application (Remote Console) that can be launched from the embedded web server from a remote console. USB1.1 or USB 2.0 based mouse and keyboard redirection are supported. It is also possible to use the KVM-redirection (KVM-r) session concurrently with media-redirection (media-r). This feature allows a user to interactively use the keyboard, video, and mouse (KVM) functions of the remote server as if the user were physically at the managed server.

KVM redirection console support the following keyboard layouts: English, Dutch, French,

German, Italian, Russian, and Spanish.



KVM redirection includes a “soft keyboard” function. The “soft keyboard” is used to simulate an entire keyboard that is connected to the remote system.

The “soft keyboard” functionality supports the following layouts: English, Dutch, French, German, Italian, Russian, and Spanish.

The KVM-redirection feature automatically senses video resolution for best possible screen capture and provides high-performance mouse tracking and synchronization. It allows remote viewing and configuration in pre-boot POST and BIOS setup, once BIOS has initialized video.

Other attributes of this feature include:

 Encryption of the redirected screen, keyboard, and mouse

 Compression of the redirected screen.

 Ability to select a mouse configuration based on the OS type.

 supports user definable keyboard macros.

KVM redirection feature supports the following resolutions and refresh rates:

 640x480 at 60Hz, 72Hz, 75Hz, 85Hz, 100Hz

 800x600 at 60Hz, 72Hz, 75Hz, 85Hz

 1024x768 at 60Hx, 72Hz, 75Hz, 85Hz

 1280x960 at 60Hz

 1280x1024 at 60Hz

 1600x1200 at 60Hz

 1920x1080 (1080p),

 1920x1200 (WUXGA)

 1650x1080 (WSXGA+)

4.7.2.1 Force-enter BIOS Setup

KVM redirection can present an option to force-enter BIOS Setup. This enables the system to enter F2 setup while booting which is often missed by the time the remote console redirects the video.

4.7.3 Media Redirection

The embedded web server provides a Java applet to enable remote media redirection. This may be used in conjunction with the remote KVM feature, or as a standalone applet.

The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server.

Once mounted, the remote device appears just like a local device to the server, allowing system administrators or users to install software (including operating systems), copy files, update BIOS, and so on, or boot the server from this device.

The following capabilities are supported:

 The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are useable in parallel.

 Either IDE (CD-ROM, floppy) or USB devices can be mounted as a remote device to the server.

 It is possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. See the

Tested/supported Operating System List for more information.

 Media redirection supports redirection for both a virtual CD device and a virtual

Floppy/USB device concurrently. The CD device may be either a local CD drive or else an

ISO image file; the Floppy/USB device may be either a local Floppy drive, a local USB device, or else a disk image file.



 The media redirection feature supports multiple encryption algorithms, including RC4 and

AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities.

 A remote media session is maintained even when the server is powered-off (in standby mode). No restart of the remote media session is required during a server reset or power on/off. An BMC reset (for example,due to an BMC reset after BMC FW update) will require the session to be re-established

 The mounted device is visible to (and useable by) managed system’s OS and BIOS in both pre-boot and post-boot states.

 The mounted device shows up in the BIOS boot order and it is possible to change the

BIOS boot order to boot from this remote device.

 It is possible to install an operating system on a bare metal server (no OS present) using the remotely mounted device. This may also require the use of KVM-r to configure the OS during install.

USB storage devices will appear as floppy disks over media redirection. This allows for the installation of device drivers during OS installation.

If either a virtual IDE or virtual floppy device is remotely attached during system boot, both the virtual IDE and virtual floppy are presented as bootable devices. It is not possible to present only a single-mounted device type to the system BIOS.



4.8 Intel

®

4.8.1 Overview

Power management deals with requirements to manage processor power consumption and manage power at the platform level to meet critical business needs. Node Manager (NM) is a platform resident technology that enforces power capping and thermal-triggered power capping policies for the platform. These policies are applied by exploiting subsystem knobs (such as processor P and T states) that can be used to control power consumption. NM enables data center power management by exposing an external interface to management software through which platform policies can be specified. It also implements specific data center power management usage models such as power limiting, and thermal monitoring.

The NM feature is implemented by a complementary architecture utilizing the ME, BMC, BIOS, and an

ACPI-compliant OS. The ME provides the NM policy engine and power control/limiting functions (referred to as Node Manager or NM) while the BMC provides the external LAN link by which external management software can interact with the feature. The BIOS provides system power information utilized by the NM algorithms and also exports ACPI Source Language (ASL) code used by OS-Directed Power

Management (OSPM) for negotiating processor P and T state changes for power limiting. PMBus*compliant power supplies provide the capability to monitoring input power consumption, which is necessary to support NM.

4.8.1.1 Hardware Requirements

NM is supported only on platforms that have the NM FW functionality loaded and enabled on the

Management Engine (ME) in the SSB and that have a BMC present to support the external LAN interface to the ME. NM power limiting features requires a means for the ME to monitor input power consumption for the platform. This capability is generally provided by means of PMBus*-compliant power supplies although an alternative model using a simpler SMBus* power monitoring device is possible (there is potential loss in accuracy and responsiveness using non-PMBus* devices). The NM SmaRT/CLST feature does specifically require PMBus*-compliant power supplies as well as additional hardware on the baseboard.

4.8.1.2 Features

NM provides feature support for policy management, monitoring and querying, alerts and notifications, and an external interface protocol. The policy management features implement specific IT goals that can be specified as policy directives for NM. Monitoring and querying features enable tracking of power consumption. Alerts and notifications provide the foundation for automation of power management in the data center management stack. The external interface specifies the protocols that must be supported in this version of NM.

4.8.1.3 ME Firmware Update

On server platforms, the ME FW uses a single operational image with a limited-functionality recovery image. In order to upgrade an operational image, a boot to recovery image must be performed. Unlike last generation platforms, the ME FW does not support an IPMI update mechanism except for the case that the system is configured with a dual-ME (redundant) image.

In order to conserve flash space, which the ME FW shares with BIOS, EPSD systems only support a single ME image. For this case, ME update is only supported by means of BIOS performing a direct update of the flash component. The recovery image only provides the basic functionality that is required to perform the update; therefore other ME FW features are not functional therefore when the update is in progress.



4.8.1.4 SmaRT/CLST

The power supply optimization provided by SmaRT/CLST relies on a platform HW capability as well as

ME FW support. When a PMBus*-compliant power supply detects insufficient input voltage, an overcurrent condition, or an over-temperature condition, it will assert the SMBAlert# signal on the power supply SMBus* (that is, the PMBus*). Through the use of external gates, this results in a momentary assertion of the PROCHOT# and MEMHOT# signals to the processors, thereby throttling the processors and memory. The ME FW also sees the SMBAlert# assertion, queries the power supplies to determine the condition causing the assertion, and applies an algorithm to either release or prolong the throttling, based on the situation.

System power control modes include:

1. SmaRT: Low AC input voltage event; results in a onetime momentary throttle for each event to the maximum throttle state

2. Electrical Protection CLST: High output energy event; results in a throttling hiccup mode with fixed maximum throttle time and a fix throttle release ramp time.

3. Thermal Protection CLST: High power supply thermal event; results in a throttling hiccup mode with fixed maximum throttle time and a fix throttle release ramp time.

When the SMBAlert# signal is asserted, the fans will be gated by HW for a short period (~100ms) to reduce overall power consumption. It is expected that the interruption to the fans will be of short enough duration to avoid false lower threshold crossings for the fan tach sensors; however, this may need to be comprehended by the fan monitoring FW if it does have this side-effect.

ME FW will log an event into the SEL to indicate when the system has been throttled by the

SmaRT/CLST power management feature. This is dependent on ME FW support for this sensor. Please refer ME FW EPS for SEL log details.

4.8.1.4.1 Dependencies on PMBus*-compliant Power Supply Support

The SmaRT/CLST system feature depends on functionality present in the ME NM SKU. This feature requires power supplies that are compliant with the PMBus Specification, Revision 1.2.

4.9 EU Lot 6 Mode

The European Union has set forth a stringent standby power consumption target for systems that are used as primary computing devices in office environments. Owing to the fact in office environments, pedestal servers are being used more and more as workstations and that Value servers could make their way into Home servers, this solution is being requested for some pedestal servers. HW support for EU

Lot6 will only be available for specific EPSD pedestal products.

In order to meet the standby power requirements for EU Lot6 it is necessary to remove power to the BMC, along with other components, when in the S5 state. As this operational mode impacts system feature support, the user has the option of enabling and disabling this mode from the BIOS setup screen utility.

BIOS is responsible for enabling/disabling the system hardware for EU Lot6 operation. It notifies the BMC of the current state with the OEM command Set EULot6 Mode. The BMC saves the state in persistent store and uses it to control special EU Lot6 internal processing during boot, sensor monitoring, and so on as needed.

Wake-on-LAN (WOL) is not supported in EU Lot6 mode.

4.9.1.1 Impact to System Features

The following system features are lost or impacted when EU Lot6 mode is enabled:

 Increased boot time (~15-20s) when system is DC power cycled.


System Security o This is due to the fact that both the BMC and BIOS are booting at the same time when the system is powered on (to S0 state). BIOS will need to allow extra time for the BMC to initialize to the point where it can communicate with BIOS.

Note: Even when EU Lot6 is not enabled and the system is AC cycled, this increased boot time is applicable if a user immediately attempts to power the system up (for example, pressing the power button), as in this case both the BMC and BIOS are booting at the same time.

 No LAN manageability when on standby, and therefore no remote OOB power on by

BMC.

 No support for SOL or KVM for monitoring the entire boot process. o Since BMC is initializing at the same time as BIOS, it will not be possible to have an SOL or KVM session established from the beginning of the system boot.

 FP status LED will behave differently (it will be off when on standby) rather than showing fault conditions present at the time the system was powered down.

 No beep code due to uninstalled CPU.

 No monitoring of any sensors when on standby.

 No detection/logging of any ThermTrip faults. o These result as the system is shut down by HW so BMC will not be available to detect that they occurred.

 Sensor monitoring after DC power-on will be delayed by the time it takes BMC to initialize its sensor subsystem (~15 to 20s), possibly losing SEL events or failing to provide correct FP LED status LED indication.

Note: This delay occurs on each AC cycle even when EU Lot6 mode is disabled.

 Chassis intrusion not detected when in standby

5. System Security

5.1 BIOS Password Protection

The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering.


System Security

There is also an option to require a Power On password entry in order to boot the system. If the

Power On Password function is enabled in Setup, the BIOS will halt early in POST to request a password before continuing POST.

Both Administrator and User passwords are supported by the BIOS. An Administrator password must be installed in order to set the User password. The maximum length of a password is

14 characters. A password can have alphanumeric (a-z, A-Z, 0-9) characters and it is case sensitive. Certain special characters are also allowed, from the following set:

! @ # $ % ^ & * ( ) - _ + = ?

The Administrator and User passwords must be different from each other. An error message will be displayed if there is an attempt to enter the same password for one as for the other.

The use of “Strong Passwords” is encouraged, but not required. In order to meet the criteria for a “Strong Password”, the password entered must be at least 8 characters in length, and must include at least one each of alphabetic, numeric, and special characters. If a “weak” password is entered, a popup warning message will be displayed, although the weak password will be accepted.

Once set, a password can be cleared by changing it to a null string. This requires the

Administrator password, and must be done through BIOS Setup or other explicit means of changing the passwords. Clearing the Administrator password will also clear the User password.

Alternatively, the passwords can be cleared by using the Password Clear jumper if necessary.

Resetting the BIOS configuration settings to default values (by any method) has no effect on the

Administrator and User passwords.

Entering the User password allows the user to modify only the System Time and System Date in the Setup Main screen. Other setup fields can be modified only if the Administrator password has been entered. If any password is set, a password is required to enter the BIOS setup.

The Administrator has control over all fields in the BIOS setup, including the ability to clear the

User password and the Administrator password.

It is strongly recommended that at least an Administrator Password be set, since not having set a password gives everyone who boots the system the equivalent of Administrative access.

Unless an Administrator password is installed, any User can go into Setup and change BIOS settings at will.

In addition to restricting access to most Setup fields to viewing only when a User password is entered, defining a User password imposes restrictions on booting the system. In order to simply boot in the defined boot order, no password is required. However, the F6 Boot popup prompts for a password, and can only be used with the Administrator password. Also, when a

User password is defined, it suppresses the USB Reordering that occurs, if enabled, when a new USB boot device is attached to the system. A User is restricted from booting in anything other than the Boot Order defined in the Setup by an Administrator.

As a security measure, if a User or Administrator enters an incorrect password three times in a row during the boot sequence, the system is placed into a halt state. A system reset is required to exit out of the halt state. This feature makes it more difficult to guess or break a password.

In addition, on the next successful reboot, the Error Manager displays a Major Error code 0048, which also logs a SEL event to alert the authorized user or administrator that a password


System Security access failure has occurred.

5.2 Trusted Platform Module (TPM) Support

The Trusted Platform Module (TPM) option is a hardware-based security device that addresses the growing concern on boot process integrity and offers better data protection. TPM protects the system start-up process by ensuring it is tamper-free before releasing system control to the operating system. A TPM device provides secured storage to store data, such as security keys and passwords. In addition, a TPM device has encryption and hash functions. The server board implements TPM as per TPM PC Client Specifications revision 1.2 by the Trusted Computing

Group (TCG).

A TPM device is optionally installed onto a high density 14pin connector labeled “TPM” on the server board, and is secured from external software attacks and physical theft. A pre-boot environment, such as the BIOS and operating system loader, uses the TPM to collect and store unique measurements from multiple factors within the boot process to create a system fingerprint. This unique fingerprint remains the same unless the pre-boot environment is tampered with. Therefore, it is used to compare to future measurements to verify the integrity of the boot process.

After the system BIOS completes the measurement of its boot process, it hands off control to the operating system loader and in turn to the operating system. If the operating system is

TPMenabled, it compares the BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before continuing the operating system boot process. Once the operating system is in operation, it optionally uses TPM to provide additional system and data security (for example, Microsoft Vista* supports Bitlocker drive encryption).

5.2.1 TPM security BIOS

The BIOS TPM support conforms to the TPM PC Client Implementation Specification for

Conventional BIOS and to the TPM Interface Specification, and the Microsoft Windows

BitLocker* Requirements. The role of the BIOS for TPM security includes the following:

 Measures and stores the boot process in the TPM microcontroller to allow a TPM enabled operating system to verify system boot integrity.

 Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM.

 Produces ACPI TPM device and methods to allow a TPM-enabled operating system to send TPM administrative command requests to the BIOS.

 Verifies operator physical presence. Confirms and executes operating system TPM administrative command requests.

 Provides BIOS Setup options to change TPM security states and to clear TPM ownership.

For additional details, refer to the TCG PC Client Specific Implementation Specification, the

TCG PC Client Specific Physical Presence Interface Specification, and the Microsoft BitLocker*


System Security

Requirement documents.

5.2.2 Physical Presence

Administrative operations to the TPM require TPM ownership or physical presence indication by the operator to confirm the execution of administrative operations. The BIOS implements the operator presence indication by verifying the setup Administrator password.

A TPM administrative sequence invoked from the operating system proceeds as follows:

1.

User makes a TPM administrative request through the operating system’s security software.

2. The operating system requests the BIOS to execute the TPM administrative command through TPM

ACPI methods and then resets the system.

3. The BIOS verifies the physical presence and confirms the command with the operator.

4. The BIOS executes TPM administrative command(s), inhibits BIOS Setup entry and boots

directly to the operating system which requested the TPM command(s).

5.2.3 TPM Security Setup Options

The BIOS TPM Setup allows the operator to view the current TPM state and to carry out rudimentary TPM administrative operations. Performing TPM administrative options through the

BIOS setup requires TPM physical presence verification.

Using BIOS TPM Setup, the operator can turn ON or OFF TPM functionality and clear the TPM ownership contents. After the requested TPM BIOS Setup operation is carried out, the option reverts to No Operation.

The BIOS TPM Setup also displays the current state of the TPM, whether TPM is enabled or disabled and activated or deactivated. Note that while using TPM, a TPM-enabled operating system or application may change the TPM state independent of the BIOS setup. When an operating system modifies the TPM state, the BIOS Setup displays the updated TPM state.

The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and allows the operator to take control of the system with TPM. You use this option to clear security settings for a newly initialized system or to clear a system for which the TPM ownership security key was lost.

5.2.3.1 Security Screen

To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel logo displays. The following message displays on the diagnostics screen and under the Quiet Boot logo screen:

Press <F2> to enter setup

When the Setup is entered, the Main screen displays. The BIOS Setup utility provides the

Security screen to enable and set the user and administrative passwords and to lock out the front panel buttons so they cannot be used. The Intel

®

Server Board S5520URT provides TPM settings through the security screen.

To access this screen from the Main screen, select the Security option.


System Security

Main Advanced

Main Advanced Security

Administrator Password Status

User Password Status

Set Administrator Password

Set User Password

Front Panel Lockout

TPM State

TPM Administrative Control

Server Management

<Installed/Not Installed>

<Installed/Not Installed>

[1234aBcD]

[1234aBcD]

Enabled/Disabled

Boot Options Boot Manager

<Enabled & Activated/Enabled & Deactivated/Disabled &

Activated/Disabled & Deactivated>

No Operation/Turn On/Turn Off/Clear Ownership

Figure 26. Setup Utility

– TPM Configuration Screen

Setup Item

TPM State*

TPM

Administrative

Control**

Table 28. TSetup Utility

– Security Configuration Screen Fields

Options

Enabled and

Activated

Enabled and

Deactivated

Disabled and

Activated

Disabled and

Deactivated

No Operation

Turn On

Turn Off

Clear Ownership

Help Text

[No Operation] - No changes to current state.

[Turn On] - Enables and activates

TPM.

[Turn Off] - Disables and deactivates

TPM.

Comments

Information only.

Shows the current TPM device state.

A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available.

An enabled and deactivated TPM is in the same state as a disabled

TPM except setting of TPM ownership is allowed if not present already.

An enabled and activated TPM executes all commands that use

TPM functions and TPM security operations will be available.


System Security

Setup Item Options Help Text

[Clear Ownership] - Removes the

TPM ownership authentication and returns the TPM to a factory default state.

Note: The BIOS setting returns to

[No Operation] on every boot cycle by default.

Comments

5.3 Intel

®

The Intel

®

Xeon

®

Processor E5-4600/2600/2400/1600 Product Families support Intel

Execution Technology (Intel

®

®

Trusted

TXT), which is a robust security environment. Designed to help protect against software-based attacks, Intel

®

Trusted Execution Technology integrates new security features and capabilities into the processor, chipset and other platform components.

When used in conjunction with Intel

®

Virtualization Technology, Intel

®

Trusted Execution

Technology provides hardware-rooted trust for your virtual applications.

This hardware-rooted security provides a general-purpose, safer computing environment capable of running a wide variety of operating systems and applications to increase the confidentiality and integrity of sensitive information without compromising the usability of the platform.

Intel

®

Trusted Execution Technology requires a computer system with Intel

®

Virtualization

Technology enabled (both VT-x and VT-d), an Intel

®

Trusted Execution Technology-enabled processor, chipset and BIOS, Authenticated Code Modules, and an Intel

®

Trusted Execution

Technology compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel

®

Trusted Execution

Technology requires the system to include a TPM v1.2, as defined by the Trusted Computing

Group TPM PC Client specifications, Revision 1.2.

When available, Intel Trusted Execution Technology can be enabled or disabled in the processor by a BIOS Setup option.

For general information about Intel

®

TXT, visit the Intel

®

Trusted Execution Technology website, http://www.intel.com/technology/security/ .


Connector/Header Locations and Pin-outs Intel® Workstation Board W2600CR TPS

6. Connector/Header Locations and Pin-outs

6.1 Power Connectors

6.1.1 Main Power Connector

Main server board power is supplied by one 12-pin power connector. The connector is labeled as “MAIN

PWR” on the left bottom of the server board. The following tables provide the pin-out for “MAIN PWR” connector.

Table 29. Main Power Connector Pin-out

8

9

10

11

12

4

5

6

7

Pin

1

2

3

Signal name

P3V3

P3V3

GND

P5V

GND

P5V

GND

PWRGD_PS_PWROK_PSU_R1

P5V_STBY_PSU

P12V

P12V

P3V3

20

21

22

23

24

Pin

13

14

15

16

17

18

19

Signal name

P3V3

N12V

GND

FM_PS_EN_PSU_N

GND

GND

GND

NC_PS_RES_TP

P5V

P5V

P5V

GND

6.1.2 CPU Power Connectors

On the server board are two white 8pin CPU power connectors labeled “CPU_1 PWR” and “CPU_2

PWR”. The following table provides the pin-out for both connectors.

Pin

1

2

3

4

GND

GND

GND

GND

Table 30. CPU_1 Power Connector Pin-out

Signal name Pin

5

6

7

8

P12V1

P12V1

P12V3A

P12V3A

Signal name

Table 31. CPU_2 Power Connector Pin-out

Pin

1

2

3

4

GND

GND

GND

GND

Signal name Pin

5

6

7

8

P12V2

P12V2

P12V3B

P12V3B

Signal name

6.1.3 Add-in Card Power Connectors

The serve board includes white 2x2-pin power connectors that provide supplemental power to high power PCIe x16 add-in cards (Video or GPGPU) that have power requirements that exceed the maximum power supplied by the riser slot. A cable from this connector may be routed to a matching connector on a riser card designed to support it or directly to the add-in cards that need them. Available power to each of these connectors is limited by the amount of


Server Board S2600IP and Intel® Connector/Header Locations and Pin-outs power provided by the power supply and the total power draw for the rest of the system. A power budget for the complete system should be performed to determine how much supplemental power is available to support any high power add-in cards.

Each connector is labeled as “OPT_12V_PWR” on the server board. The following table provides the pin-out for both connectors.

15

17

19

21

23

25

27

29

Pin

1

3

5

7

9

11

13

Table 32. Add-in Slot Power Pin-input ("OPT_12V_PWR")

Pin

1

2

Signal Name

GND

GND

Pin Signal Name

3 +12V

4 +12V

6.2 Front Panel Header and Connectors

The server board includes several connectors that provide various possible front panel options. This section provides a functional description and pin-out for each connector.

6.2.1 Front Panel Header

Included on the left edge of the server board is a 30-pin header consists of a 24-pin SSI compatible front panel header and a 4-pin header to support optional NIC3/4 LEDs. The 24-pin

SSI front panel header provides various front panel features including:

 Power/Sleep Button

 System ID Button

 NMI Button

 NIC Activity LEDs

 Hard Drive Activity LEDs

 System Status LED

 System ID LED

The following table provides the pin-out for this 30-pin header.

Table 33. Front Panel Header Pin-out

P3V3_AUX

Signal name

Key

FP_PWR_LED_BUF_N

P3V3

LED_HDD_ACTIVITY_N

FP_PWR_BTN_N

GND

FP_RST_BTN_N

GND

FP_ID_BTN_N

PU_FM_SIO_TEMP_SENSOR

FP_NMI_BTN_N

<Empty Pin>

LED_NIC_LINK2_ACT_FP_N

LED_NIC_LINK2_LNKUP_FP_N

16

18

20

22

24

26

28

30

Pin

2

4

6

8

10

12

14

Signal name

P3V3_AUX

P5V_STBY

FP_ID_LED_BUF_N

FP_LED_STATUS_GREEN_BUF_N

FP_LED_STATUS_AMBER_BUF_N

LED_NIC_LINK0_ACT_BUF_N

LED_NIC_LINK0_LNKUP_BUF_N

SMB_SENSOR_3V3STBY_DATA

SMB_SENSOR_3V3STBY_CLK

FP_CHASSIS_INTRUSION

LED_NIC_LINK1_ACT_BUF_N

LED_NIC_LINK1_LNKUP_BUF_N

<Empty Pin>

LED_NIC_LINK3_ACT_FP_N

LED_NIC_LINK3_LNKUP_FP_N



6.2.2 Front Panel USB Connector

The server board includes a 10-pin connector, that when cabled, can provide up to two USB ports to a front panel. The following table provides the connector pin-out.

Table 34. Front Panel USB Connector Pin-out

Pin

1

3

5

7

9

Signal Name

P5V_USB_FP

USB2_P13_F_DN

USB2_P13_F_DP

GND

KEY

Pin

2

Signal Name

P5V_USB_FP

4

6

USB2_P11_F_DN

USB2_P11_F_DP

8 GND

10 NA

6.2.3 Local Control Panel Connector

The server board includes a 7-pin connector that is used when the system is configured with the

Intel Local Control Panel with LCD support. The following table provides the pin-out for this connector.

Table 35. Local Front Panel Connector Pin-out

Pin

1

3

5

7

Signal Name

SMB_SENSOR_3V3STBY_DATA

SMB_SENSOR_3V3STBY_CLK

FM_LCP_ENTER_N

FM_LCP_RIGHT_N

6.3 On Board Storage Connectors

Pin

2

4

6

Signal Name

GND

P3V3_AUX

FM_LCP_LEFT_N

The server board provides connectors for support of several storage device options. This section provides a functional overview and pin-out of each connector.

6.3.1 SATA Connectors: 6Gbps

The board includes two white single port SATA only connectors capable of transfer rates of up to 6Gb/s. The following table provides the pin-out for both connectors.

Table 36. SATA 6Gbps Connector Pin-out

Pin

1

2

3

4

5

6

7

Signal Name

GND

SATA_TX_P

SATA_TX_N

GND

SATA_RX_N

SATA_RX_P

GND


Server Board S2600IP and Intel® Connector/Header Locations and Pin-outs

6.3.2 Multiport Mini-SAS/SATA Connectors

The board includes two 40-pin high density multiport mini-SAS/SATA connectors. On the board, these connectors are labeled as “SCU0 port(0-3)” supporting the chipset embedded SCU0 controller, and “SCU1 Port(4-7)”, supporting the embedded SCU1 controller. Both connectors can support up to four SATA or SAS ports each. By default, only the connector labeled “SCU0

Port(0-

3)” is enabled and has support for up to four SATA ports capable. The connector labeled

“SCU1 Port(4-7)” is only enabled when an optional 8-port SAS or SATA Intel ®

RAID C600

Upgrade Key is installed. The following tables provide the pin-out for each connector.

Table 37. Multiport SAS/SATA Connector Pin-out ("SCU_0 (0-3)")

Pin

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

Pin

A1

A2

A3

A4

A5

A6

A7

GROUND

SAS0_RX_C_DP

SAS0_RX_C_DN

GROUND

Signal name

A8

A9

A10

A11

A12

A13

A14

A15

SAS1_RX_C_DP

SAS1_RX_C_DN

GROUND

TP_SAS1_BACKPLANE_TYPE

GROUND

SGPIO_SAS1_DATAOUT

SGPIO_SAS1_DATAIN

A16

A17

A18

GROUND

SAS2_RX_C_DP

SAS2_RX_C_DN

GROUND

SAS3_RX_C_DP

SAS3_RX_C_DN

GROUND

MTH1 GROUND

MTH2 GROUND

MTH3 GROUND

MTH4 GROUND

Pin

B1

B2

B3

B4

B5

B6

B7

GROUND

SAS0_TX_C_DP

SAS0_TX_C_DN

GROUND

Signal name

SAS1_TX_C_DP

SAS1_TX_C_DN

GROUND

B8

B9

SGPIO_SAS1_CLOCK

SGPIO_SAS1_LOAD

B10 GROUND

B11 PD_SAS1_CONTROLLER_TYPE

B12 GROUND

B13 SAS2_TX_C_DP

B14 SAS2_TX_C_DN

B15 GROUND

B16 SAS3_TX_C_DP

B17 SAS3_TX_C_DN

B18 GROUND

MTH5 GROUND

MTH6 GROUND

MTH7 GROUND

MTH8 GROUND

Table 38. Multiport SAS/SATA Connector Pin-out ("SCU_1 (4-7)")

Signal name

GROUND

SAS4_RX_C_DP

SAS4_RX_C_DN

GROUND

SAS5_RX_C_DP

SAS5_RX_C_DN

GROUND

TP_SAS2_BACKPLANE_TYPE

GROUND

SGPIO_SAS2_DATAOUT

SGPIO_SAS2_DATAIN

GROUND

SAS6_RX_C_DP

Pin

B1

B2

B3

B4

Signal name

GROUND

SAS4_TX_C_DP

SAS4_TX_C_DN

GROUND

B5

B6

B7

B8

SAS5_TX_C_DP

SAS5_TX_C_DN

GROUND

SGPIO_SAS2_CLOCK

B9 SGPIO_SAS2_LOAD

B10 GROUND

B11 PD_SAS2_CONTROLLER_TYPE

B12 GROUND

B13 SAS6_TX_C_DP



Pin

A14

A15

A16

A17

A18

Signal name

SAS6_RX_C_DN

GROUND

SAS7_RX_C_DP

SAS7_RX_C_DN

GROUND

MTH1 GROUND

MTH2 GROUND

MTH3 GROUND

MTH4 GROUND

Pin Signal name

B14 SAS6_TX_C_DN

B15 GROUND

B16 SAS7_TX_C_DP

B17 SAS7_TX_C_DN

B18 GROUND

MTH5 GROUND

MTH6 GROUND

MTH7 GROUND

MTH8 GROUND

6.3.3

Intel

®

Key Connector

The server board provides one connector to support Intel

®

RAID C600 Upgrade Key. The Intel

®

RAID

C600 Upgrade Key is a small PCB board that enables different versions of RAID 5 software stack and/or upgrade from SATA to SAS storage functionality. The pin configuration of connector is identical and defined in the following table.

Table 39. Intel

®

RAID C600 Upgrade Key Connector Pin-out

6.3.4

Pin

1

2

3

4

Signal Name

GND

FM_PBG_DYN_SKU_KEY

GND

FM_SSB_SAS_SATA_RAID_KEY

HSBP_I2C Header

Table 40. HSBP_I2C Header Pin-out

Pin

1

2

3

Signal Name

SMB_HSBP_3V3STBY_DATA

GND

SMB_HSBP_3V3STBY_CLK

6.3.5 HDD LED Header

The server board includes a 2-pin hard drive activity LED header used with some SAS/SATA controller add-in cards. The header has the following pin-out.

Table 41. HDD LED Header Pin-out

Pin

1

Signal Name

LED_HDD_ACT_N

Pin

2 NA

Signal Name

6.3.6 Internal Type- A USB Connector

The server board includes two internal Type-A USB connector. The following table provides the pin-out for this connector.

Pin

1

3

Table 42. Type-A USB Connector Pin-out

Signal Name

P5V

USB2_P2_F_DP

Pin

2

4

Signal Name

USB2_P2_F_DN

GND



6.3.7 Internal eUSB SSD Header

The server board includes one 10-pin internal eUSB header with an intended usage of supporting USB

SSD devices. The following table provides the pin-out for this connector.

Table 43. eUSB SSD Header Pin-out

Pin

1

3

5

7

9

Signal Name

5V

USB2_P0_DN

USB2_P0_DP

GND

Key

Pin

2

4

6

Signal Name

NC

NC

NC

8 NC

10 LED_HDD_ACT_ZEPHER_N

6.4 Management and Security Connectors

6.4.1 RMM4_Lite Connector

A 7-pin Intel ® RMM4 Lite connector is included on the server board to support the optional Intel ® Remote

Management Module 4. There is no support for third-party management cards on this server board.

Pin

1

3

5

7

Table 44. RMM4_Lite Connector Pin-out

Signal Name

P3V3_AUX

KEY

DO

CS_N

Pin

2

4

6

8

DI

CLK

Signal Name

GND

GND

6.4.2 RMM4_NIC Connector

Table 45. RMM4_NIC Connector Pin-out

Pin

1

3

5

7

Signal Name

3V3_AUX

3V3_AUX

GND

GND

9 GND

11 GND

13 GND

15 GND

17 GND

19 GND

21 GND

23 GND

25 GND

27 GND

29 GND

10

12

14

16

18

20

Pin

2

4

6

8

22

24

26

28

30

Signal Name

MDIO

MDC

TXD_0

TXD_1

TXD_2

TXD_3

TX_CTL

RX_CTL

RXD_0

RXD_1

RXD_2

RXD_3

TX_CLK

RX_CLK

PRESENT#



6.4.3 TPM Connector

Table 46. TPM Connector Pin-out

Pin

1

3

5

7

9

Key

Signal Name

LPC_LAD<0>

IRQ_SERIAL

P3V3

RST_IBMC_NIC_N_R2

11 LPC_LAD<3>

13 GND

Pin

2

4

Signal Name

LPC_LAD<1>

GND

6

8

LPC_FRAME_N

GND

10 CLK_33M_TPM

12 GND

14 LPC_LAD<2>

6.4.4 PMBus* Connector

Table 47. PMBus* Connector Pin-out

Pin

1

2

3

4

5

Signal name

SMB_PMBUS_CLK_R

SMB_PMBUS_DATA_R

IRQ_SML1_PMBUS_ALERT_RC_N

GND

P3V3

6.4.5 Chassis Intrusion Header

The server board includes a 2-pin chassis intrusion header which can be used when the chassis is configured with a chassis intrusion switch. The header has the following pin-out.

Table 48. Chassis Intrusion Header Pin-out

6.4.6

Header State

Pins 1 and 2 closed

Pins 1 and 2 open

IPMB Connector

Description

FM_INTRUDER_HDR_N is pulled HIGH. Chassis cover is closed.

FM_INTRUDER_HDR_N is pulled LOW. Chassis cover is removed.

Table 49. IPMB Connector Pin-out

6.5 FAN Connectors

Pin

1

2

3

4

Signal Name

SMB_IPMB_5VSTBY_DATA

GND

SMB_IPMB_5VSTBY_CLK

P5V_STBY

The server board provides support for nine fans. Seven of them are system cooling fans, two of them are CPU fans.



6.5.1 System FAN Connectors

The six system cooling fan connectors near the front edge of the board are 6-Pin connectors; the one system cooling fan near edge of the board is a 4-Pin connectors. Following table provides the pin-out for all system fan connectors.

Table 50. 6-pin System FAN Connector Pin-out

Pin

1

2

3

4

5

6

Signal Name

GND

12V

TACH

PWM

PRSNT

FAULT

Table 51. 4-pin System FAN Connector Pin-out

Pin

1

2

3

4

Signal Name

GND

12V

TACH

PWM

6.5.2 CPU FAN Connector

The two CPU fan connectors are 4-pin fan connectors. Following table provides the pin-out for

CPU fan connectors.

Table 52. CPU FAN Connector Pin-out

Pin

1

2

3

4

Signal Name

GND

12V

TACH

PWM

6.6 Serial Port and Video Connectors

The server board includes two serial port connectors.

6.6.1 Serial Port A Connector (DB9, for Intel

®

Server Board S2600IP only)

Serial-A is an external RJ45 type connector and has the following pin-out configuration.

Pin

1

3

5

7

9

Table 53. Serial Port A Connector Pin-out

Signal Name

SPA_DCD

SPA_SOUT_N

GND

SPA_RTS

SPA_RI

Pin

2

4

6

8

SPA_SIN

SPA_DTR

SPA_DSR

SPA_CTS

Signal Name



6.6.2 Serial Port B Connector

Serial-B is an internal 10-pin DH-10 connector and has the following pin-out.

Table 54. Serial Port B Connector Pin-out

Pin

1

3

5

7

9

Signal Name

SPA_DCD

SPA_SIN

SPA_SOUT_N

SPA_DTR

GND

Pin

2

4

6

8

Signal Name

SPA_DSR

SPA_RTS

SPA_CTS

SPA_RI

6.6.3 Video Connector (For Intel

®

Server Board S2600IP only)

The following table details the pin-out definition of the external VGA connector.

Table 55. Video Connector Pin-out details

8

9

10

11

12

13

14

15

4

5

6

7

Pin

1

2

3

CRT_RED

CRT_GREEN

CRT_BLUE

Signal Name

N/C

GND

GND

GND

GND

P5V

GND

NC

CRT_DDCDATA

CRT_HSYNC

CRT_VSYNC

CRT_DDCCLK

96

Figure 27. Video Connector Pin-out



6.6.4 Internal Video header (For Intel

®

Workstation Board W2600CR only)

7

8

9

10

11

12

13

14

Pin

1

2

3

4

5

6

Signal Name

CRT_RED

GND

CRT_Green

GND

CRT_Blue

GND

CRT_VSYNC

GND

CRT_HSYN

Key

CRT_DDCDATA

VIDEO_IN_USE signal

CRT_DDCCLK

5V

Note: Intel

®

Corporation server boards support peripheral components and can contain a number of high-density VLSI and power delivery components that need adequate airflow to cool.

Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel

®

developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits.


Jumper Blocks

7. Jumper Blocks

The server boards have several 3-pin jumper blocks that you can use to configure, protect, or recover specific features of the server boards.

The following symbol identifies Pin 1 on each jumper block on the silkscreen:

▼

Figure 28. Jumper Blocks (J1C3, J1F1, J1F2, J2F3, J2F2)

Table 56. Server Board Jumpers (J1C3, J1F1, J1F2, J2F3, J2F2)

Jumper Name

J1F2: BIOS Recovery

J1F1: Bios Default

(CMOS Clear)

Pins System Results

1-2 Pins 1-2 should be connected for normal system operation. (Default)

2-3

1-2

2-3

J2F2: ME Force 1-2

The main system BIOS does not boot with pins 2-3 connected. The system only boots from EFI-bootable recovery media with a recovery BIOS image present.

These pins should have a jumper in place for normal system operation.

(Default)

If pins 2-3 are connected when AC power unplugged, the CMOS settings clear in 5 seconds. Pins 2-3 should not be connected for normal system operation.

ME Firmware Force Update Mode

– Disabled (Default)


Jumper Blocks

Jumper Name

Update

J1C1: BMC Force

Update

J2F3: Password Clear

Pins System Results

2-3

1-2

2-3

ME Firmware Force Update Mode

– Enabled

BMC Firmware Force Update Mode

– Disabled (Default)

BMC Firmware Force Update Mode

– Enabled

1-2

These pins should have a jumper in place for normal system operation.

(Default)

2-3

To clear administrator and user passwords, power on the system with pins 2-3 connected. The administrator and user passwords clear in 5-10 seconds after power on. Pins 2-3 should not be connected for normal system operation.

7.1 BIOS Default and Password Reset Usage Procedure

The BIOS Default (CMOS Clear) and Password Reset recovery features are designed to achieve the desired operation with minimum system down time. The usage procedure for these two features has changed from previous generation Intel

®

boards. The following procedure outlines the new usage model.

7.1.1 Set BIOS to default (Clearing the CMOS)

1. Power down the server and unplug the AC power cord.

2. Open the server chassis. For instructions, see your server chassis documentation.

3. Move the jumper from the default operating position (covering pins 1 and 2) to the reset/clear position (covering pins 2 and 3).

4. Wait five seconds.

5. Move the jumper back to the default position, covering pins 1 and 2.

6. Close the server chassis and reconnect the AC power cord.

7. Power up the server.

The CMOS is now cleared and you can reset it by going into the BIOS setup.

Note: Removing AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down, after the procedure is followed and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and reinstall the AC power cord. Power up the system and proceed to the <F2> BIOS Setup utility to reset the preferred settings.

7.1.2 Clearing the Password

1. Power down the server. Do not unplug the power cord.

2. Open the chassis. For instructions, see your server chassis documentation.

3. Move the jumper from the default operating position (covering pins 1 and 2) to the password clear position (covering pins 2 and 3).

4. Close the server chassis.

5. Power up the server and then press <F2> to enter the BIOS menu to check if the password is cleared.

6. Power down the server.


Jumper Blocks

7. Open the chassis and move the jumper back to its default position (covering pins 1 and 2).


9. Power up the server.

The password is now cleared and you can reset it by going into the BIOS setup.

7.2 Force BMC Update Procedure

When performing a standard BMC firmware update procedure, the update utility places the

BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event the BMC firmware update process fails due to the BMC not being in the proper update state, the server boards provide a Force BMC Update jumper that forces the BMC into the proper update state. In the event the standard BMC firmware update process fails, complete the following procedure:

1. Power down and remove the AC power cord.

2. Open the server chassis. See your server chassis documentation for instructions.

3. Move the jumper from the default operating position (covering pins 1 and 2) to the enabled position (covering pins 2 and 3).


5. Reconnect the AC power cord and power up the server.

6. Perform the BMC firmware update procedure as documented in the BMC firmware update package. After successful completion of the firmware update process, the firmware update utility may generate an error stating the BMC is still in update mode.


8. Open the server chassis.

9. Move the jumper from the enabled position (covering pins 2 and 3) to the disabled position

(covering pins 1 and 2).


11. Reconnect the AC power cord and power up the server.

Note: When the Force BMC Update jumper is set to the enabled position, normal BMC functionality is disabled. You should never run the server with the Force BMC Update jumper set in this position. You should only use this jumper setting when the standard firmware update process fails. When the server is running normally, this jumper must remain in the default/disabled position.

7.3 BIOS Recovery Jumper

The following procedure boots the recovery BIOS and flashes the normal BIOS:

1. Turn off the system power.

2. Move the BIOS recovery jumper to the recovery state.

3. Insert a bootable BIOS recovery media containing the new BIOS image files.

4. Turn on the system power.


Jumper Blocks

The BIOS POST screen will appear displaying the progress, and the system will boot to the EFI shell.

The EFI shell then executes the Startup.nsh batch file to start the flash update process. The user should then switch off the power and return the recovery jumper to its normal position. The user should not interrupt the BIOS POST on the first boot after recovery.

When the flash update completes:

1. Remove the recovery media.

2. Turn off the system power.

3. Restore the jumper to its original position.

4. Turn on the system power.

5. Re-flash any custom blocks, such as user binary or language blocks.

The system should now boot using the updated system BIOS.

7.4 ME Force Update Jumper

When performing the standard ME force update procedure, the update utility places the ME into an update mode, allowing the ME to load safely onto the flash device. In the unlikely event ME firmware update process fails due to ME not being in the proper update state, the server board provides an

Integrated BMC Force Update jumper, which forces the ME into the proper update state. The following procedure should be completed in the event the standard ME firmware update process fails.


2. Open the server chassis. For instructions, see your server chassis documentation.

3. Move jumper from the default operating position (covering pins 1 and 2) to the enabled position

(covering pins 2 and 3).


5. Reconnect the AC cord and power up the server.

6. Perform the ME firmware update procedure as documented in the README.TXT file that is included in the given ME firmware update package (same package as BIOS).


8. Open the server chassis.

9. Move jumper from the enabled position (covering pins 2 and 3) to the disabled position (covering pins 1 and 2).


11. Reconnect the AC cord and power up the server.


8. Intel

®

Light Guided Diagnostics

Both server boards have several onboard diagnostic LEDs to assist in troubleshooting board-level issues.

This section provides a description of the location and function of each LED on the server boards.

8.1 5-volt Stand-by LED

Several server management features of these server boards require a 5-V stand-by voltage supplied from the power supply. The features and components that require this voltage must be present when the system is “power-down”. The LED is illuminated when AC power is applied to the platform and 5-V standby voltage is supplied to the server board by the power supply.

8.2 Fan Fault LED

Fan fault LEDs are present for the two CPU fans and the one rear system fan. The fan fault LEDs illuminate when the corresponding fan has fault.

8.3 CPU Fault LED

CPU fault LED should correspond to the socket with the failed or disabled CPU. The CPU LEDs illuminate when CPU failure or Disable.


Figure 29. Stand by LED, Fan Fault LED and CPU Fault LED Location


8.4 DIMM Fault LEDs

The server board provide memory fault LED for each DIMM socket. These LEDs are located as shown in the following figure. The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs.

Figure 30

. DIMM Fault LED’s Location

8.5 System ID LED, System Status LED and POST Code Diagnostic LEDs

The server boards provide LEDs for system ID, system status and POST code. These LEDs are located in the rear I/O area of the server board as shown in the following figure.


Figure 31. Location of System Status, System ID and POST Code Diagnostic LEDs

LED Name

A

B

LSB 1 2 3 4 5 6 MSB

Description

System Status LED

System ID LED

Post Code Diagnostic LEDs

8.5.1 System ID LED

You can illuminate the blue System ID LED using either of the following two mechanisms:

 By pressing the System ID Button on the system front control panel, the ID LED displays a solid blue color until the button is pressed again.

 By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either blink blue for

15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off.


8.5.2 System Status LED

The bi-color (green/amber) System Status LED operates as follows:

Table 57. System Status LED

Color State

Green Solid on Ok

Criticality Description

Indicates that the System Status is ‘Healthy’. The system is not exhibiting any errors. AC power is present and BMC has booted and manageability functionality is up and running.

Green ~1 Hz blink Degraded

System degraded:

1. Redundancy loss such as power-supply or fan. Applies only if the associated platform sub-system has redundancy capabilities.

2. Fan warning or failure when the number of fully operational fans is more than minimum number needed to cool the system.

3. Non-critical threshold crossed

– Temperature (including HSBP temp), voltage, input power to power supply, output current for main power rail from power supply and Processor Thermal Control (Therm Ctrl) sensors.

4. Power supply predictive failure occurred while redundant power supply configuration was present.

5. Unable to use all of the installed memory (more than 1 DIMM installed).

6. Correctable Errors over a threshold and migrating to a spare DIMM

(memory sparing). This indicates that the user no longer has spared

DIMMs indicating a redundancy lost condition. Corresponding DIMM LED lit.

7. In mirrored configuration, when memory mirroring takes place and system loses memory redundancy.

8. Battery failure.

9. BMC executing in uBoot. (Indicated by Chassis ID blinking at Blinking at

3Hz). System in degraded state (no manageability). BMC uBoot is running but has not transferred control to BMC Linux. Server will be in this state 6-

8 seconds after BMC reset while it pulls the Linux image into flash

10. BMC booting Linux. (Indicated by Chassis ID solid ON). System in degraded state (no manageability). Control has been passed from BMC uBoot to BMC Linux itself. It will be in this state for ~10-~20 seconds.

11. BMC Watchdog has reset the BMC.

12. Power Unit sensor offset for configuration error is asserted.

13. HDD HSC is off-line or degraded.

Amber ~1 Hz blink Non-critical

Non-fatal alarm

– system is likely to fail:

1. Critical threshold crossed

– Voltage, temperature (including HSBP temp), input power to power supply, output current for main power rail from power supply and PROCHOT (Therm Ctrl) sensors.

2. VRD Hot asserted.

3. Minimum number of fans to cool the system not present or failed

4. Hard drive fault

5. Power Unit Redundancy sensor

– Insufficient resources offset (indicates not enough power supplies present).

6. In non-sparing and non-mirroring mode if the threshold of correctable errors is crossed within the window


Color State

Amber Solid on

Criticality

Critical, nonrecoverable

Description

Fatal alarm

– system has failed or shutdown:

1. CPU CATERR signal asserted.

2. MSID mismatch detected (CATERR also asserts for this case).

3. CPU 1 is missing.

4. CPU ThermalTrip.

5. No power good

– power fault.

6. DIMM failure when there is only 1 DIMM present and hence no good memory present.

7. Runtime memory uncorrectable error in non-redundant mode 1.

8. DIMM Thermal Trip or equivalent.

9. SSB Thermal Trip or equivalent.

10. CPU ERR2 signal asserted.

11. BMC/Video memory test failed. (Chassis ID shows blue/solid-on for this condition).

12. Both uBoot BMC FW images are bad. (Chassis ID shows blue/solid on for this condition).

13. 13. 240VA fault

Not ready AC power off Off N/A

8.5.3 POST Code Diagnostic LEDs

During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the

BIOS displays the given POST code to the POST code diagnostic

LED’s on the back edge of the server boards. To assist in troubleshooting a system hang during the POST process, you can use the diagnostic

LEDs to identify the last POST process executed.

Table 58. POST Code Diagnostic LEDs

A. Diagnostic LED #7 (MSB LED)

B. Diagnostic LED #6

C. Diagnostic LED #5

D. Diagnostic LED #4

E. Diagnostic LED #3

F. Diagnostic LED #2

G. Diagnostic LED #1

H. Diagnostic LED #0 (LSB LED)


Design and Environmental Specifications Intel® Workstation Board W2600CR TPS

9. Design and Environmental Specifications

9.1 Products Design Specifications

The following table defines the Intel operating and non-operating environmental limits. Operation of the Intel

Intel

®

®


®


®

Server Board S2600IP and

Workstation Board W2600CR at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.

Table 59. Server Board Design Specifications

Operating Temperature

Non-Operating Temperature

DC Voltage

Shock (Unpackaged)

0º C to 55º C

1

(32º F to 131º F)

-40º C to 70º C (-40º F to 158º F)

± 5% of all nominal voltages

Trapezoidal, 35g , 170 inches/sec

Shock (Packaged)

< 20 pounds

20 to < 40 pounds

40 to < 80 pounds

36 inches

30 inches

24 inches

80 to < 100 pounds

100 to < 120 pounds

120 pounds

18 inches

12 inches

9 inches

5 Hz to 500 Hz 3.13 g RMS random

Vibration (Unpackaged)

Note:

1.

Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel

®

server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel

®

developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits.

Disclaimer Note: Intel

®

ensures the unpackaged server board and system meet the shock requirement mentioned above through its own chassis development and system configuration. It is the responsibility of the system integrator to determine the proper shock level of the board and system if the system integrator chooses different system configuration or different chassis. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits.

9.2 MTBF

The following is the calculated Mean Time Between Failures (MTBF) 30



C (ambient air). These values are derived using a historical failure rate and multiplied by factors for application, electrical and/or thermal stress and for device maturity. You should view

MTBF estimates as “reference numbers” only.

 Calculation Model: Telcordia* Issue 2, method I case 3

 Operating Temperature: Server in 30°C ambient air

 Operating Environment: Ground Benign, Controlled


Server Board S2600IP and Intel® Design and Environmental Specifications

 Duty Cycle: 100%

 Quality Level: II

Table 60. Intel

®

Server Board S2600IP MTBF Estimate

Assembly Name

Mother Board

Integrated Circuits

Transistor_Bipolar

Transistor_MOSFET

Diodes

Diodes_LED

Resistors

Capacitors

Cap, Al Elect

Inductors

Connections

Misc

Failure Rate

4,981.828605

888.017556

142.288706

394.540757

24.364143

30.002406

1,134.467959

379.972284

741.486991

148.990773

1,213.354514

94.901757

MTBF

200,730

1,126,104

7,027,965

2,534,592

41,043,923

33,330,661

881,470

2,631,771

1,348,641

6,711,825

824,161

10,537,213

Table 61. Intel

®

Workstation Board W2600CR MTBF Estimate

Assembly Name

Mother Board

Integrated Circuits

Transistor_Bipolar

Transistor_MOSFET

Diodes

Diodes_LED

Resistors

Capacitors

Cap, Al Elect

Inductors

Connections

Failure Rate

5,247.668190

951.031471

147.372000

404.110588

36.808324

30.002406

1,204.023273

413.065171

770.924084

175.282101

1,216.849949

MTBF

190,561

1,051,490

6,785,549

2,474,570

27,167,768

33,330,661

830,549

2,420,925

1,297,145

5,705,089

821,794


Design and Environmental Specifications Intel® Workstation Board W2600CR TPS

Misc

Assembly Name Failure Rate

127.585507 7,837,881

MTBF


Design and Environmental Specifications

9.3 Server Board Power Requirements

This section provides power supply design guidelines for a system using the Intel

®

Server Board S2600IP and Workstation Board W2600CR including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on these server boards.

Revision 1.2

Figure 32. Power Distribution Block Diagram



9.3.1 Processor Power Support

The server boards support the Thermal Design Power (TDP) guideline for Intel

®

Xeon

® processors. The Flexible Motherboard Guidelines (FMB) is followed to determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for DTS, TDP power and T

CASE

for the compatible Intel

®

E5-2600 processor family series.

Table 62. Intel

®

Xeon

®

Processor Dual Processor TDP profile

Max TDP Power

130W

150W

85°C

67°C

104.4 for 6 core

100 for 8 core

84.8

9.4

Power Supply Output Requirements

This section is for reference purposes only. The intent is to provide guidance to system designers to determine a power supply to use with these server boards. This section specifies the power supply requirements Intel used to develop a power supply for its server system.

9.4.1 Output Power/Currents

The following tables define the minimum power and current ratings. The power supply must meet both static and dynamic voltage regulation requirements for all conditions.

Table 63. Minimum Load Ratings

Parameter

3.3V

5V

12V1

12V2

12V3



12V

5Vstby

Min

0.5

0.3

0.7

0.7

1.5

0.0

0.0

Max.

18.0

15.0

24.0

24.0

18.0

0.5

3.0

Peak

28.0

28.0

3.5

Unit

A

A

A

A

A

A

A

Notes:

1. Combined continuous power for all output shall not exceed 550W.

2. Peak combined power for all outputs shall not exceed 630W for 20 seconds.

3. Max combined power of 12V1, 12V2, and 12V3 shall not exceed 530W.

4. Max combined power on 3.3V and 5V shall not exceed 120W.

9.4.2 Cross Loading

The power supply shall maintain voltage regulation limit when operated over the following cross loading conditions.



Table 64. Loading Conditions

Load1

Load2

Load3

Load4

Load5

Load6

Load7

3.3V

18

13.5

2.5

2.5

0.5

16

16

5V

12.1

15

2

2

0.3

4

13

12V1

12

12

20

13.1

15

1

1

12V2

12

12

20

13.1

15

1

1

12V3

11.7

11.2

4.2

18

6.5

3.5

9

-12V

0

0.5

0

0

0.5

0

0.5

5Vstby

0.3

0.3

0.3

0.3

3

0.3

3

Total

Power

550

549

550

550

462

140

271

12V

Power

428

422

530

530

438

66

132

9.4.3 Standby Output

The 5VSB output shall be present when an AC input greater than the power supply turn on voltage is applied.

9.4.4 Voltage Regulation

3.3V/5V

Power

120

120

18

18

3

73

118

The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.

These shall be measured at the output connectors.

Table 65.Voltage Regulation Limits

Parameter

+3.3V

+5V

+12V1

+12V2

+12V3

- 12V

+5VSB

Tolerance

- 3%/+5%

- 4%/+5%

- 4%/+5%

- 4%/+5%

- 4%/+5%

- 10%/+10%

- 4%/+5%

Min

+3.20

+4.80

+11.52

+11.52

+11.52

- 13.20

+4.80

Nom

+3.30

+5.00

+12.00

+12.00

+12.00

-12.00

+5.00

Max

+3.46

+5.25

+12.60

+12.60

+12.60

-10.80

+5.25

Units

V rms

V rms

V rms

V rms

V rms

V rms

V rms

9.4.5 Dynamic Loading

The output voltages shall remain within limits specified for the step loading and capacitive loading specified in the table below. The load transient repetition rate shall be tested between

50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The



step load may occur anywhere within the MIN load to the MAX load conditions.

Output

+3.3V

+5V

12V1+12V2+12V3

+5VSB

Table 66. Transient Load Requirements



Step Load Size

(See note 2)

6.0A

4.0A

23A

0.5A

Load Slew Rate

0.5 A/

 sec

0.5 A/

 sec

0.5 A/

 sec

0.5 A/

 sec

Test capacitive Load

970



F

400



F

2200



F

1,2

20



F



Notes:

1. Step loads on each 12V output may happen simultaneously.

2. The +12V should be tested with 2200



F evenly split between the four +12V rails

3. This will be tested over the range of load conditions in section 9.4.2

9.4.6 Capacitive Loading

The power supply shall be stable and meet all requirements with the following capacitive loading ranges.

Table 67. Capacitive Loading Conditions

Output

+3.3V

+5V

+12V

-12V

+5VSB

Min

250

400

500

1

20

Max

5000

5000

8000

350

350

Units



F



F



F



F



F

9.4.7 Grounding

The output ground of the pins of the power supply provides the output power return path. The output connector ground pins shall be connected to the safety ground (power supply enclosure).

This grounding should be well designed to ensure passing the max allowed Common Mode

Noise levels.

The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth ground. Resistance of the ground returns to chassis shall not exceed 1.0 m



. This path may be used to carry DC current.

9.4.8 Closed loop stability

The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive load ranges specified in Section 4.6. A minimum of 45 degrees phase

margin and -10dB-gain margin is required. The power supply manufacturer shall provide proof of the unit’s closed-loop stability with local sensing through the submission of Bode plots.

Closed-loop stability must be ensured at the maximum and minimum loads as applicable.

9.4.9 Residual Voltage Immunity in Standby mode

The power supply should be immune to any residual voltage placed on its outputs (Typically a leakage voltage through the system from standby output) up to 500mV. There shall be no additional heat generated, nor stressing of any internal components with this voltage applied to any individual or all outputs simultaneously. It also should not trip the protection circuits during turn on.

The residual voltage at the power supply outputs for no load condition shall not exceed 100mV when AC voltage is applied and the PSON# signal is de-asserted.

9.4.10 Common Mode Noise

The Common Mode noise on any output shall not exceed 350mV pk-pk over the frequency band of 10

Hz to 20MHz. The measurement shall be made across a 100Ω resistor between each of DC outputs, including ground at the DC power connector and chassis ground (power subsystem enclosure). The test set-up shall use a FET probe such as Tektronix model P6046 or equivalent.



9.4.11 Soft Starting

The Power Supply shall contain control circuit which provides monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions.

9.4.12 Zero Load Stability Requirements

When the power subsystem operates in a no load condition, it does not need to meet the output regulation specification, but it must operate without any tripping of over-voltage or other fault circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and source current without fault.

9.4.13 Ripple/Noise

The maximum allowed ripple/noise output of the power supply is defined in the table below. This is measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors. A

10



F tantalum capacitor in parallel with a 0.1



F ceramic capacitor is placed at the point of measurement.

+3.3V

50mVp-p

Table 68. Ripples and Noise

+5V

50mVp-p

+12V1,2,3

120mVp-p

-12V

200mVp-p

+5VSB

50mVp-p

The test set-up is shown below.

AC HOT

POWER SUPPLY

AC NEUTRAL

V

OUT

V

RETURN

10uF

.1uF

LOAD

LOAD MUST BE

ISOLATED FROM

THE GROUND OF

THE POWER

SUPPLY

AC GROUND

GENERAL NOTES:

1. LOAD THE OUTPUT WITH ITS MINIMUM

LOAD CURRENT.

2. CONNECT THE PROBES AS SHOWN.

3. REPEAT THE MEASUREMENTS WITH THE

MAXIMUM LOAD ON THE OUTPUT.

SCOPE

SCOPE NOTE:

USE A TEKTRONIX 7834 OSCILLOSCOPE WITH 7A13 AND

DIFFERENTIAL PROBE P6055 OR EQUIVALENT.

Figure 33. Differential Noise test setup

Note:

When performing this test, the probe clips and capacitors should be located close to the load.

9.4.14 Timing Requirements

These are the timing requirements for the power supply operation. The output voltages must rise from 10% to within regulation limits (T vout_rise

) within 2 to 50ms, except for 5VSB - it is allowed to rise from 1 to 25ms. The +3.3V, +5V and +12V1,+12V2 ,+12V3 output voltages should start to rise approximately at the same time. All outputs must rise monotonically.

Each output voltage shall reach regulation within 50ms (T vout_on

) of each other during turn on of


Appendix A: Integration and Usage Tips the power supply. Each output voltage shall fall out of regulation within 400ms (T vout_off

) of each

other during turn off. Table 69 shows the timing requirements for the power supply being turned

on and off by the AC input, with PSON held low and the PSON signal, with the AC input applied.

All timing requirements must be met for the cross loading condition in section TBD.

Item

T vout_rise

T vout_on

T vout_off

Table 69. Output Voltage Timing

Description

Output voltage rise time from each main output.

Output rise time for the 5Vstby output.

All main outputs must be within regulation of each other within this time.

All main outputs must leave regulation within this time.

Min

2

1

Max

50

25

50

400

Units ms ms ms ms

Vout

V1

V2

V3

V4

10%

Vout

Item

T sb_on_delay

T ac_on_delay

T vout_holdup

T pwok_holdup

T vout_rise

T vout_on

Figure 34. Output Voltage Timing

T vout_off

Table 70. Turn On/Off Timing

Description

Delay from AC being applied to 5VSB being within regulation.

Delay from AC being applied to all output voltages being within regulation.

Time all output voltages stay within regulation after loss of AC. Tested at 75% of maximum load.

Delay from loss of AC to de-assertion of PWOK.

Tested at 75% of maximum load.

MIN

13

12

MAX

1500

2500

UNITS ms ms ms ms



Item

T pson_on_delay

T pson_pwok

T pwok_on

T pwok_off

T pwok_low

T sb_vout

T

5VSB_holdup

AC Input

Description

Delay from PSON

#

active to output voltages within regulation limits.

Delay from PSON

#

deactivate to PWOK being deasserted.

Delay from output voltages within regulation limits to PWOK asserted at turn on.

Delay from PWOK de-asserted to output voltages

(3.3V, 5V, 12V, -12V) dropping out of regulation limits.

Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal.

Delay from 5VSB being in regulation to O/Ps being in regulation at AC turn on.

Time the 5VSB output voltage stays within regulation after loss of AC.

T vout_holdup

Vout

T sb_on_delay

PWOK

T

AC_on_delay

T pwok_on

T pwok_holdup

T pwok_off

T pwok_low

T sb_on_delay

5VSB

T sb_vout

T

5VSB

_holdup

PSON

100

10

70

T pwok_on

T pson_on_delay

MIN

5

100

1

MAX

400

50

500

1000

T

T pwok_off pson_pwok

UNITS ms ms ms ms ms ms ms

AC turn on/off cycle

PSON turn on/off cycle

Figure 35. Turn On/Off Timing (Power Supply Signals)



Appendix A: Integration and Usage Tips

 When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.

 This server board supports The Intel

®

Xeon

®

Processor E5-2600 product family and E5-2600 v2 product family with a Thermal Design Power (TDP) of up to and including 135 Watts (TDP of up to 150W only for Workstation board). Previous generations of Intel

®

Xeon

®

processors are not supported.

 Processors must be installed in order. CPU 1 must be populated for operating the server board.

 On the back edge of the server board are eight diagnostic LEDs that display a sequence of amber POST codes during the boot process. If the server board hangs during POST, LEDs display the last POST event run before the hang.

 This server board only supports registered DDR3 DIMMs (RDIMMs) and unbuffered DDR3

DIMMs (UDIMMs). Mixing of RDIMMs and UDIMMs is not supported.

 For the best performance, the number of DDR3 DIMMs installed should be balanced across both processor sockets and memory channels. For example, a two-DIMM configuration performs better than a one-DIMM configuration. In a two-DIMM configuration, DIMMs should be installed in

DIMM sockets A1 and D1.

 The Intel

®

Remote Management Module 4 (Intel

® previous versions of the Intel

®

RMM4) connector is not compatible with any

Remote Management Module (Product Order Code

– AXXRMM,

AXXRMM2, and AXXRMM3).

 Clear the CMOS with AC power cord plugged. Removing the AC power before performing the

CMOS clear operation causes the system to automatically power up and immediately power down after the CMOS clear procedure is followed and AC power is re-applied. If this happens, remove the AC power cord, wait 30 seconds, and then reconnect the AC power cord. Power up the system and proceed to the <F2> BIOS Setup utility to reset the desired settings.

 Normal Integrated BMC functionality is disabled with the BMC Force Update jumper set to the

“enabled” position (pins 2-3). The server should never be run with the BMC Force Update jumper set in this position and should only be used when the standard firmware update process fails.

This jumper should remain in the default (disabled) position (pins 1- 2) when the server is running normally.

 When performing a normal BIOS update procedure, the BIOS recovery jumper must be set to its default position (pins 1-2).



Appendix B: BMC Sensor Tables

This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.

Sensor Type Codes

Sensor table given below lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. Refer to the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.

 Sensor Type

The sensor type references the values in the Sensor Type Codes table in the Intelligent Platform

Management Interface Specification Second Generation v2.0. It provides a context to interpret the sensor.

 Event/Reading Type

The event/reading type references values from the Event/Reading Type Code Ranges and the

Generic Event/Reading Type Code tables in the Intelligent Platform Management Interface

Specification Second Generation v2.0. Digital sensors are specific type of discrete sensors that only have two states.

 Event Thresholds/Triggers

The following event thresholds are supported for threshold type sensors:

-

[u,l][nr,c,nc] upper non-recoverable, upper critical, upper non-critical, lower non-recoverable, lower critical, lower non-critical uc, lc upper critical, lower critical

Event triggers are supported event-generating offsets for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Code or Sensor Type Code tables in the Intelligent

Platform Management Interface Specification Second Generation v2.0, depending on whether the sensor event/reading type is generic or a sensor-specific response.

 Assertion/Deassertion

Assertion and de-assertion indicators reveal the type of events this sensor generates:

- As: Assertion

-

De: De-assertion

 Readable Value/Offsets

- Readable value indicates the type of value returned for threshold and other nondiscrete type sensors.

-

Readable offsets indicate the offsets for discrete sensors that are readable by means of the Get Sensor Reading command. Unless otherwise indicated, event triggers are readable. Readable offsets consist of the reading type offsets that do not generate events.

 Event Data

Event data is the data that is included in an event message generated by the associated sensor.

For threshold-based sensors, these abbreviations are used:

- R: Reading value

-

T: Threshold value

 Rearm Sensors



The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used in the comment column to describe a sensor:

-

A: Auto-rearm

-

M: Manual rearm

-

I: Rearm by init agent

 Default Hysteresis

The hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which can be 1 or 2 (positive or negative hysteresis).

 Criticality

Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the front panel status LED.

 Standby

Some sensors operate on standby power. These sensors may be accessed and/or generate events when the main (system) power is off, but AC power is present.



Note: All sensors listed below may not be present on all platforms. Please check platform EPS section for platform applicability and platform chassis section for chassis specific sensors. Redundancy sensors will be only present on systems with appropriate hardware to support redundancy (for instance, fan or power supply).

Full Sensor Name

(Sensor name in SDR)

Sensor

#

Platform

Applicability

Power Unit Status

(Pwr Unit Status)

01h All

Table 71. Integrated BMC Core Sensors

Sensor Type Event/Reading

Type

Power Unit

09h

Sensor

Specific

6Fh

Event Offset Triggers

00 - Power down

02 - 240 VA power down

04 - A/C lost

05 - Soft power control failure

06 - Power unit failure

00 - Fully Redundant

Contrib. To

System

Status

OK

Assert/Deassert

Readable

Value/

Offsets

Fatal

OK

Fatal

OK

As and

De

–

Event

Data

Trig

Offset

Rearm Standby

A X

01 - Redundancy lost Degraded

Power Unit

Redundancy

1

(Pwr

Unit Redund)

02h

Chassisspecific

Power Unit

09h

Generic

0Bh

02 - Redundancy degraded

03 - Non-redundant: sufficient resources.

Transition from full redundant state.

04

– Non-redundant: sufficient resources.

Transition from insufficient state.

05 - Non-redundant: insufficient resources

06

– Redundant: degraded from fully redundant state.

Degraded

Degraded

Degraded

Fatal

Degraded

As and

De

–

Trig

Offset

M X



Full Sensor Name


IPMI Watchdog

(IPMI Watchdog)

Physical Security

(Physical Scrty)

FP Interrupt

(FP NMI Diag Int)

SMI Timeout

(SMI Timeout)

System Event Log

(System Event

Log)

System Event

(System Event)

Button Sensor

(Button)

BMC Watchdog

Sensor

#

03h

08h

09h

0Ah

Platform

Applicability

All

All

All

All


Type

Watchdog 2

23h

Sensor

Specific

6Fh


07

– Redundant:

Transition from nonredundant state.

00 - Timer expired, status only

01 - Hard reset

02 - Power down

03 - Power cycle

08 - Timer interrupt

00 - Chassis intrusion

04 - LAN leash lost

Contrib. To

System

Status

Degraded

Assert/Deassert

Readable

Value/

Offsets

OK

Degraded

OK

As

As and

De

–

–

04h

Chassis

Intrusion is chassisspecific

05h

06h

07h

Chassis specific

All

All

Physical

Security

05h

Critical

Interrupt

13h

SMI Timeout

F3h

Event Logging

Disabled

10h

System Event

12h

Button/Switch

14h

Mgmt System

Health

28h

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Digital

Discrete

03h

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Digital

Discrete

03h

00 - Front panel

NMI/diagnostic interrupt

01

– State asserted

02 - Undetermined system H/W failure

04

00

02

– PEF action

– Power Button

– Reset Button

01

02 - Log area reset/cleared

– State Asserted

OK

Fatal

OK

Fatal

OK

OK

Degraded

As

As and

De

As

As and

De

As

AS

As

–

–

–

-

_

–

Event

Data

Rearm Standby

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

A

A

A

A

A

A

A

A

X

X

–

–

X

X

X

-



Full Sensor Name


Voltage Regulator

Watchdog

(VR Watchdog)

Sensor

#

Platform

Applicability

0Bh All

Fan Redundancy

1

(Fan Redundancy)

0Ch

SSB Thermal Trip

(SSB Therm Trip)

0Dh

IO Module

Presence

(IO Mod Presence)

SAS Module

Presence

(SAS Mod

Presence)

0Eh

0Fh

Chassisspecific

All


Type

Voltage

02h

Fan

04h

Digital

Discrete

03h

Generic

0Bh


01

– State Asserted

Contrib. To

System

Status

Assert/Deassert

Fatal

As and

De

Readable

Value/

Offsets

–

00 - Fully redundant

OK

01 - Redundancy lost

Degraded

02 - Redundancy degraded

Degraded

03 - Non-redundant:

Sufficient resources.

Transition from redundant

04 - Non-redundant:

Sufficient resources.

Transition from insufficient.

Degraded

Degraded

05 - Non-redundant: insufficient resources.

06

– Non-Redundant: degraded from fully redundant.

07 - Redundant degraded from nonredundant

Non-Fatal

Degraded

Degraded

As and

De

–

Temperature

01h

Platformspecific

Module/Board

15h

Platformspecific

Module/Board

15h

Digital

Discrete

03h

Digital

Discrete

08h

Digital

Discrete

08h

01

01

01

– State Asserted

– Inserted/Present


Fatal

OK

OK

As and

De

As and

De

As and

De

–

–

–

Event

Data

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Rearm Standby

M

A

M

M

M

X

–

X

-

X



Full Sensor Name


BMC Firmware

Health

(BMC FW Health)

Sensor

#

10h

System Airflow

(System Airflow)

11h

FW Update Status 12h

Platform

Applicability

All

All

All


Type


Mgmt Health

28h

Other Units

0Bh

Version

Change 2Bh

Sensor

Specific

6Fh

Threshold

01h

OEM defined x70h

04

– Sensor Failure

–

00hUpdate started

01hUpdate completed successfully.

Contrib. To

System

Status

Degraded

Assert/Deassert

As

Readable

Value/

Offsets

-

–

OK

–

As

Analog

_

02hUpdate failure

IO Module2

Presence

(IO Mod2

Presence)

Baseboard

Temperature 5

(Platform Specific)

13h

14h

Platformspecific

Module/Board

15h

Platformspecific

Temperature

01h

Digital

Discrete

08h

Threshold

01h

01


[u,l] [c,nc]

Baseboard

Temperature 6

(Platform Specific)

IO Module2

Temperature

(I/O Mod2 Temp)

PCI Riser 3

Temperature

(PCI Riser 5 Temp)

15h

16h

17h

Platformspecific

Platformspecific

Platformspecific

Temperature

01h

Temperature

01h

Temperature

01h

Threshold

01h

Threshold

01h

Threshold

01h

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

OK nc =

Degraded c = Nonfatal nc =



Degraded c = Nonfatal

As and

De

As and

De

As and

De

As and

De

As and

De

–

Analog

Analog

Analog

Analog

Event

Data

Rearm Standby

Trig

Offset

–

Trig

Offset

Trig

Offset

R, T

R, T

R, T

R, T

A

–

A

M

A

A

A

A

X

–

_

-

X

X

X

X



Full Sensor Name


PCI Riser 4

Temperature

(PCI Riser 4 Temp)

Sensor

#

Platform

Applicability

18h

Platformspecific

Sensor Type

Temperature

01h

Event/Reading

Type

Threshold

01h


[u,l] [c,nc]

Baseboard +1.05V

Processor3 Vccp

(BB +1.05Vccp P3)

19h

Baseboard +1.05V

Processor4 Vccp

(BB +1.05Vccp P4)

1Ah

Platformspecific

Baseboard

Temperature 1

(Platform Specific)

20h

Front Panel

Temperature

(Front Panel Temp)

21h

SSB Temperature

(SSB Temp)

22h

Baseboard

Temperature 2

(Platform Specific)

23h

Baseboard

Temperature 3

(Platform Specific)

24h

Platformspecific

Platformspecific

All

All

Platformspecific

Platformspecific

Voltage

02h

Voltage

02h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc] nc =





Contrib. To

System

Status nc =





Assert/Deassert

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

Readable

Value/

Offsets

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Event

Data

R, T

R, T

R, T

R, T

R, T

R, T

R, T

R, T

Rearm Standby

A

A

A

A

A

A

A

A

X

–

–

X

X

X

X

X



Full Sensor Name


Baseboard

Temperature 4

(Platform Specific)

Sensor

#

Platform

Applicability

25h

Platformspecific

Sensor Type

Temperature

01h

Event/Reading

Type

Threshold

01h


[u,l] [c,nc]

IO Module

Temperature

(I/O Mod Temp)

26h

Platformspecific

Temperature

01h

PCI Riser 1

Temperature

(PCI Riser 1 Temp)

27h

Platformspecific

Temperature

01h

IO Riser

Temperature

(IO Riser Temp)

Hot-swap

Backplane 1

Temperature

(HSBP 1 Temp)

Hot-swap

Backplane 2

Temperature

(HSBP 2 Temp)

Hot-swap

Backplane 3

Temperature

(HSBP 3 Temp)

28h

29h

2Ah

2Bh

PCI Riser 2

Temperature

(PCI Riser 2 Temp)

2Ch

Platformspecific

Chassisspecific

Chassisspecific

Chassisspecific

Platformspecific

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc] nc =




Contrib. To

System

Status nc =






Assert/Deassert

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

Readable

Value/

Offsets

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Event

Data

Rearm Standby

R, T

R, T

R, T

R, T

R, T

R, T

R, T

R, T

A

A

A

A

A

A

A

A

X

X

X

X

X

X

X

X



Full Sensor Name


SAS Module

Temperature

(SAS Mod Temp)

Sensor

#

Platform

Applicability

2Dh

Platformspecific

Sensor Type

Temperature

01h

Event/Reading

Type

Threshold

01h


[u,l] [c,nc]

Chassis and

Platform

Specific

Temperature

01h

Threshold

01h

[u,l] [c,nc]

Exit Air

Temperature

(Exit Air Temp)

2Eh

Network Interface

Controller

Temperature

(LAN NIC Temp)

Fan Tachometer

Sensors

(Chassis specific sensor names)

Fan Present

Sensors

(Fan x Present)

2Fh

30h

–

3Fh

40h

–

4Fh

All

Chassis and

Platform

Specific

Chassis and

Platform

Specific

Temperature

01h

Fan

04h

Fan

04h

Threshold

01h

Threshold

01h

Generic

08h

[u,l] [c,nc]

[l] [c,nc]

01 - Device inserted

Power Supply 1

Status

(PS1 Status)

Power Supply 2

Status

(PS2 Status)

50h

51h

Chassisspecific

Power Supply

08h

Chassisspecific

Power Supply

08h

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Contrib. To

System

Status nc =





2

Assert/Deassert

As and

De

As and

De

As and

De

As and

De

Readable

Value/

Offsets

Analog

Analog

Analog

Analog

OK

00 - Presence

01 - Failure Degraded

02

– Predictive Failure Degraded

03 - A/C lost

06

– Configuration error

OK

Degraded

OK

00 - Presence OK

01 - Failure Degraded

02

– Predictive Failure Degraded

Degraded 03 - A/C lost

06

– Configuration error

OK

As and

De

As and

De

As and

De

-

–

–

Event

Data

R, T

R, T

R, T

R, T

Triggered

Offset

Auto

Trig

Offset

Trig

Offset

Rearm Standby

A

A

A

M

A

A

X

X

X

-

-

X

X



Full Sensor Name


Power Supply 1

AC Power Input

(PS1 Power In)

Sensor

#

Platform

Applicability

54h

Chassisspecific

Power Supply 2

AC Power Input

(PS2 Power In)

55h

Power Supply 1

+12V % of

Maximum Current

Output

(PS1 Curr Out %)

Power Supply 2

+12V % of

Maximum Current

Output

(PS2 Curr Out %)

58h

59h

Power Supply 1

Temperature

(PS1 Temperature)

5Ch

Chassisspecific

Chassisspecific

Chassisspecific

Chassisspecific

Power Supply 2

Temperature

(PS2 Temperature)

5Dh

Chassisspecific

Hard Disk Drive 16

- 24 Status

(HDD 16 - 24

Status)

60h

–

68h

Chassisspecific


Type


Other Units

0Bh

Other Units

0Bh

Current

03h

Threshold

01h

Threshold

01h

Threshold

01h

[u] [c,nc]

[u] [c,nc]

[u] [c,nc]

Contrib. To

System

Status nc =



Assert/Deassert

Readable

Value/

Offsets

As and

De

As and

De

Analog

Analog nc =


As and

De

Analog

Current

03h

Temperature

01h

Temperature

Drive Slot

0Dh

Threshold

01h

Threshold

01h

Threshold

01h

Sensor

Specific

6Fh

[u] [c,nc] nc =


[u] [c,nc]

[u] [c,nc]

00 - Drive Presence nc =



OK

01- Drive Fault Degraded

07 - Rebuild/Remap in progress

Degraded

As and

De

As and

De

As and

De

As and

De

Analog

Analog

Analog

–

Event

Data

Rearm Standby

R, T

R, T

R, T

R, T

R, T

R, T

Trig

Offset

A

A

A

A

A

A

A

X

X

X

X

X

X

X



Full Sensor Name


Sensor

#

Platform

Applicability

69h

-

6Bh

Chassisspecific


Type


Microcontroller

16h

Discrete 0Ah

04- transition to Off

Line

Processor 1 Status

(P1 Status)

Processor 2 Status

(P2 Status)

Processor 3 Status

(P3 Status)

Processor 4 Status

(P4 Status)

70h

71h

72h

73h

All

All

Platformspecific

Platformspecific

Processor

07h

Processor

07h

Processor

07h

Processor

07h

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Sensor

Specific

6Fh

01 - Thermal trip

07 - Presence

01 - Thermal trip

07 - Presence

01 - Thermal trip

07 - Presence

01 - Thermal trip

07 - Presence

Processor 1

Thermal Margin

(P1 Therm Margin)

Processor 2

Thermal Margin

(P2 Therm Margin)

Processor 3

Thermal Margin

(P3 Therm Margin)

Processor 4

Thermal Margin

(P4 Therm Margin)

Processor 1

Thermal

Control %

(P1 Therm Ctrl %)

74h

75h

76h

77h

78h

All

All

Platformspecific

Platformspecific

All

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

-

-

-

-

[u] [c,nc]

-

-

-

-

Contrib. To

System

Status

Assert/Deassert

Readable

Value/

Offsets

Degraded

Fatal

OK

Fatal

OK

Fatal

OK

Fatal

OK nc =


As and

De

As and

De

As and

De

As and

De

-

-

-

-

As and

De

–

–

–

–

–

Analog

Analog

Analog

Analog

Analog

Event

Data

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

R, T

R, T

R, T

R, T

Trig

Offset

Rearm Standby

M

M

M

M

A

A

A

A

A

X

X

X

X

X

–

–

–

–

–



Full Sensor Name


Processor 2

Thermal

Control %

(P2 Therm Ctrl %)

Processor 3

Thermal

Control %

(P3 Therm Ctrl %)

Processor 4

Thermal

Control %

(P4 Therm Ctrl %)

Processor 1 ERR2

Timeout

(P1 ERR2)

Processor 2 ERR2

Timeout

(P2 ERR2)

Processor 3 ERR2

Timeout

(P3 ERR2)

Processor 4 ERR2

Timeout

(P4 ERR2)

Sensor

#

Platform

Applicability

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

All

Platformspecific

Platformspecific

All

All

Platformspecific

Platformspecific

Sensor Type

Temperature

01h

Temperature

01h

Temperature

01h

Processor

07h

Processor

07h

Processor

07h

Processor

07h

Event/Reading

Type

Threshold

01h

Threshold

01h

Threshold

01h

Catastrophic Error

(CATERR)

80h All

Processor

07h

Digital

Discrete

03h

Digital

Discrete

03h

Digital

Discrete

03h

Digital

Discrete

03h

Digital

Discrete

03h

Processor1 MSID

Mismatch

(P1 MSID

Mismatch)

81h All

Processor

07h

Digital

Discrete

03h


[u] [c,nc]

[u] [c,nc]

[u] [c,nc]

01

– State Asserted

01

– State Asserted

01

– State Asserted

01

– State Asserted

01

– State Asserted

01

– State Asserted

Contrib. To

System

Status nc =




Assert/Deassert

Readable

Value/

Offsets

As and

De

As and

De

As and

De

Analog

Analog

Analog fatal fatal fatal fatal fatal fatal

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

–

–

–

–

–

–

Event

Data

Rearm Standby

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

A

A

A

A

A

A

A

M

M

–

–

–

–

–

–

–

–

–



Full Sensor Name


Processor

Population Fault

(CPU Missing)

Processor 1 DTS

Thermal Margin

(P1 DTS Therm

Mgn)

Processor 2 DTS

Thermal Margin

(P2 DTS Therm

Mgn)

Processor 3 DTS

Thermal Margin

(P3 DTS Therm

Mgn)

Processor 4 DTS

Thermal Margin

(P4 DTS Therm

Mgn)

Processor2 MSID

Mismatch

(P2 MSID

Mismatch)

Processor 1 VRD

Temperature

(P1 VRD Hot)

Processor 2 VRD

Temperature

(P2 VRD Hot)

Sensor

#

Platform

Applicability

82h

83h

84h

85h

86h

87h

90h

91h

All

All

All

All

All

All

All

All

Processor 3 VRD

Temperature

(P3 VRD Hot)

92h All


Type

Processor

07h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Processor

07h

Temperature

01h

Temperature

01h

Temperature

01h

Digital

Discrete

03h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Digital

Discrete

03h

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h


01

– State Asserted

-

-

-

-

01

– State Asserted

01 - Limit exceeded

Contrib. To

System

Status

Assert/Deassert

Fatal

As and

De

Readable

Value/

Offsets

–

-

-

-

- fatal

01 - Limit exceeded Non-fatal


Fatal

-

-

-

-

As and

De

As and

De

As and

De

As and

De

Analog

Analog

Analog

Analog

–

–

–

–

Event

Data

Trig

Offset

R, T

R, T

R, T

R, T

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Rearm Standby

M

A

A

A

A

M

M

M

M

–

–

–

–

–

–

–

–

–



Full Sensor Name


Processor 4 VRD

Temperature

(P4 VRD Hot)

Processor 1

Memory VRD Hot

0-1

(P1 Mem01 VRD

Hot)

Processor 1

Memory VRD Hot

2-3

(P1 Mem23 VRD

Hot)

Processor 2

Memory VRD Hot

0-1

(P2 Mem01 VRD

Hot)

Processor 2

Memory VRD Hot

2-3

(P2 Mem23 VRD

Hot)

Processor 3

Memory VRD Hot

0-1

(P3 Mem01 VRD

Hot)

Processor 3

Memory VRD Hot

2-3

(P4 Mem23 VRD

Hot)

Processor 4

Memory VRD Hot

0-1

(P4 Mem01 VRD

Hot)

Sensor

#

Platform

Applicability

93h

94h

95h

96h

97h

98h

99h

9Ah

All

All

All

All

All

All

All

All

Sensor Type

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Event/Reading

Type

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h

Digital

Discrete

05h


01 - Limit exceeded

Contrib. To

System

Status

Assert/Deassert

Readable

Value/

Offsets

Fatal

As and

De

–








As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

–

–

–

–

–

–

–

Event

Data

Rearm Standby

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

M

A

A

A

A

A

A

A

–

–

–

–

–

–

–

–



Full Sensor Name


Processor 4

Memory VRD Hot

2-3

(P4 Mem23 VRD

Hot)

Power Supply 1

Fan Tachometer 1

(PS1 Fan Tach 1)

Power Supply 1

Fan Tachometer 2

(PS1 Fan Tach 2)

Power Supply 2

Fan Tachometer 1

(PS2 Fan Tach 1)

Power Supply 2

Fan Tachometer 2

(PS2 Fan Tach 2)

Processor 1 DIMM

Aggregate Thermal

Margin 1

(P1 DIMM Thrm

Mrgn1)

Processor 1 DIMM

Aggregate Thermal

Margin 2

(P1 DIMM Thrm

Mrgn2)

Processor 2 DIMM

Aggregate Thermal

Margin 1

(P2 DIMM Thrm

Mrgn1)

Processor 2 DIMM

Aggregate Thermal

Margin 2

(P2 DIMM Thrm

Mrgn2)

Sensor

#

Platform

Applicability

9Bh

A0h

A1h

A4h

A5h

B0h

B1h

B2h

B3h

All

Chassisspecific

Chassisspecific

Chassisspecific

Chassisspecific

All

All

All

All

Sensor Type

Temperature

01h

Fan

04h

Fan

04h

Fan

04h

Fan

04h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Event/Reading

Type

Digital

Discrete

05h

Generic digital

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

– discrete

Generic

– digital discrete

Generic


Generic



01 - Limit exceeded

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

Contrib. To

System

Status

Non-fatal

01

– State Asserted

Non-fatal

01

– State Asserted

Non-fatal

01

– State Asserted

Non-fatal

01

– State Asserted

Non-fatal nc =





Assert/Deassert

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

Readable

Value/

Offsets

–

-

-

-

-

Analog

Analog

Analog

Analog

Event

Data

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

Trig

Offset

R, T

R, T

R, T

R, T

Rearm Standby

A

M

M

M

M

A

A

A

A

–

-

-

-

-

–

–

–

–



Full Sensor Name


Processor 3 DIMM

Aggregate Thermal

Margin 1

(P3 DIMM Thrm

Mrgn1)

Processor 3 DIMM

Aggregate Thermal

Margin 2

(P3 DIMM Thrm

Mrgn2)

Processor 4 DIMM

Aggregate Thermal

Margin 1

(P4 DIMM Thrm

Mrgn1)

Processor 4 DIMM

Aggregate Thermal

Margin 2

(P4 DIMM Thrm

Mrgn2)

Fan Tachometer

Sensors

(Chassis specific sensor names)

Processor 1 DIMM

Thermal Trip

(P1 Mem Thrm

Trip)

Processor 2 DIMM

Thermal Trip

(P2 Mem Thrm

Trip)

Processor 3 DIMM

Sensor

#

Platform

Applicability

B4h

B5h

B6h

B7h

BAh

–

BFh

C0h

C1h

Platform

Specific

Platform

Specific

Platform

Specific

Platform

Specific

Chassis and

Platform

Specific

All

All

Thermal Trip

(P3 Mem Thrm

Trip)

C2h All

Sensor Type

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Fan

04h

Memory

0Ch

Memory

0Ch

Memory

0Ch

Event/Reading

Type

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Digital

Discrete

03h

Digital

Discrete

03h

Digital

Discrete

03h


[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[l] [c,nc]

0A- Critical overtemperature



Contrib. To

System

Status nc =






2

Assert/Deassert

As and

De

As and

De

As and

De

As and

De

As and

De

Readable

Value/

Offsets

Analog

Analog

Analog

Analog

Analog

Fatal

Fatal

Fatal

As and

De

As and

De

As and

De

–

–

–

Event

Data

Rearm Standby

R, T

R, T

R, T

R, T

R, T

Trig

Offset

Trig

Offset

Trig

Offset

A

A

A

A

M

M

M

M

–

–

–

–

-

-

-

X



Full Sensor Name


Processor 4 DIMM

Sensor

#

Platform

Applicability


Type


Thermal Trip

(P4 Mem Thrm

Trip)

Global Aggregate

Temperature

Margin 1

(Agg Therm Mrgn

1)

Global Aggregate

Temperature

Margin 2

(Agg Therm Mrgn

2)

Global Aggregate

Temperature

Margin 3

(Agg Therm Mrgn

3)

Global Aggregate

Temperature

Margin 4

(Agg Therm Mrgn

4)

Global Aggregate

Temperature

Margin 5

(Agg Therm Mrgn

5)

Global Aggregate

Temperature

Margin 6

(Agg Therm Mrgn

6)

Global Aggregate

Temperature

Margin 7

(Agg Therm Mrgn

7)

C3h

C8h

C9h

CAh

CBh

CCh

CDh

CEh

All

Platform

Specific

Platform

Specific

Platform

Specific

Platform

Specific

Platform

Specific

Platform

Specific

Platform

Specific

Memory

0Ch

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Temperature

01h

Digital

Discrete

03h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h


-

-

-

-

-

-

-

Contrib. To

System

Status

Assert/Deassert

Readable

Value/

Offsets

Fatal

As and

De

–

Event

Data

Trig

Offset

Rearm Standby

M X

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Analog

Analog

Analog

Analog

Analog

Analog

Analog

R, T

R, T

R, T

R, T

R, T

R, T

R, T

A

A

A

A

A

A

A

–

–

–

–

–

–

–



Full Sensor Name


Global Aggregate

Temperature

Margin 8

(Agg Therm Mrgn

8)

Sensor

#

Platform

Applicability

CFh

Platform

Specific

Sensor Type

Temperature

01h

Event/Reading

Type

Threshold

01h


-

Contrib. To

System

Status

Assert/Deassert

Readable

Value/

Offsets

- - Analog

Baseboard +12V

(BB +12.0V)

D0h

Baseboard +5V

(BB +5.0V)

D1h

Baseboard +3.3V

(BB +3.3V)

D2h

Baseboard +5V

Stand-by

(BB +5.0V STBY)

D3h

Baseboard +3.3V

Auxiliary

(BB +3.3V AUX)

D4h

Baseboard +1.05V

Processor1 Vccp

(BB +1.05Vccp P1)

D6h

Baseboard +1.05V

Processor2 Vccp

(BB +1.05Vccp P2)

D7h

All

All

All

All

All

All

All

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc] nc =








As and

De

Analog

As and

De

Analog

As and

De

Analog

As and

De

Analog

As and

De

Analog

As and

De

Analog

As and

De

Analog

Event

Data

Rearm Standby

R, T

R, T

R, T

R, T

R, T

R, T

R, T

R, T

A

A

A

A

A

A

A

A

–

–

–

–

X

X

–

–



Full Sensor Name


Baseboard +1.5V

P1 Memory AB

VDDQ

(BB +1.5 P1MEM

AB)

Baseboard +1.5V

P1 Memory CD

VDDQ

(BB +1.5 P1MEM

CD)

Baseboard +1.5V

P2 Memory AB

VDDQ

(BB +1.5 P2MEM

AB)

Baseboard +1.5V

P2 Memory CD

VDDQ

(BB +1.5 P2MEM

CD)

Sensor

#

Platform

Applicability

D8h

D9h

DAh

DBh

All

All

All

All

Baseboard +1.8V

Aux

(BB +1.8V AUX)

DCh All

Baseboard +1.1V

Stand-by

(BB +1.1V STBY)

DDh

Baseboard CMOS

Battery

(BB +3.3V Vbat)

DEh

All

All


Type


Voltage

02h

Threshold

01h

[u,l] [c,nc]

Contrib. To

System

Status nc =


Assert/Deassert

Readable

Value/

Offsets

As and

De

Analog

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc] nc =







As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

Analog

Analog

Analog

Analog

Analog

Analog

Event

Data

R, T

R, T

R, T

R, T

R, T

R, T

R, T

Rearm Standby

A

A

A

A

A

A

A

–

–

–

–

–

–

–



Full Sensor Name


Baseboard +1.35V

P1 Low Voltage

Memory AB VDDQ

(BB +1.35 P1LV

AB)

Baseboard +1.35V

P1 Low Voltage

Memory CD VDDQ

Sensor

#

Platform

Applicability

E4h

E5h

All

All

(BB +1.35 P1LV

CD)

Baseboard +1.35V

P2 Low Voltage

Memory AB VDDQ

(BB +1.35 P2LV

AB)

E6h All

Baseboard +1.35V

P2 Low Voltage

Memory CD VDDQ

(BB +1.35 P2LV

CD)

Baseboard +3.3V

Riser 1 Power

Good

(BB +3.3 RSR1

PGD)

Baseboard +3.3V

Riser 2 Power

Good

(BB +3.3 RSR2

PGD)

E7h

EAh

EBh

All

Platform

Specific

Platform

Specific

Hard Disk Drive 1 -

15 Status

F0h

-

Chassisspecific


Type


Voltage

02h

Threshold

01h

[u,l] [c,nc]

Contrib. To

System

Status nc =


Assert/Deassert

Readable

Value/

Offsets

As and

De

Analog

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Drive Slot

0Dh

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Sensor

Specific

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc] nc =





[u,l] [c,nc]

00 - Drive Presence

01- Drive Fault nc =


OK

Degraded

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

Analog

Analog

Analog

Analog

Analog

–

Event

Data

Rearm Standby

R, T

R, T

R, T

R, T

R, T

R, T

Trig

Offset

A

A

A

A

A

A

A

–

–

–

–

–

–

X



Full Sensor Name


(HDD 1 - 15

Status)

Sensor

#

FEh

Platform

Applicability


Type

6Fh

Event Offset Triggers Contrib. To

System

Status

07 - Rebuild/Remap in progress

Degraded

Assert/Deassert

Readable

Value/

Offsets

Event

Data

Rearm Standby

Notes:

1. Redundancy sensors will be only present on systems with appropriate hardware to support redundancy (for instance, fan or power supply).

2. This is only applicable when the system doesn't support redundant fans. When fan redundancy is supported, then the contribution to system state is driven by the fan redundancy sensor.


Appendix C: Platform Specific BMC Appendix

Intel

®

Server Board S2600IP

Introduction

This is an addendum document to BMC core EPS. This document describes platform and chassis specific information.

Product ID

Bytes 11:12 (product ID) of Get Device ID command response: 55h 00h

IPMI Channel ID Assignments

The following table provides information on the BMC channel assignments:

Table 72. Intel

®

Server Board S2600IP - BMC Channel Assignments

Channel ID Interface Supports

Sessions

Yes

Yes

Yes

Yes

0

1

2

3

4

5

6

Primary IPMB

LAN 1

LAN 2

(platform specific)

LAN3

1


®


Reserved

USB

Secondary IPMB

7

8

– 0Dh

0Eh

0Fh

Notes:

SMM

Reserved

Self

2

SMS/Receive Message Queue

1. Optional HW supported by the server system.

Yes

No

No

No

–

–

No


ACPI S3 Sleep State Support

Not supported.


®

 Intel ®

Xeon

®

processor E5-2600 and E5-2600 v2 product family up to 135 Watt

Supported Chassis









Intel

®

Server Chassis P4208 (UPL with redundant fan 4U)

Intel

®


Intel

®


Intel

®















Intel

®

Server Chassis P4XXX (UPL with redundant fan 4U)

Intel

®

Server Chassis R2208 (BHP with redundant fan 2U)

Intel

®


Intel

®


Intel

®


Intel

®


Chassis-specific sensors

Table 73. Intel

®

Server Board S2600IP - Chassis-specific Sensors

Intel

®

Server Chassis

P4208/P4216/P4224/

P4308/P4XXX (UPL with redundant fan

4U)

R2208/R2216/R2224/P

2308/P2312 (BHP with redundant fan 2U)

Fan Tachometer

Sensors

Fan Presence Sensors Physical Security

(Chassis intrusion) sensor

FP Interrupt

(FP NMI Diag Int)

System Fan 1(30h) Fan 1 Present (40h) Physical Scrty (04h) FP NMI Diag Int (05h)

System Fan 2(31h) Fan 2 Present (41h) NA

System Fan 3 (32h) Fan 3 Present (42h) NA



NA

NA

NA

NA

System Fan 1 (30h) Fan 1 Present (40h) Physical Scrty (04h) FP NMI Diag Int (05h)

System Fan 2 (31h) Fan 2 Present (41h) NA NA



NA

NA



NA

NA





















Hot-plug fan support

Supported on:

Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Fan redundancy support







Supported on:

Intel

®


Intel

®


Intel

®

















Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Fan domain definition

Chassis

Table 74. Intel

®

Server Board S2600IP - Fan Domain Definition

P4208/P4216/P4224/P4

308/P4XXX (UPL with redundant fan 4U)

Fan Domain

0

1

2

3

Major Components Cooled

(Temperature sensor number)

 SSB Temp(22h)

 BB BMC Temp(23h)

 BB MEM VR Temp(25h)

 I/O Mod Temp(26h)

 HSBP 1 Temp(29h)

 HSBP 2 Temp(2Ah)

 SAS Mod Temp(2Dh)

 Exit Air Temp(2Eh)

 LAN NIC Temp(2Fh)

 SSB Temp(22h)









 BB P2 VR Temp(24h)




 HSBP 3 Temp(2Bh)



 HDD 20 Status(64h)


 DIMM Thrm Mrgn 2(B1h)





 P1 Therm Margin(74h)

Fans

(Sensor number)

System Fan 1(30h)

System Fan 2(31h)

System Fan 3(32h)

System Fan 4(33h)


Chassis

R2208/R2216/R2224/P2

308/P2312 (BHP with redundant fan 2U)

Fan Domain

4

0

1

2

3









 PS1 Temperature(5Ch)

 PS2 Temperature(5Dh)





 SSB Temp(22h)









 SSB Temp(22h)









 SSB Temp(22h)






 P2 DTS Therm Mgn(84h)











Fans

(Sensor number)

System Fan 5(34h)

System Fan 1(30h)

System Fan 2(31h)

System Fan 3(32h)

System Fan 4(33h)

143

Chassis

Fan Domain

4

5

HSC Availability

















Intel

®

Server Chassis P4208 (UPL) o 8bay 2.5” HDD – FXX8X25HSBP

Intel

®


Intel

®


Intel

®

Server Chassis P4308 (UPL) o 8-bay 3

.5” HDD – FUP8X35HSBP

Intel

®

Server Chassis R2208 (BHP) o 8bay 2.5” HDD – FXX8X25HSBP

Intel

®


Intel

®


Intel

®

Server Chassis R2308 (BHP) o 8-bay 3

.5” HDD – F2U8X35HSBP







 SSB Temp(22h)






 P2 DTS Therm Mgn(84h)














144 Intel order number G34153-003

Fans

(Sensor number)

System Fan 5(34h)

System Fan 6(35h)

Revision 1.2



Intel

®

Server Chassis R2312 (BHP) o 12-bay 3

.5” HDD – F2U12X35HSBP

Power unit support



Intel

®

Server Chassis P4208/P4216/P4224/P4308 (UPL)

Table 75. Intel

®

Server Chassis P4208/P4216/P4224/P4308 (UPL) Power support



PS Module

Number

PMBus*

Product Name (in product area of the FRU)

PSU

Redundant

Cold

Redundant

Fans in each PS

750W HS

Power Supply

1200W HS

Power Supply

Supported

Supported

DPS-750XB A

DPS-1200TB A

Supported

Supported

Supported

Supported

Intel

®

Server Chassis R2208/R2216/R2224/R2308/R2312 (BHP)

1 PS fan

2 PS fan

Table 76. Intel

®

Server Chassis R2208/R2216/R2224/R2308/R2312 (BHP) Power support

PS Module

Number

PMBus*

Product Name(in product area of the FRU)

PSU

Redundant

Cold

Redundant

Fans in each PS

750W HS

Power Supply

Supported FS750HS1-00 Supported Supported 1 PS fan


®





















Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Fan Fault LED support









Fan fault LEDs are available on the baseboard and on the hot-swap redundant fans available on the following chassis:

Intel

®


Intel

®


Intel

®


Intel

®















Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Intel

®


Memory Throttling support



Baseboard supports this feature.

Intel

®

Workstation Board W2600CR

Introduction

This is an addendum document to BMC core EPS. This document describes platform and chassis specific information.

Product ID

Bytes 11:12 (product ID) of Get Device ID command response: 56h 00h

IPMI Channel ID Assignments

The following table provides information on the BMC channel assignments:

Table 77. Intel

®

Workstation Board W2600CR - BMC Channel Assignments

Channel ID Interface Supports

Sessions

Yes

Yes

Yes

Yes

0

1

2

3

4

5

6

Primary IPMB

LAN 1

LAN 2 (platform specific)

LAN3

1


®


Reserved

USB

Secondary IPMB

7

8

– 0Dh

0Eh

0Fh

Notes:

SMM

Reserved

Self

2

SMS/Receive Message Queue

1. Optional HW supported by the server system.

Yes

No

No

No

–

–

No


ACPI S3 Sleep State Support

Supported



®

 Intel

®

Xeon

®

processor E5-2600 product family up to 150 Watt

 Intel

®

Xeon

®

processor E5-2600 v2 product family up to 150 Watt

Supported Chassis



Intel

®

Server Chassis P4304 (UPL with fixed fan 4U)

Chassis-specific sensors

Table 78. Intel

®

Workstation Board W2600CR - Chassis-specific sensors

Intel

®

Server Chassis

P4304 (UPL with fixed fan 4U)

Hot-plug fan support

Not supported.

Fan redundancy support

Not supported.

Fan Tachometer Sensors

System Fan 1(30h)

System Fan 2(31h)

Processor 1 Fan (36h) NA

Processor 2 Fan (37h) detected

NA

Fan

Presene

Sensors

NA

NA

Physical Security

(Chassis intrusion) sensor

FP Interrupt

(FP NMI Diag Int)

Physical Scrty(04h) FP NMI Diag Int(05h)

NA NA

NA

NA

NA

NA

Board specific feature

Board has not supported serial port A, and SOL will only use serial port B.

Fan domain definition

Table 79. Intel

®

Workstation Board W2600CR - Fan domain definition

Chassis

P4304 (UPL with fixed fan 4U)

Fan Domain

0

1



 SSB Temp(22h)















Fans

(Sensor number)

System Fan 1(30h)

System Fan 2(31h)


Chassis

Fan Domain

6

7











Fans

(Sensor number)

Processor 1 Fan(36h)

Processor 2 Fan(37h)

HSC Availability

Not supported.

Power unit support



Intel

®

Server Chassis P4304 (UPL)

Table 80. Intel

®

Server Chassis P4304 (UPL) Power support

PS Module

Number

PMBus*

Product Name (in product area of the

FRU)

750W HS

Power Supply

1200W HS

Power Supply

Supported

Supported

DPS-750XB A

DPS-1200TB A


®

Not supported.

Fan Fault LED support

Not supported.

Memory Throttling support



Baseboard supports this feature.

PSU Redundant

Supported

Supported

Cold

Redundant

Fans in each

PS

Supported 1 PS fan

Supported 2PS fan


Appendix D: POST Code Diagnostic LED Decoder

During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the Diagnostic LEDs can be used to identify the last POST process that was executed.

Each POST code is represented by a sequence of eight amber diagnostic LEDs. The POST codes are divided into two nibbles, an upper nibble and a lower nibble. The upper nibble bits are represented by diagnostic LEDs #4, #5, #6, and #7. The lower nibble bits are represented by diagnostics LEDs #0, #1, #2, and #3. If the bit is set in the upper and lower nibbles, then the corresponding LED is lit. If the bit is clear, then the corresponding LED is off.

The diagnostic LED #7 is labeled as “MSB”, and the diagnostic LED #0 is labeled as “LSB”.

Revision 1.2

Figure 36.

POST Code Diagnostic LED Decoder


Note: Diagnostic LEDs are best read and decoded when viewing the LEDs from the back of the system

Table 81. POST Progress Code LED Example

LEDs

Status

MSB

LED #7

8h

ON

Upper Nibble AMBER LEDs

LED #6

4h

LED #5

2h

OFF ON

LED #4

1h

OFF

LED #3

8h

ON

Lower Nibble GREEN LEDs

LED #2

4h

LED #1

2h

ON OFF

LSB

LED #0

1h

OFF

1 0 1 0 1 1 0 0

Results

Ah Ch

Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as

ACh

The following table provides a list of all POST progress codes.

Table 82. POST Progress Codes

Diagnostic LED Decoder

1 = LED On, 0 = LED Off

Upper Nibble Lower Nibble

Checkpoint

MSB LSB

8h 4h 2h 1h 8h 4h 2h 1h

LED # #7 #6 #5 #4 #3 #2 #1 #0

SEC Phase

01h

02h

0

0

0

0

0

0

0

0

0

0

0

0

0

1

Description

1 First POST code after CPU reset

0 Microcode load begin

03h

04h

05h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

1 CRAM initialization begin

0 Pei Cache When Disabled

1 SEC Core At Power On Begin.

06h

07h

08h

09h

0Eh

0Fh

PEI Phase

10h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

1

1

0 Early CPU initialization during Sec Phase.

1 Early SB initialization during Sec Phase.

0 Early NB initialization during Sec Phase.

1 End Of Sec Phase.

0 Microcode Not Found.

1 Microcode Not Loaded.

0 0 0 1 0 0 0 0 PEI Core

11h

15h

0

0

0

0

0

0

1

1

0

0

0

1

0

0

1 CPU PEIM

1 NB PEIM

19h 0 0 0 1 1 0 0 1 SB PEIM

MRC Process Codes

– MRC Progress Code Sequence is executed - See Table 83.

PEI Phase continued…

31h

32h

0 0 1 1 0 0 0 1 Memory Installed

0 0 1 1 0 0 1 0 CPU PEIM (Cpu Init)

33h

34h

0 0 1 1 0 0 1 1 CPU PEIM (Cache Init)

0 0 1 1 0 1 0 0 CPU PEIM (BSP Select)

35h 0 0 1 1 0 1 0 1 CPU PEIM (AP Init)

36h

4Fh

0

0

0

1

1

0

1

0

0

1

1

1

1

1

0 CPU PEIM (CPU SMM Init)

1 Dxe IPL started

DXE Phase

60h

61h

62h

0 1 1 0 0 0 0 0 DXE Core started

0 1 1 0 0 0 0 1 DXE NVRAM Init

0 1 1 0 0 0 1 0 SB RUN Init


ABh

ACh

ADh

AEh

AFh

B0h

B1h

A2h

A3h

A4h

A5h

A6h

A7h

A8h

A9h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

A1h




Checkpoint

MSB LSB

8h 4h 2h 1h 8h 4h 2h 1h

LED # #7 #6 #5 #4 #3 #2 #1 #0

63h 0 1 1 0 0 0 1 1 Dxe CPU Init

68h

69h

6Ah

70h

71h

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

0

0

0 DXE PCI Host Bridge Init

1 DXE NB Init

0 DXE NB SMM Init

0 DXE SB Init

1 DXE SB SMM Init

Description

72h

78h

79h

90h

91h

92h

93h

0 1 1 1 0 0 1 0 DXE SB devices Init

0 1 1 1 1 0 0 0 DXE ACPI Init

0 1 1 1 1 0 0 1 DXE CSM Init

1 0 0 1 0 0 0 0 DXE BDS Started

1 0 0 1 0 0 0 1 DXE BDS connect drivers

1 0 0 1 0 0 1 0 DXE PCI Bus begin

1 0 0 1 0 0 1 1 DXE PCI Bus HPC Init

1 0 0 1 0 1 0 0 DXE PCI Bus enumeration

1 0 0 1 0 1 0 1 DXE PCI Bus resource requested

1

1

1

1

1

0

0

0

1 0 0 1 1 0 0 1 DXE SIO Init

1 0 0 1 1 0 1 0 DXE USB start

0

0

0

0

0

0

0

1

1

1

1

1

0

0

1

1

1

1

1

0

0

1

1

1

0

1

0

0 DXE PCI Bus assign resource

1 DXE CON_OUT connect

0 DXE CON_IN connect

1 DXE USB reset

0 DXE USB detect

1 0 0 1 1 1 0 1 DXE USB enable

1 0 1 0 0 0 0 1 DXE IDE begin

1 0 1 0 0 0 1 0 DXE IDE reset

1 0 1 0 0 0 1 1 DXE IDE detect

1 0 1 0 0 1 0 0 DXE IDE enable

1 0 1 0 0 1 0 1 DXE SCSI begin

1 0 1 0 0 1 1 0 DXE SCSI reset

1 0 1 0 0 1 1 1 DXE SCSI detect

1 0 1 0 1 0 0 0 DXE SCSI enable

1 0 1 0 1 0 0 1 DXE verifying SETUP password

1 0 1 0 1 0 1 1 DXE SETUP start

1 0 1 0 1 1 0 0 DXE SETUP input wait

1 0 1 0 1 1 0 1 DXE Ready to Boot

1 0 1 0 1 1 1 0 DXE Legacy Boot

1 0 1 0 1 1 1 1 DXE Exit Boot Services

1 0 1 1 0 0 0 0 RT Set Virtual Address Map Begin

1 0 1 1 0 0 0 1 RT Set Virtual Address Map End


Checkpoint

LED #

B2h




MSB LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0 Description

1 0 1 1 0 0 1 0 DXE Legacy Option ROM init

B3h 1 0 1 1 0 0 1 1 DXE Reset system

B4h

B5h

1 0 1 1 0 1 0 0 DXE USB Hot plug

1 0 1 1 0 1 0 1 DXE PCI BUS Hot plug

B6h

B7h

1 0 1 1 0 1 1 0 DXE NVRAM cleanup

1 0 1 1 0 1 1 1 DXE Configuration Reset

00h

S3 Resume

E0h

0 0 0 0 0 0 0 0 INT19

E1h

E2h

E3h

1 1 0 1 0 0 0 0 S3 Resume PEIM (S3 started)

1 1 0 1 0 0 0 1 S3 Resume PEIM (S3 boot script)

1 1 0 1 0 0 1 0 S3 Resume PEIM (S3 Video Repost)

1 1 0 1 0 0 1 1 S3 Resume PEIM (S3 OS wake)

BIOS Recovery

F0h 1 1 1 1 0 0 0 0 PEIM which detected forced Recovery condition

F1h 1 1 1 1 0 0 0 1 PEIM which detected User Recovery condition

F2h 1 1 1 1 0 0 1 0 Recovery PEIM (Recovery started)

F3h 1 1 1 1 0 0 1 1 Recovery PEIM (Capsule found)

F4h 1 1 1 1 0 1 0 0 Recovery PEIM (Capsule loaded)

POST Memory Initialization MRC Diagnostic Codes

There are two types of POST Diagnostic Codes displayed by the MRC during memory initialization; Progress Codes and Fatal Error Codes.

The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step.

Table 83. MRC Progress Codes

Checkpoint




MSB

LED

MRC Progress Codes

LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0

B0h

B1h

B2h

B3h

B4h

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

0 Detect DIMM population

1 Set DDR3 frequency

Description

0 Gather remaining SPD data

1 Program registers on the memory controller level

0 Evaluate RAS modes and save rank information


Checkpoint

LED

B5h

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BFh




MSB LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0

Description

1 0 1 1 0 1 0 1 Program registers on the channel level

1 0 1 1 0 1 1 0 Perform the JEDEC defined initialization sequence

1 0 1 1 0 1 1 1 Train DDR3 ranks

1 0 1 1 1 0 0 0 Initialize CLTT/OLTT

1 0 1 1 1 0 0 1 Hardware memory test and init

1 0 1 1 1 0 1 0 Execute software memory init

1 0 1 1 1 0 1 1 Program memory map and interleaving

1 0 1 1 1 1 0 0 Program RAS configuration

1 0 1 1 1 1 1 1 MRC is done

Memory Initialization at the beginning of POST includes multiple functions, including: discovery, channel training, validation that the DIMM population is acceptable and functional, initialization of the IMC and other hardware settings, and initialization of applicable RAS configurations.

When a major memory initialization error occurs and prevents the system from booting with data integrity, a beep code is generated, the MRC will display a fatal error code on the diagnostic

LEDs, and a system halt command is executed. Fatal MRC error halts do NOT change the state of the System Status LED, and they do NOT get logged as SEL events. The following table lists all MRC fatal errors that are displayed to the Diagnostic LEDs.

Table 84. MRC Fatal Error Codes



Checkpoint Upper Nibble

MSB

Lower Nibble

LSB

8h 4h 2h 1h 8h 4h 2h 1h

LED #7 #6 #5 #4 #3 #2 #1 #0

MRC Fatal Error Codes

E8h

E9h

EAh

EBh

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

1

0

1

Description

No usable memory error

01h = No memory was detected by SPD read, or invalid config that causes no operable memory.

02h = Memory DIMMs on all channels of all sockets are disabled due to hardware memtest error.

3h = No memory installed. All channels are disabled.

Memory is locked by Intel Trusted Execution Technology and is inaccessible

DDR3 channel training error

01h = Error on read DQ/DQS (Data/Data Strobe) init

02h = Error on Receive Enable

3h = Error on Write Leveling

04h = Error on write DQ/DQS (Data/Data Strobe

Memory test failure

01h = Software memtest failure.


Checkpoint

LED

EDh

EFh




1 1 1 0 1 1 0 1

1 1 1 0 1 1 1 1

Description

MSB LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0

02h = Hardware memtest failed.

03h = Hardware Memtest failure in Lockstep Channel mode requiring a channel to be disabled. This is a fatal error which

requires a reset and calling MRC with a different RAS mode to

retry.

DIMM configuration population error

01h = Different DIMM types (UDIMM, RDIMM, LRDIMM) are detected installed in the system.

02h = Violation of DIMM population rules.

03h = The 3rd DIMM slot cannot be populated when QR DIMMs are installed.

04h = UDIMMs are not supported in the 3rd DIMM slot.

05h = Unsupported DIMM Voltage.

Indicates a CLTT table structure error


Appendix E: POST Error Messages and Handling

Most error conditions encountered during POST are reported using POST Error Codes. These codes represent specific failures, warnings, or are informational. POST Error Codes may be displayed in the Error Manager display screen, and are always logged to the System Event Log

(SEL). Logged events are available to System Management applications, including Remote and

Out of Band (OOB) management.

There are exception cases in early initialization where system resources are not adequately initialized for handling POST Error Code reporting. These cases are primarily Fatal Error conditions resulting from initialization of processors and memory, and they are handed by a

Diagnostic LED display with a system halt.

The following table lists the supported POST Error Codes. Each error code is assigned an error type which determines the action the BIOS will take when the error is encountered. Error types include Minor, Major, and Fatal. The BIOS action for each is defined as follows:



Minor: The error message is displayed on the screen or on the Error Manager screen, and an error is logged to the SEL. The system continues booting in a degraded state.

The user may want to replace the erroneous unit. The POST Error Pause option setting in the BIOS setup does not have any effect on this error.



Major: The error message is displayed on the Error Manager screen, and an error is logged to the SEL. The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting.

Note that for 0048 “Password check failed”, the system halts, and then after the next reset/reboot will displays the error code on the Error Manager screen.



Fatal: The system halts during post at a blank screen with the text

“Unrecoverable

fatal error found. System will not boot until the error is resolved” and “Press <F2>

to enter setup” The POST Error Pause option setting in the BIOS setup does not have any effect with this class of error.

When the operator presses the F2 key on the keyboard, the error message is displayed on the Error Manager screen, and an error is logged to the SEL with the error code. The system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.

Note: The POST error codes in the following table are common to all current generation Intel server platforms. Features present on a given server board/system will determine which of the listed error codes are supported.

0012

Error Code

0048

0140

Table 85. POST Error Codes and Messages

System RTC date/time not set

Error Message

Password check failed

PCI component encountered a PERR error

Response

Major

Major

Major


84FF

8500

8501

8520

8521

8522

8523

8524

8525

8526

8172

8173

8180

8181

8182

8183

8190

8198

8300

8305

83A0

83A1

84F2

84F3

84F4

5221

5224

8130

8131

8132

8133

8160

8161

8162

8163

8170

8171

0141

Error Code

0146

0191

0192

0194

0195

0196

0197

5220

Error Message

PCI resource conflict

PCI out of resources error

Processor core/thread count mismatch detected

Processor cache size mismatch detected

Processor family mismatch detected

Processor Intel(R) QPI link frequencies unable to synchronize

Processor model mismatch detected

Processor frequencies unable to synchronize

BIOS Settings reset to default settings

Passwords cleared by jumper

Password clear jumper is Set

Processor 01 disabled




Processor 01 unable to apply microcode update




Processor 01 failed Self Test (BIST)




Processor 01 microcode update not found




Watchdog timer failed on last boot

OS boot watchdog timer failure

Baseboard management controller failed self-test

Hot Swap Controller failure

Management Engine (ME) failed Selftest

Management Engine (ME) Failed to respond.

Baseboard management controller failed to respond

Baseboard management controller in update mode

Sensor data record empty

System event log full

Memory component could not be configured in the selected RAS mode

DIMM Population Error

DIMM_A1 failed test/initialization



DIMM_B1 failed test/initialization



DIMM_C1 failed test/initialization

Minor

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Minor

Minor

Minor

Minor

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Response

Major

Major

Fatal

Fatal

Fatal

Fatal

Fatal

Fatal

Major


8547

8548

8549

854A

854B

854C

854D

854E

854F

8550

8551

8552

8553

8540

8541

8542

8543

8544

8545

8546

8527

Error Code

8528

8529

852A

852B

852C

852D

852E

852F

8530

Error Message



DIMM_D1 failed test/initialization



DIMM_E1 failed test/initialization



DIMM_F1 failed test/initialization


8531

8532

8533

8534

8535

8536

8537

8538


DIMM_G1 failed test/initialization



DIMM_H1 failed test/initialization



DIMM_I1 failed test/initialization

8539

853A

853B

853C

853D



DIMM_J1 failed test/initialization



853E DIMM_K1 failed test/initialization

853F (Go to 85C0) DIMM_K2 failed test/initialization

DIMM_A1 disabled

DIMM_A2 disabled

DIMM_A3 disabled

DIMM_B1 disabled

DIMM_B2 disabled

DIMM_B3 disabled

DIMM_C1 disabled

DIMM_C2 disabled

DIMM_C3 disabled

DIMM_D1 disabled

DIMM_D2 disabled

DIMM_D3 disabled

DIMM_E1 disabled

DIMM_E2 disabled

DIMM_E3 disabled

DIMM_F1 disabled

DIMM_F2 disabled

DIMM_F3 disabled

DIMM_G1 disabled

DIMM_G2 disabled


Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Response

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

157

8564

8565

8566

8567

8568

8569

856A

856B

856C

8554

Error Code

8555

8556

8557

8558

8559

855A

855B

855C

855D

855E

855F

(Go to 85D0)

8560

8561

8562

8563

856D

856E

856F

8570

8571

8572

8573

8574

8575

8576

8577

8578

8579

857A

857B

857C

857D

857E

857F

(Go to 85E0)

Error Message

DIMM_G3 disabled

DIMM_H1 disabled

DIMM_H2 disabled

DIMM_H3 disabled

DIMM_I1 disabled

DIMM_I2 disabled

DIMM_I3 disabled

DIMM_J1 disabled

DIMM_J2 disabled

DIMM_J3 disabled

DIMM_K1 disabled

DIMM_K2 disabled

DIMM_A1 encountered a Serial Presence Detection (SPD) failure



DIMM_B1 encountered a Serial Presence Detection (SPD) failure



DIMM_C1 encountered a Serial Presence Detection (SPD) failure



DIMM_D1 encountered a Serial Presence Detection (SPD) failure



DIMM_E1 encountered a Serial Presence Detection (SPD) failure



DIMM_F1 encountered a Serial Presence Detection (SPD) failure



DIMM_G1 encountered a Serial Presence Detection (SPD) failure



DIMM_H1 encountered a Serial Presence Detection (SPD) failure



DIMM_I1 encountered a Serial Presence Detection (SPD) failure



DIMM_J1 encountered a Serial Presence Detection (SPD) failure



DIMM_K1 encountered a Serial Presence Detection (SPD) failure


158 Intel order number G34153-003

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Response

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Revision 1.2

85CA

85CB

85CC

85CD

85CE

85CF

85D0

85D1

85D2

85D3

85D4

85D5

85D6

85D7

85D8

Error Code

85C0

85C1

85C2

85C3

85C4

85C5

85C6

85C7

85C8

85C9

85E0

85E1

85E2

85E3

85E4

85E5

85E6

85E7

85E8

85E9

85EA

85EB

85EC

85D9

85DA

85DB

85DC

85DD

85DE

85DF

Error Message

DIMM_K3 failed test/initialization

DIMM_L1 failed test/initialization



DIMM_M1 failed test/initialization



DIMM_N1 failed test/initialization



DIMM_O1 failed test/initialization



DIMM_P1 failed test/initialization



DIMM_K3 disabled

DIMM_L1 disabled

DIMM_L2 disabled

DIMM_L3 disabled

DIMM_M1 disabled

DIMM_M2 disabled

DIMM_M3 disabled

DIMM_N1 disabled

DIMM_N2 disabled

DIMM_N3 disabled

DIMM_O1 disabled

DIMM_O2 disabled

DIMM_O3 disabled

DIMM_P1 disabled

DIMM_P2 disabled

DIMM_P3 disabled


DIMM_L1 encountered a Serial Presence Detection (SPD) failure



DIMM_M1 encountered a Serial Presence Detection (SPD) failure



DIMM_N1 encountered a Serial Presence Detection (SPD) failure



DIMM_O1 encountered a Serial Presence Detection (SPD) failure



Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Response

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major

Major


Error Code

85ED

85EE

85EF

8604

8605

8606

92A3

92A9

A000

A001

A002

A003

A100

A421

A5A0

A5A1

A6A0

Error Message

DIMM_P1 encountered a Serial Presence Detection (SPD) failure



POST Reclaim of non-critical NVRAM variables

BIOS Settings are corrupted

NVRAM variable space was corrupted and has been reinitialized

Serial port component was not detected

Serial port component encountered a resource conflict error

TPM device not detected.

TPM device missing or not responding.

TPM device failure.

TPM device failed self test.

BIOS ACM Error

PCI component encountered a SERR error

PCI Express* component encountered a PERR error

PCI Express* component encountered an SERR error

DXE Boot Services driver: Not enough memory available to shadow a

Legacy Option ROM.

POST Error Beep Codes

The following table lists the POST error beep codes. Prior to system video initialization, the

BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user-visible code on the POST Progress LEDs

Table 86. POST Error Beep Codes

1

3

2

Beeps

USB device action

1 long Intel

Error Message

®

TXT security violation

Memory error

POST Progress Code

NA

0xAE, 0xAF

Description

Short beep sounded whenever a USB device is discovered in POST, or inserted or removed during runtime

System halted because Intel

®

Trusted Execution

Technology detected a potential violation of system security.

See Tables 28 and 29 System halted because a fatal error related to the memory was detected.

NA Recovery boot has been initiated

4

BIOS Recovery started

BIOS Recovery failure

NA BIOS recovery has failed. This typically happens so quickly after recovery us initiated that it sounds like a 2-4 beep code.

The Integrated BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously. Codes that are common across all Intel server boards and systems that use same generation chipset are listed in the following table. Each digit in the code is represented by a sequence of beeps whose count is equal to the digit.

Minor

Minor

Major

Fatal

Minor

Fatal

Minor

Response

Major

Major

Major

Minor

Major

Major

Major

Major

Minor

Minor


Table 87. Integrated BMC Beep Codes


1-5-2-1 No CPUs installed or first CPU socket is empty.

Associated Sensors

CPU1 socket is empty, or sockets are populated incorrectly

CPU1 must be populated before CPU2.

1-5-2-4 MSID Mismatch

1-5-4-2 Power fault

1-5-4-4 Power control fault (power good assertion timeout).

1-5-1-2 VR Watchdog Timer sensor assertion

1-5-1-4 Power Supply Status

MSID mismatch occurs if a processor is installed into a system board that has incompatible power capabilities.

DC power unexpectedly lost (power good dropout)

–

Power unit sensors report power unit failure offset

Power good assertion timeout

– Power unit sensors report soft power control failure offset

VR controller DC power on sequence was not completed in time.

The system does not power on or unexpectedly powers off and a Power Supply Unit (PSU) is present that is an incompatible model with one or more other PSUs in the system.


Glossary

Glossary

GB

GPIO

GTL

HSC

Hz

I2C

IA

IBF

ICH

ICMB

IERR

IFB

DPC

EEPROM

EHCI

EMP

EPS

FMB

FMC

FMM

FRB

FRU

FSB

This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, 82460GX) with alpha entries following (for example, AGP 4x). Acronyms are then entered in their respective place, with non-acronyms following.

Term

ACPI

AP

APIC

ASIC

BIOS

BIST

BMC

Bridge

BSP byte

CBC

CEK

CHAP

CMOS

Advanced Configuration and Power Interface

Application Processor

Advanced Programmable Interrupt Control

Application Specific Integrated Circuit

Basic Input/Output System

Definition

Built-In Self Test

Baseboard Management Controller

Circuitry connecting one computer bus to another, allowing an agent on one to access the other

Bootstrap Processor

8-bit quantity.

Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis.

Common Enabling Kit

Challenge Handshake Authentication Protocol

In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board.

Direct Platform Control

Electrically Erasable Programmable Read-Only Memory

Enhanced Host Controller Interface

Emergency Management Port

External Product Specification

Flexible Mother Board

Flex Management Connector

Flex Management Module

Fault Resilient Booting

Field Replaceable Unit

Front Side Bus

1024MB

General Purpose I/O

Gunning Transceiver Logic

Hot-Swap Controller

Hertz (1 cycle/second)

Inter-Integrated Circuit Bus

Intel

®

Architecture

Input Buffer

I/O Controller Hub

Intelligent Chassis Management Bus

Internal Error

I/O and Firmware Bridge


Intel®

MD2

MD5 ms

MTTR

Mux

NIC

NMI

LED

LPC

LUN

MAC

MB mBMC

MCH

Term

INTR

IP

IPMB

IPMI

IR

ITP

KB

KCS

LAN

LCD

Definition

Interrupt

Internet Protocol

Intelligent Platform Management Bus

Intelligent Platform Management Interface

Infrared

In-Target Probe

1024 bytes

Keyboard Controller Style

Local Area Network

Liquid Crystal Display

Light Emitting Diode

Low Pin Count

Logical Unit Number

Media Access Control

1024KB

National Semiconductor© PC87431x mini BMC

Memory Controller Hub

Message Digest 2

– Hashing Algorithm

Message Digest 5

– Hashing Algorithm – Higher Security milliseconds

Memory Tpe Range Register

Multiplexor

Network Interface Controller

Nonmaskable Interrupt

OBF

OEM

Ohm

PEF

PEP

PIA

PLD

PMI

POST

PSMI

PWM

RAM

RASUM

Output Buffer

Original Equipment Manufacturer

Unit of electrical resistance

Platform Event Filtering

Platform Event Paging

Platform Information Area (This feature configures the firmware for the platform hardware)

Programmable Logic Device

Platform Management Interrupt

Power-On Self Test

Power Supply Management Interface

Pulse-Width Modulation

Random Access Memory

Reliability, Availability, Serviceability, Usability, and Manageability

RISC

ROM

RTC

SDR

Reduced Instruction Set Computing

Read Only Memory

Real-Time Clock (Component of ICH peripheral chip on the server board)

Sensor Data Record

SECC Single Edge Connector Cartridge

SEEPROM Serial Electrically Erasable Programmable Read-Only Memory

SEL System Event Log

SIO Server Input/Output

Glossary


Glossary

SMI

Term

SMM

SMS

SNMP

TBD

TIM

UART

UDP

UHCI

UTC

VID

VRD

Word

ZIF

Definition

Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)

Server Management Mode

Server Management Software

Simple Network Management Protocol

To Be Determined

Thermal Interface Material

Universal Asynchronous Receiver/Transmitter

User Datagram Protocol

Universal Host Controller Interface

Universal time coordinare

Voltage Identification

Voltage Regulator Down

16-bit quantity

Zero Insertion Force


Intel® Reference Documents

Reference Documents

See the following document for additional information:



BIOS for EPSD Platforms Based on Intel

®

Xeon Processor E5-4600/2600/2400/1600

Product Families External Product Specification



EPSD Platforms Based On Intel Xeon

®

Processor E5 4600/2600/2400/1600 Product













Families BMC Core Firmware External Product Specification

Intel

®

Intel

®

Intel

®

Server System P4000IP/CR Technical Product Specification

Server System R2000IP Technical Product Specification

Remote Management Module 4 Technical Product Specification

Intelligent Platform Management Interface Specification

SmaRT and

CLST Architecture on “Romley” Systems and Power Supplies Specification

(Doc Reference # 461024)



Intel Integrated RAID Module RMS25PB080, RMS25PB040, RMS25CB080, and

RMS25CB040 Hardware User

’s Guide


Mouser Electronics

Authorized Distributor

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