AMS AS8530 Datasheet
광고
광고
AS8530
LIN Transceiver with Integrated Voltage Regulator and
MCU Interface for Automotive Applications
1 General Description
Typically 45µA quiescent current in standby mode,
Typically 35µA quiescent current in sleep mode
The AS8530 is a general purpose companion IC for sensor and actuator LIN slaves offering LIN transceiver and low drop voltage regulator.
It also provides a 2-wire microcontroller interface through shared EN and TX pins to access a window watchdog with RC oscillator, control registers, backup registers and monitoring information.
The IC is fabricated in a high voltage CMOS technology which is able to withstand voltages up to 42V.
Under voltage reset with factory options
LIN bus transceiver l conforming to LIN 2.1, TX time out fail safe feature, over temperature warning and shut down
Window watchdog if factory enabled
Micro controller 2-wire interface through shared pins for watchdog trigger, monitoring, register read /write
Chip ID for traceability and module ID
The product is available in ep-SOIC8 package.
8 Backup registers to store data during VCC shut down
2 Key Features
ep-SOIC8 package
-40ºC to +125ºC ambient operating temperature
Operating voltage 6V to 18V
Linear, low-drop voltage regulator: VCC = 5V ±5% or 3.3V ±5% as a factory programming option
50mA load current
Operating modes: Normal and Standby or Normal and Sleep as a factory option
3 Applications
The AS8530 is a System Basis Chip for automotive LIN networked sensor or actuator slaves.
Figure 1. AS8530 LIN Transceiver Block Diagram
VSUP
LDO VCC
EN
LIN
GND
POR-VSUP
RESET_VSUP_N
Temperature
Limiter
TSHD
Mode
Control
RESET_VSUP_N
LIN
Wakeup
POR-VCC
AS8530
RESET_VCC_N
Control
Signals
WWD Output
Reset
Block
2-Wire
Interface
Window
Watchdog
(WWD)
VSUP
Receiver
30k
Transmitter
15k
VCC
Slew
Control
LIN Transceiver
RESET
RX
TX
www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - C o n t e n t s
Contents
4
6
6
7
7
8
CC
Undervoltage Reset and Window Watchdog..............................................................................................................................
11
12
13
13
SUP
Undervoltage Reset .................................................................................................................................................................
13
Undervoltage in Normal Mode......................................................................................................................................... 13
Undervoltage in Standby Mode / Sleep Mode................................................................................................................. 13
Undervoltage in Low Slew Mode..................................................................................................................................... 13
14
CC
Undervoltage Reset ...................................................................................................................................................................
14
14
15
15
17
18
19
19
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AS8530
Datasheet (discontinued) - C o n t e n t s
19
20
21
23
26
www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
EN
1
VSUP
2
LIN
3
VSS
4
AS8530
8
VCC
7
RESET
6
TX
5
RX
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number Pin Name
1 EN
2
3
4
5
6
7
8
V
SUP
LIN
VSS
RX
TX
RESET
VCC
Pin Type
Digital input with pull-down
Supply pad
Analog I/O
Supply pad
Digital output with pull-up
Digital input with pull-up
Digital output
Supply pad
Special Requirements
2kV ESD
Load dump (42V max),
4kV HBM ESD,
Jump start (27V max)
Conforms to LIN 2.1,
6kV HBM ESD
LIN Bus
Description
Enable high-voltage compatible pin with pull down to VSS and ½ VCC trigger level, active high.
Battery supply
2kV ESD
LIN transceiver receive signal, data out in test mode
LIN transceiver transmit signal, clock in test mode
Digital output referenced to VCC, active low
Regulated 5V / 3.3V supply for loads up to 50mA.
OTP selectable www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2
may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
Electrical Characteristics on page 6 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Electrical Parameters
V
SUP
Min Max Units
V
Comments
Transient up to 500ms duration
DC Supply Voltage
EN
V
CC
LIN
RESET, RX, TX
Input current (latchup immunity) I scr
Electrostatic Discharge
-0.3
-0.3
42
V
SUP
+
0.3
7 -0.3
-27 +40
-0.3
V
CC
+ 0.3
-100 100
V
V
V
V mA Norm: JEDEC 78
Electrostatic Discharge (ESD)
Norm: AEC-Q-100-002
±2
±4
±6 kV
For on board signals V
CC
, TX, RX, Reset
For V
SUP
LIN to V
SS
, HBM Model
Continuous Power Dissipation
Total operating power dissipation
(all supplies and outputs) P t
Temperature Ranges and Storage Conditions
Storage temperature (T strg
) -55
0.25
+150
W
ºC epSOIC8 in still air, soldered on JEDEC standard board @125º ambient, static operation = no time limit
Package body temperature (T body
) +260 ºC
The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/
JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin (100% Sn).
Humidity non-condensing
Moisture Sensitive Level
5
3
85 %
Represents a maximum floor life time of 168h www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
6.1 Operating Conditions
Symbol
V
SUP
VSS
T
AMB
I supp
Parameter
Positive Supply Voltage
Negative Supply Voltage
Ambient temperature
Supply Current
Conditions
Normal operating condition
Maximum junction temperature (T
J
) 150ºC
Min
6
0
-40
Typ Max
18
+125
65
6.2 Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. RESET and RX have been measured with 100pF load.
Symbol Parameter Min Typ
V
IH
High level input voltage
Conditions
EN Input
High Voltage Pin which can also be connected to VSUP
0.8V
CC
V
IL
I
LEAK
I pd_en
Low level input voltage
Input leakage current
Pull down current
TX
EN = L
EN = V
CC
-1
20
Max
0.2V
CC
+1
40
V
IH
V
IL
I
LEAK
I pu
High level input voltage
Low level input voltage
Input leakage current
Pull up current
TX = V
CC
TX pulled to VSS
RESET
0.8V
CC
-1
-30
0.2V
CC
+1
-10
V
OH
High level output voltage I
OUT
= 1 mA, V
SUP
≥ 6V
V
CC
-
0.5
V
OL
Low level output voltage V
SUP
≥ 6V
VSS
+ 0.4
RX
V
OH
High level output voltage
V
CC
-
0.5
V
OL
Low level output voltage
I
OUT
= 1 mA, V
SUP
≥ 6V
VSS +
0.4
Units
V
V
V
V
V
V
µA
µA
V
V
µA
µA
Units
V
V
ºC mA www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6.3 Detailed System and Block Specifications
6.3.1 Electrical System Specifications
Symbol Parameter
IDD nom
1
Current consumption
Normal mode
Stand-by mode
Sleep mode
Conditions
No load on V
CC
, LIN recessive, V
SUP
= 12V
No load on V
CC
, LIN dominant, V
SUP
= 12V
Up to 125°C ambient (no load), V
SUP
= 12V
Up to 125°C ambient (no load), V
SUP
=12V
1. No external load on the LIN bus
Min Typ
300
700
45
35
Max
6.4 Low Dropout Regulator
The LDO block is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage (V
CC
) from the battery supply voltage (V
SUP
).
(6V < V
SUP
< 18V for option 1, 6V <VSUP <18V option2; -40°C < T
J
< 150°C; all voltages are with respect to ground (VSS); positive current flows into the pin), normal operating mode if not otherwise mentioned.
Symbol Parameter Typ Units
V
CC
T
J
V
SUP
V
CC
ICC_SH
Regulated supply voltage
I
LOAD
0mA to 50mA
Junction Temperature
Supply Voltage Range
Output Voltage Range
Output Short Circuit Current
Conditions
Option 1
Option 2
Option 1
Load < 50mA
50mA to 65mA
Standby mode @ ICC < 5mA
Load-dump condition,
I
LOAD
< 50mA
Load < 50mA
50mA to 65mA
Option 2
Standby mode @ ICC < 5mA
Load-dump condition,
I
LOAD
< 50mA
Normal mode
Standby mode
Δ V
CC
/ Δ V
SUP
Δ V
CC
/ Δ ICCn (for I
LOAD
> 500µA)
Δ
V
CC
/
Δ
ICCn (for I
LOAD
> 500µA)
Min
4.75
3.135
-40
6
4.75
4.5
4.5
3.135
2.97
2.97
50
5
12
5.0
3.3
3.3
Max
5.25
3.465
150
18
5.25
5.5
5.5
5.5
3.465
3.63
3.63
3.63
V
ºC
V
V mA dV
CC
1
Line Regulation
LOREG_SM Load Regulation (Standby mode)
LOREG_NM
Load Regulation (Normal mode)
CL1
Output Capacitor (Electrolytic)
ESR1
CL2
Output Capacitor (Ceramic)
ESR2
CSUP1E
Input capacitor (Electrolytic)
ESR1_CSUP
CSUP2C
Input capacitor (Ceramic)
ESR2_CSUP
For EMC suppression
2.2
1
100
0.02
10
1
100
0.02
1
100
10
220
1
1
10
10
220
250
250
8
10 mV/V mV/mA mV/mA
µF
Ω nF
Ω
µF
Ω nF
Ω
Units
µA
µA
µA
µA www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6.5 LIN Transceiver
6.5.1 DC Electrical Characteristics
(4.5V < V
CC
< 5.5V; 6V < V
SUP
< 18V; -40°C < T
J
< 150°C, VBUS is the voltage on the LIN node. All voltages are with respect to ground (VSS); positive current flows into the pin.
Symbol
Driver
Parameter Conditions Min Typ Max Units
I bus_lim
LIN_V
OL
I bus_leak_rec
Pull-up resistor
Current limitation in Dominant State
1
LIN = V
SUP
_max
Output Voltage BUS (dominant state),
I
LIN
= 40mA
(short-circuit condition tested at V
OL
= 2.5V)
Normal mode
(recessive BUS level on TX pin)
Driver OFF;
V
SUP
= 7.0V, 8V < VBUS < 18
40
20
120
40
200
2
60
20 mA
V k Ω
µA
Receiver
I bus_leak_dom
I bus_no_GND
I bus_no_bat
Input Leakage current at receiver
Input Leakage current at receiver
Driver OFF; Vbus = 0V; V
SUP
= 12V;
V
CC
= 5V
VSS = V
SUP
; V
SUP
= 12V;
0V < VBUS < 18V, V
CC
= 5V
V
SUP
= VSS;
0V < VBUS < 18V, V
CC
= VSS
2
-1
-1 1
100 mA mA
µA
V bus_dom
V bus_rec
V bus_cnt
V hys
V bus_cnt
= (V th_dom
+ V th_rec
)/2
3
V hys
= (V th_dom
– V th_rec
)
0.6
0.475
0.05
0.4
V
SUP
V
SUP
0.525
V
SUP
0.175
V
SUP
1. This failure condition triggers thermal shut down when shut down temperature threshold is exceeded.
2. Not production tested.
3. Vth_dom: Receiver threshold of the recessive to dominant LIN bus edge
Vth_rec : Receiver threshold of the dominant to recessive LIN bus edge www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6.5.2 AC Electrical Characteristics
LIN Driver, Bus load conditions (C
BUS
; R
BUS
): 1nF; 1k
Ω
/ 6,8nF; 660
Ω
/ 10nF; 500
Ω
Symbol
D1
(worst case 20Kbps transmission)
D2
(worst case 20kbps transmission)
D3
(worst case 10.4kbps transmission)
D4
(worst case 10.4kbps transmission) t dLR t dHR t
RS t wake
t sln t nsl t rec_deb
C int
Conditions
V th_rec
(max) = 0.744 x VSUP;
V th_dom
(max) = 0.581 x VSUP;
VSUP = 6.0V to 18V; tbit = 50 μ s;
D1 = tbus_rec(min) / (2 x tbit)
V
V th_rec
(min) = 0.422 x VSUP; th_dom
(min) = 0.284 x VSUP;
VSUP = 6V to 18V; tbit = 50 μ s;
D2 = tbus_rec(max) / (2 x tbit)
V th_rec
(max) = 0.778 x VSUP;
V th_dom
(max) = 0.616 x VSUP;
VSUP = 6.0V to 18V; tbit = 96 μ s;
D3 = tbus_rec(min) / (2 x tbit)
V
V th_rec
(min) = 0.389 x VSUP; th_dom
(min) = 0.251 x VSUP;
VSUP = 6V to18V; tbit = 96 μ s;
D4 = tbus_rec(max) / (2 x tbit)
V
CC
= 5V;
Propagation delay bus dominant to RX LOW
V
CC
= 5V;
Propagation delay bus dominant to RX HIGH
Receiver Delay symmetry
Wake-up delay time
Transition from standby mode to normal mode
(clock frequency is 128kHz ± 25%)
Transition from normal mode to standby mode
(clock frequency is 128kHz ± 25%)
Receiver De-bounce time
Guaranteed by design
Min
0.369
0.417
-2
30
1
Typ
4
6
220
Max
0.581
0.59
6
6
2
150
3
250
Units
Note:
Sleep-mode to Normal mode transition is identical to the Power-ON sequence after the remote wakeup event on LIN bus. The transition time will include the t
Res
(RESET time) and start-up time for the LDO.
µs
µs
µs
µs
Clock cycles
Clock cycles
µs pF www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
Figure 3. LIN Timing
t bit t bit
TXD t bus_dom(max) t bus_rec(min)
LIN
Vth_rec(max)
Vth_dom(max)
Vth_rec(min)
Vth_dom(min) t bus_dom(min) t bus_rec(max)
6.5.3 Temperature Limiter
Symbol
T sd
T ret
T otset
T otclear
Parameter
Shut down temperature
Return temperature
Over-temp warning flag set
Over-temp warning flag clear
Conditions
Junction temperature
During shut down, the sensor must be powered by VSUP.
Thermal shut down disables LDO and sets all drivers to high impedance, the IC returns from shut down with POR.
The temperature beyond which the warning flag is set.
The return temperature when the warning flag is cleared
Min
139
121
121
103
6.5.4 TX Timeout Watchdog
Symbol
t lin_wdog
Parameter
Time out duration (dominant state)
Conditions Min
0.5
Typ Max
171
Units
ºC
149
149
127
ºC
ºC
ºC
Typ
1
Max
2
Units
s www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6.6 V
CC
Undervoltage Reset and Window Watchdog
The values in this table are valid for normal and standby modes. All parameters are tested, unless mentioned otherwise.
Symbol Conditions Min Typ
Vuvr_off
Vuvr_on
Vuvr1_off
Vuvr1_on
Vuvr2_off
Vuvr2_on
Vuvr3_off
Vuvr3_on
Vhyst_vcc t rr
Vsuvr_off
Vsuvr_on
Parameter
V
CC
under-voltage threshold off
(Default)
V
CC
under voltage threshold on
(Default)
V
CC
under voltage threshold off
(Factory Option)
V
CC
under voltage threshold on
(Factory Option)
V
CC
under voltage threshold off
(Factory Option)
V
CC
under voltage threshold on
(Factory Option)
V
CC
under-voltage threshold off
(Factory Option)
V
CC
under voltage threshold on
(Factory Option)
Hysteresis of under-voltage threshold on/off V
CC
Spike filter on V
CC
V
SUP
under-voltage threshold off
V
SUP
under-voltage threshold on
Rising edge of V
CC
Falling edge of V
CC
Rising edge of V
CC
1
Falling edge of V
CC
Rising edge of V
CC
Falling edge of V
CC
Rising edge of V
CC
Falling edge of V
CC
Default and all other factory options
To remove disturbance
BOR level (considered to be the Master
Reset for AS8530)
2.55
2.3
3.0
2.75
3.5
3.25
4.0
3.75
0.1
4
0.25
3.85
3.25
WD_TCL
WD_TSV
WWD non-service time
(if factory enabled)
WWD Service – time
(if factory enabled)
2
RESET will not be generated
0-75
Max
2.95
2.7
3.4
3.15
3.9
3.65
4.4
4.15
0.4
0 -100 0-125
Units
V
V
V
V
V
V
V
V
V
µs
V
V ms
75-150 100-200 125-250 ms t
Res
Reset delay time
4ms, 16ms, 32ms (typ) are factory options
(min = -25% and max = +50% of typical)
6 8 12 ms
T shd
Temporary shutdown reset active time 0.1
1 s
1. These are factory options which could be made available on specific request.
2. -40%, -20%, +20%, +60%, and +100% timings are available as factory options.
www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6.7 Two Port Serial Interface
Symbol
General
BR
2WIRE_SPI
T
ENSCLK_H
T
ENSCLK_L
Write timing
t
DI_SU t
DI_HD
Read timing
t
DO_S t
DO_HD t
DO_D
Parameter
Bit rate
Clock high time
Clock low time
Data in setup time
Data in hold time
Data out setup time
Data out hold time
Data out delay
Conditions
t
DI_HZ
Data in to high impedance delay
Timing parameters when entering 2-Wire SP mode
T tx_su
T tx_hd
T tx_SP_trigger
T
STNDY_trigger
TX setup time before EN goes Low
TX hold time after EN goes High
EN falling edge to TX falling edge
TX high time from EN falling edge
T en_ENSCLK
EN falling edge to start of 2-wire serial port clock
Time for the Microcontroller to release the TX bus
To enter into 2-Wire SP mode
To enter into Sleep/Standby mode
Min
20
10
2
2
130
135
2
5
20
20
5
Typ Max Units
250 Kbps
µs
µs ns ns
80
80
10 ns ns
µs cycles cycles ns ns ns ns www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The AS8530 chip consists of a low drop-out regulator and a LIN bus transceiver, which is a bi-directional bus interface for data transfer between
LIN bus and the LIN protocol controller. Additionally integrated is a RESET unit with a power-on-reset delay and a programmable window watchdog. It also includes a watchdog time-out on LIN TX node to indicate if the microcontroller is stuck in a loop and to release unintentional
LIN bus dominant state.
7.1 Voltage Regulator (LDO)
The voltage regulator has three operating modes. The features of the operating modes are given below:
Normal mode:
Stability to be better ±0.25V over input range and temperature for load current up to 50mA. The LDO Output provides a voltage of 5V or 3.3V as OTP option.
Standby mode:
The Standby mode is a low quiescent current mode used in car applications that are always switched on. The load current in standby mode is 5mA. Quiescent current (no load) is less than 45mA typically at room temperature.
Sleep mode:
Power down or temporary shutdown of the regulator can be set by a register bit. This bit can be written through 2-wire MCU interface.
The LDO takes the input from bandgap and scales it up to the required voltage. The LDO starts charging only after the POR-V
SUP
event occurs
(RESET_VSUP_N switched from low to high). The LDO can be powered-down by a control signal (temporary shutdown register) for the temporary shutdown mode.
7.2 Temperature Limiter
Temperature limiter produces a power down when temperature exceeds 155ºC ±10%. It powers up and generates a reset when it returns to
135ºC ±10% junction temperature. During thermal shut down, temperature sensor is supplied by V
SUP
. During the temperature ramp-up phase, as soon as the temperature exceeds 135ºC ±10%, a warning signal is issued and is written into the diagnostic register, which can be read through the SP interface.
7.3 V
SUP
Undervoltage Reset
V
SUP
undervoltage reset generates a reset RESET_VSUP_N, switched from low to high when V
SUP
ramps up above VSUVR_OFF. This is used to enable proper initialization of mode control and diagnostic registers. If V
SUP
< VSUVR_ON, then RESET_VSUP_N switches from high level to low level (active). This is considered to be the master reset and will have the highest priority over all other signals. As soon as V
SUP
<
VSUVR_ON, the LDO, LIN Transceiver is completely shut off and system comes to a complete stop. AS8530 enters into the normal operating mode only after V
SUP
> VSUVR_OFF.
7.3.1 V
SUP
Undervoltage in Normal Mode
Supply Voltages below VSUVR_OFF and above VSUVR_ON do not influence the voltage regulator. The output voltage V
CC
follows V
SUP
.
7.3.2 V
SUP
Undervoltage in Standby Mode / Sleep Mode
No exit from the sleep mode or standby mode take place if the V
SUP
voltage drops down to VSUVR_OFF. If V
SUP
goes below VSUVR_ON,
RESET_VSUP_N is active and resets the mode control and diagnostic register. The voltage regulator, LIN Transceiver modules are turned off. If
V
SUP
rises again above VSUVR_OFF, RESET_VSUP_N is switched from low to high. The system enters normal mode where LIN Transceiver and LDO are switched on.
7.3.3 V
SUP
Undervoltage in Low Slew Mode
The behavior of AS8530 at low V
SUP
voltages is equal to the sleep mode. The low slew mode (set by control register through serial interface as an option) will be cancelled, if V
SUP
drops below VSUVR_ON in this mode. The AS8530 enters the normal mode, if V
SUP
rises again above
VSUVR_OFF.
www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
13 - 32
AS8530
Datasheet (discontinued) - D e t a i l e d D e s c r i p t i o n
7.4 RESET
Reset generates an external RESET signal to reset the microcontroller and all other external circuits. The reset functionality is illustrated in
V
CC
) and Window watchdog output. All those conditions which cause a drop in the V
CC
voltage will be detected from the low voltage reset unit, which in-turn generates a reset signal. States like Temporary shut-down, Over-temperature monitor will influence the RESET output through
RESET_VCC_N signal only.
Figure 4. Reset Functionality
VSUP
VCC
VUVR_OFF
VUVR_ON t
Res
RESET
T>Tj T<Tj t rr t
Res t<t rr t
Res
MISSING
WATCHDOG
ACCESS t
Res
Initialization
Thermal shutdown Spike VSUP Low voltage VSUP t
Res
Current limitation active
7.5 V
CC
Undervoltage Reset
The POR-VCC generates RESET_VCC_N signal as output which determines under-voltage reset of the output of the LDO. The rising edge of the V
CC
gives an under-voltage reset “off” and the falling edge of the V
CC
gives an under-voltage reset “on”. This under-voltage signal is used to control the RESET output. When V
CC
rises up Vuvr_off for a period greater than reset duration (tRes) then RESET_VCC_N switches from low level to high level and pin RESET is inactive (high). If V
CC
falls below Vuvr_on for a period greater than a predetermined delay (trr) then
RESET_VCC_N switches from high level to low level and pin RESET is active (low). The RESET_VCC_N signal is used to initializes Window watchdog timer, TX time-out, Test control circuits, 2-wire SP, and logic associated with SP (everything other than the SP control registers). V
CC under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface.
7.6 Window Watchdog (WWD)
To keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. The WWD trigger is generated by external MCU through SP interface. If the window is missed, a reset on the RESET pin with certain reset time (t
Res
) is generated. The WWD function can be enabled or disabled by factory setting. The watchdog is started after the ASSP exits reset. Under normal working conditions, microcontroller gives a WWD trigger every time in the window period of WD_TSV (service time). If the trigger does not occur during WD_TSV or occurs too early during WD_TCL (non-service time), then RESET output is pulled low (active), which will reset the micro-controller. WWD circuit is turned on after the RESET pin goes back to high (inactive). If V
CC
< Vuvr_on, WWD circuit is switched off. When the WWD function is enabled, there is a 3-bit factory programming available to set the trigger window.
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Figure 5. Window Watchdog Trigger
Period
Non-Service time (WD_TCL)
Trigger restart period
50 %
Service time (WD_TSV)
100 %
Trigger via SPI
Last trigger point
Unwanted trigger point
(System will be RESET)
Earliest possible trigger point
(System will not RESET)
Latest possible trigger point
(System will not be RESET)
Valid Trigger point
(System will not be RESET)
7.7 LIN Transceiver
The transceiver provides short circuit limitation, hardware watchdog and over temperature shut down features. The TX watchdog timer is active when TX is pulled low (active). As soon as the TX watchdog timeout occurs, the LIN bus is released from dominant state to recessive state. The
LIN transceiver has a pull-up resistor (for the slave node; extra resistor externally for the master node) to the V
SUP
. A diode protection is available to protect it from back supply from bus line.
The LIN transmitter has the basic functionality of relaying the data from the micro-controller on to the LIN. The data on the LIN needs to have controlled slew to have reduced EMI. The receiver relays the data from the LIN to the micro-controller. This transmitter has optimized EMC performance across different loading conditions conforming to the LIN 2.1 standards. The wake-up detects a wake up event on the LIN.
7.8 Operating Modes and States
The AS8530 provides four main operating modes “normal”, “sleep/stand-by” (programmed by OTP), “temporary shutdown” and “thermal shutdown”. The LIN transceiver can be programmed to operate with lower slew in the normal mode. Refer to
for a detailed description on transition for each mode.
7.8.1 Normal Mode
This is the mode after the power-up. In normal mode, LDO, LIN Transceiver, Window Watchdog, Resistive divider and the line drivers are all turned on. All the blocks are completely functional. LDO is now capable of delivering maximum load current possible as per the device specifications. The LIN Transceiver is capable of sending the TX data from microcontroller to the LIN bus at a maximum rate of 20Kbps. EN signal is set to high and LIN, TX, RX pins can be driven into dominant (low) or recessive (high) states. If the junction temperature increases more than T otset
, a warning flag is set in the diagnostic register, which can be read through the 2-wire interface.
7.8.2 Standby Mode
Standby mode is a functional low-power mode where LIN Transceiver is disabled. The LIN wake-up circuit and over-temperature monitor circuit is enabled. Window watchdog, TX timeout watchdog, Resistive divider, relay driver circuits are disabled. EN pin held low in this mode. TX pin is in recessive state (high). CS is pulled to V
CC
while SDI and SCLK outputs are pulled to VSS.
7.8.3 Sleep Mode
As a factory programming option on request the AS8530 offers as a replacement to the standby mode with sleep mode. Sleep mode is the most current saving mode. If EN is held low, the LDO, LIN Transceiver and the reset and window watchdog unit will be switched off. V
CC
is pulled down to zero. The LIN wake-up circuit, oscillator and over-temperature monitor circuit is active. LIN bus is in recessive state (high). Only wakeup possible is through remote wake-up, through LIN pin, pulling it to dominant state for 100µs typical (low), can change the state of the system. www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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Datasheet (discontinued) - D e t a i l e d D e s c r i p t i o n
7.8.4 Temporary Shutdown Mode
In this mode, the V
CC
is pulled down and the LDO is powered down. This mode is introduced to interface with other components which do not have a pin for the reset functionality. This provides an alternative way to reset those components interfacing with AS8530. This mode is default disabled but can be enabled by an OTP option. In this mode, all internal modules supplied by the LDO are disabled. Only the oscillator, control registers are enabled. The V
CC
output can be temporarily switched off and pulled to VSS. EN signal, RX, TX is pulled low and LIN Transceiver along with the LIN wake-up circuit is powered down. No remote wake-up functionality is possible. LIN bus enters into recessive state. The system goes out of this mode to normal mode after the time-out of an internal counter delay (T shd
). Normal mode to temporary shutdown transition will be controller by register bit in configuration register.
7.8.5 Thermal Shutdown State
If the junction temperature T
J
is higher than T sd
, the AS8530 will be switched into the thermal shutdown mode. The transceiver is completely disabled. No wake-up functionality is available. Window watchdog, TX timeout watchdog, and LDO are completely turned off. Only the overtemperature monitor would be working. As soon as the temperature returns back to T ret
, the system enters normal mode. For more information on transition, see
.
Table 3. Transition Table
Transition
From mode To mode LIN
Interface
RX TX EN
Reg.
0x05
D0 rwake Uvbat
Flags
OT Uvcc
Comments
Normal
Mode
Stand-By
Sleep
1
Temporary
Shutdown
X-RS
X-RS
X-RS
X-H
2
X-H
2
X-H
2
H
3
H
3
X
H-L
3
H-L
3
H
3
L
L
H
X
X
X
X
X
X inactive inactive inactive inactive set set
TX is high for
T
STNDY_triggerr
TX is high for
T
STNDY_triggerr
1
The Control Bit is set through the 2-Wire SP interface
Over-
Temperature
X-RS
X-H
2
X X L X X set set
Normal (LW) X
H-X
2
X
L-H
3
L X X inactive inactive
Stand-By
Mode
Normal (RW)
Temporary
Shutdown
X
RS
H-X
2
H
2
H
H
X
L
L
H
3 set
X
X
X inactive inactive inactive set
Remote Wake up
Event occurred on LIN
The Control Bit is set through the 2-Wire SP interface
Over-
Temperature
RS
H
2
H L L X X set set
Temporary
Shutdown
Mode
Normal RS-X
H-X
2
X X L X X inactive clear
Internal 128ms timer expired
Sleep Mode
3
Normal
Over-
Temperature
RS-X
RS
H-X
2
H
2
X
X
X
X
L
L set
X
X
X inactive set clear hold
Remote Wake up
Event occurred on LIN
Temperature monitor output asserted
(covered by scan)
All States Power Off X X X X X X
L-H
3
X X
1. Chosen by factory programming option
2. Effect of Transition
3. Cause for Transition
Note:
L = low state, H = high state, OT = Over-temperature Reset, Uvcc = Undervoltage V
CC
, Uvbat = Undervoltage VBAT, rwake =remote wake, X = do not care.
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7.9 State Diagram
other “wait” states have been included for the sake of completeness.
Figure 6. Finite State Machine Model for the AS8530 System
Temperature < Tret
INIT0
Vsup > Vsuvr_off
OTP LOAD OVTEMP
otp_load
Temperature > Tsd
Temperature > Tsd
Temperature > Tsd
Temporary
Shutdown
SLEEP
128msec
RESET TIMEOUT
Tem shutd porary
RESET time > t
RES rwake
Standby & sleep
NORMAL
Vcc < Vuvr_on || wwdtimeout test_en
RX=0
RX=0 otp_e n
Temperature > Tsd
Temperature > Tsd
Temperature > Tsd m shu
Tem tdow porar n y
! sta ndb y stan dby
Vcc < Vuvr_on
STANDBY
shu tdo
Te m wn po rary rw ak e_ wa it
STANDBY WAIT
Vcc < Vuvr_on
Vcc < Vuvr_on || wwdtimeout
TXWD WAIT
Temperature > Tsd
WAIT_TEST
WAIT_OTP www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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8 Application Information
8.1 Initialization
When the power supply is switched on, if V
SUP
> VSUVR_OFF, RESET_VSUP_N becomes inactive (high). After this, the voltage regulator starts with a default LDO output setting of 3.3V and Vuvr_off setting of 2.75V. If V
CC
> Vuvr_off (2.75V), active-low PORN_2_OTP is generated.
The rising edge of PORN_2_OTP loads contents of fuse onto the OTP latch after load access time T
Load
. LOAD_OTP_IN_PREREG signal loads contents of OTP latch onto the pre-regulator domain register. This register gives actual settings of LDO, Vuvr_off and Reset Timeout period T
Res
.
This is done because the OTP block is powered by the V
CC
. If V
CC
> Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is deasserted after Reset Timeout period T
Res
(phase 2) and then device enters into normal mode. The circuit initializes correctly also for very slow ramp on V
SUP
(of the order of 0.5V/min).
Figure 7. Initialization Sequence for AS8530
Vsuvr_off
VSUP
RESET_VSUP_N
Device
Settings
LDO
Off
PHASE 1
LDO On
Vuvr_off = 2.75V, LDO setting = 3.3V
t
RES
= 4msec
PHASE 2
LDO On
Vuvr_off = from OTP Block, LDO setting = from OTP Block t
RES
= from OTP Block
Vuvr_off
VCC
RESET_VCC_N
PORN_2_OTP
LOAD_OTP_IN_PREREG
RESET
Vuvr_off
6 Cycles of
RC-Oscillator
If Phase 1 POR threshold != Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
If Phase 1 POR threshold == Phase 2 POR threshold
Tres = Reset Timeout from OTP Block www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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Table 4. V
SUP
>Vsuvr_on and
V
CC
<Vuvr_on
Block
TRANSCEIVER = Enabled (disabled only during initial V
SUP
ramp-up)
LDO = Enabled (disabled only during initial ramp-up)
RELAY DRIVER = Enabled
RESET = Enabled
RESISTIVE DIVIDER = Enabled
Table 5. V
SUP
<Vsuvr_on
Block
TRANSCEIVER = Disabled
LDO = Disabled
RELAY DRIVER = Disabled
RESET = Disabled
RESISTIVE DIVIDER = Disabled
Output Signal
LIN = high-z, RX = follows V
V
CC
= low
LDRIVE1 = high, LDRIVE2 = high
RESET = high-z
VBAT= high, VBAT_DIV = enabled
Output Signal
LIN = high-z, RX = high-z
V
CC
= low
LDRIVE1 = high, LDRIVE2 = high
RESET = high-z
VBAT = high, VBAT_DIV = low
8.2 Wake-Up
If the regulator is put into sleep/standby mode, it can be woken up with the BUS interface. A transition on the BUS (high to low) with a minimum predefined low time (t wake
) puts the regulator into normal mode.
8.3 Over-Temperature Shutdown
If the junction temperature increases beyond T sd
the over-temperature recognition will be activated and the regulator voltage will be switched off.
The V
CC
voltage drops down, the reset state is entered and the bus transceiver is switched off (recessive state). After T
J
falls below T ret
, the
AS8530 will be initialized again. This initialization starts independently from the voltage levels on EN and BUS. Within the thermal shutdown mode, the transceiver cannot switch to the normal mode either with local or with remote wake-up. The operation of the AS8530 is possible between T
J
(125ºC) and the switch off temperature T sd
, but small parameter differences can appear. After over-temperature switch-off, the IC
initializes as explained in Initialization on page 18
. The low slew mode for LIN Transceiver has to be selected again on re-initialization, if necessary.
8.4 LIN BUS Transceiver
The AS8530 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed by a de-bouncing unit.
8.4.1 Transmit Mode
During transmission the data at the pin TX will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.
Transmitting will be interrupted in the following cases:
Sleep mode
Thermal Shutdown active
Master Reset (V
SUP
< Vsuvr_on)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse current of VBUS during differential voltage between V
SUP
and BUS (VBUS>V
SUP
). No additional termination resistor is necessary to use the
AS8530 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k Ω resistor in series with a diode to VBAT.
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8.4.2 Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the implemented de-bouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*V
SUP
and 0.6*V
SUP
will be securely observed.
Figure 8. Receive Mode Impulse Diagram
BUS
60%
50%
40%
V thr_max
V thr_hys
V thr_min
V thr_cnt t < t deb_BUS
RX
t < t deb_BUS
8.5 RX and TX Interface
Input TX.
The 5V input TX controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on TX leads to the
LIN bus being pulled low (dominant state) too. The TX pin has an internal active pull up connected to V
CC
. This guarantees that an open TX pin generates a recessive BUS level.
Figure 9. TX Input Circuitry
MCU
VCC
I
PU_TXD
TX
VCC
RC-Filter
(10ns)
AS8530
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Datasheet (discontinued) - A p p l i c a t i o n I n f o r m a t i o n
Output RX.
The received BUS signal will be output to the RX pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys → RX = low
BUS > Vthr_cnt + 0.5 * Vthr_hys → RX = high
This output is a push-pull driver between V
CC
and GND with an output current of 1mA.
Figure 10. RX Output Circuitry
AS8530
VCC
RX
MCU
8.6 MODE Input EN
The AS8530 is switched from normal mode to the standby/sleep mode with a falling edge on EN and keeping TX high for T
STNDY_trigger
time.
Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for AS8530 with a falling edge at EN can be done independently from the state of the bus transceiver. Device enters into Serial port mode by forcing EN low and driving TX high to low within T tx_SP_trigger
time after EN forced to low.
This ensures the direct control of device to enter into Standby/Sleep mode by microcontroller using EN pin.
Figure 11. EN Pin Functionality
Entry into Serial
Port Mode
T en_ENSCLK
EN
TX
T tx_su
Normal
Mode
T
STNDY_trigger
T tx_hd
Standby/Sleep
Mode
T tx_su
Normal Mode
RD
WR
LEN
1
LEN
0
A4
T tx_SP_trigger
D3 D2 D1 D0
Serial Port Mode Normal Mode
The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
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Figure 12. Enable Controlled via. MCU
V
BAT
EN
VSUP
LIN
VSS
VCC
RESET
TX
RX
C load
+
+ 5V
MCU
If the application doesn’t need the wake up capability of the AS8530, a direct connection EN to V
CC
is possible. In this case the AS8530 operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via. V
SUP
signal as shown below.
Figure 13. Permanent Normal Mode
V
BAT
EN
VSUP
LIN
VSS
VCC
RESET
TX
RX
C load
+
+ 5V
MCU
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AS8530
Datasheet (discontinued) - A p p l i c a t i o n I n f o r m a t i o n
8.7 Serial Port Interface
The interface is essentially used to trigger the window watchdog, to access test mode and read out diagnostic information for the AS8530. The description of this interface and the protocol is explained below. Information on block status and errors can be displayed by diagnosis registers.
8.7.1 Device Configuration using 2-Wire Serial Port
The AS8530 device configuration register is programmed via a 2-wire Serial Programming Interface. EN/SCL is used as Serial Clock and TX/
SDA_IO is used as Serial Data. EN is used as clock input to access serial port registers in serial port mode. Also EN is used to control transition from normal mode to standby/sleep mode. The TX input of the device will be multiplexed as following:
LIN TX for transmitting data from microcontroller on LIN bus
SDA_IO for Serial data input/output, this will be used for serially accessing data from configuration and status register
SP Frame.
A frame is formed by first byte for command and address/configuration and following bit stream that can be formed by an integer number of bytes. Command is coded RD/WR on the first bits, length of the transfer is indicated by LEN1, LEN2 bits while address is given on
LSB 5 bits.
Table 6. Command Bits
RD/WR
Command Bits
LEN1 LEN2 A4
Register Address or Transmission Configuration
A3 A2 A1 A0
RD/WR
0
1
Command
WRITE
READ
<A4:A0>
ADDRESS
ADDRESS
Description
Writes data byte on the given starting address.
Read data byte from the given starting address.
Table 7. Transfer Length
LEN1 LEN2 Length
0
0
1
1
0
1
0
1
1
2
4
8
Description
Transfer consists of single Data phase. After completion of single Data phase device comes out of Serial port interface.
Transfer consist of two Data phase.
Transfer consist of four Data phase.
Transfer consist of eight Data phase.
Write Command.
For Write command RD/WR = 0
After the command code, length of the transfer is send in next two bits, the address of register to be written has to be provided from the MSB to the LSB. Then one, two, four, or eight data bytes can be transferred from the MSB to the LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the 2-Wire SP master on the SP clock (EN pin) positive edge and the 2-Wire SP slave (device) samples this bit on the next SP clock (EN pin) negative edge. In the following figures two examples of write command (without and with address self-increment).
Figure 14. Protocol for Serial Data Write with Length = 1
EN
TX 0
LEN1 LEN0
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Command & Address Phase
Data Phase
LEN1 = 0 LEN0 = 0
Length of Transaction = 1
Transfer edge Sampling edge
Data D7 – D0 is moved to Address A4..A0 here www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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Figure 15. Protocol for Serial Data Write with Length = 4
EN
TX
1 1 0
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
LEN1 LEN0
Command & Address
Phase
LEN1 = 1 LEN0 = 0
Length = 4
Data1 Phase
Data2 Phase
Data D7-D0 is moved to Address
A4-A0 here
Data D7-D0 is
A4-A0 + 1 here
Data3 Phase moved to Address
Data4 Phase
Data D7-D0 is moved to Address
A4-A0 + 2 here
Data D7-D0 is moved to Address
A4-A0 + 3 here
Read Command.
For Read command RD/WR=1.
After the command code, length of the transfer is send in next two bits, the address of register to be read has to be provided from the MSB to the
LSB. Then one, two, four or eight data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB.
Each bit of the command and address sections of the frame have to be driven by the 2-Wire SP master on the SP clock (EN pin) positive edge and the 2-Wire SP slave (device) samples this bit on the next SP clock (EN pin) negative edge. Each bit of the data phase of the frame has to be driven by the 2-Wire SP slave (device) on the SP clock (EN pin) positive edge and the 2-Wire SP master samples this bit on the next SP clock
(EN pin) negative edge. The following figures illustrate two examples of read command (without and with address self-increment.)
Figure 16. Protocol for Serial Data Read with Length = 1
EN
TX
0 LEN1 LEN0 A4 A3 A2 A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
Command & Address Phase
Transfer edge Sampling edge
Data D7 – D0 at address A4 ..A0 is read here
Data Phase
LEN1 = 0 LEN0 = 0
Length of Transaction = 1
Transfer edge Sampling edge www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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Figure 17. Protocol for Serial Data Read with Length = 4
EN
TX 1 1 0
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
LEN1 LEN0
Command & Address
Phase
LEN1 = 1 LEN0 = 0
Length = 4
Data1 Phase
Data D7-D0 at
Address A4-A0 is read here
Data D7-D0 at
Address A4-A0 +1 is read here
Data2 Phase Data3 Phase
Data D7-D0 at
Address A4-A0 +2 is read here is read here
Data4 Phase
Data D7-D0 at
Address A4-A0 +3
Data D7-D0 at
Address A4-A0 +4 is read here
Timing.
The following figures illustrate timing waveforms and parameters.
Figure 18. Timing for Writing
T
ENSCLK_H
T
ENSCLK_L
EN
TX
T
DI_SU
T
DI_HD
DATAI DATAI
Figure 19. Timing for Reading
EN
TX
T
ENSCLK_H
T
ENSCLK_L
T
D0_D
T
DI_SU
T
DI_HD
DATAI
T
DI_HZ
DATAO
T
D0_D
DATAO www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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8.8 Control and Diagnosis Registers
The serial interface can be used as interface between the ASSP AS8530 and an external micro-controller. The interface is a slave and only the micro-controller can start the communication. This interface will be used for device configuration, entering into test mode and carrying out
diagnostic options. Refer to Table 8
for details on the configuration registers.
8.8.1 Definition of Control and Status Registers
A total of 32 control, diagnosis and test registers, each of 8-bit can be accessed using the 2-wire serial interface.
provides a description of all control and status registers.
Table 8. Configuration Registers
Address Register Name
Control and Configuration Register
POR Value RD / WR Description
0 x 03
Device Configuration
Register
On
POR_VCC
0000_1111
RD / WR
D0 Reserved
D1 Reserved
D2 Reserved
D3 Enable / Disable LIN Transceiver
0 Disabled
1 Enabled
D7…D4 Reserved
0 x 04 Device Control Register On
POR_VSUP
0000_0001
RD / WR D7... D1 Reserved
0 x 05
0 x 06
Temporary Shutdown
Register
Window Watch Dog
Trigger Register
On
POR_VCC
0000_0000
On
POR_VCC
0000_0000
RD / WR
WR
D0 Temporary shutdown control bit
0 No Temporary shutdown
1 Enter into Temporary shutdown
D7…D1 Reserved
D0 Window Watch Dog Trigger
This bit will be set by MCU to indicate trigger event. If this trigger occurs outside the Window of Watch dog counter, then RESET signal is asserted. Also on this trigger WWD counter is restarted and this bit will be cleared internally within 2 cycles of 128KHz clock.
D7 … D1 Reserved
0 x 07
Low Side Driver Data
Register
On
POR_VCC
0000_0000
RD / WR D7 … D0 Reserved www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - A p p l i c a t i o n I n f o r m a t i o n
Table 8. Configuration Registers
Address Register Name
Diagnosis Register
POR Value RD / WR Description
0 x 08
0 x 09
Diagnostic Register 1
Diagnostic Register 2
On
POR_VSUP
0000_0011
On
POR_VSUP
0000_0000
RD
RD
D7..D0 = DR[7:0] 8 LSB bits of the 24 bit Diagnostic Register
D0 PORVSUP (set when VSUP < Vsuvr_on, cleared after µC read)
D1 UVVCC Under voltage VCC (set when VCC < Vuvr_on, cleared after µC read)
D2 OTEMP160 Over-temperature Reset. (set when temp > T sd
, cleared after µC read)
D3 OTEMP140 Over-temperature warning (set when temp > T otset
, cleared after µC read)
D4 OVVBAT Overvoltage VBAT. (set when VSUP > Vovthh, cleared after µC read)
D5 Reserved
D6 RWAKE Remote Wakeup (set on Remote Wakeup event on LIN
Bus, cleared after µC read)
D7 WWDT Window watchdog timeout. (set on failure of Window watchdog timeout, cleared after µC read)
D7..D0 = DR[15:8] next 8 LSB bits of the 24 bit Diagnostic
Register.
D0 TXTIMEOUT Tx timeout of 1sec. (set on TX low > 1sec, cleared after µC read)
D1 TEMPSHUT this bit is set on entering into temporary shutdown state and cleared after µC read.
D7 D2 Reserved
Note:
When the device is powered ON @ ambient temperature of 125ºC, the status of the OVTEMP140 can be HIGH indicating an over temperature warning. This is because 125ºC is within the limits for the OVTEMP140.
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AS8530
Datasheet (discontinued) - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The device is available in a ep-SOIC8 package.
Figure 20. Drawings and Dimensions
YYWWIZZ
AS8530
*
*
The device marking for the VCC=5V option will change to
AS8530A
.
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AS8530
Datasheet (discontinued) - P a c k a g e D r a w i n g s a n d M a r k i n g s
Symbol
A
A1
A2 b c
D
D1 e
L
E
E1
E2
Min
-
0.00
1.25
0.31
0.17
-
2.24
-
-
1.55
-
0.41
Nom
-
-
-
-
-
4.90 BSC
3.10
6.00 BSC
3.90 BSC
2.41
1.27 BSC
0.64
Max
1.70
0.15
-
0.51
0.25
-
3.20
-
-
2.51
-
0.89
Notes:
1. Dimensions and tolerancing conform to
ASME Y14.5M -1994
.
2. All dimensions are in miilimeters. Angles are in degrees.
3. Datums A and B to be determined at datum H.
4. Extrusion of exposed area in bottom side is 0.20mm typical.
Marking: YYWWIZZ.
YY
Last two digits of the manufacturing year
WW
Manufacturing Week
Symbol
L1
L2 h
θ aaa bbb ccc ddd eee fff
N
I
Plant Identifier
-
-
-
-
-
-
Min
-
-
0.25
0º
Nom
1.04 REF
0.25 BSC
-
-
0.10
0.20
0.10
0.25
0.10
0.15
8
ZZ
Traceability Code
-
-
-
-
-
-
Max
-
-
0.50
8º www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - R e v i s i o n H i s t o r y
Revision History
Revision
1.0
1.1
1.2
Date
26 Nov, 2010
29 Nov, 2010
03 Jun, 2011
Dec 31, 2012
Jul 03, 2017
Owner
mbl kpt mbl sju
Note:
Typos may not be explicitly mentioned under revision history.
Description
Initial release
Marking details updated under Ordering Information.
Updated Package Drawings and Markings, Ordering Information.
Updated ordering table.
Update of document status
Update of Ordering Information section by adding NRND statement www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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AS8530
Datasheet (discontinued) - O r d e r i n g I n f o r m a t i o n
10 Ordering Information
The devices are available as the standard products shown in Table 9 .
Table 9. Ordering Information
1
Ordering Code
AS8530-ASOP
AS8530-ASOM
Description
LIN Transceiver with Integrated Voltage Regulator and
MCU Interface (3.3V Version)
2
Delivery Form
Tape and Reel (2500 pcs)
Tape and Reel (500 pcs)
Package
SOIC-8
SOIC-8
1. For both product versions, the RESET delay time t
Res
as well as undervoltage threshold are set to default value and window watchdog is disabled. On special request, optional factory settings can be made available on specific vendor addendum.
2. Also available as 5V version.
Note:
All products are RoHS compliant and ams green.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
For further information and requests, email us at [email protected]
(or) find your local distributor at www.ams.com/distributor
Not Recommended for New Designs!
ams AG is discontinuing production of this device. Final lifetime buy order must be placed by DECEMBER 31, 2017.
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AS8530
Datasheet (discontinued) - C o p y r i g h t s
Copyrights
Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel : +43 (0) 3136 500 0
Fax : +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.ams.com/contact www.ams.com/Lin_CompanionIC/AS8530 Revision 1.2
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