STMicroelectronics L99PM62XP Datasheet

L99PM62XP

Power management IC with LIN and high speed CAN

Features

■

■

■

■

■

■

■

■

■

■

■

■

■

■

■

■

Two 5V voltage regulators for microcontroller and peripheral supply

No electrolytic capacitor required on regulator outputs

Ultra low quiescent current in standby modes

Programmable reset generator for power-on and undervoltage

Configurable window watchdog and fail safe output

LIN 2.1 compliant (SAEJ2602 compatible) transceiver

Advanced HS CAN transceiver (ISO 11898-2/-

5 and SAE J2284 compliant) with local failure and bus failure diagnosis

HS CAN transceiver supports partial networking

Complete 3 channel contact monitoring interface with programmable cyclic sense functionality

Programmable periodic system wake up feature

ST SPI interface for mode control and diagnosis

5 fully protected high-side drivers with internal

4-channel PWM generator

2 low-side drivers with active zener clamping

4 internal PWM timers

2 operational amplifiers with rail-to-rail outputs

(V

S

) and low voltage inputs

Temperature warning and thermal shutdown

Applications

■ Automotive ECU's such as door zone and body control modules

PowerSSO-36

Description

The L99PM62XP is a power management system

IC providing electronic control units with enhanced system power supply functionality including various standby modes as well as LIN and HS CAN physical communication layers. It contains two low drop voltage regulators to supply the system microcontroller and external peripheral loads such as sensors and provides enhanced system standby functionality with programmable local and remote wake up capability.

In addition, five high-side drivers, two low-side drivers and two operational amplifiers increase the system integration level.

The ST standard SPI interface (3.0) allows control and diagnosis of the device and enables generic software development.

Table 1.

Package

Device summary

Order codes

Tube Tape and reel

PowerSSO-36 L99PM62XP L99PM62XPTR

September 2013 Doc ID 16363 Rev 4 1/98 www.st.com

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Contents

Contents

L99PM62XP

Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1

Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

Voltage regulator: V

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Voltage regulator: V

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Increased output current capability for voltage regulator V

2

. . . . . . . . . 13

Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Voltage regulator behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Timer interrupt / wake-up of microcontroller by timer . . . . . . . . . . . . . . . 19

2.3

Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4

Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.1

Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5

Fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.5.1

Single failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.6

Reset output (NRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.7

Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.8

LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.8.1

2.8.2

2.8.3

Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LIN pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.9

High speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.9.1

2.9.2

2.9.3

CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Wake up (from CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

CAN sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/98 Doc ID 16363 Rev 4

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2.9.4

2.9.5

CAN receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

CAN looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.10

Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 33

Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1

Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1.1

3.1.2

Vs overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Vs undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 37

3.3

High-side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.4

Low-side driver outputs REL1, REL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.5

SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1

Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.4

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.1

PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Voltage regulator V

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Voltage regulator V

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.5.8

5.5.9

High-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.5.10

Wake up inputs (WU1... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.5.11

High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.5.12

LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.5.13

Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.5.14

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Doc ID 16363 Rev 4 3/98

Contents

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L99PM62XP

5.5.15

Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . 62

ST SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1

SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.1.7

6.1.8

6.1.9

Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . 70

Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . 72

6.1.10

Read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.1.11

Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.1

6.2.2

6.2.3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.2

PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4/98 Doc ID 16363 Rev 4

L99PM62XP

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Wake up sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Persisting fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9.

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 10.

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11.

Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 12.

Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 13.

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 14.

Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 15.

Voltage regulator V

1

Table 16.

Voltage regulator V

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 17.

Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 18.

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 19.

Output (OUT_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 20.

Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 21.

Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 22.

Wake up inputs (WU1... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 23.

CAN transmit data input: pin TXDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 24.

CAN receive data output: pin RXDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 25.

CAN bus common mode stabilization output termination: pin SPLIT . . . . . . . . . . . . . . . . . 54

Table 26.

CAN transmitter and receiver: pins CANH and CANL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 27.

CAN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 28.

LIN transmit data input: pin TXD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 29.

LIN receive data output: pin RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 30.

LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 31.

LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 32.

LIN pull-up: pin LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 33.

Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 34.

Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 35.

Input CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 36.

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 37.

DO output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 38.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 39.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 40.

Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 41.

Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 42.

Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 43.

Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 44.

Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 45.

Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 46.

Write command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 47.

Write command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 48.

Write command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Doc ID 16363 Rev 4 5/98

List of tables L99PM62XP

Table 49.

Format of data shifted out at SDO during write cycle: global status register . . . . . . . . . . . 70

Table 50.

Format of data shifted out at SDO during write cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 70

Table 51.

Format of data shifted out at SDO during write cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 70

Table 52.

Read command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 53.

Read command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 54.

Read command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 55.

Format of data shifted out at SDO during read cycle: global status register. . . . . . . . . . . . 72

Table 56.

Format of data shifted out at SDO during read cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 72

Table 57.

Format of data shifted out at SDO during read cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 72

Table 58.

Read and clear status command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 59.

Read and clear status command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 60.

Read and clear status command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 61.

Format of data shifted out at SDO during read and clear status: global status register . . . 73

Table 62.

Format of data shifted out at SDO during read and clear status: data byte 1. . . . . . . . . . . 73

Table 63.

Format of data shifted out at SDO during read and clear status: data byte 2. . . . . . . . . . . 73

Table 64.

Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 65.

ID-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 66.

Family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 67.

Silicon version identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 68.

SPI-frame-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 69.

SPI register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 70.

SPI register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 71.

SPI register: CTRL register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 72.

SPI register: STAT register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 73.

Overview of control registers data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 74.

Control register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 75.

Control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 76.

Control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 77.

Control register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 78.

Control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 79.

Control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 80.

Control register 3: command data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 81.

Control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 82.

Control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 83.

Control register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 84.

Control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 85.

Control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 86.

Control register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 87.

Control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 88.

Control register 5, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 89.

Control register 6: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 90.

Control register 6, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 91.

Control register 6, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 92.

Overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 93.

Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 94.

Status register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 95.

Status register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 96.

Status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 97.

Status register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 98.

Status register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 99.

Status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 100.

Status register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6/98 Doc ID 16363 Rev 4

L99PM62XP List of tables

Table 101.

Status register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 102.

Status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 103.

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 104.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Doc ID 16363 Rev 4 7/98

List of figures

List of figures

L99PM62XP

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2.

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3.

Voltage source with external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4.

Voltage source with external PNP and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

Voltage source with external NPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

Voltage source with external NPN and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

Voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8.

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9.

Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10.

Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11.

Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12.

Change watchdog timing within long open window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13.

Change watchdog timing within window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.

General procedure to change watchdog timing out of fail safe mode. . . . . . . . . . . . . . . . . 25

Figure 15.

Change watchdog timing out of fail safe mode (watchdog failure) . . . . . . . . . . . . . . . . . . . 25

Figure 16.

Example: exit fail safe mode from watchdog failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 17.

LIN master node configuration using LIN_PU (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 18.

CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19.

Over voltage and under voltage protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 20.

Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 21.

Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 22.

PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23.

PowerSSO-36 thermal resistance junction to ambient vs PCB copper area (V1 ON) . . . . 44

Figure 24.

PowerSSO-36 Thermal Impedance junction to ambient vs PCB copper area (single pulse with V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25.

PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 26.

Watchdog timing (long, early, late and safe window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 27.

Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 28.

LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29.

SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 30.

SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 31.

SPI output timing (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 32.

SPI output timing (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 33.

SPI – CSN low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 65

Figure 34.

Read configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 35.

Write configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 36.

Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 37.

Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 38.

Format of data shifted out at SDO during read and clear status operation . . . . . . . . . . . . 74

Figure 39.

PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8/98 Doc ID 16363 Rev 4

L99PM62XP

1

Block diagram and pin descriptions

Block diagram and pin descriptions

Figure 1.

Block diagram

9

V

9

9

15HVHW

&61

&/.

',

'2

7HPS3UHZDUQLQJ

6KXWGRZQ

8QGHUYROWDJH

2YHUYROWDJH

6KXWGRZQ

95(*

9P$

95(*

9P$

FKDQQHO

3:0*HQHUDWRU

7LPHU

7LPHU

63,

:LQGRZ

:DWFKGRJ

/,1

/,138

5['B/1,17

7['B/

/,1

6$(-

/,1FHUWLILHG

$*1'

/2*,&

+6&$1

,62

3*1'

+LJK6LGH

P$

+LJK6LGH

P$

+LJK6LGH

P$

+LJK6LGH

P$

+LJK6LGH

P$

:DNH8S,Q

:DNH8S,Q

:DNH8S,Q

/RZ6LGH

P$

2XWSXW&ODPS

/RZ6LGH

P$

2XWSXW&ODPS

5(/

5(/

23

23

23BRXW

23

23

23BRXW

287B+6

287

287

287)62

287

:8

:8

:8

&$16XSSO\

&$1B+

63/,7

&$1B/

7['B&

5['B&

$*9

Doc ID 16363 Rev 4 9/98

Block diagram and pin descriptions L99PM62XP

3

4

5

1

2

6

7

8

9

25

26

27

28

29

30

31

32

33

34

13

14

15

16

17

18

19

20…22

23

24

Table 2.

Pin

10

11

12

Pin definition

Symbol Function

AGND

RxDC

TxDC

CANH

CANL

Analog ground

CAN receive data output

CAN transmit data input

CAN high level voltage I/O

CAN low level voltage I/O

SPLIT CAN reference voltage output, CAN termination

CANSUP CAN supply input; to allow external CAN supply from V

1

or V

2

regulator.

NRESET Nreset output to micro controller; Internal pull-up of typ. 100 K Ω (reset state = LOW)

V

1

Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver

V

2

TxDL

Voltage regulator 2 output: 5 V supply for external loads (IR receiver, potentiometer, sensors) or CAN Transceiver. V

2

is protected against reverse supply.

LIN Transmit data input

RxDL/NINT

OP2+

RxDL -> LIN receive data output

NINT -> indicates local/remote wake-up events or provides a programmable timer interrupt signal

Non inverting input of operational amplifier 2

OP2Inverting input of operational amplifier 2

OP2_OUT Output of operational amplifier 2

DI SPI: serial data input

DO

CLK

CSN

SPI: serial data output

SPI: serial clock input

SPI: chip select not input

WU1…3 Wake-up Inputs 1to 3: Input pins for static or cyclic monitoring of external contacts

OP1_OUT Output of operational amplifier 1

OP1Inverting input of operational amplifier 1

OP1+ Non inverting input of operational amplifier 1

OUT4 High-side driver output (7

Ω

, typ)

OUT3/FSO Configurable as high-side driver output (7 Ω , typ) or fail safe output pin (default)

OUT2 High-side driver output (7

Ω

, typ)

OUT1

OUT_HS

High-side driver output (7 Ω , typ)

High-side driver (1 Ω , typ)

V

S

LINPU

Power supply voltage

High-side driver output to switch off LIN master pull up resistor

LIN

REL1

LIN bus line

Low-side driver output (2

Ω

typ)

10/98 Doc ID 16363 Rev 4

L99PM62XP Block diagram and pin descriptions

Table 2.

Pin

35

36

Pin definition (continued)

Symbol

REL2

PGND

Function

Low-side driver output (2

Ω

typ)

Power ground (REL1/2, LIN and CAN GND), to be externally connected to AGND

Figure 2.

Pin connection (top view)

$*1'

5['&

7['&

&$1+

&$1/

63/,7

&$1683

15(6(7

9

9

7['/

5['/1,17

233

230

23287

',

'2

&/.

3RZHU662

3*1'

5(/

5(/

/,1

/,138

9V

287B+6

287

287

287)62

287

233

230

23287

:8

:8

:8

&61

Note:

7$% $*1'

It is recommended to connect the PGND pin directly to the TAB.

$*9

Doc ID 16363 Rev 4 11/98

Description

2 Description

L99PM62XP

2.1.1

2.1.2

The L99PM62XP contains 2 independent and fully protected low drop voltage regulators, which are designed for very fast transient response and do not require electrolytic output capacitors for stability.

The output voltage is stable with ceramic load capacitors > 220 nF.

Voltage regulator: V

1

The V

1

voltage regulator provides 5 V supply voltage and up to 250 mA continuous load current and is mainly intended for supply of the system microcontroller. The V

1

regulator is embedded in the power management and fail-safe functionality of the device and operates according to the selected operating mode.

It can be used to supply the internal HS CAN Transceiver via the CANSUP pin externally. In case of a short circuit condition on the CAN bus, the output current of the transmitter is limited to 100 mA and the transceiver is turned off in order to ensure continued supply of the microcontroller.

In addition the regulator V

1

drives the L99PM62XP internal 5 V loads. The voltage regulator is protected against overload and overtemperature. An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. The output voltage precision is better than +/- 2% (incl. temperature drift and line-/load regulation) in active mode; respectively

+/- 3% during low current operation (i. e. in V

1 standby mode). Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors > 220 nF.

If the device temperature exceeds the TSD1 threshold, all outputs (OUTx, RELx, V

2

, LIN) is deactivated except V

1

. Hence the micro controller has the possibility for interaction or error logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V

1

is deactivated (see state chart in

Chapter 3: Protection and diagnosis ). A timer is started and the voltage

regulator is deactivated for t

TSD

= 1sec. During this time, all other wakeup sources (CAN,

LIN, WU1 to3 and wake up of µC by timer) are disabled. After 1 sec, the voltage regulator tries to restart automatically. If the restart fails 7 times, within one minute, without clearing and thermal shutdown condition still exists, the L99PM62XP enters the forced V

BAT

Mode.

standby

In case of short to GND at “V

1

” after initial turn on (V

1

< 2V for at least 4ms) the L99PM62XP enters the forced V

BAT standby Mode. Reactivation (wake-up) of the device can be achieved

with signals from CAN, LIN, WU1..3 or periodic wake by timer (see Section 2.2.8: Timer interrupt / wake-up of microcontroller by timer ).

Voltage regulator: V

2

The voltage regulator V

2

can supply additional 5 V loads (e.g. logic components or the integrated HS CAN transceiver or external loads such as sensors or potentiometers). The

12/98 Doc ID 16363 Rev 4

L99PM62XP

2.1.3

Description maximum continuous load current is 100 mA. The regulator provides accuracy better than

+ 3% at 50 mA (4 % at 100 mA and is protected against.

● Overload

●

●

●

Overtemperature

Short circuit (short to ground and battery supply voltage)

Reverse biasing

Increased output current capability for voltage regulator V

2

For applications which require high output currents, the output current capability of the regulator can be increased my means of the integrated operational amplifiers and an external pass transistor.

Figure 3.

Voltage source with external PNP

/30

9V

9

&

5

5E

5

23[B287

0-'&

9

&L

23[

23[

5

& &

&HP 5 5

$*9

Figure 4.

Voltage source with external PNP and current limitation

/30

9V

9

23[B287

&

5

5E

5

5

%&

0-'&

&L

9

23[

23[

5

& &

&HP 5 5

$*9

Figure 3 shows a possible configuration with a PNP pass element using voltage regulator 2

to provide the voltage reference for the regulated output voltage V3.

Doc ID 16363 Rev 4 13/98

Description L99PM62XP

The Vs operating range for this circuit is 5.5 V to 18 V. It is important the respect the input common mode range specified for the operational amplifiers.

The output voltage V3 can be calculated using the following formula: v

3

= v

------

2

⋅

R +

---------------------

R

2

R

[ ]

The circuit in

Figure 4 provides additional current limitation using an additional PNP

transistor and R6 which allows setting the current limit.

Figure 5.

Voltage source with external NPN

/30

9

9V

&

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Voltage source with external NPN and current limitation

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Figure 5 shows a possible configuration with an NPN pass element using voltage regulator

2 to provide the voltage reference for the regulated output voltage V3. This circuit requires

fewer components compared to the configuration in Figure 3

but has a limited Vs operating range (6 V to 18 V).

14/98 Doc ID 16363 Rev 4

L99PM62XP

2.1.4

Description

The output voltage V3 can be calculated using the following formula: v

3

= v

------

2

⋅

R +

---------------------

R

2

R

2

V

The circuit in

Figure 6 provides additional current limitation using an additional NPN

transistor and R5 which allows setting the current limit.

Alternatively, voltage regulator 1 can be used to provide the 5 V reference for this topology.

However, the additional current consumption through R3 and R4 has to be considered in

V

1 standby mode.

Voltage regulator failure

The V

1, and V

2

regulator output voltages are monitored.

In case of a drop below the V

1,

V

2

– fail thresholds (V

1,2

< 2 V, typ for t > 2 µs), the V

1,2

-fail bits are latched. The fail bits can be cleared by a dedicated SPI command.

Short to ground detection

If 4 ms after turn on of the regulator the V

1,2 voltage is below the V

1,2

fail thresholds,

(independent for V

1,2

), the L99PM62XP identifies a short circuit condition at the related regulator output and the regulator is switched off.

In case of V

1

short to GND failure the device enters V

BAT

standby mode automatically. Bits

Forced V

BAT

STD2/SHTV

1

and V

1

fail were set.

In case of a V

2

short to GND failure the V

2 short and V

2

fail bit is set.

If the output voltage of the corresponding regulator once exceeded the V

1,2

fail thresholds the short to ground detection is disabled. If a short to ground condition occurs the regulator outputs switches off due to thermal shutdown (V

1

at TSD2; V

2

at TSD1).

Doc ID 16363 Rev 4 15/98

Description L99PM62XP

2.1.5 Voltage regulator behaviour

Figure 7.

Voltage regulator behaviour and diagnosis during supply voltage ramp-up / rampdown conditions

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The L99PM62XP can be operated in 4 different operating modes:

● Active

●

●

●

Flash

V

1

standby

V

BAT

standby

A cyclic monitoring of wake-up inputs and a periodic interrupt/wake-up by timer is available in standby modes.

All functions are available and the device is controlled by the ST SPI Interface.

To program the system microcontroller, the L99PM62 can be operated in Flash mode where the internal watchdog is disabled. This mode can also be used for software debugging.

Doc ID 16363 Rev 4

L99PM62XP Description

Note:

Except for the disabled watchdog, the Flash mode is identical to active mode and all device features are available.

The mode can be entered if one of the following conditions is applied:

●

●

V

TxDL

> V

Flash

V

TxDC

> V

Flash

At exit from Flash mode (V

TxD

< V

Flash starts with a long open window.

) no NReset pulse is generated and the watchdog

Setting both TxDL and TxDC to high voltage levels (> V

Flash

) is not allowed

2.2.3 V

1 standby mode

Note:

The transition from active mode to V

1

standby mode is controlled by SPI.

To supply the micro controller in a low power mode, the voltage regulator 1 (V

1

) remains active. In order to reduce the current consumption, the regulator goes in low current mode as soon as the supply current of the microcontroller goes below the I cmp

At this transition, the L99PM62 also deactivates the internal watchdog.

current threshold.

Relay outputs, LIN and CAN transmitters is switched off in V

1 standby mode. High-side outputs and the V

2

regulator remain in the configuration programmed prior to the standby command.

A cyclic supply of external contacts and a synchronized monitoring of the contact state can be activated and configured by SPI.

In V

1 standby mode various wake up sources can be individually programmed. Each wake up event puts the device into active mode and forces the RxDL/NINT pin to a low level indicating the wake-up condition to the microcontroller.

After power ON reset (POR) all wake up sources are activated by default except the periodic interrupt/wake timer.

With the interrupt timer the micro controller can be forced from ‘stop’ to ‘run’ after a programmable period. The RxDL/NINT pin is forced low after the timer is elapsed. The

L99PM62XP enters active mode and is awaiting a valid watchdog trigger.

Both internal timers can be used for this feature.

The interrupt timer (T

INT

) at pin RxDL/NINT is only available in V

1

standby mode.

Inputs TxDL, TxDC and CSN must be at high level or at high impedance in order to achieve

minimum standby current in V

1

standby mode.

Inputs DI and CLK must be at GND or at high impedance to achieve minimum standby current in V

1

standby mode.

Interrupt

The interrupt signal (linked to RxDL/NINT internally) indicates a wake-up event from V

1 standby mode. In case of a wake-up by Wake-up Inputs, activity on LIN or CAN, SPI access or timer-interrupt the NINT pin is pulled low for 56 µs.

In case of V

1

standby mode and (I

V1

> I cmp

), the device remains in standby mode, the V

1 regulator switches to high current mode and the watchdog starts. No Interrupt signal is generated.

Doc ID 16363 Rev 4 17/98

Description L99PM62XP

2.2.4 V

BAT standby mode

Note:

The transition from active mode to V

BAT

standby mode is initiated by an SPI command.

In V

BAT

standby mode, the V

1

voltage regulator, relay outputs, LIN and CAN transmitters are switched off. High-side outputs and the V

2

regulator remain in the configuration programmed prior to the standby command.

In V

BAT

standby mode the current consumption of the L99PM62XP is reduced to a minimum level.

Inputs TXDL, TXDC and CSN must be terminated to GND in V

BAT

standby to achieve minimum standby current.

This can be achieved with the internal ESD protection diodes of the microcontroller

(microcontroller is not supplied in this mode; V

1

is pulled to GND).

2.2.5

Wake up from standby modes

A wake-up from standby mode switches the device to active mode. This can be initiated by one or more of the following events:

Table 3.

Wake up sources

Wake up source Description

LIN bus activity

CAN bus activity

Can be disabled by SPI

Can be disabled by SPI

I

Level change of WU1 - 3 Can be individually configured or disabled by SPI

V1

> I cmp

Device remains in V

1

standby mode but watchdog is enabled (If

I cmp

= 0) and the V

1

regulator goes into high current mode (increased current consumption). No interrupt is generated.

Timer interrupt / wake up of µC by TIMER

SPI access

Programmable by SPI

– V

1 standby mode: device wakes up and Interrupt signal is generated at RxDL/NINT when programmable timeout has elapsed

– V

BAT standby mode: device wakes up, V

1

regulator is turned on and

NReset signal is generated when programmable timeout has elapsed

Always active (except in V

BAT

standby mode)

Wake up event: CSN is low and first rising edge on CLK

To prevent the system from a deadlock condition (no wake up possible) a configuration where the periodic timer interrupt and wake up by LIN and HS CAN are disabled, is not allowed. The default configuration is entered for all wake-up sources in case of such an invalid setting.

All wake-up events from V

1 standby mode (except I

V1

> I cmp

) are indicated to the microcontroller by a low-pulse at RxDL/NINT (duration: 56 µs).

Wake-up from V

1 standby by SPI Access might be used to check the interrupt service handler.

18/98 Doc ID 16363 Rev 4

L99PM62XP Description

The de-bounced digital inputs WU1 to WU3 can be used to wake up the L99PM62XP from standby modes. These inputs are sensitive to any level transition (positive and negative edge)

For static contact monitoring, a filter time of 64 µs is implemented at WU1-3. The filter is started when the input voltage passes the specified threshold.

In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a cyclic sense functionality is implemented. This feature allows periodical activation of the wake-up inputs to read the status of the external contacts. The periodical activation can be

linked to Timer1 or Timer2 (see Section 2.2.7: Cyclic contact supply ). The input signal is

filtered with a filter time of 16 µs after a programmable delay (80 µs or 800 µs) according to the configured timer on-time. A wake-up is processed if the status has changed versus the previous cycle.

The outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up inputs.

If the wake-up inputs are configured for cyclic sense mode the input filter timing and input filter delay (WUx_filt in control register 2) must correspond to the setting of the high-side output which supplies the external contact switches (OUTx in control register 0).

In standby mode, the inputs WU1-3 are SPI configurable for pull-up or pull-down current source configuration according to the setup of the external. In active mode the inputs have a pull down resistor.

In active mode, the input status can be read by SPI (Status Register 2). Static sense should be configured (Control Register 2) before the read operation is started (In cyclic sense configuration, the input status is updated according to the cyclic sense timing; Therefore, reading the input status in this mode may not reflect the actual status).

2.2.8

In V

1 standby and V

BAT standby modes, any high-side driver output (OUT1..4, OUTHS) can be used to periodically supply external contacts.

The timing is selectable by SPI

Timer 1: period is Xs. The on-time is 10 ms resp. 20 ms: With X ∈ {1, 2, 3, 4 s}

Timer 2: period is X ms. The on- time is 100 µs resp. 1ms: With X ∈ {10, 20, 50, 200 ms}

Timer interrupt / wake-up of microcontroller by timer

During standby modes the cyclic wake up feature, configured via SPI, allows waking up the

µC after a programmable timeout according to timer1 or timer2.

From V

1

standby mode, the L99PM62XP wakes up (after the selected timer has elapsed) and sends an interrupt signal (via RxDL/NINT pin) to the µC. The device enters active mode and the watchdog is started with a long open window. The microcontroller can send the device back into V

1

standby after finishing its tasks.

From V

BAT standby mode, the L99PM62XP wakes up (after the selected timer has elapsed), turns on the V

1

regulator and provides an NReset signal to the µC. The device enters active mode and the watchdog is started with a long open window. The microcontroller can send the device back into V

BAT standby after finishing its tasks.

Doc ID 16363 Rev 4 19/98

Description L99PM62XP

2.3 Functional overview (truth table)

Functional overview (truth table) Table 4.

Operating modes

Function

Voltage-regulator, V

Voltage-regulator, V

Reset-generator

Window watchdog

1

2

V

V

V

1

Comments

OUT

OUT

= 5 V

= 5 V

monitor

On

On/ Off (2)

On

On

Active mode

V

1

-standby static mode

(cyclic sense)

On

(1)

On

(2)

/ Off

V

BAT

-standby static mode

(cyclic sense)

Off

On

(2)

/ Off

On Off

Off (On: I_V

1

> I cmp threshold and I cmp

-

= 0)

Active

(3)

Off

Active

(3)

Wake up

HS-cyclic supply

Relay driver

Operational amplifiers

Off

Oscillator time base

On / Off

On

On

On

Off

Off

(2)

/ Off On

Off

Off

(2)

/ Off

LIN LIN 2.1

On Off

(4)

Off

(4)

Off

(4)

Off

(4)

HS_CAN

FSO (if configured by

SPI), active by default

Oscillator

Fail safe output

On

OUT3/FSO Off

(5)

OUT3/FSO Off

(5)

OUT3/FSO Off

(5)

Vs-monitor

On

On

(6)

(7)

(6)

(7)

1.

Supply the processor in low current mode.

2.

Only active when selected via SPI.

3.

Unless disabled by SPI.

4.

The bus state is internally stored when going to standby mode. A change of bus state leads a wake-up after exceeding of internal filter time (if wake-up by LIN or CAN is not disabled by SPI).

5.

ON in fail-safe condition: If Standby mode is entered with active Fail Safe mode, the output remains ON in Standby mode.

6.

Activation = ON if cyclic sense is selected.

7.

cyclic activation = pulsed ON during cyclic sense.

20/98 Doc ID 16363 Rev 4

L99PM62XP

Figure 8.

Operating modes

Description

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2.4 Configurable window watchdog

During normal operation, the watchdog monitors the micro controller within a programmable trigger cycle: (10 ms, 50 ms, 100 ms, 200 ms)

In V

BAT

standby and Flash program modes, the watchdog circuit is automatically disabled.

In V

1

standby mode a wake up by timer is programmable in order to wake up the µC (see

Section 2.2.8: Timer interrupt / wake-up of microcontroller by timer ). After wake-up, the

watchdog starts with a long open window. After serving the watchdog, the µC may send the device back to V

1 standby mode.

Doc ID 16363 Rev 4 21/98

Description L99PM62XP

After power-on or standby mode, the watchdog is started with a long open window (65 ms nominal). The long open window allows the micro controller to run its own setup and then to trigger the watchdog via the SPI. The trigger is processed when the CSN input becomes

HIGH after the transmission of the SPI word.

Writing ‘1’ to the watchdog trigger bit terminates the long open window and start the window watchdog (the timing is programmable by SPI). Subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer to

Figure 27 ). A correct watchdog trigger signal is immediately start the next cycle.

After 8 watchdog failures in sequence, the V

1

regulator is switched off for 200ms. If subsequently, 7 additional watchdog failures occur, the V

1

regulator is completely turned off and the device goes into V

BAT standby mode until a wakeup occurs.

In case of a watchdog failure, the outputs (RELx, OUTx, V

2

) are switched off and the device enters fail-safe mode (i. e. all control registers are set to default values except the ‘OUT3 control bit’).

The following diagrams illustrate the watchdog behavior of the L99PM62. The diagrams are split into 3 parts. First diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. Third diagram shows the transition in and out of Flash mode.

All 3 diagrams can be overlapped to get all the possible state transitions under all circumstances. For a better readability, they were split in normal operating, operating with errors and Flash mode.

Figure 9.

Watchdog in normal operating mode (no errors)

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22/98 Doc ID 16363 Rev 4

L99PM62XP

Figure 10.

Watchdog with error conditions

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2.4.1 Change watchdog timing

There are 4 programmable watchdog timings available, which represent the nominal trigger time in window mode. To change the watchdog timing, a new timing has to be written by

SPI. The new timing gets active with the next valid watchdog trigger. The following figures illustrate the sequence, which is recommended to use, changing the timing within long open window and within window mode.

Doc ID 16363 Rev 4 23/98

Description L99PM62XP

Figure 12.

Change watchdog timing within long open window

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Figure 13.

Change watchdog timing within window mode

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If the device is in fail-safe mode, the control registers are locked for writing. To change the watchdog timing out of fail-safe mode, first the fail-safe condition must be solved, respective confirmed from the microcontroller. Afterwards the new watchdog timing can be

programmed using the sequence from Figure 14 . Since the actions to remove, a fail-safe

condition can differ from the root cause of the fail safe the following diagram shows the

general procedure how to change the watchdog timing out of fail-safe mode. Figure 15

shows the procedure to change watchdog timing with a previous watchdog failure, since this is a special fail-safe scenario.

24/98 Doc ID 16363 Rev 4

L99PM62XP Description

Figure 14.

General procedure to change watchdog timing out of fail safe mode

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Figure 15.

Change watchdog timing out of fail safe mode (watchdog failure)

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2.5 Fail mode

L99PM62XP enters fail safe mode in case of:

●

●

●

●

●

Watchdog failure

V

1

turn on failure

– V

1

short (V

1

< V

1fail

for t > 4 ms)

V

1

undervoltage (V

1

< Vrth for t > 8 µs)

Thermal shutdown TSD2

SPI failure

– DI stuck to GND or V

CC

(SPI frame = ’00 00 00’ or ‘FF FF FF’

Doc ID 16363 Rev 4 25/98

Description L99PM62XP

The fail safe functionality is also available in V

1

standby mode. During V

1

standby mode the fails safe mode is entered in the following cases:

●

●

●

V

1

undervoltage (V

1

< Vrth for t > 8 µs)

Watchdog failure (if watchdog still running due to I

V1

> I cmp

)

Thermal shutdown TSD2

In fail safe mode the L99PM62 returns to a default. The fail safe condition is indicated to the remaining system in the global status register. The conditions during fails safe mode are:

●

●

All outputs are turned off

All control registers are set to default values (except OUT3/FSO configuration)

●

●

Write operations to control registers are blocked until the fail safe condition is cleared

(see

Table 5 )

LIN and HS CAN transmitter, OpAmps and SPI remain on

●

●

●

Corresponding failure bits in status registers are set.

FSO Bit (Bit 0 global status register) is set

OUT3/FSO is activated if configured as fail safe output

If OUT3 is configured as FSO, the internal fail safe mode can be monitored at OUT3 (highside driver is turned on in fail-safe mode). Self protection features for OUT3 when

configured as FSO are active (see Section 3.3: High-side driver outputs ).

OUT3 is configured as fail safe output by default. It can be configured to normal high-side driver operation by SPI. It this case, the configuration remains until Vs power on.

If the fail safe mode was entered it keeps active until the fail safe condition is removed and the fail safe was read by spi. depending on the root cause of the fail safe operation, the actions to exit fail safe mode are as shown in the following table.

Table 5.

Fail safe conditions and exit modes

Failure source Failure condition Diagnosis Exit from fail-safe mode

µC (oscillator)

V

1

Temperature

Watchdog early write failure or expired window

Fail-safe = 1

WDfail = n+1

Short at turn-on

Undervoltage

T j

> TSD2

Fail-safe = 1

Forced Sleep TSD2/SHTV

1

= 1

Fail-safe = 1

V

1fail

= 1

(1)

Fail-safe = 1

TW = 1

TSD1 = 1

TSD2 = 1

SPI DI short to GND or V

CC

Fail-safe = 1

1.

if V

1

< V

1fail

(for t >2µs)

The fail-safe bit is located in the global status register (Bit 0) multiple failures – entering forced V

BAT

standby mode

TRIG = 1 during LOWi and read fail-safe bit

Read&Clear SR3 after wake

V

1

> Vrth

Read Fail-safe bit

T j

< TSD2

Read&Clear SR3

Valid SPI command

If the fail-safe condition persists and all attempts to return to normal system operation fail, the L99PM62 enters the forced V

BAT standby mode in order to prevent damage to the

26/98 Doc ID 16363 Rev 4

L99PM62XP Description

Table 6.

system. The forced V

BAT standby mode can be terminated by any regular wake-up event.

The root cause of the forced V

BAT standby is indicated in the SPI status registers

The forced V

BAT standby mode is entered in case of:

● Multiple watchdog failures: forced sleep WD = 1 (15x watchdog failure)

●

●

Multiple thermal shutdown 2: forced sleep TSD2/SHTV1 = 1 (7x TSD2)

V

1

short at turn-on: forced sleep TSD2/SHTV1 = 1 (V

1

< V

1fail

for t > 4 ms)

Persisting fail safe conditions and exit modes

Failure source Failure condition Diagnosis Exit from fail-safe mode

µC (oscillator)

15 consecutive watchdog failures

Fail-safe = 1

ForcedSleepWD = 1

Wake-up

TRIG = 1 during LOWi read & clear SR3

V

1

Temperature short at turn-on

7 times TSD2

Fail-safe = 1

ForcedSleepTSD2/SHTV

1

= 1

Fail-safe = 1

TW = 1

TSD1 = 1

TSD2 = 1

ForcedSleepTSD2/SHTV

1

= 1

Read&clear SR3 after wake-up

Read&clear SR3 after wake-up

Figure 16.

Example: exit fail safe mode from watchdog failure

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Doc ID 16363 Rev 4 27/98

Description

2.6

Note:

L99PM62XP

Reset output (NRESET)

If V

1

is turned on and the voltage exceeds the V

1

reset threshold, the reset output

“NRESET” is pulled up by internal pull up resistor to V

1

voltage after a 2 ms reset delay time.

This is necessary for a defined start of the micro controller when the application is switched on. Since the NRESET output is realized as an open drain output it is also possible to connect an external NRESET open drain NRESET source to the output. It must be considered that as soon the NRESET is released from the L99PM62 the Watchdog timing starts.

A reset pulse (2 ms) is generated in case of:

●

●

V

1

drops below Vrth (configurable by SPI) for more than 8 µs

Watchdog failure

An external pull-up resistor (1k

Ω

) to V

1

is recommended in order to ensure I

LOAD1

> I cmp during reset condition

The operational amplifiers are especially designed to be used for sensing and amplifying the voltage drop across ground connected shunt resistors. Therefore the input common mode range includes -0.2 V to 3 V.

The operational amplifiers are designed for -0.2 V to +3 V input voltage swing and rail-to-rail output voltage range.

All pins (positive, negative and outputs) are available to be able to operate in non-inverting and inverting mode. Both operational amplifiers are on-chip compensated for stability over the whole operating range within the defined load impedance.

The operational amplifiers may also be used to setup an additional high current voltage source with an external pass element. Refer to

Section 2.1.3

for a detailed description.

2.8 LIN interface

Features:

●

●

Speed communication up to 20 kbit/s.

LIN 2.1 compliant (SAEJ2602 compatible) transceiver.

●

●

●

●

Function range from +40 V to -18 V DC at LIN pin.

GND disconnection fail safe at module level.

Off mode: does not disturb network.

GND shift operation at system level.

●

●

●

●

●

Micro controller Interface with CMOS compatible I/O pins.

Internal pull up resistor.

Internal high-side switch to disconnect master pull-up resistor in case of short circuit of bus signal.

ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2.

Matched output slopes and propagation delay.

28/98 Doc ID 16363 Rev 4

L99PM62XP

Note:

Description

In order to further reduce the current consumption in standby mode, the integrated LIN bus interface offers an ultra low current consumption.

Use of master pull-up switch is optional.

2.8.2

Note:

The L99PM62XP provides the following 3 error handling features which are not described in the LIN Spec. V

2.1

, but are realized in different stand alone LIN transceivers / micro controllers to switch the application back to normal operation mode.

Dominant TxDL time out

If TXDL is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the status bit is latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared. This feature can be disabled via SPI.

Permanent recessive

If TXDL changes to dominant (low) state but RXDL signal does not follow within 40 µs the transmitter is disabled, the status bit is latched and can be read and optionally cleared by

SPI. The transmitter remains disabled until the status register is cleared.

Permanent dominant

If the bus state is dominant (low) for more than 12 ms a permanent dominant status is detected. The status bit is latched and can be read and optionally cleared by SPI. The transmitter is not disabled.

Wake up (from LIN)

In standby mode the L99PM62XP can receive a wake up from LIN bus. For the wake up feature the L99PM62XP logic differentiates two different conditions.

Normal wake up

Normal wake up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high) state. A dominant level at LIN for t linbus

, switches the L99PM62XP to active mode.

Wake up from short to GND condition

If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for t linbus

, switches the L99PM62XP to active mode.

A wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode.

The master node pull-up resistor (1 k Ω ) can be connected to Vs using the internal LIN_PU high-side switch. This high-side switch can be controlled by SPI in order to allow disconnection of the pull-up resistor in case of LIN bus short to GND conditions.

Doc ID 16363 Rev 4 29/98

Description

Figure 17.

LIN master node configuration using LIN_PU (optional)

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LIN_PU high-side driver characteristics:

● Activated by default and can be turned off by SPI command (CR4).

●

●

●

●

Remains active in standby modes.

Switch off only in case of over temperature (TSD2 = thermal shutdown #2).

No over current protection.

Typical R

DS on, 10 Ω .

High speed CAN bus transceiver

General requirements

● Speed communication up to 1 Mbit/s.

●

●

ISO 11898-2 and ISO 11898-5 compliant

SAE J2284 compliant

●

●

●

●

Function range from +40 V to -27 V DC at CAN pins.

GND disconnection fail safe at module level.

GND shift operation at system level.

Micro controller Interface with CMOS compatible I/O pins.

●

●

●

●

ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

Matched output slopes and propagation delay

Split output pin for stabilizing the recessive bus level

Receive-only mode available

In order to further reduce the current consumption in standby mode, the integrated CAN bus interface offers an ultra low current consumption.

30/98 Doc ID 16363 Rev 4

L99PM62XP

2.9.1

2.9.2

Description

CAN error handling

The L99PM62XP provides the following 4 error handling features which are not described in the ISO 11898-2/ISO 11898-5, but are realized in different stand alone CAN transceivers / micro controllers to switch the application back to normal operation mode.

Dominant TxDC time out

If TXDC is in dominant state (low) for t > t dom(TxD)

the transmitter is disabled, status bit is latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.

CAN permanent recessive

If TXDC changes to dominant (low) state but CAN bus does not follow for 4 times, the transmitter is disabled, status bit is latched and can be read and optionally cleared by SPI.

The transmitter remains disabled until the status register is cleared.

CAN permanent dominant

If the bus state is dominant (low) for t > t

CAN

a permanent dominant status is detected. The status bit is latched and can be read and optionally cleared by SPI. The transmitter is not disabled.

RXDC permanent recessive

If RXDC pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RXDC does not follow TXDC for 4 times the transmitter is disabled. The status bit is latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.

Wake up (from CAN)

When the L99PM62XP is in standby mode with CAN wake up option enabled, the CAN bus traffic is detected. For the wake up feature the L99PM62XP logic differentiates different conditions. During V

1

Standby mode RXDC output is kept at recessive level. Independent from the wakeup pattern selected and independent from the previous Standby mode, the

RXDC reflect immediately the bus state after the wakeup. This feature allows implementation of a ‘partial networking’ functionality controlled by the system microcontroller.

Normal pattern wake up

Normal pattern wake up can occur when CAN pattern wake up option is enabled and the

CAN transceiver was set in standby mode while CAN bus was in recessive (high) state or dominant (low) state. In order to wake up the L99PM62XP, the following criteria must be fulfilled:

●

●

The CAN interface wake-up receiver must receive a series of two consecutive valid dominant pulses, each of which must be longer than 2 µs

The distance between 2 pulses must be longer than 2 µs.

● The two pulses must occur within a time frame of 1.0 ms

Doc ID 16363 Rev 4 31/98

Description L99PM62XP

Note:

Wake up from short to GND condition

Even if CAN pattern wake up option is enabled, but the CAN transceiver was set in standby mode after a qualified permanent dominant state, recessive level at CAN, switches the

L99PM62XP to active mode.

No pattern wake up

If the CAN pattern wake up option is disabled, any transition either dominant (low) state to recessive (high) state or recessive (high) state to dominant (low) state switches the

L99PM62XP to active mode (after a filtering time of 2 µs).

A wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode.

Figure 18.

CAN wake up capabilities

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Pictures above illustrate the wake up behaviour from V

1 standby mode. For wake up from

V

BAT

standby mode the NRESET signal (with 2 ms timing) is generated instead of the RXDL

(Interrupt) signal.

CAN sleep mode

During active mode it is possible to deactivate the CAN transceiver with a dedicated SPI command (CR4, CAN_act = 0). The CAN transceiver remains deactivated until it is activated again. With a deactivated CAN the receiver input termination network is disconnected from the bus and the CANH, CANL bus lines is driven to GND. The SPLIT output is also deactivated in this case.

32/98 Doc ID 16363 Rev 4

L99PM62XP

2.9.4

2.9.5

Description

CAN receive only mode

With the CAN_rec_only bit in control register 4 it is possible to disable the CAN transmitter in active mode. In this mode it is possible to listen to the bus but not sending to it. The receiver termination network is still activated in this mode.

CAN looping mode

If the CAN_Loop_en bit in control register 4 is set the TXDC input is mapped directly to the

RXDC pin. This mode can be used in combination with the CAN receive only mode, to run diagnosis for the CAN protocol handler of the micro controller.

2.10 Serial peripheral interface (ST SPI standard)

A 24 bit SPI is used for bi-directional communication with the micro controller.

During active mode, the SPI

● Triggers the watchdog

●

●

●

Controls the modes and status of all L99PM62XP modules (incl. input and output drivers)

Provides driver output diagnostic

Provide L99PM62XP diagnostic (incl. over temperature warning, L99PM62XP operation status)

The SPI can be driven by a micro controller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible output pins and one input pin is needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin reflects the global error flag

(fault condition) of the device.

Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame.

If CSN = low for t > t

CSNfail

the DO output is switched to high impedance in order to not block the signal line for other SPI nodes.

Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.

At the rising edge of the CSN signal the contents of the shift register is transferred to Data

Input Register. The writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock

Doc ID 16363 Rev 4 33/98

Description

Note:

L99PM62XP pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

Serial data out (DO)

The data output driver is activated by a logical low level at the CSN input and goes from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK shifts the next bit out.

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 1MHz.

34/98 Doc ID 16363 Rev 4

L99PM62XP

3 Protection and diagnosis

3.1 Power supply fail

Over and under-voltage detection on Vs

Protection and diagnosis

If the supply voltage Vs reaches the over voltage threshold (V

SOV

):

● Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).

CAN is not disabled. Recovery of outputs when the overvoltage condition disappears is depending on the setting of VLOCKOUT_EN bit in Control Register 4.

– VLOCKOUT_EN = 1: Outputs are off until read and clear SR3.

– VLOCKOUT_EN = 0: Outputs switch automatically on when overvoltage condition disappears.

●

●

The over voltage bit is set and can be cleared with a ‘Read and Clear’ command. The overvoltage bit is removed automatically if VLOCKOUT_EN = 0 and the overvoltage condition disappears.

Outputs REL1,2 can be excluded from a shutdown in case of overvoltage by SPI

(LSOVUV_ Shutdown_en in CR4)

If the supply voltage Vs drops below the under voltage threshold voltage (V

SUV

)

● Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).

CAN is not disabled. Recovery of outputs when the undervoltage condition disappears is depending on the setting of VLOCKOUT_EN bit.

VLOCKOUT_EN = 1: Outputs are off until read and clear SR3.

VLOCKOUT_EN = 0: Outputs switch on automatically when undervoltage condition disappears.

●

●

The undervoltage bit is set and can be cleared with a ‘Read and Clear’ command. The undervoltage bit is removed automatically if VLOCKOUT_EN = 0 and the undervoltage condition disappears

Outputs REL1,2 can be excluded from a shutdown in case of undervoltage by SPI

(LSOVUV_shutdown_en in CR4)

Doc ID 16363 Rev 4 35/98

Protection and diagnosis

Figure 19.

Over voltage and under voltage protection and diagnosis

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36/98 Doc ID 16363 Rev 4

L99PM62XP Protection and diagnosis

3.2 Temperature warning and thermal shutdown

Figure 20.

Thermal shutdown protection and diagnosis

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The thermal state machine recovers the same state were it was before entering standby mode. In case of a TSD2 it enters TSD1 state.

Doc ID 16363 Rev 4 37/98

Protection and diagnosis

3.3

Note:

L99PM62XP

High-side driver outputs

The component provides a total of 4 high-side outputs Out1 to 4, (7

Ω typ. at @ 25°C) to drive e.g. LED's or hall sensors and 1 high-side output OUT_HS with 1

Ω typ. at @ 25 °C).

The high-side outputs switch off in case of:

● Vs over and undervoltage

●

●

Over current

Overtemperature with pre warning

(a)

In case of overload or over temperature (TSD1) condition, the drivers switchs off. The according status bit is latched and can be read and optionally cleared by SPI. The drivers remain off until the status is cleared.

In case over/under voltage condition, the drivers is switched off. The according status bit is latched and can be read and optionally cleared by SPI. If the Vlockout bit (Control Register

4) is set to ‘1’ the drivers remain off until the status is cleared. If the Vlockout bit is set to ‘0’ the drivers switches on automatically if the error condition disappears.

In case of open-load condition, the according status register is latched. The status can be read and optionally cleared by SPI. The high-sides not switches off.

For OUT_HS the auto recovery feature (OUTHSREC bit Control Register 4) can be enabled. If this bit is set to ‘1’ the driver is automatically restart from a overload condition.

This overload recovery feature is intended for loads which have an initial current higher than the over current limit of the output (e.g. Inrush current of cold light bulbs). During auto recovery mode the over current status bit can not be read from SPI.

The device itself can not distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example, the micro controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.

After clearing the recovery bit, the output is automatically disabled if the overload condition still exists.

In case of a fail safe condition, the high-side drivers are switched off. The control bits are set to default values. (except OUT3/FSO if it is used as a high-side driver output)

The maximum voltage and current applied to the high-side outputs is specified in

Section 2.1: Voltage regulators

. Appropriate external protection may be required in order to respect these limits under application conditions.

3.4 Low-side driver outputs REL1, REL2

The outputs REL1, REL2 (R

DSon

= 2

Ω

typ. @25

°

C) are specially designed to drive relay loads.

The outputs provide an active output zener clamping (45 V typ.) feature for the demagnetization of the relay coil, even though a load dump condition exists.

For fail-safe reasons the relay drivers are linked with the fail safe operation: in case of entering the fail safe mode, the relay drivers switchs off and the SPI control bits are set to default (i.e. driver is off).

38/98 a.

Except OUT3 when configured as FSO.

Doc ID 16363 Rev 4

L99PM62XP Protection and diagnosis

The low-side drivers switch off in case of:

● Vs over and undervoltage

●

●

Over current

Overtemperature with pre warning

In case of overload or overtemperature (TSD1) condition, the drivers switches off. The according status bit is latched and can be read and optionally cleared by SPI. The drivers remain off until the status is cleared.

In case Vs over/undervoltage condition, the drivers is switched off. The according status bit is latched and can be read and optionally cleared by SPI. If the Vlockout bit (Control

Register 4) is set to ‘1’ the drivers remain off until the status is cleared. If the Vlockout bit is set to ‘0’ the drivers is switched on automatically if the error condition disappears.

With the LSOVUV_shutdown_en bit (Control Register 4) the drivers can be excluded from a switch off in case of Vs over/undervoltage. If the bit is set to ‘1’ the driver switchs off, otherwise the drivers remain on.

Digital diagnosis features are provided by SPI (for details please refer to

Section 6.2: SPI registers .

●

●

V

1

reset threshold programmable

Overtemperature including. pre warning

●

●

●

●

●

●

Open-load separately for each output stage except REL1/REL2

Overload status separately for each output stage

Vs-supply over/under voltage

V

1

and V

2

fail bit

V

2

output short to GND

Status of the WU1 to 3

●

●

●

●

●

●

●

●

●

●

●

Wake-up sources (CAN, LIN, SPI, Timer, WU1…3) chip reset bit (start from power-on reset)

Number of unsuccessful V

1

restarts after thermal shutdown

Number of sequential watchdog failures

LIN diagnosis (permanent recessive/dominant, dominant TxD)

CAN diagnosis (permanent recessive/dominant, dominant TxD, recessive RXD)

Device State (wake-up from V1 standby or V

BAT standby)

Forced V

BAT standby after WD-fail, forced V

BAT standby after overtemperature

Watchdog timer state (diagnosis of watchdog)

Fail-safe status

SPI communication error

Doc ID 16363 Rev 4 39/98

Typical application L99PM62XP

Figure 21.

Typical application diagram

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40/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Table 7.

Absolute maximum rating

Symbol Parameter/test condition

V

S

V

1

V

2

V

DI

V

CLK

V

DO

V

RXDL

V

NRESET

V

RXDC

V

TXDC,

V

TXDL

, V

CSN

V

REL1,

V

REL2,

V

OUT1..3,

V

OUT_HS

V

WU1...4

V

OP1P,

V

OP1M,

V

OP2P,

V

OP2M,

V

OPOUT1,

V

OPOUT2

V

LIN,

V

LINPU

I

Input

Iout_inj

DC supply voltage / “jump start”

Single pulse / t max

< 400 ms “transient load dump”

Stabilized supply voltage, logic supply

Stabilized supply voltage

Logic input / output voltage range

Multi level inputs

Low-side output voltage range

High-side output voltage range

Wake up input voltage range

Opamp1 input voltage range

Opamp2 input voltage range

Analog Output voltage range

LIN bus I/O voltage range

Current injection into Vs related input pins

Current injection into Vs related outputs

V

CANSUP

V

CANH,

V

CANL,

V

SPLIT

CAN supply

CAN bus I/O voltage range

Note:

Value [DC voltage]

-0.3 to +28

-0.3 to +40

-0.3 to +5.25

-0.3 to +28

-0.3 to V

1

+0.3

-0.3 to Vs+0.3

-0.3 to +40

-0.3 to V

S

+0.3

-0.3 to V

S

+0.3

-0.3 to V

1

+0.3

-0.3 to V

S

+0.3

-20 to +40

10

10

-0.3 to +5.25

-27 to +40

Unit

V

V

V

V

V

All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit!

Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current.

V

V mA mA

V

V

V

V

V

V

V

Doc ID 16363 Rev 4 41/98

Electrical specifications L99PM62XP

Table 8.

All pins

(1)

All output pins

(2)

LIN

ESD protection

Parameter

CAN_H, CAN_L

Value

+/-2

+/-4

+/-8

(2)

+/-6

(3)

+/-8

(2)

+/-6

(3)

+/-500

Unit kV kV kV kV

All pins (charge device model) V

Corner pins (charge device model)

All pins

(4)

+/-750

+/-200

V

V

1.

HBM (human body model, 100pF, 1.5 k

Ω

) according to MIL 883C, method 3015.7 or EIA/JESD22A114-A

2.

HBM with all none zapped pins grounded.

3.

EN / IEC61000-4-2 according to report from external test house.

4.

Acc. machine model: C = 200 pF; R = 0

Ω

.

Table 9.

Symbol

T j

R thjA

Operating junction temperature

Parameter

Operating junction temperature

Thermal resistance junction / ambient

Value

-40 to 150

See

Figure 23

Unit

°C

°K/W

Table 10.

Temperature warning and thermal shutdown

Symbol Parameter

T

W ON

T

SD1 OFF

T

SD2 OFF

T

SD2 ON

T

SD12hys

1.

Non-overlapping

Thermal over temperature warning threshold

T j

(1)

Thermal shutdown junction temperature 1 T j

(1)

T j

(1)

Thermal shutdown junction temperature 2

Hysteresis

Min.

Typ.

Max.

Unit

120 130 140

130 140 150

140 155 170

5

°C

°C

°C

°C

42/98 Doc ID 16363 Rev 4

L99PM62XP

5.4 Package and PCB thermal data

Figure 22.

PowerSSO-36 PC board

Electrical specifications

Note:

$*9

Layout condition of R th and Z th measurements (board finish thickness 1.6 mm +/- 10% board double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070 mm (front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm,

Cu thickness on vias 0.025 mm).

Doc ID 16363 Rev 4 43/98

Electrical specifications L99PM62XP

Figure 23.

PowerSSO-36 thermal resistance junction to ambient vs PCB copper area

(V1 ON)

57+MDPE

57+MBDPE &:

57+MDPE

3&%&XKHDWVLQNDUHDFPA

$*9

Figure 24.

PowerSSO-36 Thermal Impedance junction to ambient vs PCB copper area (single pulse with V1 ON)

AG00025V1

44/98 Doc ID 16363 Rev 4

L99PM62XP

Figure 25.

PowerSSO-36 thermal fitting model (V1 ON)

Electrical specifications

$*9

Equation 1: pulse calculation formula

Z

TH δ

= R

TH

⋅ δ

+ Z

THtp

( 1 –

δ ) where

δ

= t p

⁄ T

Table 11.

Thermal parameter

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

Footprint

0.01

0.1

0.8

2

2

8

20

36

2

4

15.5

29

0.2

1

3

8

0.2

1.5

6

4

10

18

Doc ID 16363 Rev 4 45/98

Electrical specifications L99PM62XP

5.5.1 Supply and supply monitoring

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin T j

= -40 °C to 130 °C, unless otherwise specified.

Table 12.

Supply and supply monitoring

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

V

S

V

SUV

V hyst_UV

V

SOV

V hyst_OV t ovuv_filt

Supply voltage range

V

S

undervoltage threshold

Vs undervoltage hysteresis

V

S

overvoltage threshold

Vs overvoltage hysteresis

Vs over/undervoltage filter time

V

S

increasing / decreasing

V

S

increasing / decreasing

Hysteresis

I

I

V(act)

V(BAT)

Current consumption in active mode

Current consumption in

V

BAT

standby mode

Vs = 12V

TxD CAN = high

TxD LIN = high

V

1

= on, V

2

= on

V

S

= 12V

Both voltage regulators deactivated, no wake-up request

(1)

I

V(BAT)CS

Current consumption in

V

BAT

standby mode with cyclic sense enabled

V

S

= 12V

Both voltage regulators deactivated,

T = 50 ms, ton = 100 µs no wake-up request

(1)

6

5.11

0.0

18.5

0.5

8

40

13.5

0.1

1

64*T

6

12

75 osc

I

V(BAT)CW

Current consumption in

V

BAT standby mode with cyclic wake enabled

V

S

= 12V

Both voltage regulators deactivated

During standby phase no wake-up request

(1)

40 75

I

(V1)

Current consumption in

V

1

-standby mode

V

S

= 12V

Voltage Regulator V

1

active,

(I v1

< I cmp

) no wake-up request

(1)

16 51

1.

Conditions for no wake-up request are (all conditions must be met):

2 V < LIN < (Vs-2 V)

0.4 V < (CAN_H – CAN_L) < 1,2 V

1 V < V

WUth

< (Vs-2 V)

The current consumption in standby modes with cyclic sense can be calculated using the following formulas:

I

V(BAT)CS

I

(V1)CS

= I

V(BAT)

= I

V1

+ 55 µA + (2 mA * (t

+ 55 µA + (2 mA * (t

ON

ON

+ 100 µs) / T)

+ 100 µs) / T)

18

5.81

0.15

22

1.5

12

28

125

125

76 mA

µA

µA

µA

µA

V

V

V

V

V

46/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

5.5.2 Oscillator

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V < V

S

< 28 V; all outputs open; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 13.

Oscillator

Symbol Parameter

F

CLK

Oscillation frequency

Test condition Min.

0.80

Typ.

Max.

Unit

1.0

1.35

MHz

All outputs open; T j

= -40°C to 130°C, unless otherwise specified.

Table 14.

Power-on reset (V s

)

Symbol Parameter Test condition

V

POR

V

POR

V

V

POR

POR

threshold

threshold

Vs increasing

Vs decreasing

(1)

1.

This threshold is valid if Vs had already reached 7V previously

Min.

2.65

Typ.

Max.

Unit

3.45

4.5

3.5

V

V

5.5.4 Voltage regulator V

1

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V < V

S

< 28 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 15.

Voltage regulator V

1

Symbol Parameter Test condition

V

1

Output voltage

V

V

V

V

1 hc

STB

DP

1

1

1

Output voltage tolerance

Active mode

Output voltage tolerance active mode, high current

Output voltage tolerance

V

1

-standby mode

Drop-out Voltage

I

LOAD1

= 1mA to 100 mA,

V

S

= 13.5 V

I

LOAD1

= 100 mA to 250 mA,

V

S

= 13.5 V

I

LOAD1

= 250 mA

V

S

= 13.5 V

I

LOAD1

= 0 µA to 1 mA,

V

S

= 13.5 V

I

LOAD1

= 50 mA, V

S

= 5 V

I

LOAD1

= 100 mA, V = 4.5 V

I

LOAD1

= 100 mA, V

S

= 5 V

I

LOAD1

= 150 mA, V

S

= 4.5 V

I

LOAD1

= 150 mA, V

S

= 5.0 V

I

I

CC

1 Output current in active mode Max. continuous load current

CC max1 Short circuit output current Current limitation

C load1

Load capacitor1 Ceramic (+/- 20%)

Min.

400

0.22

(1)

Typ.

5.0

0.2

0.2

0.3

0.45

0.45

600

Max.

Unit

V

+/- 2

+/- 3

+/- 5%

+/- 4%

0.4

0.5

0.5

0.6

0.6

250

950

%

%

%

%

V

V

V

V

V mA mA

µF

Doc ID 16363 Rev 4 47/98

Electrical specifications L99PM62XP

Table 15.

Voltage regulator V

1

(continued)

Symbol Parameter Test condition Min.

Typ.

Max.

Unit t

TSD

V

1

deactivation time after thermal shutdown

1 sec

I cmp_ris

I cmp_fal

I cmp_hys

V

1fail tV tV

1fail

1short

Current comp. rising thresh.

Current comp. falling threshold

Current comp. hysteresis

V

1

fail threshold

V

1

fail filter time

V

1

short filter time

Rising current

Falling current

V

1

forced

1.2

0.8

2.5

1.95

0.5

2

2

4

4

2.8

1.

Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20 %). Capacitor must be located close to the regulator output pin.

mA mA mA

V

µs ms

5.5.5 Voltage regulator V

2

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V < V

S

< 28 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 16.

Voltage regulator V

2

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

V

V

V

V

2

2 hc1

2

Output voltage

Output voltage tolerance active mode

Output voltage tolerance active mode

Output voltage tolerance active mode, high current

I

I

I

LOAD2

V

V

S

S

= 1 mA to 50 mA,

= 13.5 V

LOAD2

= 50 mA to 80 mA,

= 13,5 V

LOAD2

= 100 mA, V

S

= 13,5 V

5,0

+/- 3

+/- 4

+/- 6

V

%

%

%

V

V

STB2

DP2

Output voltage tolerance

V

1

standby mode

Drop-out voltage

I

LOAD2

= 0 µA to 1 mA

V

S

= 13,5 V

I

LOAD2

= 25 mA, Vs = 5.25 V

I

LOAD2

= 50 mA, Vs = 5.25 V

Max. continuous load current

0.3

0.4

+/-6

0.4

0.7

%

V

V

I

CC2

I

CCmax2

C load

V

2fail t t

V2fail

V2short

Output current in active mode

Short circuit output current

Load capacitor

V

2

fail threshold

V

2

fail filter time

V

2

short filter time

Current limitation

Ceramic (+/- 20 %)

V

2

forced

200

0.22

(1)

300

2

4

100

500

2

1.

Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20 %). Capacitor must be located close to the regulator output pin.

mA mA

µF

V

µs ms

48/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 4.0 V < V

S

= 28 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 17.

Reset output

Symbol Parameter Test condition

V

V

RT1

V

RT2

RESET

Reset threshold voltage1

Reset threshold voltage2

V

RT3

V

RT4

Reset threshold voltage3

Reset threshold voltage4

VRT4 Reset threshold voltage4

Reset pin low output voltage

V

1

decreasing

V

1

decreasing

V

1

decreasing

V1

decreasing

V

1

increasing

V

1

> 1V, I

RESET

5 mA

=

R

RESET t

RR t

UV1

Trd

Reset pull up int. resistor

Reset reaction time

V

1

under-voltage filter time

Reset pulse duration

I

LOAD1

= 1 mA

Min.

Typ.

Max.

Unit

3.7

4.2

4.25

4.5

4.7

3.9

4.3

4.4

4.60

4.8

4.1

4.45

4.55

4.75

4.9

V

V

V

V

V

80

6

1.5

0,2

110

16

2

0,4

150

40

2.5

V k Ω

µs

µs ms

5.5.7 Watchdog

4.5 V < V

S

< 28 V; 4.8 V < V

Figure 26

and Figure 27 .

1

< 5.2 V; T j

= -40 °C to 130 °C, unless otherwise specified, see

Table 18.

Watchdog

Symbol Parameter t

LW

T

EFW1

T

LFW1

T

SW1

T

EFW2

T

LFW2

T

SW2

T

EFW3

T

LFW3

T

SW3

T

EFW4

T

LFW4

T

SW4

Long open window

Early failure window 1

Late failure window 1

Safe window 1

Early failure window 2

Late failure window 2

Safe window 2

Early failure window 3

Late failure window 3

Safe window 3

Early failure window 4

Late failure window 4

Safe window 4

TBD

Test condition Min.

48,75

20

7.5

100

37.5

200

75

400

150

Typ.

Max.

Unit

65 81,25

4.5

12

22.5

60

45

120

90

240 ms ms ms ms ms ms ms ms ms ms ms ms ms

Doc ID 16363 Rev 4 49/98

Electrical specifications

Figure 26.

Watchdog timing (long, early, late and safe window)

1RUPDOVWDUWXSRSHUDWLRQDQGWLPHRXWIDLOXUHV

FRUUHFWWULJJHUWLPLQJ

HDUO\WULJJHUWLPLQJ

PLVVLQJWULJJHU

7

/:

ORQJZLQGRZ

7

&:

FORVHGZLQGRZ

7

2:

RSHQZLQGRZ

7

:'5

ZDWFKGRJUHVHW

7

&:

7

2:

7

&:

7

2: 7

&:

7

/:

:'

WULJJHU

7

/:

7

/:

L99PM62XP

WULJJHUVLJQDO

WLPHPV

15(6

2XW

7

:'5

7

:'5

QRUPDORSHUDWLRQ PLVVLQJ

WULJJHU

0LVVLQJX&WULJJHUVLJQDO

HDUO\

ZULWH

WLPHPV

:'

WULJJHU

7

/:

7

/:

7

/:

WLPHPV

15(6

2XW

7

:'5

7

:'5

7

:'5

WLPHPV

$*9

50/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 27.

Watchdog early, late and safe windows

76:Q 6DIHZLQGRZ

7():Q (DUO\)DLOXUHZLQGRZ

7/):Q /DWHIDLOXUHZLQGRZ

7/):QBPLQ

76:QBPD[

76:QBPLQ

7():QBPD[

(DUO\

:DWFKGRJ

IDLOXUH

XQGHILQHG VDIHWULJJHUDUHD XQGHILQHG /DWH

ZDWFKGRJ

IDLOXUH

WLPH

$*9

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.8 V < V

1

< 5.2 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 19.

Output (OUT_HS)

Symbol Parameter

R

DS

ON

Static drain source on-resistance

(IOUT_HS = 150 mA)

Switch on delay time t d

ON t d

OFF Switch off delay time t

SCF

Short circuit filter time t d

ARHS Auto recovery filter time dV

OUT

/dt Slew rate

I

OUT

Short circuit shutdown current

I

OLD t

OLDT

Open-load detection current

I

FW

1

Open-load detection time

Loss of GND current

(ESD structure)

Test condition

T j

= 25 °C

T j

= 125 °C

0.2 V

S

0.8 V

S

Tested by scan chain

Tested by scan chain

Min.

5

40

0,18

Typ.

1,0

1.6

35

95

64*T

OSC

400*T

OSC

0,5

Max.

Unit

2

3

60

Ω

Ω

µs

150 µs

0,8 V/µs

Tested by scan chain

480

40

100

900

80

64*T

OSC

1320 mA

120 mA mA

Doc ID 16363 Rev 4 51/98

Electrical specifications L99PM62XP

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.8 V < V

1

< 5.2 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 20.

Outputs (OUT1...4)

Symbol Parameter

R t

DS

ON

OLDT

Static drain source on-resistance

(IOUT_HS = 150mA)

Open-load detection time

1.

Parameter guaranteed by design

I

T

LOAD j

= 60 mA @

= +25 °C

I

OUT

Short circuit shutdown current 8 V < V s

< 16 V

I

OLD

Open-load detection current 1 dV

OUT

/dt Slew rate

Switch ON delay time t dON t dOFF t

SCF

Switch OFF delay time

Short circuit filter time

0.2 V s

0.8 V s

Tested by scan chain

I

FW

(1)

Loss of GND current

(ESD structure)

Tested by scan chain

Min.

Typ.

7

140

0.9

0.2

5

30

235

2

0.5

35

95

64*T

OSC

350 mA

4.5

mA

0.8

V/µs

60

150

µs

µs

100 mA

64*T

OSC

Max.

Unit

13 Ω

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.8 V < V

1

< 5.2 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 21.

Relay drivers

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

R

DSON

I

OUT

V

Z t

ONHL

DC output resistance

Short circuit shutdown current

Output clamp voltage

(1)

Turn on delay time to 10% V

OUT

I

LOAD

8 V < V s

I

LOAD

= 100 mA @ T

< 16 V

= 100 mA j

= +25 °C

250

40

5

2

375

50

3

Ω

500 mA

48

100

V

µs t

OFFLH t

SCF

Turn off delay time to 90% V

Short circuit filter time

OUT

Tested by scan chain

5 50

64*T

OSC

100 µs dV

OUT

/dt Slew Rate 0.2

2 4

1.

The output is capable to switch off relay coils with the impedance of R

L dump condition)

= 160 Ω ; L = 300mH (R

L

= 220 Ω ; L = 420mH); at V

S

= 40V (Load

V/µs

52/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

5.5.10 Wake up inputs (WU1... WU3)

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 22.

Wake up inputs (WU1... WU3)

Symbol Parameter

V

V

WUthp

WUthn

Wake-up negative edge threshold voltage

Wake-up positive edge threshold voltage

V

HYST t

WU_stat

I

WU_stdby

Hysteresis

Static wake filter time

Input current in standby mode

R

WU_act

Input resistor to Gnd in active mode and in standby mode during wake-up request t

WU_cyc

Cyclic wake filter time

1.

Blanking time 80 µs or 800 µs.

1 V > V in

> (V s

- 2 V)

Min.

0,4*V s

0,5*V s

Typ.

0.45*V s

0,55*V s

Max.

Unit

0,5*V s

0,6*V s

0.05*V s

10

0.1*V s

64*T

OSC

20

0.15*V s

30

80 160

16

(1)

300

V

V

V

µs

µA k Ω

µs

5.5.11

High speed CAN transceiver

(b)

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

6 V < V

S

< 18 V; 4.8 V < Vcansup. < 5.2 V; T junction

= -40 °C to 130 °C, unless otherwise specified.

Table 23.

CAN transmit data input: pin TXDC

Symbol

V

TXDCLOW

Parameter Test condition

Input voltage dominant level

Active mode, V

1

= 5 V

V

TXDCHIGH

V

TXDCHYS

R

TXDCPU

Input voltage recessive level

Active mode, V

1

= 5 V

V

TXDCHIGH

-V

TXDCLOW

Active mode, V

1

= 5 V

TXDC pull up resistor Active mode, V

1

= 5 V

Min.

1.35

0.7

10

Typ.

1.8

2.5

1

20

Max.

2.8

35

Unit

V

V

V k Ω

Table 24.

CAN receive data output: pin RXDC

Symbol Parameter Test condition

V

RXDCLOW

V

RXDCHIGH

Output voltage dominant level Active mode, V

1

= 5 V, 2 mA

Output voltage recessive level Active mode, V

1

= 5 V, 2 mA

Min.

4.5

Typ.

Max.

Unit

0.2

0.5

V

V b.

ISO 11898-2 and ISO 11898-5 compliant; SAE J2284 compliant.

Doc ID 16363 Rev 4 53/98

Electrical specifications L99PM62XP

Table 25.

CAN bus common mode stabilization output termination: pin SPLIT

Symbol Parameter Test Condition Min.

Typ.

V

SPLIT,l

Split output voltage, loaded condition (normal mode)

Active mode;

V

TXDC

= V

TXDCHIGH

;

|Isplit| = 500 µA

V

SPLIT,u

Split output voltage, unloaded condition (normal mode)

I

SPLIT

Split leakage current (low power mode)

Active mode;

V

TXDC

= V

TXDCHIGH

; No Load

V

1

-standby mode;

-12 V < V

SPLIT

< 12 V

Max.

0.3*

V

CANSUP

0.5*

V

CANSUP

0.7*

V

CANSUP

0.5*

V

CANSUP

0.55*

V

CANSUP

5

Unit

V

V

µA

Table 26.

CAN transmitter and receiver: pins CANH and CANL

Symbol Parameter Test Condition

V

V

V

DIFF,domOUT

V

CANHdom

CANLdom

V

CM

CANHrec

CANH voltage level in dominant state

Active mode;

V

TXDC

R

L

= V

= 60 Ω

TXDCLOW

;

CANL voltage level in dominant state

Active mode;

V

TXDC

R

L

= V

= 60 Ω

TXDCLOW

;

Differential output voltage in dominant state:

V

CANHdom

- V

CANLdom

Driver symmetry:

V

CANHdom

+ 0V

CANLdom

Active mode;

V

TXDC

R

L

= V

= 60 Ω

TXDCLOW

;

Active mode;

V

TXDC

R

L

= V

= 60 Ω ;

TXDCLOW

;

C

SPLIT

= 4.7 pF

CANH voltage level in recessive state (normal mode)

Active mode;

V

TXDC

= V no load

TXDCHIGH

;

V

V

CANLrec

CANHrecLP

CANL voltage level in recessive state (normal mode)

Active mode;

V

TXDC

= V no load

TXDCHiGH

;

CANH voltage level in recessive state (low power mode)

V

1

standby mode;

V

TXDC no load

= V

TXDCHIGH

;

V

V

CANLrecLP

DIFF,recOUT

V

DIFF,recOUTL

P

CANL voltage level in recessive state (low power mode)

V

1

standby mode;

V

TXDC

= V

TXDCHiGH

; no load

Differential output voltage in recessive state (normal mode):

V

CANHrec

- V

CANLrec

Differential output voltage in recessive state (low power mode): V

CANHrec

- V

CANLrec

Active mode;

V

TXDC no load

= V

TXDCHIGH

;

V

1

V

standby mode;

TXDC no load

= V

TXDCHIGH

;

Min.

2.75

0.5

1.5

Typ.

Max.

Unit

4.5

2.25

3

0.9*

V

CANSUP

V

CANSUP

1.1*

V

CANSUP

2

2

-0.1

-0.1

-50

-50

2.5

2.5

0

0

3

3

0.1

0.1

50

50

V

V

V

V

V

V

V

V mV mV

54/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Table 26.

CAN transmitter and receiver: pins CANH and CANL (continued)

Symbol Parameter Test Condition Min.

Typ.

V

CANHL,CM

I

OCANH,dom

I

OCANL,dom

I

Leakage

R in

R in,diff

C in

C in,diff

V

THdom

V

THdomLP

V

THrec

V

THrecLP

Common mode Bus voltage

CANH output current in dominant state

CANL output current in dominant state

Input leakage current

Internal resistance

Differential receiver threshold voltage dominant to recessive state (normal mode)

Differential receiver threshold voltage dominant to recessive state (low power mode)

Measured with respect to the ground of each CAN node

Active mode;

V

TXDC

V

CANH

= V

TXDCLOW

;

= 0 V

Active mode;

V

TXDC

V

CANL

= V

TXDCLOW

;

= 5 V

Unpowered device;

V

BUS

= 5 V

Active mode & V

1 standby mode;

V

TXDC no load

= V

TXDCHIGH

;

Differential internal resistance Active mode & V

1 standby mode;

V

TXDC no load

= V

TXDCHIGH

;

Internal capacitance Guaranteed by design

Differential internal capacitance Guaranteed by design

Active mode Differential receiver threshold voltage recessive to dominant state (normal mode)

Differential receiver threshold voltage recessive to dominant state (low power mode)

V

1

standby mode

Active mode

V

1

standby mode

-12

-160

45

0

20

50

0.5

0.4

-75

75

27.5

60

20

10

Max.

Unit

12 V

-45 mA

160 mA

250 µA

38

75

0.9

1.15

k Ω k Ω pF pF

V

V

V

V

Table 27.

CAN transceiver timing

Symbol Parameter tTXpd,hl tTXpd,lh t wake

Propagation delay TXDC to

RXDC (high to low)

Propagation delay TXDC to

RXDC (low to high)

Wake up filter time

Test condition

Active mode; 50 % V

TXDC

to 50 %

V

RXDC

; C

RXDC

= 100 pF; R

L

= 60

Ω

Active mode; 50 % V

TXDC

to 50 %

V

RXDC

; C

RXDC

= 100 pF; R

L

= 60

Ω

Min.

Typ.

Max.

Unit

0 255 ns

0

0.5

255

5 ns

µs

Doc ID 16363 Rev 4 55/98

Electrical specifications

Table 27.

CAN transceiver timing (continued)

Symbol Parameter Test condition t dom(TXDC) t

CAN

TXDC dominant time-out

CAN permanent dominant time-out

L99PM62XP

Min.

Typ.

Max.

Unit

700 µs

700 µs

5.5.12

LIN transceiver

(c)

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

6 V < V

S

< 18 V; 4.8 V < V

1

< 5.2 V; T junction

= -40 °C to 130 °C unless otherwise specified.

Table 28.

LIN transmit data input: pin TXD

Symbol Parameter Test condition

V

TXDLOW

V

TXDHIGH

V

TXDHYS

R

TXDPU

Input voltage dominant level Active mode; V

1

= 5 V

Input voltage recessive level Active mode; V

1

= 5 V

V

TXDHIGH

-V

TXDLOW

TXD pull up resistor

Active mode; V

Active mode; V

1

1

= 5 V

= 5 V

Min.

Typ.

Max.

Unit

1,35 1.8

0.7

10

2.5

1

20

2.8

35

V

V

V k Ω

Table 29.

LIN receive data output: pin RXD

Symbol Parameter Test condition

V

RXDLOW

V

RXDHIGH

Output voltage dominant level

Active mode;

V

1

= 5 V, I

LOAD1

= 2 mA

Output voltage recessive level

Active mode;

V

1

= 5 V, I

LOAD1

= 2 mA

Table 30.

LIN transmitter and receiver: pin LIN

Symbol Parameter Test condition

V

THdom

V

THrec

V

THhys

V

THcnt

V

THwkup

Receiver threshold voltage recessive to dominant state

Receiver threshold voltage dominant to recessive state

Receiver threshold hysteresis:

V

THrec

-V

THdom

Receiver tolerance center value: (V

THrec

+V

THdom

)/2

Receiver wakeup threshold voltage

Min.

Typ. Max.

Unit

0.2

0.5

V

4.5

V

Min.

Typ.

Max.

0.4*V

S

0.45*V

S

0.5*V

S

Unit

V

0.5*V

S

0.55*V

S

0.6*V

S

V

0.07*V

S

0.1*V

S

0.175*V

S

V

0.475*V

S

0.5*V

S

0.525*V

S

V

1.0

1.5

2 V c.

LIN 2.1 compliant for Baud rates up to 20 kBit/s

SAE J2602 compatible

56/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Table 30.

LIN transmitter and receiver: pin LIN (continued)

Symbol Parameter Test condition

V

THwkdwn

Receiver wakeup threshold voltage t linbus

Dominant time for wakeup via bus

Sleep mode; edge: rec-dom

I bus_PAS_dom

I

I

LINDomSC bus_PAS_rec

Transmitter input current limit in dominant state

V

TXD

= V

TXDLOW

;

V

LIN

= V

BATMAX

= 18 V

Input leakage current at the receiver incl. pull-up resistor

Transmitter input current in recessive state

V

TXD

V

LIN

= V

TXDHIGH

;

= 0 V; V

BAT

= 12 V

(1)

V

TXD

= V

TXDHIGH

;

8 V < V

LIN

;

V

BAT

< 18 V; V

LIN

>= V

BAT in standby modes

I bus_NO_GND

V

V

LINdom

R

I bus

LINrec

LINup

1.

Slave mode.

Input current if loss of GND at device

Input current if loss of V device

BAT

LIN voltage level in dominant state

LIN voltage level in recessive state

LIN output pull up resistor

at

GND = V

S

;

0 V < V

LIN

< 18 V;

V

BAT

= 12 V

GND = V

S

;

0 V < V

LIN

< 18 V

Active mode;

I

V

TXD

LIN

= V

TXDLOW

= 40 mA

;

Active mode;

I

V

TXD

LIN

= V

TXDHIGH

= 10 µA

;

V

LIN

= 0 V

Min.

V

S

-3.5

40

-1

-1

0.8*V

S

20

Typ.

V

S

-2.5

64*T

OSC

100

40

Max.

V

S

-1.5

180

20

1

100

1.2

1

60

Unit

V

µs mA mA

µA mA

µA

V

V k Ω

Table 31.

LIN transceiver timing

Symbol Parameter Test condition t

RXpd t

RXpd_sym

Receiver propagation delay time

Symmetry of receiver propagation delay time

(rising vs. falling edge) t

RXpd

= max(t

RXpdr

, t

RXpdf

); t

RXpdf

= t(0.5 V

RXD

) - t(0.45 V

LIN

); t

RXpdr

= t(0.5 V

RXD

) - t(0.55 V

LIN

);

V

S

= 12 V; C

RXD

= 20 pF;

R bus

, = 1 k Ω , C bus

= 1 nF;

R bus

= 660 Ω , C bus

= 6.8 nF;

R bus

= 500 Ω , C bus

= 10 nF t

RXpd_sym

= t

RXpdr

- t

RXpdf

;

V

S

= 12 V;

R bus

= 1 k

Ω

, C bus

= 1 nF

Min.

Typ.

Max.

Unit

-2

6

2

µs

µs

Doc ID 16363 Rev 4 57/98

Electrical specifications

Table 31.

LIN transceiver timing (continued)

Symbol Parameter Test condition

D1

D2

D3

D4

Duty cycle 1

Duty cycle 2

Duty cycle 3

Duty cycle 4

TH

Rec

(max) = 0.744*V

S

;

TH

Dom

(max) = 0.581*V

S

;

V

S

= 7 V to 18 V, t bit

= 50 µs;

D1 = t bus_rec

(min)/(2xt bit

);

R

R

R bus bus bus

= 1 k

Ω

, C

= 660 Ω bus

, C

= 500

Ω

, C

= 1 nF; bus bus

= 6.8 nF;

= 10 nF

TH

Rec

(min) = 0.284*V

S

;

TH

Dom

(min) = 0.422*V

S

;

V

S

= 7.6 to 18 V, t bit

= 50 µs;

D2 = t bus_rec

(max)/(2xt bit

);

R

R

R bus bus bus

= 1 k Ω , C

= 660

Ω bus

, C

= 500 Ω , C

= 1 nF; bus bus

= 6.8 nF;

= 10 nF

TH

Rec

(max) = 0.778*V

S

;

TH

Dom

(max) = 0.616*V

S;

V

S

= 7 V to 18 V, t bit

= 96 µs;

D3 = t bus_rec

(min)/(2xt bit

);

R

R

R bus bus bus

= 1 k

Ω

, C

= 660 Ω bus

, C

= 500 Ω , C

= 1 nF; bus bus

= 6.8 nF;

= 10 nF

TH

Rec

(min) = 0.251*V

S

;

TH

Dom

(min) = 0.389*V

S

;

V

S

= 7.6 V to 18 V, t bit

= 96 µs;

D4 = t bus_rec

(max)/(2xt bit

);

R

R

R bus bus bus

= 1 k Ω , C

= 660 Ω bus

, C

= 500 Ω , C

= 1 nF; bus bus

= 6.8 nF;

= 10 nF t dom(TXDL)

TXDL dominant time-out t

LIN

LIN permanent recessive time-out t dom(BUS)

LIN bus permanent dominant time-out

Table 32.

LIN pull-up: pin LINPU

Symbol Parameter

RDS

ON

I leak

ON resistance

Leakage current

Test condition

L99PM62XP

Min.

Typ.

Max.

Unit

0.396

0.417

12

40

12

0.581

0.590

Min.

Typ.

Max.

Unit

10.5

16

1

Ω

µA ms

µs ms

58/98 Doc ID 16363 Rev 4

L99PM62XP

Figure 28.

LIN transmit, receive timing

W

7;SGI

9

7['

9

/,1

9

7+UHF

9

7+GRP

9

/,1GRP

9

5['

W

5;SGI

9

/,1UHF

W

7;SGU

Electrical specifications

WLPH

W

5;SGU

WLPH

WLPH

$*9

Note:

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; T j

= -40 °C to 130 °C, unless otherwise specified.

Table 33.

Operational amplifier

Symbol Parameter Min.

Typ.

Max.

GBW GBW product

AVOL

DC

DC open loop gain

PSRR Power supply rejection

1

80

3.5

7.0

DC, Vin = 150 mV 80

V off

Input offset voltage -5 +5

V

ICR

V

OH

V

OL

I

Lim+

Common mode input range

Output voltage range high I

LOAD

Output voltage range low I

LOAD

Output current limitation + DC

I lim-

Output current limitation -

SR+ Slew rate positive

DC

= 1 mA to V

S

-0.2

0

10

-10

1

0 3

= 1 mA to Gnd V

S

-0.2 V

S

15

15

4

0.2

30

-30

10

SRSlew rate negative -1 -4 -10

Unit

V

V

V mA

MHz dB dB mV mA

V/µs

V/µs

The operational amplifier is on-chip stabilized for external capacitive loads C

L

< 25 pF (all operating conditions)

Doc ID 16363 Rev 4 59/98

Electrical specifications L99PM62XP

5.5.14 SPI

Input: CSN

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.5 V < V

130 °C, unless otherwise specified.

1

< 5.3 V; all outputs open; T j

= -40 °C to

Input: CSN

Table 34.

Input: CSN

Symbol Parameter

VCSNLOW Input voltage low level

VCSNHIGH Input voltage high level

VCSNHYS VCSNHIGH - VCSNLOW

ICSNPU CSN pull up resistor

Test condition

Normal mode, V

1

= 5 V

Normal mode, V

1

= 5 V

Normal mode, V

1

= 5 V

Normal mode, V

1

= 5 V

Min.

Typ.

Max.

Unit

1.35

0.6

10

1.8

2

1.0

20

2.8

1.5

35

V

V

V k Ω

CLK, DI

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.5 V < V

1

< 5.3 V; all outputs open; T j

= -40 °C to

130 °C, unless otherwise specified.

Table 35.

Input CLK, DI

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

V in H

V in Hyst

C f t

V

I set in L

in in

(1)

CLK delay time from standby to active mode

Switching from standby to active mode. Time until output drivers are enabled after CSN going to high.

input low level input high level input hysteresis

V

1

= 5 V

V

1

= 5 V

V

1

= 5 V pull down current at input

V in

= 1.5 V input capacitance at input CSN, CLK, DI and

PWM

1,2

0 V < V

1

< 5.3 V

SPI input frequency at

CLK

1.0

1.5

0.4

5

160

2.05

2.8

0.75

30

10

1.

Value of input capacity is not measured in production test. Parameter guaranteed by design.

300

2.5

3.5

1.5

60

15

1

µs

µA pF

MHz

V

V

V

DI timing

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.5 V < V

130 °C, unless otherwise specified.

1

< 5.3 V; all outputs open; T j

= -40 °C to

60/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Table 36.

DI timing

(1)

Symbol Parameter Test condition t t t t t t

CLK

CLKH

CLKL set CSN set CLK t set DI hold DI t t r in f in

Clock period

Clock high time

V

1

= 5 V

V

1

= 5 V

Clock low time V

1

= 5 V

CSN setup time, CSN low before rising edge of CLK

V

1

= 5 V

CLK setup time, CLK high before rising edge of CSN

V

1

= 5 V

DI setup time V

1

= 5 V

V

1

= 5 V DI hold time

Rise time of input signal

DI, CLK, CSN

V

1

= 5 V

Fall time of input signal

DI, CLK, CSN

V

1

= 5 V

1.

See

Figure 30

.

Min.

1000

400

400

400

Typ.

Max.

Unit

-

-

ns ns ns

ns

400

200

200 -

-

-

-

ns ns ns

100 ns

100 ns

DO

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.5 V < V

130 °C, unless otherwise specified.

1

< 5.3 V; all outputs open; T j

= -40 °C to

Table 37.

DO output pin

Symbol Parameter

V

DOL

V

DOH

I

DOLK

C

DO

2

Test condition

Output low level V

1

= 5 V, I

D

= -4 mA output high level V = 5 V, I

D

= 4 mA

3-state leakage current V

CSN

= V

1

, 0 V < V

DO

< V

1

3-state input capacitance

V

CSN

= V

1

,

0 V < V

1

< 5.3 V

Min.

Typ.

Max.

0.5

4.5

-10 10

10 15

Unit

V

V

µA pF

DO timing

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.5 V < V

1

< 5.3 V; all outputs open; T j

= -40 °C to

130 °C, unless otherwise specified.

Table 38.

DO timing

(1)

Symbol Parameter t t r DO f DO t en DO tri L

DO rise time

DO fall time

DO enable time from 3-state to low level

Test condition

C

L

= 100 pF, I

LOAD

= -1 mA

C

L

= 100 pF, I

LOAD

= 1 mA

C

L

= 100 pF, I

LOAD

= 1 mA pull-up load to V

1

Min.

Typ.

Max.

Unit

-

50

50

100

100 ns ns

50 250 ns

Doc ID 16363 Rev 4 61/98

Electrical specifications L99PM62XP

Table 38.

DO timing

(1)

(continued)

Symbol Parameter t dis DO L tri

DO disable time from low level to 3-state t en DO tri H

DO enable time from 3-state to high level t dis DO H tri

DO disable time from high level to 3-state t d DO

DO delay time

Test condition

C

L

= 100 pF, I

LOAD

= 4 mA pull-up load to V

1

C

L

= 100 pF, I

LOAD

= -1 mA pull-down load to GND

C

L

= 100 pF, I

LOAD

= -4 mA pull-down load to GND

V

DO

< 0.3 V

1

,

V

DO

> 0.7 V

1

,

C

L

= 100 pF

1.

See

Figure 31

and Figure 32 .

Min.

Typ.

Max.

Unit

-

-

-

50

50

50

50

250

250

250

250 ns ns ns ns

CSN timing

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

S

< 18 V; 4.5 V < V

130 °C, unless otherwise specified.

1

< 5.3 V; all outputs open; T j

= -40 °C to

Table 39.

CSN timing

(1)

Symbol Parameter tCSN_HI,min

Minimum CSN HI time, active mode t

CSNfail

1.

See

Figure 33

.

CSN low timeout

Test Condition

Transfer of SPI-command to Input register

Tested by scan chain

Min. Typ. Max. Unit

6 µs

20 35 50 ms

6 V

≤

Vs

≤

18 V; 4.5 V

≤

V

1

≤

5.3 V; T j

= -40 °C to 130 °C, voltages are referred to PGND, all outputs open

Table 40.

Inputs TxD_C and TxD_L for Flash mode

Symbol Parameter Test condition

V

FlashL

V

FlashH

V

FlashHYS

Input low level (V

TXDC/L

rising) V

1

= 5 V

Input high level (V

TXDC/L

falling) V

1

= 5 V

Input Voltage Hysteresis V

1

= 5 V

Min.

Typ.

Max.

Unit

6.1

7.4

0.6

7.25

8.4

0.8

8.4

9.4

1.0

V

V

V

62/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 29.

SPI – transfer timing diagram

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&61

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The SPI can be driven by a micro controller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

Figure 30.

SPI - input timing

&61

9&&

9&&

W

VHW &61

W

&/.+

W

VHW &/.

&/.

9&&

9&&

W

VHW ',

W

KROG ',

W

&/./

', 9DOLG 9DOLG

9&&

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$*9

Doc ID 16363 Rev 4 63/98

Electrical specifications

Figure 31.

SPI output timing (part 1)

7I

&/.

&/.

7U

'2

'2

ORZWRKLJK

7G

'2

7I

'2

'2

KLJKWRORZ

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&/.

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L99PM62XP

9FF

9FF

9FF

7HQ

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7GLV

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7HQ

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Doc ID 16363 Rev 4

7GLV

'2B+BWUL

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9FF

9FF

9FF

9FF

9FF

9FF

9FF

L99PM62XP Electrical specifications

Figure 32.

SPI output timing (part 2)

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Figure 33.

SPI – CSN low to high transition and global status bit access

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Doc ID 16363 Rev 4 65/98

ST SPI L99PM62XP

6.1 SPI communication flow

6.1.2

The proposed SPI communication is based on a standard SPI interface structure using CSN

(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock) signal lines.

At device start-up the master reads the <SPI-frame-ID> register (ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length (24bit) and the availability of additional features.

Each communication frame consists of an instruction byte which is followed by 2 data bytes.

The data returned on SDO within the same frame always starts with the <Global Status> register. It provides general status information about the device. It is followed by 2 data bytes (i. e. ‘In-frame-response’).

For write cycles the <Global Status> register is followed by the previous content of the addressed register.

For read cycles the <Global Status> register is followed by the content of the addressed register.

A write command is only accepted as a valid command by the device if the counted number of clocks is exact 24, otherwise the command is rejected.

Command byte

Each communication frame starts with a command byte. It consists of an operating code which specifies the type of operation (<Write>, <Read>, <Read and Clear>, <Read Device

Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits are unused but are reserved.

Table 41.

Command byte

MSB

OC1

Op code

OC0 A5 A4 A3

Address

A2 A1

LSB

A0

OCx: operating code

Ax: address

Operating code definition

Table 42.

Operating code definition

OC1 OC0

0

0

0

1

Meaning

<Write Mode>

<Read Mode>

66/98 Doc ID 16363 Rev 4

L99PM62XP

Table 42.

Operating code definition (continued)

OC1

1

1

OC0

0

1

Meaning

<Read and Clear Status>

<Read Device Information>

ST SPI

The <Write Mode> <Read Mode> and <Read and Clear Status> operations allow access to the RAM of the device, i. e. to write to control registers or read status information.

A <Read and Clear Status> operation addressed to a device specific status register reads back and subsequently clear this status register.

A <Read and Clear Status> operation with address 3FH clears all status registers (including the Global Status Register). Configuration register is read by this operation.

<Read Device Information> allows access to the ROM area which contains device related information such as the product family, product name, silicon version, register width and availability of a watchdog.

More detailed descriptions of the device information are available in ‘Read Device

Information’.

register

(d)

Table 43.

Global status register

Bit 7 Bit 6 Bit 5

Global error flag (GEF)

Comm error

Not (chip reset

OR comm error)

Bit 4

TSD2

Bit 3

TSD1

Bit 2

V

1

Fail

Bit 1

VS Fail

(OV/UV)

Bit 0

Fail safe

The <Configuration> register is accessible at RAM address 3FH.

For the config register, the 8 bits are located in the low byte (LSB).

The configuration register is implemented for compliance purpose to ST SPI standard.

Table 44.

Configuration register

Bit 7 Bit 6 Bit 5 Bit 4

0 0 0 0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

WD trigger

<WD trigger>: this bit is reserved to serve the watchdog.

d.

See

Section 6.2

for details.

Doc ID 16363 Rev 4 67/98

ST SPI

Figure 34.

Read configuration register

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1.

The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the watchdog trigger bit at D0

Figure 35.

Write configuration register

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1.

The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the watchdog trigger bit at D0

68/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

Table 45.

Address mapping

RAM adress

Description

3FH

13H

12H

11H

06H

05H

04H

03H

02H

01H

00H

<Configuration>

Status register 3

Status register 2

Status register 1

Control register 6

Control register 5

Control register 4

Control register 3

Control register 2

Control register 1

Reserved

Access

R/W

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

ROM adress

3FH

3EH

…

03H

Description

Reserved

<SPI frame ID>

Unused

<product code 2>

Access

N/A

R

N/A

N/A

02H

01H

00H

<product code 1>

<silicon version>

<ID Header>

R

R

R

The RAM memory area consists of 16 bit registers.

For the device information (ROM memory area) the eight most significant bits of the memory cell are used. The remaining 8 are zero.

All unused RAM and ROM addresses is read as ‘0’.

Note: 1 The register definition for RAM address 00H is unused. A register value of all 0 must cause the device to enter a fail-safe state (interpreted as ‘SDI stuck to GND’ failure).

2 ROM address 3FH is unused. An attempt to access this address must be recognized as a

communication error (‘SDI stuck to V

CC

’ failure) and must cause the device to enter a failsafe state.

The write operation starts with a command byte followed by 2 data bytes. The number of data bytes is specified in the <SPI-frame-ID>.

Write command format

Table 46.

Write command format: command byte

MSB

Op Code Address

0 0 A5 A4 A3 A2 A1

LSB

A0

Doc ID 16363 Rev 4 69/98

ST SPI

6.1.7

L99PM62XP

Table 47.

Write command format: data byte 1

MSB

D15 D14 D13 D12 D11

Table 48.

Write command format: data byte 2

MSB

D7 D6 D5 D4 D3

D10 D9

LSB

D8

D2 D1

LSB

D0

OC0, OC1: operating code (00 for ‘write’ mode)

A0 to A5: address bits

An attempt to write 00H at RAM address 00H is recognized as a failure (SDI stuck to GND).

The device enters a fail-safe state.

Format of data shifted out at SDO during write cycle

Table 49.

Format of data shifted out at SDO during write cycle: global status register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error flag (GEF)

Comm error

Not (chip reset or comm error)

TSD2 TSD1 V

1

Fail

V

S

Fail

(OV/UV)

Fail safe

Table 50.

Format of data shifted out at SDO during write cycle: data byte 1

MSB Previous content of addressed register LSB

D15 D14 D13 D12 D11 D10 D9 D8

Table 51.

Format of data shifted out at SDO during write cycle: data byte 2

MSB Previous content of addressed register LSB

D7 D6 D5 D4 D3 D2 D1 D0

Failures are indicated by activating the corresponding bit of the <Global Status> register.

The returned data byte(s) represent(s) the previous content of the accessed register.

70/98 Doc ID 16363 Rev 4

L99PM62XP

Figure 36.

Format of data shifted out at SDO during write cycle

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The read operation starts with a command byte followed by 2 data bytes. The number of data bytes is specified in the <SPI-frame-ID>. The content of the data bytes is ‘don’t care’.

The content of the addressed register is shifted out at SDO within the same frame (‘in-frame response’).

Read command format

Table 52.

Read command format: command byte

MSB

Op Code Address

0 1 A5 A4 A3 A2 A1

LSB

A0

Table 53.

Read command format: data byte 1

MSB

0 0 0 0 0

Table 54.

Read command format: data byte 2

MSB

0 0 0 0 0

OC0, OC1: operating code (01 for ‘read’ mode)

A0 to A5: address bits

0

0

0

0

LSB

0

LSB

0

Doc ID 16363 Rev 4 71/98

ST SPI

6.1.9

L99PM62XP

Format of data shifted out at SDO during read cycle

Table 55.

Format of data shifted out at SDO during read cycle: global status register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error flag (GEF)

Comm error

Not (chip reset or comm error)

TSD2 TSD1 V

1

Fail

V

S

Fail

(OV/UV)

Fail safe

Table 56.

Format of data shifted out at SDO during read cycle: data byte 1

MSB Previous content of addressed register LSB

D15 D14 D13 D12 D11 D10 D9 D8

Table 57.

Format of data shifted out at SDO during read cycle: data byte 2

MSB Previous content of addressed register LSB

D7 D6 D5 D4 D3 D2 D1 D0

Failures are indicated by activating the corresponding bit of the <Global Status> register.

The returned data byte(s) represent(s) the content of the register to be read.

Figure 37.

Format of data shifted out at SDO during read cycle

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6.1.10 Read and clear status operation

The ‘Read and Clear Status’ operation starts with a command byte followed by 2 data bytes.

The number of data bytes is specified in the <SPI-frame-ID>. The content of the data bytes

72/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI is ‘don’t care’. The content of the addressed status register is transferred to SDO within the same frame (‘in-frame response’) and is subsequently cleared.

A ‘Read and Clear Status’ operation with address 3FH clears all status registers (incl. the

<Global Status> register). The configuration register is read by this operation.

Read and clear status command format

Table 58.

Read and clear status command format: command byte

MSB

1

Op Code

01 A5 A4 A3

Address

A2 A1

LSB

A0

Table 59.

Read and clear status command format: data byte 1

MSB

0 0 0 0 0 0

Table 60.

Read and clear status command format: data byte 2

MSB

0 0 0 0 0 0

0

LSB

0

0

LSB

0

OC0, OC1: operating code (10 for ‘read and clear status’ mode)

A0 to A5: address bits

Format of data shifted out at SDO during read and clear status operation

Table 61.

Format of data shifted out at SDO during read and clear status: global status register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error flag (GEF)

Comm error

Not (chip reset or comm error)

TSD2 TSD1 V

1

Fail

V

S

Fail

(OV/UV)

Fail safe

Table 62.

Format of data shifted out at SDO during read and clear status: data byte 1

MSB Previous content of addressed register

D15 D14 D13 D12 D11 D10 D9

LSB

D8

Table 63.

Format of data shifted out at SDO during read and clear status: data byte 2

MSB Previous content of addressed register LSB

D7 D6 D5 D4 D3 D2 D1 D0

Doc ID 16363 Rev 4 73/98

ST SPI L99PM62XP

Failures are indicated by activating the corresponding bit of the <Global Status> register.

The returned data byte(s) represent(s) the content of the register to be read.

Figure 38.

Format of data shifted out at SDO during read and clear status operation

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6.1.11 Read device information

The device information is stored at the ROM addresses defined below and is read using the respective operating code.

Table 64.

Op code

Read device information

OC1 OC0

ROM address

1 1

1

1

1

1

1

1

1

1

1

1

1

1

Device information Value

3FH

3EH

Reserved

<SPI frame ID> includes frame width and availability of watchdog

04H to 3DH unused

03H

02H

<product code 2> unique product identifier

<product code 1> unique product identifier

01H

00H

<silicon version> indicates Design Version

<ID Header> device family max adress of device information

00

42 Hex

00

4E Hex

44 Hex

According to silicon version

43 Hex

74/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

The <ID-Header> (ROM address 00H) indicates the product family and specifies the highest address which contains product information

Table 65.

ID-header

Bit 7 Bit 6 Bit 5

0

Family Identifier

1

Bit 4 Bit 3 Bit 2

0 0 0 0

Highest address containing device information

Bit 1

1

Bit 0

1

<Family Identifier>: 01 Hex (BCD)

<Highest address>: 03 Hex

Table 66.

Family identifier

Bit 7 Bit 6

0

0

1

1

0

1

0

1

Meaning

VIPower

BCD

VIPower hybrid

Tbd

The <Product Code 1> (ROM address 02H) and <Product Code 2> (ROM address 03H) represents a unique code to identify the product name.

<Product Code 1> 44 Hex

<Product Code 2> 4E Hex

The <Silicon Version> (ROM address 01H) provides information about the silicon version according to the table below:

Table 67.

Silicon version identifier

Bit 7 Bit 6 Bit 5 Bit 4

Reserved

Bit 3 Bit 2 Bit 1

Silicon version

Bit 0

The <SPI-frame-ID> (ROM address 3EH) provides information about the register width (1,

2, 3 bytes) and the availability of ‘Burst Mode Read’ and watchdog.

Table 68.

SPI-frame-ID

Bit 7 Bit 6 Bit 5

0

BR

1

WD

0

X

Bit 4

0

X

Bit 3

0

X

Bit 2

0

32-bit

Bit 1

1

24-bit

Bit 0

0

16-bit

BR: burst-mode read (1 = burst-mode read is supported)

WD: watchdog (1 = available, 0 = not available)

32-bit, 24-bit, 16-bit: width of SPI frame (see table below)

Doc ID 16363 Rev 4 75/98

ST SPI

<Burst Mode>: not supported

<Watchdog>: available

<Frame Width>: 24 bit

L99PM62XP

6.2.1 Overview

Overview command byte

Table 69.

SPI register: command byte

Read/write x x x x x

Address x

Table 72.

SPI register: STAT register selection

STAT register. 1…3

0

0

0

1

1

1

0

0

0

0

0

0

0

1

1

1

0

1

Overview of control register data bytes x x

Table 70.

SPI register: mode selection

Read/write

0

0

1

1

0

1

0

1

Table 71.

SPI register: CTRL register selection

CTRL register 1…6

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

1

0

1

1

0

1

0

1

0

1

Mode selection

Write

Read

Read and clear

Read device info

CTRL register selection

CTRL register1

CTRL register2

CTRL register3

CTRL register4

CTRL register5

CTRL register6

STAT register selection

STAT register1

STAT register2

STAT register3

76/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

Table 73.

Overview of control registers data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Defaults 0 0

Function

OUT

HS

OUT

HS

Group

0

OUT

4

0 0

OUT

4

OUT

HS_EXT

HS control

0

OUT

3

Defaults

Function Res Res

Group

0

Inp.

Filt 3

0

Inp.

Filt 3

0

Inp.

Filt 2

Wake-up control

0

Inp.

Filt 2

Control register 1, data

0

OUT

2

0

OUT

1

0

REL

2

0

REL

1

0

V

2

0

V

2

Res

0

Stby sel

LS Output, V

2

and mode control

0

Go

Stby

Control register 2, data

0

Inp.

Filt 1

0

Inp.

Filt1

0 0 0 0

Res

Input

Pu/Pd 3

Input

Pu/Pd 2

Input

Pu/Pd 1

Res

Wake-up control

1

WU

EN 3

Control register 3, data

1

WU

EN 2

0

Trig

1

WU

EN 1

Defaults

Function Res

T1

On

Group

0 0

T1

Per

0

T1

Per

Res

Timer Settings

0

T2

On

0

T2

Per

0

T2

Per

Res Res

0

WD time

0

WD time

1

LIN

WU

En

1

CAN

WU

En

Watchdog and cyclic wake up settings

0

Wake timer

En

0

Wake

Timer

Select

Control register 4, data

1 0 Defaults

Group

0

Function Res I

CMP

0

OutHS

Rec

En

1

Vlock

Out

En

Res

Control (other)

1 0

LS

OV/UV shut down_en

V

1

Reset

Level

0

V

1

Reset

Level

1

LIN

Pu

En

1

Res

Control register 5, data

1

Lin

TxD

Tout

En

1

CAN

ACT

0

CAN

Loop

En

Transceiver settings

1

CAN

Patt.

wake

En

CAN split

On

CAN

Rec

Only

Defaults 1 1 1

Function Res

PWM2

Off-

DC

PWM2

Off-

DC

PWM2

Off-

DC

Group

1

PWM2

Off-

DC

PWM2 setting

1

PWM2

Off-

DC

1 1 0 0 0 0 0 0 0 0

PWM2

Off-

DC

PWM2

Off-

DC

PWM

Freq

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1 setting

Control register 6, data

Defaults

Function Res

Group

1

PWM4

Off-DC

1

PWM4

Off-DC

1

PWM4

Off-DC

1

PWM4

Off-

DC

PWM4 setting

1

PWM4

Off-

DC

1 1

PWM4

Off-DC

PWM4

Off-DC

Res

0 0 0 0 0 0 0

PWM3

ON-

DC

PWM3

ON-

DC

PWM3

ON-

DC

PWM3

ON-

DC

PWM3

ON-

DC

PWM3

ON-

DC

PWM3

ON-

DC

PWM3 setting

Doc ID 16363 Rev 4 77/98

ST SPI L99PM62XP

Control register 1

Table 74.

Control register 1: command and data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 0 0 0 0 1 Data, 8bit

2 nd

data byte

Data, 8 bit

Table 75.

Control register 1, data bytes

1 st

data byte <15:8>

Defaults

Function

Group

0

OUT

HS_2

0

OUT

HS_1

0

OUT

4_2

0

OUT

4_1

HS control

0

OUT

HS_EXT

0

OUT

3

0

OUT

2

0

OUT

1

0

REL

2

2 nd

data byte <7:0>

0

REL

1

V

0

2_2

V

0

2_1

Res

0

Stby sel

LS Output, V

2

and mode control

0

Go

Stby

0

Trig

Table 76.

Control register 1, bits

Bit Name

OUTHS 15

14

Select mode of OUTHS

OUTHS_EXT OUTHS_2

0

1

1

0

0

0

1

1 x

0

0

1

Comment

OUTHS_1

1

0

1

0

1

0

Mode

HS off

HS cyclic on with timer 1

HS controlled by PWM4

HS cyclic on with Timer 2

PWM3

(1)

HS on

Active and standby mode

1) PWM4 (CR6) must be unequal 0% in order to enable PWM3

To turn off OUT4, we recommend to use the setting 'HS Off' (OUT4_1 = 0, OUT4_2 = 0)

13

12

OUT4 Select mode of OUT4

OUT4_2 OUT4_1

0

0

0

1

1 0

1 1

Mode

HS off

HS on

HS controlled by PWM4

Active and standby mode

HS cyclic on with Timer 2

11 OUTHS_EXT Extended function of OUTHS; see table OUTHS

78/98 Doc ID 16363 Rev 4

L99PM62XP

Table 76.

Control register 1, bits (continued)

Bit Name

10 OUT3 Select mode of OUT3

OUT3

0 Select FSO

Comment

Mode

Active and standby mode

1 Select PWM3

9 OUT2 Select mode of OUT2

OUT2

0

1

Mode

Select PWM2 Active and

Select timer2 standby mode

8 OUT1 Select mode of OUT1

OUT1

0

1

Mode

Select PWM1 Active and

Select timer1 standby mode

7

6

REL2 Select mode of REL2

REL2

0

1

REL2 off

REL2 on

REL1 Select mode of REL1

REL1

0

1

REL1 off

REL1 on

Mode

Active and standby mode

Active mode

Mode

Active and standby mode

Active mode

ST SPI

Doc ID 16363 Rev 4 79/98

ST SPI

Table 76.

Control register 1, bits (continued)

Bit Name

5

4

V

2

V

2_2

0

V

2_1

0

0

1

1

1

0

1

Comment

V

2

OFF in all modes

V

2

ON in active mode; OFF in V

1

/V

BAT standby mode

V

2

V

ON in Active/V

BAT

1

standby mode; OFF in

standby mode

V

2

ON in all modes

L99PM62XP

3

2

RES Reserved

STBY_SEL Select standby mode

0

1

V

BAT

standby mode

V

1 standby mode

1 GO_STBY Execute standby mode

0 No action

1 Execute standby mode

0 TRIG Trigger Bit for Watchdog

Control register 2

Table 77.

Control register 2: command and data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 0 0 0 1 0 Data, 8bit

2 nd

data byte

Data, 8 bit

Table 78.

Control register 2, data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Defaults 0 0 0 0 0 0 0 0 0 1 1 1

Function Res Res

Wu3

Filt_MSB

Wu3

Filt_LSB

WU2

Filt_MSB

WU2

Filt_LSB

WU1

Filt_MSB

WU1

Filt_LSB

Res

WU3

Pu/Pd

WU2

Pu/Pd

WU1

Pu/Pd

Res

WU3

EN

WU2

EN

WU1

EN

Group Wakeup control Wakeup control

80/98 Doc ID 16363 Rev 4

3

2

1

0

7

6

5

4

L99PM62XP

Table 79.

Control register 2, bits

Bit Name

15

14

13, 12

11, 10

9, 8

Res

Res

WU3_Filt

WU2_Filt

WU1_Filt

Reserved

Reserved

Wakeup filter configuration

MSB LSB

1

1

0

0

0

1

0

1

Res

WU3_Pu/Pd

WU2_Pu/Pd

WU1_Pu/Pd

Reserved

Pull up or pull down configuration

0 Pull down

1 Pull up

Res

WU3_EN

WU2_EN

WU1_EN

Reserved

Enable Wake up source

0

1

Disable

Enable

Comment

Static, 64 µs

Enabled with timer 2; 80 µs blank

Enabled with timer 2; 800 µs blank

Enabled with timer 1; 800 µs blank

ST SPI

Control register 3

Table 80.

Control register 3: command data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 0 0 0 1 1 Data, 8bit

2 nd

data byte

Data, 8 bit

Table 81.

Control register 3, data bytes

1 st

data byte <15:8>

Defaults 0

Function

Group

Res

T1

On

0

T1

Per

MSB

0

T1

Per

LSB

0

Res

Timer Settings

0

T2

On

0

T2

Per

MSB

0

T2

Per

LSB

Res

2 nd

data byte <7:0>

Res

0

WD time

MSB

0

WD time

LSB

1

LIN

WU

En

1

CAN

WU

En

Watchdog and cyclic wake up settings

0

Wake timer

En

0

Wake timer select

Doc ID 16363 Rev 4 81/98

ST SPI

Table 82.

Control register 3, bits

Bit Name

15

14

RES

T1_On

Reserved

Timer 1 “ON” time selections

0

1

10 ms

20 ms

13

12

11

10

7

6

9

8

Comment

T1_Per_MSB

T1_Per_LSB

Timer 1 period selection

MSB LSB

0

0

0

1

1 s

2 s

1

1

0

1

3 s

4 s

Timer 1 is restarted with a valid write command to control register 3

Res

T2_On Timer 2 “ON” time selection

0 0.1 ms

1 1 ms

T2_Per_MSB

T2_Per_LSB

Timer 2 period selection

Res

Res

MSB LSB

0

0

1

1

0

1

0

1

10 ms

50 ms

100 ms

200 ms

Timer 2 is restarted with a valid write command to control register 3

Reserved

Reserved

L99PM62XP

82/98 Doc ID 16363 Rev 4

L99PM62XP

Table 82.

Control register 3, bits (continued)

Bit Name

5

4

WD_time_MSB Trigger window selection

WD_time_LSB

MSB

0

0

1

1

LSB

0

1

0

1

10 ms

20 ms

50 ms

200 ms

Comment

ST SPI

3

2

LIN_WU_En Enable LIN as wake up source

0 Disabled

1 Enabled

CAN_WU_En Enable CAN as wake up source

0 Disabled

1 Enabled

1 Wake_timer_En

Enable wake up by timer from V

1 standby mode (Interrupt) or V

BAT standby Mode

(Nreset)

0 Disabled

1 Enabled

0 Wake_timer_select Timer selection for timer interrupt / wake-up of µC by timer

0

1

Timer 2

Timer 1

Control register 4

Table 83.

Control register 4: command and data bytes

Command byte 1 st

data byte x

Read/Write x

Address

0 0 0 1 0 0 Data, 8bit

2 nd

data byte

Data, 8 bit

Doc ID 16363 Rev 4 83/98

ST SPI L99PM62XP

Table 84.

Control register 4, data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Defaults

Group

0

Function RES I

CMP

0

OutHS

Rec

En

1

Vlock

Out_en

0

RES

Control (other)

1

LS

OV/UV shut down_en

0

V

1

Reset

Lev_2

0 1

V

1

Reset

Lev_1

LIN

Pu

En

1

Res

1

Lin

TxD

Tout

En

1

CAN

ACT

0

CAN

Loop

En

1

CAN

Patt.

wake

En

Transceiver settings

1 0

CAN split

On

CAN

Rec only

Table 85.

Control register 4, bits

Bit Name

15

14

Res

I cmp

Comment

Reserved; must be set to zero

V

1

load current supervision

0

Enabled; Watchdog is disabled in V

1

Standby when the

V

1loadcurrent

< I cmpthreshold

1

Disabled; Watchdog is automatically disabled when V

1 standby is entered

13 OUTHS_rec_en Overcurrent Auto recovery mode for OUTHS

0 Disabled

1 Enabled

12

11

10

Vlock_out_en Voltage lock out: OV/UV status

0

Over/under voltage status recovers automatically when condition disappears

1

Over/under voltage status is latched until a read and clear command is performed

Res

LS_OV/UV shut_down_en

Reserved

Shutdown of low-side drivers in case of over-/under voltage

0

1

No shutdown of low-sides in case of over/under voltage

Shutdown low-sides in case of over/under voltage

84/98 Doc ID 16363 Rev 4

L99PM62XP

Table 85.

Control register 4, bits (continued)

Bit Name

9

8

V1Reset_level_1 Select reset level

V1Reset_level_2

V1RSTlev_2

1

1

0

0

V1RSTlev_1

0

1

0

1

Comment

V1 reset level

4.6 V

4.35 V

4.1 V

3.8 V

ST SPI

7 LIN_PU_EN Enable internal Lin pull up

0

1

No LIN master pull-up

LIN master pull-up

6

5

Res Must be written to ‘1’

Lin_TxD_Tout_En Enable / disable monitoring via TxD

0 No TxD monitoring

1

TxD monitoring; LIN transmitter is switched off if TXDL is dominant for t > 12 ms

4 CAN_ACT Activate CAN transceiver

0

1

CAN transceiver deactivated

CAN transceiver activated

Active mode

3 CAN_Loop_En Enable looping of CANTX to CANRXD in V

1

standby0

0 No looping

1 TXDC is looped to RXDC in V

1

standby

2 CAN_Patt_wake_En Enable pattern wake up for CAN

0

1

No pattern wake up

Pattern wake up

1 CAN_split_On Enable SPLIT termination for CAN

0

1

Split termination disabled

Split termination enabled

Active mode

Doc ID 16363 Rev 4 85/98

ST SPI

Table 85.

Control register 4, bits (continued)

Bit

0

Name

CAN_Rec_only

Comment

Enable CAN receive only mode

0 CAN in transceiver mode

1 CAN in receive only mode

L99PM62XP

Active mode

Control register 5

Table 86.

Control register 5: command and data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 0 0 1 0 1 Data, 8bit

2 nd

data byte

Data, 8 bit

Table 87.

Control register 5, data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Defaults 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Function Res

PWM2

Off-

DC

PWM2

Off-

DC

PWM2

Off-

DC

PWM2

Off-

DC

PWM2

Off-

DC

PWM2

Off-

DC

PWM2

Off-

DC

PWM

Freq

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

PWM1

ON-DC

Group PWM2 setting PWM1 setting

Table 88.

Control register 5, bits

Bit Name

15 Reserved; must be set to zero

14

RES

PWM2_

Off_DC_6

13

PWM2_

Off_DC_5

PWM2

OFF_

DC_6

PWM2

OFF_

DC_5

PWM2

OFF_

DC_4

PWM2

OFF_

DC_3

12

11

10

9

8

PWM2_

Off_DC_4

PWM2_

Off_DC_3

PWM2_

Off_DC_2

PWM2_

Off_DC_1

PWM2_

Off_DC_0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

Comment

PWM2

OFF_

DC_2

1

0

0

0

...

PWM2

OFF_

DC_1

PWM2

OFF_

DC_0

1

1

0

0

1

0

1

0

PWM duty cycle

0%, HS OFF

98.5%

99.25%

100% HS ON

86/98 Doc ID 16363 Rev 4

L99PM62XP

Table 88.

Control register 5, bits (continued)

Bit Name

7

PWM_

FREQ

Select PWM frequency

0

1

128 Hz

256 Hz

Comment

6

5

4

3

2

1

0

PWM1_

ON_DC_6

PWM1_

ON_DC_5

PWM1

ON_

DC_6

PWM1

ON_

DC_5

PWM1

ON_

DC_4

PWM1

ON_

DC_3

PWM1

ON_

DC_2

PWM1

ON_

DC_1

PWM1

ON_

DC_0

PWM1_

ON_DC_4

PWM1_

ON_DC_3

PWM1_

ON_DC_2

PWM1_

ON_DC_1

PWM1_

ON_DC_0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

...

1

1

0

0

1

0

1

0

PWM duty cycle

100%, HS ON

1.5%

0.75%

0% HS OFF

ST SPI

Control register 6

Table 89.

Control register 6: command and data bytes

Command byte 1 st

data byte

Read/Write x x 0 0

Address

0 1 1 0 Data, 8bit

2 nd

data byte

Data, 8 bit

Table 90.

Control register 6, data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Defaults 1 1 1 1 1 1 1 0 0 0 0 0 0 0

Function Res

PWM4

Off_

DC_6

PWM4

Off_

DC_5

PWM4

Off_

DC_4

PWM4

Off_

DC_3

PWM4

Off_

DC_2

PWM4

Off_

DC_1

PWM4

Off_

DC_0

Res

PWM3

ON_

DC_6

PWM3

ON_

DC_5

PWM3

ON_

DC_4

PWM3

ON-DC_3

PWM3

ON_

DC_2

PWM3

ON_

DC_1

PWM3

ON_

DC_0

Group PWM4 setting PWM3 setting

Doc ID 16363 Rev 4 87/98

ST SPI L99PM62XP

Table 91.

Control register 6, bits

Bit Name

15

14

RES

PWM4_

Off_DC_6

Reserved; must be set to zero

13

PWM4_

Off_DC_5

Comment

PWM4

OFF_

DC_6

PWM4

OFF_

DC_5

PWM4

OFF_

DC_4

PWM4

OFF_

DC_3

PWM4

OFF_

DC_2

PWM4

OFF_

DC_1

PWM4

OFF_

DC_0

12

11

10

9

8

PWM4_

Off_DC_4

PWM4_

Off_DC_3

PWM4_

Off_DC_2

PWM4_

Off_DC_1

PWM4_

Off_DC_0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

...

1

1

0

0

1

0

1

0

PWM4 duty cycle

0%, HS OFF

98.5%

99.25%

100% HS ON

7

6

2

1

4

3

0

5

RES

PWM3_

ON_DC_6

Reserved; must be set to zero

PWM3_

ON_DC_5

PWM3

ON_

DC_6

PWM3

ON_

DC_5

PWM3

ON_

DC_4

PWM3

ON_

DC_3

PWM3

ON_

DC_2

PWM3

ON_

DC_1

PWM3

ON_

DC_0

PWM3 duty cycle

PWM3_

ON_DC_4

PWM3_

ON_DC_3

PWM3_

ON_DC_2

PWM3_

ON_DC_1

PWM3_

ON_DC_0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

...

1

1

0

0

1

0

1

0

100%, HS ON

1.5%

0.75%

0% HS OFF

88/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

Table 92.

Overview of status register data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Function

Group

OL

HS

OL

OUT4

OL

OUT3

OL

OUT2

OL

OUT1

Diagnosis 1

UV

Status register 1, data <15:0>

V

2 fail

V

2 short

OV

OC

HS

OC

Out4

OC

Out3

OC

OUT2

Diagnosis 2

Status register 2, data <15:0>

OC

Out1

OC

Rel2

OC

Rel1

Function

WU3 state

WU2 state

WU1 state

Group

WU3 wake

WU2 wake

WU1

Wake

Wake

CAN

Wake

LIN

Wake

Timer int

LIN perm.

dom.

LIN

TxD perm dom.

LIN perm.

rec.

CAN

RxD perm rec.

CAN perm.

rec.

CAN perm.

dom.

CAN

TxD perm dom

Diagnosis 3 Diagnosis 4

Status register 3, data <15:0>

Function TSD1 TW

Device state

Device state

V

1 fail

V

1 restart

V

1 restart

V

1 restart

WD fail

Group Diagnosis 5

WD fail

WD fail

WD fail

Forced sleep

WD

Forced sleep

TSD2

SHTV1

WD timer state

Diagnosis 6

WD timer state

Table 93.

Global status register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Hex value

Active high/low

Default value in normal mode - after correct WD trigger or after read & clear on error flags

Power ON

Power ON weak battery

(7)

Communication error

Vs over or under-voltage

WD failure

High

0

1

1

1

1

1

High

0

1

0

0

0

0

Low

1

0

1

1

0

0

High High High High High

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

1

0

0

20

C0

A2

A1

80

82

Doc ID 16363 Rev 4 89/98

ST SPI

Table 93.

Global status register (continued)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

L99PM62XP

Hex value

SPI error (DI stuck)

TSD1

TSD2

1

1

1

0

0

0

1

1

1

0

0

1

0

1

1

0

0

0

0

0

0

1

0

1

A1

A8

B9

V

1 fail 1 0 1 0 0 1 0 0 A4

Other device failure

(8)

1 0 1 0 0 0 0 0 A0

1.

The following status bits are reported in the global error flag:

Global status register: Bits 0 - 6

Status register 1: Bits 0 – 10

Status register 3: Bits 2, 3, 15

2.

Invalid CLOCK COUNT.

3.

Cleared with CLR command on SR3.

4.

Cleared with “READ and CLEAR” on SR3 (-> TSD1).

5.

Diagnosis bit only, Vs Fail is not a fail-safe event; cleared by read&clear. Bit is automatically cleared at (Vs > VsUV) and.

(Vs < VsOV) if Vlock_out_en = 0.

6.

Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure.

7.

Slow Vs ramp-up (Vs undervoltage is filtered with 64 µs after Power-on reset).

8.

The global error flag is raised due to a failure condition which is not reported in the global status register. The Failure is reported in the status registers 1 – 3.

Status register 1

Table 94.

Status register 1: command and data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 1 0 0 0 1

Bit <15:8>

Data, 8bit

2 nd

data byte

Bit<7:0>

Data, 8 bit

Table 95.

Status register 1, data bytes

1 st

data byte <15:8>

Function

Group

OL

HS

OL

OUT4

OL

OUT3

OL

OUT2

Diagnosis 1

OL

OUT1

UV

V

2 fail

V

2 short

OV

OC

HS

OC

Out4

2 nd

data byte <7:0>

OC

Out3

OC

OUT2

Diagnosis 2

OC

Out1

OC

Rel2

OC

Rel1

90/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

Table 96.

Status register 1, bits

Bit Name Comment

15

14

13

12

11

10

OL_HS

OL_OUT4

OL_OUT3

OL_OUT2

OL_OUT1

UV

Open-load event occurred since last read out

Information storage

Bit is latched until a “read and clear” access

Under voltage event on V

S occurred since last read out

VLOCKOUTEN

(CR4)

0

1

Information storage automatically reset when UV condition disappears

Bit is latched until a “read and clear” access

8

7

9 V

2

_fail

V

2

_short

V

2

fail (V

2

< 2 V for t> 2 µs) event occurred since last readout

Bit is latched until a “Read and clear” access

V

2

short (V

2

< 2 V for t > 4ms during start up) event occurred since last readout

Bit is latched until a “Read and clear” access

OV

VLOCKOUTEN

(CR4)

Information storage

Over voltage event on V

S occurred since last read out

0

1 automatically reset when OV condition disappears

Bit is latched until a “read and clear” access

6

5

4

3

2

1

0

OC_HS

OC_OUT4

OC_OUT3

OC_OUT2

OC_OUT1

OC_REL2

OC_REL1

Over current event occurred since last read out

Bit is latched until a “read and clear” access

Doc ID 16363 Rev 4 91/98

ST SPI L99PM62XP

Status register 2

Table 97.

Status register 2: command and data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 1 0 0 1 0

Bit <15:8>

Data, 8bit

2 nd

data byte

Bit<7:0>

Data, 8 bit

Table 98.

Status register 2, data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Function

WU3 state

WU2 state

WU1 state

WU3 wake

WU2 wake

WU1 wake

Wake

CAN

Wake

LIN

Wake

Timer int

LIN perm.

dom.

LIN

TxD perm dom.

LIN perm.

rec.

CAN

RxD perm rec.

CAN perm.

rec.

CAN perm.

dom.

CAN

TxD perm dom

Group Diagnosis 3 Diagnosis 4

11

10

9

8

7

6

15

14

13

12

Table 99.

Status register 2, bits

Bit Name

5

4

3

2

1

0

Comment Information storage

WU3_state

WU2_state

WU1_state

WU3_wake

State of WUx input; “Live bits” not clearable

WU2_wake

WU1_wake

WAKE_CAN

WAKE_LIN

Wake_TIMER_int

LIN_perm_DOM

Shows wake up source (‘1’ = wake-up)

LIN_TxD_perm_DOM

LIN_perm_REC

CAN_RxD_perm_rec

LIN bus is dominant for t > 12 ms

TxDL pin is dominant for t > 12 ms;

Transmitter is disabled

LIN bus does not follow TxDL within

40 µs; Transmitter is disabled

RxDC has not followed TxDC for 4 times;

Transmitter is disabled

Bits are latched until a “Read and clear” access

CAN_perm_REC

CAN has not followed TxDC for 4 times;

Transmitter is disabled

CAN bus is dominant for t > 700 µs CAN_perm_DOM

CAN_TxD_perm_DOM

TxDC pin is dominant for t > 700 µs;

Transmitter is disabled

92/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

Status register 3

Table 100. Status register 3: command and data bytes

Command byte 1 st

data byte x

Read/write x

Address

0 1 0 0 1 1

Bit <15:8>

Data, 8bit

2 nd

data byte

Bit<7:0>

Data, 8 bit

Table 101. Status register 3, data bytes

1 st

data byte <15:8> 2 nd

data byte <7:0>

Function TSD1 TW

Device state_2

Device state_1

V

1 fail

V

1 restart_2

V

1 restart_1

V

1 restart_0

WD fail_3

WD fail_2

WD fail_1

WD fail_0

Forced sleep

WD

Forced sleep

TSD2

SHTV1

WD timer state_1

WD timer state_0

Group Diagnosis 5 Diagnosis 6

11

10

9

8

7

6

5

4

Table 102. Status register 3, bits

Bit Name

15

14

13

TSD1

TW

Comment

Thermal warning / shutdown1 occurred since last readout

State from which the device woke up

12

Device_state

Device state_2

0

0

1

1

Device state_1

0

1

0

1

State from which the device woke up

Active

V

1

standby

V

BAT

standby

Flash

Information storage

Bit is latched until a

“read and clear access”

Bit is latched until a

“read and clear access” after a “read and clear access”, the device state is updated after a wake up, device state is

01: V

1

standby or

10: V

BAT

standby

V

1

_fail

V

1

_restart_2

V

1

_restart_1

V

1

_restart_0

WD_fail_3

WD_fail_2

WD_fail_1

WD_fail_0

V

1

fail (V

1

< 2 V for t > 2 µs) event occurred since last read out

Bit is latched until a

“read and clear access”

Number of TSD2 events which caused a restart of V regulator

(7 TSD2 events forces the device into V

BAT

standby)

1

Bits are not clearable; is cleared automatically if no additional TSD2 event occurs within 1 min.

Number of missing watchdog triggers

(15 missing watchdog trigger forces the device into V

BAT standby)

Bits are not clearable; is cleared with a proper

Watchdog trigger

Doc ID 16363 Rev 4 93/98

ST SPI L99PM62XP

Table 102. Status register 3, bits (continued)

Bit Name Comment Information storage

3 Forced_sleep_WD

Device was forced to V

BAT

standby mode because of multiple watchdog errors

2

Forced_sleep_TSD

2_SHTV

1

Device was forced to V

BAT

standby or multiple thermal shutdown events or a short on V

1

during startup.

1 WD_timer_state_1 Status of watchdog counter of selected watchdog timing

Bits are latched until a read and clear access

0 WD_timer_state_0

WD_timer_state_1 WD_timer_state_0 Counter

Bits are not clearable

0

0

1

0

1

1

0 – 33%

33 – 66%

66 – 100%

94/98 Doc ID 16363 Rev 4

L99PM62XP

7

Package and packing information

Package and packing information

7.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

7.2 PowerSSO-36 package information

Figure 39.

PowerSSO-36 package dimensions

AG00066V1

Doc ID 16363 Rev 4 95/98

Package and packing information h k

G

H e e3

F

A

A2 a1 b c

D

E

S

T

U

X

Y

L

M

N

O

Q

Table 103. PowerSSO-36 mechanical data

Symbol

Min.

—

10.1

—

0°

—

—

—

2.15

2.15

0

0.18

0.23

10.10

7.4

—

—

—

4.1

6.5

0.55

—

—

—

—

Millimeters

Typ.

—

—

—

—

0.5

8.5

2.3

—

—

—

—

—

—

—

2.9

3.65

1.0

—

—

—

4.3

-

1.2

0.8

L99PM62XP

Max.

0.1

10.5

0.4

8°

—

—

—

2.45

2.35

0.1

0.36

0.32

10.50

7.6

—

—

—

4.7

7.1

0.85

—

10°

—

—

96/98 Doc ID 16363 Rev 4

L99PM62XP Revision history

Table 104. Document revision history

Date Revision

14-Dec-2009

18-Dec-2009

29-Nov-2011

19-Sep-2013

1

2

3

4

Change

Initial release.

Updated

Table 5: Fail safe conditions and exit modes

.

Table 12: Supply and supply monitoring

:

– Updated I

V(BAT)CS and I

V(BAT)CW max value from 110µA to 125µA

Table 19: Output (OUT_HS)

:

– Updated t d

ON min value from 10µs to 5µs.

Table 20: Outputs (OUT1...4) :

– Updated I

OLD

min value from 1mA to 0.9mA and max value from

4mA to 4.5mA

Table 39: CSN timing :

– Added t

CSNfail parameter.

Updated footnote on

Table 21: Relay drivers

Updated

Figure 39: PowerSSO-36 package dimensions

Updated

Table 103: PowerSSO-36 mechanical data

Updated disclaimer.

Doc ID 16363 Rev 4 97/98

L99PM62XP

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