STMicroelectronics STM8 Series Microcontroller CPU Programming Manual
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PM0044
Programming manual
STM8 CPU programming manual
Introduction
The STM8 family of HCMOS microcontrollers is designed and built around an enhanced industry standard 8-bit core and a library of peripheral blocks, which include ROM, Flash,
RAM, EEPROM, I/O, Serial Interfaces (SPI, USART, I2C,...), 16-bit Timers, A/D converters, comparators, power supervisors etc. These blocks may be assembled in various combinations in order to provide cost-effective solutions for application-specific products.
The STM8 family forms a part of the STMicroelectronics 8-bit MCU product line, which finds its place in a wide variety of applications such as automotive systems, remote controls, video monitors, car radio and numerous other consumer, industrial, telecom, and multimedia products.
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Contents
Contents
PM0044
STM8 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Enhanced STM8 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8 core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM8 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory interface architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Description of pipelined execution stages . . . . . . . . . . . . . . . . . . . . . . . . 20
Decoding and addressing stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pipelined execution examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Optimized pipeline example – execution from Flash Program memory . 24
Optimize pipeline example – execution from RAM . . . . . . . . . . . . . . . . 26
Pipeline with Call/Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Direct addressing mode (Short, Long, Extended) . . . . . . . . . . . . . . . . . . 34
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Contents
Short Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Long Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Extended Direct addressing mode (only for CALLF and JPF) . . . . . . . . 38
Indexed addressing mode (No Offset, Short, SP, Long, Extended) . . . . . 39
No Offset Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Short Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SP Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Long Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Extended Indexed (only LDF instruction) . . . . . . . . . . . . . . . . . . . . . . . . 44
Indirect (Short Pointer Long, Long Pointer Long) . . . . . . . . . . . . . . . . . . . 45
Short Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . 46
Long Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . . 47
Indirect Indexed (Short Pointer Long, Long Pointer Long,
Long Pointer Extended) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . 48
Short Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . 49
Long Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . . 51
Long Pointer Indirect Extended Indexed addressing mode . . . . . . . . . . . 53
Relative Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Bit Direct (Long) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Bit Direct (Long) Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . 59
Code condition bit value notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Memory and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Operation code notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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List of tables
List of tables
Available Long Pointer Long and Short Pointer Long Indirect Instructions. . . . . . . . . . . . . 45
Available Long Pointer Long and Short Pointer Long Indirect
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List of figures
List of figures
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Long Pointer Indirect Extended Indexed addressing mode example . . . . . . . . . . . . . . . . . 54
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PM0044 STM8 architecture
The 8-bit STM8 Core is designed for high code efficiency. It contains 6 internal registers, 20 addressing modes and 80 instructions. The 6 internal registers include two 16-bit Index registers, an 8-bit Accumulator, a 24-bit Program Counter, a 16-bit Stack Pointer and an 8bit Condition Code register. The two Index registers X and Y enable Indexed Addressing modes with or without offset, along with read-modify-write type data manipulation. These registers simplify branching routines and data/arrays modifications.
The 24-bit Program Counter is able to address up to 16-Mbyte of RAM, ROM or Flash memory. The 16-bit Stack Pointer provides access to a 64K-level Stack. The Core also includes a Condition Code register providing 7 Condition flags that indicate the result of the last instruction executed.
The 20 Addressing modes, including Indirect Relative and Indexed addressing, allow sophisticated branching routines or CASE-type functions. The Indexed Indirect Addressing mode, for instance, permits look-up tables to be located anywhere in the address space, thus enabling very flexible programming and compact C-based code. The stack pointer relative addressing mode permits optimized C compiler stack model for local variables and parameter passing.
The Instruction Set is 8-bit oriented with a 2-byte average instruction size. This Instruction
Set offers, in addition to standard data movement and logic/arithmetic functions, 8-bit by 8bit multiplication, 16-bit by 8-bit and 16-bit by 16-bit division, bit manipulation, data transfer between Stack and Accumulator (Push / Pop) with direct stack access, as well as data transfer using the X and Y registers or direct memory-to-memory transfers.
The number of Interrupt vectors can vary up to 32, and the interrupt priority level may be managed by software providing hardware controlled nested capability. Some peripherals include Direct Memory Access (DMA) between serial interfaces and memory. Support for slow memories allows easy external code execution through serial or parallel interface
(ROMLESS products for instance).
The STM8 has a high energy-efficient architecture, based on a Harvard architecture and pipelined execution. A 32-bit wide program memory bus allows most of the instructions to be fetched in 1 CPU cycle. Moreover, as the average instruction length is 2 bytes, this allows for a reduction in the power consumption by only accessing the program memory half of the time, on average. The pipelined execution allowed the execution time to be minimized, ensuring high system performance, when needed, together with the possibility to reduce the overall energy consumption, by using different power saving operating modes. Power-saving can be managed under program control by placing the device in SLOW, WAIT, SLOW-WAIT,
ACTIVE-HALT or HALT mode (see product datasheet for more details).
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STM8 architecture PM0044
Additional blocks
The additional blocks take the form of integrated hardware peripherals arranged around the central processor core. The following (non-exhaustive) list details the features of some of the currently available blocks:
Boot ROM Memory area containing the bootloader code
RAM
Data EEPROM
Timers
A/D converter
I2C
SPI
USART
Watchdog
I/O ports
Sizes up to several Kbytes
Sizes up to several Kbytes. Erase/programming operations do not require additional external power sources.
Different versions based on 8/16-bit free running or autoreload timer/counter are available. They can be coupled with either input captures, output compares or
PWM facilities. PWM functions can have software programmable duty cycle between 0% to 100% in up to 256/65536 steps. The outputs can be filtered to provide D/A conversion.
The Analog to Digital Converter uses a sample and hold technique. It has 12-bit resolution.
Multi/master, single master, single slave modes, DMA or 1byte transfer, standard and fast I2C modes, 7 and 10-bit addressing.
The Serial peripheral Interface is a fully synchronous 3/4 wire interface ideal for
Master and Slave applications such as driving devices with input shift register
(LCD driver, external memory,...).
The USART is a fast synchronous/asynchronous interface which features both duplex transmission, NRZ format, programmable baud rates and standard error detection. The USART can also emulate RS232 protocol.
It has the ability to induce a full reset of the MCU if its counter counts down to zero prior to being reset by the software. This feature is especially useful in noisy applications.
They are programmable by software to act in several input or output configurations on an individual line basis, including high current and interrupt generation. The basic block has eight bit lines.
The STM8 family of MCUs is supported by a comprehensive range of development tools.
This family presently comprises hardware tools (emulators, programmers), a software package (assembler-linker, debugger, archiver) and a C-compiler development tool.
STM8 and ST7 CPUs are supported by a single toolchain allowing easy reuse and portability of the applications between product lines.
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1.2
STM8 architecture
●
●
●
●
●
●
●
Enhanced STM8 features
●
●
●
●
●
16-Mbyte linear program memory space with 3 FAR instructions (CALLF, RETF, JPF)
16-Mbyte linear data memory space with 1 FAR instruction (LDF)
Up to 32 24-bit interrupt vectors with optimized context save management
16-bit Stack Pointer (SP=SH:S) with stack manipulation instructions and addressing modes
New register and memory access instructions (EXG, MOV)
New arithmetic instructions: DIV 16/8 and DIVW 16/16
New bit handling instructions (CCF, BCPL, BCCM)
2 x 16-bit index registers (X=XH:XL, Y=YH:YL). 8-bit data transfers address the low byte. The high-byte is not affected, with a reset value of 0. This allows the use of X/Y as
8-bit values.
Fast interrupt handling through alternate register files (up to 4 contexts) with standard stack compatible mode (for real time OS kernels)
16-bit/8-bit stack operations (X, Y, A, CC stacking)
16-bit pointer direct update with 16-bit relative offset (ADDW/SUBW for X/Y/SP)
8-bit & 16-bit arithmetic and signed arithmetic support
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Glossary
2 Glossary
MS
LS
A
X
Y reg ndx
PC
SP
S
CC mnem src dst cy lgth op-code mem imm off ptr pos byte mnemonic source destination duration of the instruction in CPU clock cycles (internal clock) length of the instruction in byte(s) instruction byte(s) implementation (1..4 bytes), operation code.
memory location immediate value offset pointer position a byte short long represent a short 8-bit addressing mode represent a long 16-bit addressing mode
EA Effective Address: The final computed data byte address
Page Zero all data located at [00..FF] addressing space (single byte address)
(XX)
XX content of a memory location XX a byte value
Most Significant byte of a 16-bit value (MSB)
Least Significant byte of a 16-bit value (LSB)
Accumulator register
16-bit X Index register
16-bit Y Index register
A, XL or YL register (1-byte LS part of X/Y), XH or YH (1-byte MS part of X/Y) index register, either X or Y
24-bit Program Counter register
16-bit Stack Pointer
Stack Pointer LSB
Condition Code register
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3 STM8 core description
STM8 core description
3.1 Introduction
The CPU has a full 8-bit architecture, with 16-bit operations on index registers (for address computation). Six internal registers allow efficient 8-bit data manipulation. The CPU is able to execute 80 basic instructions. It features 20 addressing modes and can address 6 internal registers and 16 Mbytes of memory/peripheral registers.
The 6 CPU registers are shown in the programming model in
interrupt, the register context is saved. The context is saved by pushing registers onto the stack in the order shown in
They are popped from the stack in the reverse order.
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations.
Index registers (X and Y)
These 16-bit registers are used to create effective addresses or as temporary storage area for data manipulations. In most of the cases, the cross assembler generates a PRECODE instruction (PRE) to indicate that the following instruction refers to the Y register. Both X and
Y are automatically saved on interrupt routine branch.
Program Counter (PC)
The program counter is a 24-bit register used to store the address of the next instruction to be executed by the CPU. It is automatically refreshed after each processed instruction. As a result, the STM8 core can access up to 16-Mbytes of memory.
Figure 1.
Programming model
23
PCE
15
15
15
16 15
XH
YH
PCH
7 0
A ACCUMULATOR
8 7 0
XL X INDEX
8 7 0
YL Y INDEX
0
SP STACK POINTER
8 7 0
PCL
7
V
0
- I1 H I0 N Z C
PC PROGRAM COUNTER
CC CODE CONDITION
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STM8 core description PM0044
Note:
Stack Pointer (SP)
The stack pointer is a 16-bit register. It contains the address of the next free location of the stack. Depending on the product, the most significant bits can be forced to a preset value.
The stack is used to save the CPU context on subroutines calls or interrupts. The user can also directly use it through the POP and PUSH instructions.
After an MCU reset the Stack Pointer is set to its upper limit value. It is then decremented after data has been pushed onto the stack and incremented after data is popped from the stack. When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit. The previously stored information is then overwritten, and therefore lost.
A subroutine call occupies two or three locations.
When an interrupt occurs, the CPU registers (CC, X, Y, A, PC) are pushed onto the stack.
This operation takes 9 CPU cycles and uses 9 bytes in RAM.
The WFI/HALT instructions save the context in advance. If an interrupt occurs while the CPU is in one of these modes, the latency is reduced.
Figure 2.
Context save/restore for interrupts
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PM0044 STM8 core description
Global configuration register (CFG_GCR)
The global configuration register is a memory mapped register. It controls the configuration of the processor. It contains the AL control bit:
AL: Activation level
If the AL bit is 0 (main), the IRET will cause the context to be retrieved from stack and the main program will continue after the WFI instruction.
If the AL bit is 1 (interrupt only active), the IRET will cause the CPU to go back to WFI/HALT mode without restoring the context.
This bit is used to control the low power modes of the MCU. In a very low power application, the MCU spends most of the time in WFI/HALT mode and is woken up (through interrupts) at specific moments in order to execute a specific task. Some of these recurring tasks are short enough to be treated directly in an ISR, rather than going back to the main program. In this case, by programming the AL bit to 1 before going to low power (by executing WFI/HALT instruction), the run time/ISR execution is reduced due to the fact that the register context is not saved/restored each time.
Condition Code register (CC)
The Condition Code register is a 8-bit register which indicates the result of the instruction just executed as well as the state of the processor. These bits can be individually tested by a program and specified action taken as a result of their state. The following paragraphs describe each bit.
● V: Overflow
When set, V indicates that an overflow occurred during the last signed arithmetic operation, on the MSB operation result bit. See INC, INCW, DEC, DECW, NEG, NEGW,
ADD, ADC, SUB, SUBW, SBC, CP, CPW instructions.
● I1: Interrupt mask level 1
The I1 flag works in conjunction with the I0 flag to define the current interruptability level as shown in the following table. These flags can be set and cleared by software through the RIM, SIM, HALT, WFI, IRET, TRAP and POP instructions and are automatically set by hardware when entering an interrupt service routine.
Table 1.
Interruptability levels
Interruptability
Interruptable Main
Interruptable Level 1
Interruptable Level 2
Non Interruptable
Priority
Lowest
↕
Highest
I1
1
0
0
1
I0
0
1
0
1
● H: Half carry bit
The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines.
For ADDW, SUBW it is set when a carry occurs from bit 7 to 8, allowing to implement byte arithmetic on 16-bit index registers.
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●
●
●
●
I0: Interrupt mask level 0
See Flag I1
N: Negative
When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is negative (i.e. the most significant bit is a logic 1).
Z: Zero
When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
C: Carry
When set, C indicates that a carry or borrow out of the ALU occurred during the last arithmetic operation on the MSB operation result bit (bit 7 for 8-bit result/destination or bit 15 for 16-bit result). This bit is also affected during bit test, branch, shift, rotate and load instructions. See ADD, ADC, SUB, SBC instructions.
In bit test operations, C is the copy of the tested bit. See BTJF, BTJT instructions.
In shift and rotates operations, the carry is updated. See RRC, RLC, SRL, SLL, SRA instructions.
This bit can be set, reset or complemented by software using SCF, RCF, CCF instructions.
Example: Addition
$B5 + $94 = "C" + $49 = $149
C
0
7 0
1 0 1 1 0 1 0 1
C
+ 0
C
= 1
7 0
1 0 0 1 0 1 0 0
7 0
0 1 0 0 1 0 0 1
The results of each instruction on the Condition Code register are shown by tables in
Section 7: STM8 instruction set . The following table is an example:
V
V
I1
0 where
H I0
0
Nothing = Flag not affected
Flag name = Flag affected
0 = Flag cleared
1 = Flag set
N
N
Z
Z
C
1
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4 STM8 memory interface
STM8 memory interface
Note:
The program space is 16-Mbyte and linear. To distinguish the 1, 2 and 3 byte wide
addressing modes, naming has been defined as shown in Figure 3
:
● "Page" [0xXXXX00 to 0xXXXXFF]: 256-byte wide memory space with the same two most significant address bytes (XXXX defines the page number).
● "Section" [0xXX0000 to 0xXXFFFF]: 64-Kbyte wide memory space with the same most significant address byte (XX defines the section number).
The reset and interrupt vector table are placed at address 0x8000 for the STM8 family.
(Note: the base address may be different for later implementations.) The table has 32 4-byte entries: RESET, Trap, NMI and up to 29 normal user interrupts. Each entry consists of the reserved op-code 0x82, followed by a 24-bit value: PCE, PCH, PCL address of the respective Interrupt Service Routine. The main program and ISRs can be mapped anywhere in the 16 Mbyte memory space.
CALL/CALLR and RET must be used only in the same section. The effective address for the
CALL/RET is used as an offset to the current PCE register value. For the JP, the effective address 16 or 17-bit (for indexed addressing) long, is added to the current PCE value. In order to reach any address in the program space, the JPF jump and CALLF call instructions are provided with a three byte extended addressing mode while the RETF pops also three bytes from the stack.
As the memory space is linear, sections can be crossed by two CPU actions: next instruction byte fetch (PC+1), relative jumps and, in some cases, by JP (for indexed addressing mode).
For safe memory usage, a function which crosses sections MUST:
- be called by a CALLF
- include only far instructions for code operation (CALLF & JPF)
All label pointers are located in section 0 (JP [ptr.w] example: ptr.w is located in section 0 and the jump address in current section)
Any illegal op-code read from the program space triggers a MCU reset.
The data space is 16-Mbyte and linear. As the stack must be located in section 0 and as data access outside section 0/1 can be managed only with LDF instructions, frequently used data should be located in section 0 to get the optimum code efficiency.
All data pointers are located in section 0 only.
Indexed addressing (with 16-bit index registers and long offset) allows data access over section 0 and 1.
All the peripherals are memory mapped in the data space.
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STM8 memory interface
Figure 3.
Address spaces
0x82
PROGRAM SPACE
INT28
E
INT28
H
0xFFFFFF
INT28
L
0x00807C
0xFF0000
SECTION 256
0x82
0x82
0x82
0x82
0x82
INT1
E
INT0
E
NMI
E
TRAP
E
RESET
E
INT1
H
INT0
H
NMI
H
TRAP
H
RESET
H
INT1
L
INT0
L
NMI
L
TRAP
L
RESET
L
0x01FFFF
0x008000
0x010000
0x00FFFF
0x00807F
0x008000
SECTION 1
VECTORS
0x0000FF
0x000000
PAGE 0
DATA SPACE
3-BYTE ADDRESSING MODE
ACCESSIBLE DATA
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2-BYTE ADDRESSING MODE
BIT HANDLING CAPABILITY
POWERFUL DATA MANAGEMENT
STACK AREA
POINTERS
1-BYTE ADDRESSING MODE
BIT HANDLING CAPABILITY
FAST DATA ACCESS WITH
SHORT GENERATED CODE
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4.3
STM8 memory interface
Memory interface architecture
The STM8 uses a Harvard architecture, with separate program and data memory buses.
However, the logical address space is unified, all memories sharing the same 16-Mbytes space, non-overlapped. The memory interfaces are shown in
buses: address, data, read/write control signal (R/W) and memory acknowledge signal
(STALL).
The STALL acknowledge signal makes the CPU compatible with slow serial or parallel memory interfaces. When the memory interface is slow the CPU waits the memory acknowledge before executing the instruction. So in such a case, the instruction CPU cycle time is prolonged compare to the value given in this manual.
The program memory bus is 32-bit wide, allowing the fetch of most of the instructions in one cycle.
As the address space is unified, the architecture allows data to be stored also in the Flash memory and program to be fetched also from RAM (data bus). In this later case the performance is impacted, besides the fact that data and fetch operation share the same bus, the instructions will be fetched one byte at a time, thus taking longer (1 cycle /byte).
Figure 4.
Memory Interface Architecture
Memory Interface (Flash)
STALL
"LDF" INSTRUCTION
D31..0
A23..0
24
0x00
N
@DATABUS
Data@E Data@E0:H:L
7
Y
CPU
17
@DATABUS
24
PROGRAM COUNTER
PCE PCH PCL
24
24
RAM FETCH INSTRUCTION N Y
STALL
A15..0
D7..0
Memory Interface (RAM)
R/W
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Pipelined execution PM0044
●
●
●
The STM8 family uses a 3-stage pipeline to increase the speed of the flow of instructions sent to the processor. Pipelined execution allows several operations to be performed simultaneously, rather than serially:
Fetch
Decode and address
Execute
The Program Counter (PC) points always to the instruction in decode stage as shown in
Figure 5.
Pipelined execution principle
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7RITEBACKDATATOMEMORY
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5.1 Description of pipelined execution stages
provide a detailed description
of each stage of the pipeline execution.
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Figure 6.
Pipelined execution stages
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5.1.2
The first pipeline stage includes a 64-bit fetch buffer and a 32-bit prefetch buffer, totalling 3 words named F
1
, F
2
and F
3
. This buffer structure allows any instruction code (up to 5 bytes) to be available for decoding immediately after F
1
(and F
2
when needed) is/are loaded.
The instruction access from Flash Program memory is 32-bit wide and it is performed from an aligned address i.e. 0xXXX0, 0xXXX4, 0xXXX8, or 0xXXXC.
Unlike the decode and execute stages that are performed at every cycle, the fetch stage accesses the program memory only when needed, and stops memory access when the buffer is full. This allows reducing the core power consumption,
Reading program from RAM is similar to reading program from ROM. However, since the
RAM data bus is 8-bit wide, 4 consecutive read operations have to be performed to load one
F
X word, thus resulting in RAM execution being slower than Flash execution.
Decoding and addressing stage
The decoding stage includes an instruction alignment unit. The alignment unit uses the 64bit input from the fetch unit and feeds an instruction (from 1 to 5 bytes depending on the instruction) to the decoding unit.
●
●
The instruction code consists of 2 parts (see examples in
The op-code itself (1 or 2 bytes) and a data/address part (0 to 3 bytes).
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Pipelined execution PM0044
The op-code is decoded in this stage. When present, the instruction address is used for address computation, whilst the immediate operand is forwarded to the execution stage.
Table 2.
Data/address decoding examples
Instruction Syntax
Register to register move
Register load
Register store
Data load / store with extended address
LD A, XH
LD A,($12,SP)
LD ($12,SP),A
LDF A,($123456,Y)
Op-code Data/address
0x95
0x7B
0x6B
0x90 AF
-
0x12
0x12
0x12 34 56
Long/unaligned instructions
For long instructions (i.e. 5-bytes instructions), the fetch may need 2 program memory accesses to be completed. In this case, the decoding stage (after decoding the op-code part), is stalled waiting for the fetch stage to complete the 2nd fetch.
In case of shorter instructions, this may also happen when they cross a 32-bit boundary.
Indirect addressing
For indirect addressing, the CPU is stalled in this stage to read the pointer from the data memory (i.e. RAM). The number of cycles during which the CPU is stalled depends on the pointer size (short, long or extended addressing mode).
In the execution stage, the operation is executed and the result is stored in the accumulator, index register or RAM.
●
●
●
3 types of operations perform accesses to the data memory:
Effective address computation in case of indirect addressing
Data read: source operand
Data write: destination for store or read-modify-write operations
In case of simultaneous accesses to the same memory area both in execution stage (write) and decoding stage (read), the decode stage is stalled till the execution stage releases the resource.
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A few pipelined execution examples are reported below. The numbers of cycles for the decoding and execution stages correspond to the minimum number of cycles needed by the instruction itself. In some cases, depending on the instruction sequence, the cycle taken could be more than that number.
5.4 Conventions
●
●
Although the decode and/or execute stage of some instructions may take a different number of cycles, a simplified convention providing a good match with reality, has been used in this section:
The decode stage of each instruction takes one cycle only
The execution stage takes a number of cycles equal to
C
y
= DecCy + ExeCy – 1
Where
C y is the number of execution cycles. In case of decode and execute cycles, It corresponds to the minimum number of cycles needed by the instruction itself, and does not take into account the impact of the instruction sequence.
DecCy is the exact number of decode cycles.
ExeCy is the exact number of execute cycles.
The decode stage of the next instruction starts during the last execution cycle. In instructions performing pipeline flush, the convention is that, in case the branch is taken, the next fetch are performed during the last instruction execution cycle.
The exact number of cycles (see Table 3
) and the number of cycles obtained using this
) are identical.
Table 3.
Example with exact number of cycles
Address Instruction
Time (cycle)
Decode cycles
Execute cycles lgth
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0xC000 LDW X, [$50.w]
0xC003 ADDW X, #20
0xC006 LD A, [$30].w
0xC009 ….
4
2
3
1
2
1
3
3
3
D D D D E
F
1
F
2
D D D D D E E
D D D D D D E
F
3
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Pipelined execution PM0044
Table 4.
Example with conventional number of cycles
Address Instruction
Decode cycles
Execute cycles lgth
Time (cycle)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0xC000 LDW X, [$50.w]
0xC003 ADDW X, #20
0xC006 LD A, [$30].w
0xC009 ….
4
3
3
3
3
3
3
3
3
D E E E E
F
1
F
2
D D D D E E E
D D D D
E E E
F
3
5.4.1
Table 5.
Legend
Symbol/Color
D
E
F
D
Definition
Fetch
Decode stalled
Decode
Execute
Optimized pipeline example – execution from Flash Program memory
In the example shown in Table 6 , the code is stored in the Flash Program memory (32-bit
bus). As a result, 3 cycles are needed to fill the 96-bit prefetch buffer. At each cycle, one word is loaded and stored in F
1
, F
2
and F
3
. The next fetch operation can start only when all the instructions contained in one of the F x
word are decoded. In fact, at cycle 9, the last instruction contained in F
3
(SWAP A) is decoded, and a fetch operation can start to fill F
3 word.
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Table 6.
Add.
Optimized pipeline example - execution from Flash
Instruction
Decod. cycles
Exec. cycles lgth
Cycle
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0xC000 NEG A
0xC001 XOR A, $10
0xC003 LD A, #20
0xC005 SUB A,$1000
0xC008
0xC009
0xC00A
0xC00B
INC A
LD XL, A
SRL A
SWAP A
0xC00C
0xC00E
SLA $15
CP A,#$FE
0xC010 MOV $100, #11
0xC014 MOV $101, #22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
1
2
4
4
2
2
F
1
D E
D E
F
2
D E
D E
F
3
D E
D E
D E
D E
F
1
F
2
F
3
D E
D E
D E
D E
Table 7.
Legend
Symbol/Color
F
D
E
Definition
Fetch
Decode
Execute
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Pipelined execution PM0044
Table 8.
In the example shown in
Table 8 , the RAM is accessed through an 8-bit bus. As a result, 12
cycles are required to fill the 96-bit pre-fetch buffer. Every 4 cycles, one word is loaded and stored in F x
. The decoding of the first word instruction can start only when the F x
word is filled. This occurs for example till the 4 th
cycle, and the first instruction ( NEG A ) can be decoded only at the 5 th
cycle.
In case of read/write access to the RAM, the fetch is stalled. This occurs during the 6 th
cycle since RAM address 10 is read during the decode stage of XOR A, $10 .
Optimize pipeline example – execution from RAM
Cycle
Add.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
0xC000 NEG A 1
0xC001
XOR A,
$10
1
0xC003 LD A, #20 1
0xC005
0xC008
SUB
A,$1000
INC A
1
1
1 1
1 2
1 2
1 3
1 1
0xC009 LD XL, A 1 1 1
0xC00A SRL A
0xC00B SWAP A
0xC00C SLA $15
0xC00E
CP
A,#$FE
1
1
1
1
1
1
1
1
1
1
2
2
D D D D E
D E
FS
D D D D E
D E
FS
D D D D E
D E
D E
D E
D E
D E
Table 9.
Legend
Symbol/Color
F
FS
D
D
E
Definition
Fetch
Fetch stalled
Decode
Decode stalled
Execute
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In the example shown in Table 10
, a branch is taken after the JP/CALL instruction, and the fetched instruction(s) are lost (flush). New instructions must be fetched. 3 fetch sequences are required to refill the pre-fetch buffer. The fetch start depends on the instruction being executed.
For a JP instruction, the fetch can start during the first cycle of the "dummy" execution.
For the CALL instruction, it starts after the last cycle of the CALL execution.
Table 10.
Example of pipeline with Call/Jump
Add.
0xC000
0xC001
Instruction
INC A
JP label
1
1
1
1
1
3
Cycle
Decode cycles
Execute cycles lgth
1 2 3 4 5 6 7 8 9 10 11
F
1
D E
D E
F
2
0xC004 LDW X,[$5432.w]
0xD010
0xD011
0xD014
0xD018
0xE030 label: NEG A
CALL label2
LDW X,[$5432.w]
LDW X,[$7895.w] label2: INCW X
X
X
1
1
1
X
X
X
1
1
2
X
4
4
1
1
3
4
F
1
D E
D E E
F
2
F
3
FS
F
1
D E
Table 11.
Legend
Symbol/Color
F
FS
D
E
Definition
Fetch
Fetch stalled
Decode
Execute
The decode stage can be stalled when the execution lasts more than one cycle.
The flush is due to the branch. Fetching the branch address is performed during the second execution cycle of the BTJF instruction.
The Decode operation can also be stalled when the memory target is modified during the previous instruction. In the example given in
Table 12 , the INCW Y instruction writes the X
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Pipelined execution PM0044 register during the first execution cycle. As a result, in this cycle, the next instruction
(LD A,(X)) cannot be decoded since it reads the X register.
Table 12.
Example of stalled pipeline
Address Instruction
Decode cycles
Execute cycles lgth
Time (cycles)
1 2 3 4 7 8 9 10 11 12 13 14
0xC000
0xC002
SUB SP, #20
LD A, #20
0xC004 BTJT 0x10, #5, to
0xC009 INC A
0xC00A BTJF 0x20, #3, to
0xC00F NOP
0xC010 LDW X,[$5432.w]
0xC014 LDW X,[$1234.w]
0xD020
0xD023 to: INCW Y
LD A,(X)
X
X
1
X
1
1
1
1
1
1
X
X
2
X
1
1
2
1
1
1
4
4
5
1
2
2
5
1
2
2
F
1
D E
D E
F
2
F
3
D E E
D D E
D E E
F
1
F
2
F
3
F
1
D E
D D E
Table 13.
Legend
Symbol/Color
D
E
F
D
Definition
Fetch
Decode stalled
Decode
Execute
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5.4.5 Pipeline with 1 wait state
In the example given in Table 14 , performing the fetch takes 2 cycles, and there is no
overlap between the 2 fetch cycles.
If the instruction is decoded/executed during the last 2 fetch cycles, then the wait state is transparent compared to the no-wait state execution.
Table 14.
Pipeline with 1 wait state
Address
0xC000
0xC001
0xC004
0xC007
0xC008
0xC009
Instruction
NEG A
DEC ($10, X)
LDW X, #20
LD (X), A
INC A
NEG ($5A, Y)
Decode cycles
Execute cycles lgth
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 MS
3
3
2
F
1
3
D
MS
Time (cycle)
4
E
D
5 6 7 8 9 10
F
2
E
D
MS
E E
D D E
D E
F
3
D E
Table 15.
Legend
Symbol/Color
F
D
D
MS
E
Definition
Fetch
Decode stalled
Decode
Memory stalled
Execute
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STM8 addressing modes
6 STM8 addressing modes
PM0044
The STM8 core features 18 different addressing modes which can be classified in 8 main groups:
Table 16.
STM8 core addressing modes
Addressing mode groups
Inherent
Immediate
Direct
Indexed
SP Indexed
Indirect
Relative
Bit operation
NOP
LD A,#$55
LD A,$55
LD A,($55,X)
LD A,($55,SP)
LD A,([$55],X)
JRNE loop
BSET byte,#5
Example
The STM8 Instruction set is designed to minimize the number of required bytes per instruction. To do so, most of the addressing modes can be split in three sub-modes called extended, long and short:
● The extended addressing mode ("e") can reach any byte in the 16-Mbyte addressing space, but the instruction size is bigger than the short and long addressing mode.
Moreover, the number of instructions with this addressing mode (far) is limited (CALLF,
RETF, JPF and LDF)
●
●
The long addressing mode ("w") is the most powerful for program management, when the program is executed in the same section (same PCE value). The long addressing mode is optimized for data management in the first 64-Kbyte addressing space (from
0x000000 to 0x00FFFF) with a complete set of instructions, but the instruction size is bigger than the short addressing mode.
The short addressing mode ("b") is less powerful because it can only access the page zero (from 0x000000 to 0x0000FF), but the instruction size is more compact.
Table 17.
STM8 addressing mode overview
Mode Syntax
Destination address
Pointer address
Inherent
Immediate
Short
Long
Extended
No Offset
Short
NOP
LD A,#$55
LD A,$10 Direct
Direct
Direct
LD A,$1000
LDF A,$100000
Direct Indexed LD A,(X)
Direct Indexed LD A,($10,X)
000000..0000FF
000000..00FFFF
000000..FFFFFF
000000..00FFFF
000000..0100FE
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Table 17.
STM8 addressing mode overview (continued)
Mode Syntax
Destination address
Pointer address
Short
Long
Direct
SP
Indexed
LD A,($10,SP)
Direct Indexed LD A,($1000,X)
Extended Direct Indexed LDF A,($100000,X)
Short
Pointer Long
Indirect LD A,[$10.w]
Long Pointer
Long indirect LD A,[$1000.w]
00..(FF+Stacktop)
000000..01FFFE
000000..FFFFFF
000000..00FFFF
000000..00FFFF
Long Pointer
Extended indirect LDF A,[$1000.e]
Short
Pointer Long
Indirect Indexed LD A,([$10.w],X)
Long Pointer
Long
Indirect
Indexed
(X only)
LD A,([$1000.w],X)
Long Pointer
Extended
Indirect Indexed LDF A,([$1000.e],X)
Relative
Bit
Bit
Direct
Long
Direct
Long
Direct
Relative
JRNE loop
BSET $1000,#7
BTJT $1000,#7,skip
000000..FFFFFF
000000..01FFFE
000000..01FFFE
000000..FFFFFF
PC+127/-128
000000..00FFFF
000000..00FFFF PC+127/-128
000000..0000FF
000000..00FFFF
2
000000..00FFFF
3
000000..0000FF
2
2
000000..00FFFF
2
000000..00FFFF
3
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STM8 addressing modes
6.1
PM0044
Inherent addressing mode
All related instructions are 1 or 2 byte. The op-code fully specifies all required information for the CPU to process the operation.
Table 18.
Inherent addressing instructions
Instructions Functions
NOP
TRAP
WFI, WFE
HALT
RET
RETF
IRET
SIM
RIM
SCF
RCF
RVF
CCF
LD, LDW
No operation
S/W Interrupt
Wait For Interrupt / Event (Low Power Mode)
Halt Oscillator (Lowest Power Mode)
Sub-routine Return
Far Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
Reset Carry Flag
Reset Overflow Flag
Complement Carry Flag
Load
CLR, CLRW Clear
PUSH, POP, PUSHW, POPW Push/Pop to/from the stack
INC, DEC, INCW, DECW Increment/Decrement
TNZ, TNZW
CPL, NEG, CPLW, NEGW
MUL
DIV, DIVW
EXG, EXGW
SLA, SLL, SRL, SRA, RLC,
RRC, SLAW, SLLW, SRLW,
SRAW, RLCW, RRCW
SWAP, SWAPW
Test Negative or Zero
1’s or 2’s Complement
Byte Multiplication
Division
Exchange
Shift and Rotate Operations
Swap Nibbles/Bytes
Example:
1000 98 RCF ; Reset carry flag
1001 9D NOP ; No operation
1002 9F LD A,X; Transfer X register content into accumulator
1004 88 PUSH A; Push accumulator content onto the stack
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6.2
STM8 addressing modes
Immediate addressing mode
The data byte required for the operation, follows the op-code.
Table 19.
Immediate addressing instructions
Instructions
LD, MOV, LDW
CP, CPW
BCP
AND, OR, XOR
ADC, ADD, SUB, SBC, ADDW, SUBW
PUSH
Functions
Load and move operation
Compare
Bit Compare
Logical Operations
Arithmetic Operations
Stack Operations
These are two byte instructions, one for the op-code and the other one for the immediate data byte.
Example:
05BA AEFF LD
05BC A355 CP
05BE A6F8 LD
X,#$FF
X,#$55
A,#$F8
Action:
Load X = $FF
Compare (X, $55)
A = $F8
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STM8 addressing modes
Figure 7.
Immediate addressing mode example
Before Completion
LD A, #0F8h A6
F8
05BE
05BF
05C0
A
Previous Value
PC
05BE
6.3
PM0044
Steps to Determine
Effective Address
PC = 05BE
PC = PC + 1 = 05BF
EA = PC = 05BF
New PC = PC + 1
= 05C0
After Completion
A6
F8
05BE
05BF
05C0
A
F8
New PC
05C0
Instruction Complete
A = (EA) = F8
New PC = 05C0
VR02059A
Direct addressing mode (Short, Long, Extended)
Table 20.
Overview of Direct addressing mode instructions
Addressing mode Syntax EA formula Ptr Adr Ptr Size
Short
Long
Direct
Direct
Extended Direct shortmem (shortmem) longmem (longmem) extmem (extmem) op + 1 op + 1..2
op + 1..3
Byte
Word
Ext word
Dest adr
00..FF
0000..FFFF
000000..FFFFFF
The data byte required for the operation is found by its memory address, which follows the op-code.
Direct addressing mode is made of three sub-modes:
Table 21.
Available Long and Short Direct addressing mode instructions
Instructions Functions
LD, LDW
CP
AND, OR, XOR
ADC, ADD, SUB, SBC, ADDW, SUBW
BCP
Load
Compare
Logical Operations
Arithmetic Addition/Subtraction operations
Bit Compare
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Table 21.
Available Long and Short Direct addressing mode instructions
Instructions Functions
MOV
CLR
INC, DEC
TNZ
CPL, NEG
SLA, SLL, SRL, SRA, RLC, RRC
SWAP
CALL, JP
Move
Clear
Increment/Decrement
Test Negative or Zero
1’s or 2’s Complement
Shift and Rotate Operations
Swap Nibbles
Call or Jump subroutine
Table 22.
Available Extended Direct addressing mode instructions
Instructions Function
CALLF, JPF
LDF
Call or Jump FAR subroutine
Far load
Table 23.
Available Long Direct addressing mode instructions
Instructions Function
EXG
PUSH, POP
Exchange
Stack operation
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STM8 addressing modes
6.3.1
PM0044
Short Direct addressing mode
The address is a byte, thus require only one byte after the op-code, but only allow 00..FF addressing space.
Example:
004B 20
052D B64B coeff dc.b
LD
$20
A,coeff
Action:
A = (coeff) = ($4B) = $20
Figure 8.
Short Direct addressing mode example
Before Completion
Coeff .byte 20h
LD A,Coeff
20
B6
4B
004B
052D
052E
052F
A
Previous Value
PC
052D
Steps to Determine
Effective Address
PC = 052D
PC = PC + 1 = 052E
EA = (PC)
= (4B + 0000)
= 004B
EA 004B
Coeff .byte 20h
LD A,Coeff
20
B6
4B
004B
After Completion
A
20
052D
052E
052F
New PC
052F
Instruction Complete
A = (EA) = 20
New PC = PC + 1 = 052F
VR02059L
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6.3.2
STM8 addressing modes
Long Direct addressing mode
The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes after the op-code.
Example:
0409
06E5
Action:
C606E5
40 coeff
LD dc.b
A = (coeff) = ($06E5) = $40
A,coeff
$ 40
Figure 9.
Long Direct addressing mode example
Before Completion
LD A,Coeff C6
06
E5
0409
040A
040B
040C
06E5
A
Previous Value
PC
0409
Steps to Determine
Effective Address
PC = 0409
PC = PC + 1 = 040A
EA = (PC) : (PC+1) = 06E5
Coeff .byte 040h 40 06E5 EA 06E5
After Completion
LD A,Coeff
Coeff .byte 040h
C6
06
E5
40
0409
040A
040B
040C
06E5
New PC
040C
A
40
Instruction Complete
A = (EA) = 40
New PC = PC + 2 = 040C
VR02059B
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STM8 addressing modes
6.3.3
PM0044
Extended Direct addressing mode (only for CALLF and JPF)
The address is an extended word, thus allowing 000000 to FFFFFF addressing space, but requires 3 bytes after the op-code.
Example:
CALLF sw_routine 000409
0106E5
Action:
8D0106E5
PC = $0106E5
Figure 10.
Far Direct addressing mode example
Before Completion
CALLF sw_routine
8D
01
0 6
E5
0409
040A
040B
040C
0106E5
A
Previous Value
PC
0409
Steps to Determine
Effective Address
PC = 0409
PC=PC+1
EA=(PC):(PC+1):(PC+2)
=0106E5
New PC = EA
INC A 4C
EA 0106E5
0106E5
After Completion
CALLF sw_routine
Instruction Complete
New PC = 0106E5
INC A
8D
01
0 6
E5
4C
0409
040A
040B
040C
0106E5
New PC
0106E5
VR02059U
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6.4
STM8 addressing modes
Indexed addressing mode (No Offset, Short, SP, Long,
Extended)
Table 24.
Overview Indexed addressing mode instructions
Addressing mode Syntax EA formula Ptr Adr Ptr Size
No offset
Short
Stack
Pointer
Long
Extended
Direct Indexed (ndx) (ndx) -----
Direct Indexed (shortoff,ndx) (ptr + ndx) op + 1 Byte
Direct Indexed (shortoff,SP) (ptr + SP) op + 1 Byte
Dest adr
00..FFFF
00..100FE
00..(FF+stacktop)
Direct Indexed (longoff,ndx) (ptr.w + ndx) op + 1..2 Word 000000..01FFFE
Direct Indexed (extoff,ndx) (ptr.e + ndx) op + 1..3 Ext Word 000000..FFFFFF
The data byte required for operation is found by its memory address, which is defined by the unsigned addition of an index register (X or Y or SP) with an offset which follows the opcode.
The indexed addressing mode is made of five sub-modes:
Table 25.
No Offset, Long, Short and SP Indexed instructions
Instructions Functions
LD, LDW
CLR
CP
AND, OR, XOR
ADC, ADD, SUB, SBC, ADDW, SUBW
INC, DEC
TNZ
CPL, NEG
SLA, SLL, SRL, SRA, RLC, RRC
SWAP
Load
Clear
Compare
Logical Operations
Arithmetic Addition/Subtraction operations
Increment/Decrement
Test Negative or Zero
1’s or 2’s Complement
Shift and Rotate Operations
Swap Nibbles
Table 26.
No Offset, Long, Short Indexed Instructions
Instructions
CALL, JP
Functions
Call or Jump subroutine
Table 27.
Extended Indexed Instructions only
Instructions
LDF Far Load
Functions
Doc ID 13590 Rev 3 39/162
STM8 addressing modes
6.4.1
PM0044
No Offset Indexed addressing mode
There is no offset, (no extra byte after the op-code), but only allows 00..FF addressing space.
Example:
00B8
05F2
05F4
11223344
AEB8
F6 table dc.w $1122, $3344
LD X,#table
LD A,(X)
Action:
X = table
A = (X) = (table) = ($B8) = $11
Figure 11.
No Offset Indexed addressing mode example
Before completion
Table .word 1122
LD A,(X)
11
22
33
44
F6
00B8
00B9
00BA
00BB
05F4
A
Previous Value
X
B8
PC
05F4
EA
00B8
Steps to determine
Effective Address
PC = 05F4
EA = X + 0000 = 00B8
Table .word 1122
11
22
33
44
00B8
After completion
A
11
X
B8
Instruction Complete
A = (EA) = 11
New PC = PC +1 = 05F5
LD A,(X) F6 05F4
05F5
New PC
05F5
VR02059C
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6.4.2
STM8 addressing modes
Short Indexed addressing mode
The offset is a byte, thus requires only one byte after the op-code, but only allows 00..1FE addressing space.
Example:
0089 11223344 table dc.l
0759 AE03
075B E689
LD
$11223344
X,#3
LD A,(table,X)
Action:
X = 3
A = (table, X) = ($89, X) = ($89, 3) = ($8C) = $44
Figure 12.
Short Indexed - 8-bit offset - addressing mode example
Before completion
Table .long 11223344
LD A, (table,X)
11
22
33
44
E6
89
0089
008A
008B
008C
A
Previous Value
X
03
PC
075B
075B
075C
075D
EA
89
Adder
03
008C
Steps to determine
Effective Address
PC = 075B
PC = PC + 1 = 075C
EA = (PC) + X = 89 + 03 = 008C
Table .long 11223344
LD A, (table,X)
11
22
33
44
E6
89
0089
008A
008B
008C
075B
075C
075D
After Completion
A
44
X
03
New PC
075D
Instruction Complete
A = (EA) = 44
New PC = PC + 1 = 075D
VR02059D
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STM8 addressing modes
6.4.3
PM0044
SP Indexed addressing mode
The offset is a byte, thus require only one byte after the op-code, but only allow 00..(FF + stack top) addressing space.
Example:
0086 4B11
0087 4B22
0088 4B33
0089 7B03
PUSH #$11
PUSH #$22
PUSH #$33
LD A,($03,SP)
Action:
A = ($03, SP) = ($03, $1FFC) = ($1FFF) = $11
Figure 13.
SP Indexed - 8-bit offset - addressing mode example
Before completion
LD A, ($03,SP)
7B
03
0089
008A
008B
PC
0089
A
Previous Value
SP
1FFC
33
22
11
1FFC
1FFD
1FFE
1FFF
Steps to determine effective address
PC = 0089
PC = PC + 1 = 008A
EA = (PC) + SP=03+1FFC= 1FFF
1FFC
Adder
03
EA 1FFF
After completion
LD A, ($03,SP)
7B
03
0089
008A
008B
33
22
11
1FFC
1FFD
1FFE
1FFF
New PC
008B
SP
1FFC
A
11
Instruction Complete
A = (EA) = 11
New PC = PC+1 = 008B
VR02059D
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6.4.4
STM8 addressing modes
Long Indexed addressing mode
The offset is a word, thus allowing up to 128 KB addressing space, but requires 2 bytes after the op-code.
Example:
0690 AE02
0692 D6077E
077E BF
86
DBCF
Action: table
LD X,#2
LD A,(table,X) dc.b $BF dc.b $86 dc.w $DBCF
X = 2
A = (table, X) = ($077E, X) = ($077E, 2) = ($0780) = $DB
Figure 14.
Long Indexed - 16-bit offset - addressing mode example
Before completion
LD A, (table, X)
PC
0692
Steps to Determine
Effective Address table . byte BF
BF
86
DB
CF
D6
07
7E
0692
0693
0694
077E
077F
0780
0781
X
02
A
Previous Value
077E 02
PC = 0692
PC = PC + 1 = 0693
EA = (PC):(PC+1) + X
= 077E + 02 = 0780
Adder
LD A, (table, X) table . byte BF
D6
07
7E
BF
86
DB
CF
0692
0693
0694
0695
EA
After Completion
0780
X
02
New PC
0695
077E
077F
0780
0781
A
DB
Instruction Complete
A = (EA) = DB
New PC = PC + 2 = 0695
VR02059E
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STM8 addressing modes PM0044
The offset is an extended word, thus allowing 16Mbyte addressing space (from 000000 to
FFFFFF), but requires 3 bytes after the op-code.
Example:
0690 AE02
0692 AF010780
010780 BF table
86
DDFE
LD dc.b
dc.w
X,#2
LDF A,(table,X) dc.b
$BF
$86
$DDFE
Action:
X = 2, A = (table, X) = ($010780,X) = ($010780+2)) = ($010782) = $DD
Figure 15.
Far Indexed - 16-bit offset - addressing mode example
Before Completion
PC
Steps to determine
LDF A, (table, X) AF 0692 0692
Effective Address
01 0693
07
80
0694
0695
X
02
A
PC = 0692
PC = PC + 1 = 0693
EA= (PC):(PC+1):(PC+2)+X
= 010780+02 = 010782
Previous Value table . byte BF
BF
86
DD
FE
010780
010781
010782
010783
010780
Adder
02
LD A, (table, X) AF
01
07
80
0692
0693
0694
0695
0696
EA
After Completion
010782
X
02
New PC
0696
Instruction Complete
A = (EA) = DD
New PC = PC+3 = 0696 table . byte BF
BF
86
DD
FE
010780
010781
010782
010783
A
DD
VR02059R
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6.5
STM8 addressing modes
Indirect (Short Pointer Long, Long Pointer Long)
Table 28.
Overview of Indirect addressing instructions
Addressing mode
Short Pointer Long Indirect
Long Pointer Long Indirect
Syntax EA formula Ptr Adr
Ptr
Size
((shortptr.w)) ((shortptr.w)) 00..FF
Word
((longptr.w)) ((longptr.w)) 0000..FFFF Word
Dest adr
0000..FFFF
0000..FFFF
The data byte required for the operation is found by its memory address, located in memory
(pointer).
The pointer address follows the op-code. The indirect addressing mode is made of three sub-modes:
Table 29.
Available Long Pointer Long and Short Pointer Long Indirect Instructions
Instructions Functions
LD, LDW
CP
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
CALL, JP
Load
Compare
Logical Operations
Arithmetic Addition/Subtraction operations
Bit Compare
Call or Jump subroutine
Table 30.
Available Long Pointer Long Indirect Instructions
Instructions Functions
CLR
TNZ
CPL, NEG
SLA, SLL, SRL, SRA, RLC, RRC
SWAP
INC, DEC
Clear
Test Negative or Zero
1’s or 2’s Complement
Shift and Rotate Operations
Swap Nibbles
Increment/Decrement
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STM8 addressing modes
6.6
PM0044
Short Pointer Indirect Long addressing mode
The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB addressing space, and requires 1 byte after the op-code.
Example:
0040 42E5 ptr dc.w
var
0409
42E5
Action:
92C640
11
LD A,[shortptr.w] var dc.b
$11
A = [shortptr.w] = ((shortptr.w)) = (($40.w)) = ($42E5) =
$11
Figure 16.
Short Pointer Indirect Long addressing mode example
Before Completion
Steps to determine
Effective Address ptr .word var
LD A, [shortptr.w]
42
E5
0040
0041
A
Previous Value
PC
0409
PC = 0409
PC = PC + 2 = 40B
EA = ((PC)) :((PC)+1)
= 42E5
92
C6
40
0409
040A
040B
040C var.byte 0x011 11 42E5 EA 42E5
After Completion ptr .word var
LD A, [shortptr.w]
42
E5
92
C6
40
0040
0041
0409
040A
040B
040C var .byte 0x011 11 42E5
New PC
040C
A
0x11
Instruction Complete
A = (EA) = 0x11
New PC = PC +1 = 040C
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6.7
STM8 addressing modes
Long Pointer Indirect Long addressing mode
The pointer address is a word, the pointer size is a word, thus allowing 64 KB addressing space, and requires 2 bytes after the op-code.
Example:
1040
1409
42E5
Action:
42E5
72C61040
11 ptr var dc.w
LD dc.b
var
A,[longptr .
w]
$11
A = [longptr.w] = ((longptr.w)) = (($1040.w)) = ($42E5) = $11
Figure 17.
Long Pointer Indirect Long addressing mode example
Before Completion
Steps to determine
Effective Address ptr .word var
LD A, [longptr.w]
42
E5
72
C6
10
40
1040
1041
1409
140A
140B
140C
140D
A
Previous Value
PC
1409
PC = 1409
PC = PC + 2 = 140B
EA =((PC):(PC+1)):
((PC):(PC+1)+1)
= 42E5
EA 42E5 var.byte 0x011 11 42E5
After Completion ptr .word var 42
E5
1040
1041
Instruction complete
A = (EA) = 0x11
New PC = PC + 2 = 140D
LD A, [longptr.w] var .byte 0x11
72
C6
10
40
11
1409
140A
140B
140C
140D
42E5
New PC
040D
A
0x11 VR02059G
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STM8 addressing modes PM0044
6.8 Indirect Indexed (Short Pointer Long, Long Pointer Long,
Long Pointer Extended) addressing mode
Table 31.
Overview of Indirect indexed instructions
Addressing mode Syntax EA formula Ptr Adr Ptr Size Dest adr
Short Pointer
Long
Indirect Indexed ([shortptr.w],ndx) ((shortptr.w) + ndx) 00..FF
Word
Long Pointer
Long
Indirect Indexed ([longptr.w],ndx) ([longptr.w] +ndx) 00..FFFF
Word
000000.01FFFE
000000.01FFFE
Long Pointer
Extended
Indirect Indexed ([longptr.e],ndx) ([longptr.e] +ndx) 00..FFFF
Extword 000000.FFFFFE
This is a combination of indirect and indexed addressing mode. The data byte required for the operation is found by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the op-code.
The indirect indexed addressing mode is made of four sub-modes:
Table 32.
Available Long Pointer Long and Short Pointer Long Indirect
Indexed instructions
Instructions Functions
LD, LDW
CP
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
CALL, JP
Load
Compare
Logical Operations
Arithmetic Addition/Subtraction operations
Bit Compare
Call or Jump subroutine
Table 33.
Available Long Pointer Long Indirect Indexed instructions
Instructions Functions
CLR
TNZ
CPL, NEG
SLA,SLL, SRL, SRA, RLC, RRC
SWAP
INC, DEC
Clear
Test Negative or Zero
1’s or 2’s Complement
Shift and Rotate Operations
Swap Nibbles
Increment/Decrement
Table 34.
Long Pointer Extended Indirect Indexed instructions instruction
Instructions Functions
LDF Far load
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6.9
STM8 addressing modes
Short Pointer Indirect Long Indexed addressing mode
The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB addressing space, and requires 1 byte after the op-code.
Example:
0089 0800 ptr dc.w
table
0800 10203040 table dc.b
$10,$20,$30,$40
0690 AE03
0692 92D689
LD
LD
X,#3
A,([shortptr.w],X)
X = 3
A = ([shortptr.w],X) = ((shortptr.w), X)
= (($89.w), 3)
= ($0800,3) = ($0803) = $40
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STM8 addressing modes
Figure 18.
Short Pointer Indirect Long Indexed addressing mode example
Before completion ptr .word table
LD A,([shortptr.w],X)
08
00
0089
008A
PC
0692
Steps to determine
Effective Address table .byte 0x 10, 0x 20, 0x 30,
0x
40
10
20
30
40
92
D6
89
0692
0693
0694
800
801
802
803
X
03
A
Previous value
800
Adder
03
PC = 0692
PC = PC + 2 = 0694
EA = ((PC)) : ((PC)+1) + X
EA = 0803
EA 0803
PM0044
After completion ptr .word table
LD A,([shortptr.w],X) table .byte 0x10, 0x 20, 0x 30
0x 40
10
20
30
40
08
00
92
D6
89
0089
008A
0692
0693
0694
0695
0800
0801
0802
0803
X
03
New PC
0695
A
40
Instruction Complete
A = (EA) = 40
New PC = PC + 1 = 0695
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6.10 Long Pointer Indirect Long Indexed addressing mode
The pointer address is a word, the pointer size is a word, thus allowing up to 128 KB addressing space, and requires 2 bytes after the op-code.
Example:
1089 1800 ptr dc.w
table
1800 10203040 table dc.b
$10,$20,$30,$40
1690 AE03
1692 72D61089
LD
LD
X,#3
A,([longptr.w],X)
X = 3
A = ([longptr.w],X) = ((longptr.w), X) =
(($1089.w), 3)
= ($1800,3) = ($1803) = $40
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STM8 addressing modes
Figure 19.
Long Pointer Indirect Long Indexed addressing mode example
Before completion ptr .word table
18
00
1089
108A
Steps to determine
Effective Address
LD A,([longptr.w],X)
PC
1692 table .byte 0x 10, 0x 20, 0x 30,
0x
40
10
20
30
40
72
D6
10
89
1692
1693
1694
1695
1800
1801
1802
1803
X
03
A
Previous value
1800
Adder
03
PC = 1692
PC = PC + 2 = 1694
EA = (((PC) : (PC+1)) :
((PC) : (PC+1) +1)) + X
EA = 1803
EA 1803
After completion ptr .word table 18
00
1089
108A
Instruction Complete
LD A,([longptr.w],X) 92
D6
10
89
1692
1693
1694
1695
1696
X
03
New PC
1696
A = (EA) = 40
New PC = PC + 2 = 1696
PM0044 table .byte 0x 10, 0x 20, 0x 30,
0x 40
10
20
30
40
1800
1801
1802
1803
A
40
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6.11 Long Pointer Indirect Extended Indexed addressing mode
The pointer address is a word, the pointer size is an extended word, thus allowing 16-Mbyte addressing space, and requires 2 bytes after the op-code.
Example:
1089 180000 ptr dc.b
page(table), high(table), low(table)
180000 10203040 table dc.b
$10,$20,$30,$40
1690 AE03
1692 72A71089
LD
LDF
X,#3
A,([longptr.e],X)
X = 3
A = ([longptr.e],X) = ((longptr.e), X) =
(($1089.e), 3)
= ($180000,3) = ($180003) = $40
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STM8 addressing modes PM0044
Figure 20.
Long Pointer Indirect Extended Indexed addressing mode example ptr .word table
LDF A,([longptr.w],X) table .byte 0x 10, 0x 20, 0x 30,
0x
40
10
20
30
40
72
A7
10
89
18
00
00
1089
108A
108B
Before completion
PC
1692
1692
1693
1694
1695
X
03
A
Previous value
180000
180001
180002
180003
180000
Adder
03
Steps to Determine
Effective Address
PC = 1692
PC = PC + 2 = 1694
EA = (((PC) : (PC+1)) :
((PC) : (PC+1) +1) :
((PC) : (PC+1) +2)) + X
EA = 180003
EA 180003
After completion ptr .word table
18
00
00
1089
108A
108B
Instruction Complete
LDF A,([longptr.w],X) 72
A7
10
89
1692
1693
1694
1695
1696
X
03
New PC
1696
A = (EA) = 40
New PC = PC + 2 = 1696 table .byte
0x
10,
0x
20,
0x
30,
0x 40
10
20
30
40
180000
180001
180002
180003
A
40
VR02059I
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6.12 Relative Direct addressing mode
Table 35.
Overview of Relative Direct addressing mode instructions
Addressing mode Syntax EA formula Ptr Adr Ptr Size
Direct Relative off PC = PC + off op + 1 ---
Dest adr
PC +127/-128
This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. The offset added to the PC register value is relative to the start of the next instruction.
Table 36.
Available Relative Direct instructions
Instructions
JRxx
JRA
CALLR
Functions
Conditional Jump
Jump Relative Always
Call Relative
The offset follows the op-code.
Example:
04A7
04A9
04AA
2717
9D
9D jreq skip nop nop
04C0
Action:
20FE skip jra* ; Infinite loop if (Z == 1)then PC = PC + $17 = $04A9 + $17 = $04C0 elsePC = PC= $04A9
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STM8 addressing modes
Figure 21.
Relative Direct addressing mode example
JREQ SKIP
27
17
04A7
04A8
04A9 02
Before completion
CC
Z
PC
04A7
Adder
04A7
04A9
EA
Steps to Determine
Effective Address
PC = 04A7
PC = PC + 1 = 04A8
TEMP = (PC) = 17
PC = PC +1 = 04A9
Stop here if there is no Branch; i.e., Z = 0
EA = PC + TEMP
= 04A9 + 17
= 04C0
New PC = EA if Branch is taken
JREQ SKIP 27
17
04A7
04A8
04A9
After completion
(Branch taken)
CC
Z = 1
PC
04A9
Instruction Complete
New PC = EA = 04C0
04A9
SKIP :
04C0
17
Adder
04C0
New PC
04C0
After completion
(No branch taken)
CC
Z = 0
EA
Instruction Complete
JREQ SKIP
New PC = EA = 04A9
27
17
04A7
04A8
04A9
New PC
04A9
PM0044
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Table 37.
Overview of Bit Direct addressing mode instruction
Addressing mode Syntax EA formula Ptr Adr Ptr Size
Bit Long Direct longmem, #pos (longmem) op + 1..2
Word
Dest adr
0000..FFFF
The data byte required for the operation is found by its memory address, which follows the op-code. The bit used for the operation is selected by the bit selector which is encoded in the instruction op-code.
Table 38.
Available Bit Direct instructions
Instructions Functions
BSET
BCPL
BCCM
Bit Set
Bit Complement
Copy Carry Bit to Memory
The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes after the op-code. The bit selector #n (n=0 to 7) selects the n th
bit from the byte pointed to by the address.
Example:
0408 721006E5 BCPL coeff, #0
06E5
Action:
40 coeff dc.b
$ 40
(coeff) = ($06E5) XOR 2**0 = $40 XOR $01 = $41
Doc ID 13590 Rev 3 57/162
STM8 addressing modes
Figure 22.
Bit Long Direct addressing mode example
Before c ompletion
PM0044
BCPL Coeff,#0
Coeff .byte 040h
90
10
06
E5
40
0408
0409
040A
040B
040C
06E5
PC
0408
06E5 EA 06E5
After c ompletion
BCPL Coeff,#0
Coeff .byte 040h
90
10
06
E5
41
0408
0409
040A
040B
040C
06E5
Steps to d etermine e ffective a ddress
PC = 0408
PC = PC + 2 = 040A
EA = (PC ) : (PC+1) = 06E5
New PC
040C
40 XOR 01
Instruction c omplete
(EA) = (EA) | 2**0 = 40 | 01 = 41
New PC = PC + 2 = 040C
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Table 39.
Overview of Bit Direct (Long) Relative addressing mode
Addressing mode Syntax EA formula Ptr Adr Ptr Size Dest adr
Bit
(longmem) op + 1..2
Word 0000..FFFF
Long
Direct
Relative longmem, #pos, off
PC = PC + off op + 3 Byte
PC +127/-
128
This addressing mode is a combination between the Bit Direct addressing mode (for data addressing) and Relative Direct mode (for PC computation).
The data byte required for the operation is found by its memory address, which follows the op-code. The bit used for the test operation is selected by the bit selector which is encoded in the instruction op-code. Following the logical test operation, the PC register value can be modified, by adding an 8-bit signed offset to it.
Table 40.
Available Bit Direct Relative instructions
Instructions
BTJT, BTJF Bit Test and Jump
Functions
The data address is a word, thus allowing 0000 to FFFF addressing space (requires 2 bytes after the op-code). The bit selector #n (n=0 to 7) selects the n th
bit from the byte pointed to by the address. The offset follows the op-code and data address.
Example:
104B 00 DRA dc.b
$00 ; Port A data register (input value) bit0 equ $0 ; data bit 0
04A7 7201104BFB wait_1 BTJF DRA, bit0, wait_1
04AC ....
cont_0
Action:
Test = select_bit(0, ($4B)) = select_bit(0, DRA) if (Test /= 1) then PC = PC + $FB = $0004AC - $05 =
$0004A7 else PC = PC = $0004AC
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STM8 addressing modes PM0044
Figure 23.
Bit Long Direct Relative addressing mode example
DRA .byte wait_1
BTJF DRA, #0, wait_1 wait_1
BTJF DRA, #0, wait_1
DRA b0
104B
104C
72
01
10
4B
FB
72
01
10
4B
FB
04A7
04A8
04A9
04AA
04AB
04A7
04A8
04A9
04AA
04AB
05
DRA.b0 =? 0
PC
04A7
Adder
04A7
04AC
EA
After completion
(Branch taken)
(EA) b0 = 0
04A7
New PC
PC
04AC
FB 04AC
Steps to Determine
Effective Address
PC = 04A7
PC = PC + 2 = 04A9
EA = (PC):(PC+1) = 104B
Test = (EA).b0
PC = PC + 2 = 04AB
TEMP = (PC) = FC
PC = PC +1 = 04AC
Stop here if there is no Branch; i.e., Test = TRUE (1)
EA = PC + TEMP
= 04AA + FD
= 04A7
New PC = EA if Branch is taken
Instruction Complete
New PC = EA = 04A7
Adder wait_1
BTJF DRA, #0, wait_1
72
01
10
4B
FB
04A7
04A8
04A9
04AA
04AB
04AC
04A7
After completion
(No branch taken)
(EA) b0 = 1
EA
Instruction Complete
New PC = EA = 04AC
New PC
04AC
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7 STM8 instruction set
STM8 instruction set
7.1 Introduction
This chapter describes all the STM8 instructions. There are 96 and they are described in alphabetical order. However, they can be classified in 13 main groups as follows:
Table 41.
Instruction groups
Load and
Transfer
LD LDF CLR
Stack operation
PUSH POP
PUSH
W
Increment/
Decrement
Compare and
Tests
Logical operations
Bit Operation
Conditional Bit
Test and
Branch
Arithmetic operations
INC
CP
AND
DEC INCW DECW
BSET BRES BCPL BCCM
BTJT BTJF
NEG
TNZ
OR
ADC
BCP
XOR
ADD
MOV EXG LDW CLRW EXGW
POPW
CPW TNZW
CPL CPLW
SUB SBC MUL DIV DIVW NEGW ADDW SUBW
Shift and
Rotates
SLL SRL SRA
SWAP RLWA RRWA
RLC RRC SWAP SLLW SRLW SRAW RLCW RRCW
Unconditional
Jump or Call
Conditional
Branch/
Execution
Interrupt management
Condition
Code Flag modification
Breakpoint/ software break
JRA
JRxx
TRAP
SIM
BREAK
JRT
WFE
WFI
RIM
JRF
SCF
JP
HALT IRET
RCF
JPF CALL CALLR CALLF RET RETF NOP
CCF RVF
The instructions are described with one to five bytes.
PC-1 End of previous instruction
PC Op-code
PC+1..4 Additional word (0 to 4) according to the number of bytes required to compute the effective address(es)
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STM8 instruction set PM0044
Using a pre-code (two-byte op-codes)
In order to extend the number of available op-codes for an 8-bit CPU (256 op-codes), four different pre-code bytes are defined. These pre-codes modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-1
PC
End of previous instruction
Pre-code
PC+1 Op-code
PC+2 Additional word (0 to 3) according to the number of bytes required to compute the effective address
These pre-bytes are:
0x90 = PDY Replaces an X based instruction using immediate, direct, indexed or inherent addressing mode by a Y one.
0x92 = PIX
It also provides read/modify/write instructions using Y indexed addressing mode with long offset and two bit handling instructions
(BCPL and BCCM)
Replaces an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.
0x91 = PIY
0x72 = PWSP
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
Replace an instruction using indirect X indexed addressing mode by a Y one.
Provide long addressing mode for bit handling and read/modify/write instructions.
It also provides indirect addressing mode with two byte pointer for read/modify/write and register/memory instructions.
Finally it provides stack pointer indexed addressing mode on register/memory instructions.
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7.2 Nomenclature
7.2.1 Operators
←
↔ is loaded with ...
has its value exchanged with ...
A
X
XL
XH
Y
YL
YH
PC
PCL
PCH
PCE
SP
CC
CC.V
CC.I0
CC.H
CC.I1
CC.N
CC.Z
CC.C
accumulator
X index register (2 bytes) least significant byte of the X index register (1 byte) most significant byte of the X index register (1 byte)
Y index register (2 bytes) least significant byte of the Y index register (1 byte) most significant byte of the Y index register (1 byte) program counter register (3 bytes) low significant byte of the program counter register (1 byte) high significant byte of the program counter register (1 byte) extended significant byte of the program counter register (1 byte) stack pointer register (2 bytes)
Condition code register (1 byte) overflow flag of the code condition register (1 bit) interrupt mask bit 0 of the code condition register (1 bit) half carry flag of the code condition register (1 bit) interrupt mask bit 1 of the code condition register (1 bit) negative flag of the code condition register (1 bit) zero flag of the code condition register (1 bit) carry flag of the code condition register (1 bit)
STM8 instruction set
7.2.4
-
1
0
X bit not affected by the instruction bit forced to 1 by the instruction bit forced to 0 by the instruction bit modified by the instruction
Memory and addressing
M(...)
R
R(...)
R n
XX .
B content of a memory location
8-bit operation result value
8-bit operation result value stored into the register or memory shown inside parentheses bit n of the operation result value (0
≤ n
≤
7) bit B of the XX register or memory location imm.b
imm.w
byte immediate value
16-bit immediate value shortmem memory location with short addressing mode (1 byte) longmem memory location with long addressing mode (2 bytes) extmem memory location with extended addressing mode (3 bytes) shortoff short offset (1 byte) longoff long offset (2 bytes) extoff extended offset (3 bytes)
[shortptr.w] short pointer (1 byte) on long memory location (2 bytes). Assembler notation = [$12.w].
[longptr.w] long pointer (2 bytes) on long memory location (2 bytes). Assembler notation = [$1234.w]
[longptr.e] long pointer (2 bytes) on extended memory location (3 bytes). Assembler notation = [$1234.e]
Doc ID 13590 Rev 3 63/162
STM8 instruction set PM0044 ee ww bb ii iw rr extended order byte of 24-bit extended address high order byte of 16-bit long address or middle order byte of 24-bit extended address short address or low order byte of 16-bit long address or 24-bit extended address immediate data byte or low order byte of 16-bit immediate data high order byte of 16-bit immediate data relative offset byte in a range of [-128..+127]
Table 42.
Instruction set summary
Effect on CC register
Description
V I1 H I0 N Z C
Syntax example Operation
Example opcode(s)
ADC Add with carry ADC A,($12,SP)
A ← A + M(SP+shortoff) +
CC.C
19 bb 1
ADD
Add without carry
ADD A,($12,SP) A
←
A + M(SP+shortoff) 1B bb 1
ADD SP,#$12 SP ← SP + imm.b
5B ii 2
ADDW
Add word without carry
ADDW X,($12,SP) X
←
-X + M(SP+shortoff) 72 FB bb 2
AND Logical AND AND A,($12,SP)
A
←
A AND
M(SP+shortoff)
14 bb 1
64/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
BCCM
Copy carry in memory bit
BCCM $1234,#1
Operation
M(longmem).bit ← CC.C
Example opcode(s)
90 1n ww bb n= 2*bit
1
BCP
Logical bit compare
BCP A,($12,SP) test {A AND
M(SP+shortoff) }
N and Z are updated accordingly
15 bb 1
BCPL
BREAK
Complement bit in memory
Software breakpoint
BRES Bit reset
-
-
-
BSET
BTJF
BTJT
Bit set
Bit test and relative jump if condition is false
Bit test and relative jump if condition is true
-
-
-
CALL
Call to
Subroutine with address in same section
-
-
-
-
-
-
-
-
CALLF
Call to subroutine with extended address
-
CALLR
Call Subroutine relative
CCF
CLR
CLRW
Complement carry flag
Clears the destination byte
Clears the destination index register
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BCPL $1234,#1
SW-BREAK
BRES $1234,#1
BSET $1234,#1
M(longmem).bit
M(longmem).bit
M(longmem).bit
M(longmem).bit
←
←
←
0
1
90 1n ww bb n= 2*bit
8B
72 1n ww bb n= 1 + 2*bit
72 1n ww bb n= 2*bit
1
1
1
1 Flush bit BTJF $1234,#1,label if M(longmem).bit=0 then PC
←
PC + 4 + rr else PC
←
PC + 4
72 0n ww bb n= 1 + 2*bit
2/3
Flush
(2)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
1
1
C
-
-
-
bit BTJT $1234,#1,label
CALL [$1234.w]
CALLF $123456
CALLR label
CCF
CLR ([$1234.w],X) if M(longmem).bit=1 then PC ← PC + 4 + rr else PC ← PC + 4
PC ← PC + 4
M(SP--)
←
PCL
M(SP--) ← PCH
PCH
←
M(longmem)
PCL ← M(longmem + 1)
PC
←
PC+4
M(SP--) ← PCL
M(SP--) ← PCH
M(SP--) ← PCE
PC ← extmem
PC ← PC + 4
M(SP--)
←
PCL
M(SP--) ← PCH
PC
←
PC + rr
CC.C ← CC.C
72 0n ww bb n= 2*bit
72 CD ww bb
8D ee ww bb
AD bb
8C
M( M(longmem).w + X ) ←
0x00
72 6F ww bb
2/3
6
5
4
1
4
Flush
Flush
Flush
Flush
CLRW X X ← 0x0000 5F 1
CP Compare CP A,($12,SP) test { A - M(SP+shortoff) } 11 bb 1
Doc ID 13590 Rev 3 65/162
STM8 instruction set
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
Operation
Example opcode(s)
PM0044
CPW Compare word CPW X,($12,SP) test { X - M(SP+shortoff) } 13 bb 2
CPL
Logical 1’s complement
CPLW
Logical 1’s complement
-
-
DEC
Decrement byte by one
-
-
1 CPL ([$1234.w],X)
M(M(longmem).w +X)
←
FF - M(M(longmem).w+X) or
M(M(longmem).w+X)
XOR FF
72 63 ww bb 4
1 CPLW X
X
←
FFFF - X or
X XOR FFFF
53 2
DEC ([$1234.w],X)
M(M(longmem).w + X) ←
M(M(longmem).w + X) - 1
72 6A ww bb 4
DECW
DIV
Decrement word by one
16 by 8
Unsigned division
-
0 0 0
DECW X
DIV X,A
DIV Y,A
X ← X - 1 5A
X ← X/A (Quotient)
A ← X%A (Remainder)
Y ← Y/A (Quotient)
A ← Y%A (Remainder)
62
90 62
1
DIVW
16 by 16
Unsigned division
0 0 0 DIVW X,Y
EXG
Data byte exchange
-
EXGW
HALT
Data word exchange
Halt oscillator
(CPU +
Peripherals)
-
-
-
1 -
-
0 -
-
-
-
-
EXG A,$1234
EXG A,XL
EXG A,YL
EXGW X,Y
HALT
X ← X/Y (Quotient)
Y ← X%Y (Remainder)
65 16
A ↔ M(longmem)
A ↔ XL
A ↔ YL
X
↔
Y
CC.I0 ← 0 , CC.I1 ← 1
Oscillator stopped till an interrupt occurs
8E
31 ww bb
41
61
51
3
1
1
1
10
16
16
66/162 Doc ID 13590 Rev 3
PM0044
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
Operation
STM8 instruction set
Example opcode(s)
INC
Increment byte by one
INC ([$1234.w],X)
M(M(longmem).w + X) ←
M(M(longmem).w + X) + 1
72 6C ww bb 4
INCW
Increment word by one
INCW X X ← X + 1 5C 2
INT
IRET
Interrupt
Interrupt return
INT $123456
Updated according to the value pop from the stack into CC register IRET
JP
JPF
JRA
JRC
Jump to an address in section 0
Jump to an extended address
Unconditional relative jump
-
-
-
-
-
-
-
-
-
-
-
-
Jump if C = 1 -
-
-
JP ([$1234.w],X)
-
-
JPF $123456
JRA Label
JRC Label
JREQ
JRF
JRH
Jump if Z =
1(equal)
Never Jump
Jump if H = 1 -
-
-
-
-
-
-
-
-
-
-
JREQ Label
JRF Label
JRH Label
JRIH
Jump if Port INT pin = 1
-
JRIL
Jump if Port INT pin = 0
-
JRM
JRMI
Jump if
Interrupts are masked
Jump if N =
1(minus)
-
-
-
-
-
-
-
-
-
-
-
JRIH Label
-
-
JRIL Label
JRM Label
JRMI Label
JRNC jump if C = 0 JRNC Label
PC ← extmem
(++SP)
CC
←
M(++SP)
A
←
M(++SP)
X
←
M(++SP); SP++
Y
←
M(++SP); SP++
PCE
←
M(++SP)
PCH
←
M(++SP)
PCL
←
M(++SP)
82 ee ww bb
80
2
11 Flush
PC ← M(longmem).w + X 72 DC ww bb 5 Flush
PC
←
extmem
PC ← PC + 2+ rr if CC.C =1 then PC
←
PC + 2+ rr else PC ← PC + 2 if CC.Z = 1 then PC ← PC + 2+ rr else PC ← PC + 2
---------------if CC.H = 1 then PC ← PC + 2+ rr else PC ← PC + 2 if Port INT pin =1 then PC
←
PC + 2+ rr else PC ← PC + 2 if Port INT pin = 0 then PC ← PC + 2+ rr else PC
←
PC + 2 if I0 AND I1 = 1 then PC ← PC + 2 + rr else PC
←
PC + 2 if CC.N = 1 then PC ← PC + 2+ rr else PC ← PC + 2 if CC.C =0 then PC
←
PC + 2+ rr else PC ← PC + 2
AC ee ww bb 2 Flush
20 bb
25 bb
27 bb
21 bb
90 29 bb
90 2F bb
90 2E bb
90 2D bb
2B bb
24 bb
2 Flush
1/2
Flush
1/2
1
1/2
1/2
1/2
1/2
1/2
1/2
Flush
Flush
Flush
Flush
Flush
Flush
Flush
Doc ID 13590 Rev 3 67/162
STM8 instruction set PM0044
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
JRNE
JRNH
JRNM
JRNV
JRPL
JRSGE
JRSGT
Jump if
(Z or (N xor V))
= 0
JRSLE
Jump if
(Z or (N xor V))
= 1
JRSLT
JRT
JRUGE
JRUGT
JRULE
JRULT
JRV
Jump if Z =0
(not equal)
Jump if H = 0
Jump if
Interrupts are not masked jump if V = 0
Jump if
N = 0 (plus)
Jump if
(N xor V) = 0
Jump if
(N xor V) = 1
Jump relative
Jump if C = 0
Jump if
(C+Z = 0)
Jump if
(C+Z =1)
Jump if C = 1
Jump if V = 1
A register load
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JRNE Label
JRNH Label
JRNM Label
JRNV Label
JRPL Label
JRSGE Label
JRSGT Label
JRSLE Label
JRSLT Label
JRT Label
JRUGE Label
JRUGT Label
JRULE Label
JRULT Label
JRV Label
LD A,($12,SP)
Operation
Example opcode(s) if CC.Z = 0 then PC ← PC + 2+ rr else PC ← PC + 2 if CC.H = 0 then PC
←
PC + 2+ rr else PC ← PC + 2 if I0 AND I1= 0 then PC ← PC + 2 + rr else PC ← PC + 2 if CC.C =0 then PC ← PC + 2+ rr else PC
←
PC + 2 if CC.N = 0 then PC
←
PC + 2+ rr else PC ← PC + 2 if (CC.N xor CC.V) = 0 then PC
←
PC + 2+ rr else PC ← PC + 2 if (CC.Z or (CC.N xor
CC.V)) = 0 then PC ← PC + 2+ rr else PC
←
PC + 2 if (CC.Z or (CC.N xor
CC.V)) = 1 then PC ← PC + 2+ rr else PC
←
PC + 2 if (CC.N xor CC.V) = 1 then PC
←
PC + 2+ rr else PC ← PC + 21
PC ← PC + 2+ rr if CC.C = 0 then PC ← PC + 2+ rr else PC ← PC + 2 if (CC.C = 0 and CC.Z = 0) then PC ← PC + 2+ rr else PC
←
PC + 2 if (CC.C = 1 and CC.Z = 1) then PC ← PC + 2+ rr else PC ← PC + 2 if CC.C = 1 then PC
←
PC + 2+ rr else PC ← PC + 21 if CC.V =1 then PC ← PC + 2+ rr else PC
←
PC + 2
A
←
M(SP+shortoff)
26 bb
90 28 bb
90 2C bb
28 bb
2A bb
2E bb
2C bb
2D bb
2F bb
20 bb
24 bb
22 bb
23 bb
25 bb
29 bb
7B bb
1/2
Flush
1/2
Flush
1/2
Flush
1/2
Flush
1/2
Flush
1/2
Flush
1/2
Flush
1/2
Flush
1/2
Flush
2 Flush
1/2
Flush
1/2 Flush
1/2 Flush
1/2
Flush
1/2 Flush
1
M(SP+shortoff) ← A 6B bb 1
LD
A register store
-
Register to register move
-
-
LD ($12,SP),A
LD A, XH A ← XH 95 1
68/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
LDF
LDW
X register load
X register store
Y register load
Y register store
-
SP register load
/ store
Index register move
-
MOV Data byte move -
MUL
Data load / store with extended address
-
8 by 8 multiplication
(unsigned)
-
-
-
0 -
-
Operation
-
-
-
-
LDF A,($123456,X)
-
LDF A,($123456,Y)
LDF A,([$1234.e],X)
LDF ($123456,X),A
LDF ($123456,Y),A
LDF ([1234.e],X),A
LDW X,($12,SP)
LDW ($12,SP),X
LDW Y,($12,SP)
LDW ($12,SP),Y
LDW SP,X
LDW X,SP
LDW X, Y
-
0
MOV $1234,#$12
MOV $12,$34
MOV mem1,mem2
MOV $1234,$5678
MOV mem1,mem2
MUL X,A
MUL Y,A
A ← M(X+extoff)
A ← M(Y+extoff)
A
←
M(X+[longptr.e])
M(X+extoff)
←
A
M(Y+extoff) ← A
M(X+[longptr.e]) ← A
X
←
M(SP+shortoff)
M(SP+shortoff)
←
X
Y ← M(SP+shortoff)
M(SP+shortoff) ← Y
SP ← X
X ← SP
X
←
Y
M(longmem)
←
imm.b
M(mem1.b) ←
M(mem2.b)
M(mem1.w) ←
M(mem2.w)
X ← X*A
Y ← Y*A
Example opcode(s) bb
AF ee ww
90 AF ee ww bb
92 AF ww bb bb
A7 ee ww
90 A7 ee ww bb
92 A7 ww bb
1E bb
1F bb
16 bb
1
1
1
5
1
5
2
2
2
17 bb
94
96
93
35 ii ww bb
44 b2 b1
45 w2 b2 w1 b1
42
90 42
1
4
4
2
1
1
1
1
1
NEG
Logical 2’s complement
NEG ([$1234.w],X)
M(M(longmem) + X)
←
00 - M(M(longmem) + X)
72 60 ww bb 4
NEGW
Logical 2’s complement
NEGW X
NOP No operation NOP
X
←
0000 - X 50 2
OR Logical OR -
POP
Pop data byte from stack
Pop code condition register
POP $1234
POP CC
M(longmem)
CC ←
---------
←
M(++SP)
M(++SP)
9D
OR A,($12,SP) A ← A OR M(SP+shortoff) 1A bb
32 ww bb
86
1
1
1
1
Doc ID 13590 Rev 3 69/162
STM8 instruction set PM0044
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
POPW
PUSH
PUSHW
RCF
RET
RETF
RIM
Pop index register from stack
Push data byte onto stack
Push index register onto stack
Reset carry flag -
Subroutine return from section 0
-
-
Subroutine return from extended address
Reset interrupt mask/
Interrupt enable
-
-
-
-
-
-
-
-
-
-
1 -
-
-
-
-
-
-
-
-
-
-
-
-
0 -
-
-
-
-
-
-
-
-
-
-
-
-
POPW X
-
PUSH $1234
PUSH #$12
PUSHW X
0 RCF
RET
RETF
RIM
Operation
XH
←
M(++SP)
XL ← M(++SP)
M(SP--) ← M(longmem)
M(SP--) ← imm.b
M(SP--) ← XL
M(SP--)
←
XH
CC.C
←
0
PCH ← M(++SP)
PCL
←
M(++SP)
PCE
←
M(++SP)
PCH
←
M(++SP)
PCL
←
M(++SP)
CC.I1 ← 1
RLC
Rotate left logical through carry
RLC ([$1234.w],X)
R0
←
CC.C
R1 ← bit 0
R2
←
bit 1
R3 ← bit 2
R4
←
bit 3
R5 ← bit 4
R6
←
bit 5
R7 ← bit 6
CC.C
←
bit 7
Example opcode(s)
85
3B ww bb
4B bb
89
98
81
87
9A
72 69 ww bb
2
1
1
2
1
4 Flush
5 Flush
1
4
RLCW
Rotate word left logical through carry
RLCW X
R0
←
CC.C
R1 ← bit 0
R2
←
bit 1
...
R13
←
bit 12
R14 ← bit 13
R15
←
bit 14
CC.C
← bit 15
59 2
RLWA
Rotate word left through
Accumulator
-
RRC
Rotate right logical through carry
-
RLWA X
A
←
XH
XH ← XL
XL
←
A
RRC ([$1234.w],X)
R7 ← CC.C
R6
←
bit 7
R5 ← bit 6
R4
←
bit 5
R3 ← bit 4
R2
←
bit 3
R1 ← bit 2
R0
←
bit 1
CC.C
← bit 0
02 1
72 66 ww bb 4
70/162 Doc ID 13590 Rev 3
PM0044
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
Operation
STM8 instruction set
Example opcode(s)
RRCW
Rotate word right logical through carry
RRCW X
R15 ← CC.C
R14
←
bit 15
R13 ← bit 14
...
R2 ← bit 3
R1
←
bit 2
R0 ← bit 1
CC.C
←
bit 0
56 2
RRWA
Rotate word right through
Accumulator
RRWA X
RVF
Reset overflow flag
0 RVF
A ← XL
XL
←
XH
XH ← A
CC.V
←
0
01
9C
1
1
SBC
Subtract with carry
SBC A,($12,SP)
A ← A -M(SP+shortoff) -
CC.C
12 bb 1
SCF
SIM
Set Carry Flag
Set interrupt mask/
Disable interrupts
-
-
-
1 -
-
1 -
-
-
1 SCF
SIM
SLA
Shift left arithmetic
-
CC.C
CC.I0
CC.I1
←
←
1
1
← 1
SLA ([$1234.w],X)
R0
←
0
R1 ← bit 0
R2
← bit 1
R3 ← bit 2
R4
← bit 3
R5 ← bit 4
R6
← bit 5
R7 ← bit 6
CC.C
←
bit 7
99
9B
1
1
72 68 ww bb 4
Doc ID 13590 Rev 3 71/162
STM8 instruction set
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
Operation
SLAW
Shift word left arithmetic
SLAW X
R0 ← 0
R1
← bit 0
R2 ← bit 1
R3
← bit 2
.....
R14
← bit 13
R15 ← bit 14
CC.C
←
bit 15
58
Example opcode(s)
PM0044
2
SLL Shift left logical -
SLLW
Shift word left logical
-
SRA
Shift right arithmetic
-
SRAW
Shift word right arithmetic
-
SLL ([$1234.w],X)
R0
←
0
R1 ← bit 0
R2
← bit 1
R3 ← bit 2
R4
← bit 3
R5 ← bit 4
R6
← bit 5
R7 ← bit 6
CC.C
←
bit 7
SLLW X
R0 ← 0
R1
← bit 0
R2 ← bit 1
R3
← bit 2
.....
R14
← bit 13
R15 ← bit 14
CC.C
←
bit 15
72 68 ww bb
58
4
2
SRA ([$1234.w],X)
CC.C
←
bit 0
R0 ← bit 1
R1
←
bit 2
R2 ← bit 3
R3
←
bit 4
R4 ← bit 5
R5
←
bit 6
R6 ← bit 7
R7
←
bit 7 (unchanged)
72 67 ww bb 4
SRAW X
CC.C
←
bit 0
R0 ← bit 1
R1
←
bit 2
R2 ← bit 3
....
R12 ← bit 13
R13
←
bit 14
R14 ← bit 15
R15
←
bit 15 (unchanged)
57 2
72/162 Doc ID 13590 Rev 3
PM0044
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
SRL
Shift right logical
-
Operation
SRL ([$1234.w],X)
CC.C
←
bit 0
R0 ← bit 1
R1
←
bit 2
R2 ← bit 3
R3
←
bit 4
R4 ← bit 5
R5
←
bit 6
R6 ← bit 7
R7
←
0
SRLW
Shift word right arithmetic
SRLW X
CC.C
←
bit 0
R0 ← bit 1
R1
←
bit 2
R2 ← bit 3
....
R12 ← bit 13
R13
←
bit 14
R14 ← bit 15
R15
←
0
STM8 instruction set
Example opcode(s)
72 64 ww bb 4
54 2
SUB
Subtract without carry
SUB A,($12,SP) A ← A -M(SP+shortoff) 10 bb 1
SUB SP,#$12 SP
←
SP + imm.b
52 ii 2
SUBW
Subtract word without carry
SUBW X,($12,SP) X ← X -M(SP+shortoff) 72 F0 bb 2
SWAP Swap nibbles SWAP ([$1234.w],X)
R0 ↔ R4
R1
↔
R5
R2 ↔ R6
R3
↔
R7
72 6E ww bb 4
Doc ID 13590 Rev 3 73/162
STM8 instruction set
Table 42.
Instruction set summary (continued)
Effect on CC register
Description Syntax example
V I1 H I0 N Z C
SWAPW Swap bytes SWAPW X
Operation
R0 ↔ R8
R1 ↔ R9
R2 ↔ R10
R3 ↔ R11
R4 ↔ R12
R5 ↔ R13
R6 ↔ R14
R7 ↔ R15
TNZ
Test for negative or zero
TNZ ([$1234.w],X)
CC.N
←
R7
CC.Z ← 1 if R=$00
←
0 otherwise
Example opcode(s)
PM0044
5E 1
72 6D ww bb 4
TNZW
TRAP
XOR
Test word for negative or zero
Software interrupt
-
1 1 TRAP
Logical exclusive OR
-
-
-
TNZW X
WFE
WFI
Wait for event
(CPU stopped,
Low power mode)
Wait for interrupt
(CPU stopped,
Low power mode)
-
-
-
1
-
0 -
-
-
WFE
WFI
CC.N ← R15
CC.Z
←
1 if R=$0000
← 0 otherwise
5D
PC
←
PC+1
M(SP--)
←
PCL
M(SP--)
←
PCH
M(SP--)
←
PCE
M(SP--)
←
YL
M(SP--)
←
YH
M(SP--)
←
XL
M(SP--)
←
XH
M(SP--)
←
A
M(SP--)
←
CC
PC
←
TRAP vector address
CPU clock stopped till the event input is activated.
Internal peripherals are still running
CC.I0
←
0, CC.I1
←
1
CPU clock stopped till an interrupt occurs. Internal peripherals are still running
83
72 8F
8F
XOR A,($12,SP)
A ← A XOR
M(SP+shortoff)
18 bb
1.
Number of cycles corresponding to the example op-code.
2.
If branch taken.
2
9 Flush
1
10
1
The following pages give a detailed description of each STM8 instruction.
74/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
ADC
Syntax
Operation
Description
Addition with Carry ADC
ADC A, src
A <= A+ src + C e.g. ADC A,#$15
The source byte, along with the carry flag, is added to the contents of the accumulator and the result is stored in the accumulator. This instruction is useful for addition of operands that are larger than eight.
The source is a memory or data byte.
Instruction overview:
V mnem
⇒
ADC
Affected condition flags dst src
V I1 H I0 N
A Mem V H N
(A7.M7 + M7.R7 + R7.A7)
⊕
(A6.M6 + M6.R6 + R6.A6)
Set if the signed operation generates an overflow, cleared otherwise.
Z
Z
H
⇒
A3.M3 + M3.R3 + R3.A3
Set if a carry occurred from bit 3 of the result, cleared otherwise.
N
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
A7.M7 + M7.R7 + R7.A7
Set if a carry occurred from bit 7 of the result, cleared otherwise.
C
C
Doc ID 13590 Rev 3 75/162
STM8 instruction set
Detailed description: dst
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A src Asm
#byte shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
ADC A,#$55
ADC A,$10
ADC A,$1000
ADC A,(X)
ADC A,($10,X)
ADC A,($1000,X)
ADC A,(Y)
ADC A,($10,Y)
ADC A,($1000,Y)
ADC A,($10,SP)
[shortptr.w]
[longptr.w]
ADC A,[$10.w]
ADC A,[$1000.w]
([shortptr.w],X) ADC A,([$10.w],X)
([longptr.w],X) ADC A,([$1000.w],X)
([shortptr.w],Y) ADC A,([$10.w],Y)
See also: ADD, SUB, SBC, MUL, DIV cy
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4 lgth
2
3
4
2
3
1
2
2
2
3
3
4
3
3
4
Op-code(s)
A9 XX
B9 XX
C9 MS LS
F9
E9 XX
D9 MS LS
90 F9
90 E9 XX
90 D9 MS LS
19 XX
92 C9 XX
72 C9 MS LS
92 D9 XX
72 D9 MS LS
91 D9 XX
PM0044
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
76/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
ADD
Syntax
Addition ADD
Operation
Description
ADD A,src
A <= A+ src e.g. ADD A,#%11001010
The source byte is added to the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte.
Instruction overview dst
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Affected condition flags mnem dst src
V I1 H I0 N
V
⇒
ADD A Mem V H N
(A7.M7 + M7.R7 + R7.A7)
⊕
(A6.M6 + M6.R6 + R6.A6)
Set if the signed operation generates an overflow, cleared otherwise.
H
⇒
A3.M3 + M3.R3 + R3.A3
Set if a carry occurred from bit 3 of the result, cleared otherwise.
N
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
A7.M7 + M7.R7 + R7.A7
Set if a carry occurred from bit 7 of the result, cleared otherwise.
Z
Z
Detailed description src Asm
#byte shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
ADD A,#$55
ADD A,$10
ADD A,$1000
ADD A,(X)
ADD A,($10,X)
ADD A,($1000,X)
ADD A,(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
ADD A,($10,Y)
ADD A,($1000,Y)
ADD A,($10,SP)
ADD A,[$10.w]
[longptr.w] ADD A,[$1000.w]
([shortptr.w],X) ADD A,([$10.w],X)
([longptr.w],X) ADD A,([$1000.w],X)
([shortptr.w],Y) ADD A,([$10.w],Y)
See also: ADDW, ADC, SUB, SBC, MUL, DIV cy
4
4
4
4
1
1
1
4
1
1
1
1
1
1
1 lgth
4
3
4
3
3
4
2
3
1
2
3
2
2
2
3
Op-code(s)
AB XX
BB XX
CB MS LS
FB
EB XX
DB MS LS
90 FB
90 EB XX
90 DB MS LS
1B XX
92 CB XX
72 CB MS LS
92 DB XX
72 DB MS LS
91 DB XX
C
C
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 77/162
STM8 instruction set PM0044
ADDW Word Addition with index registers ADDW
Syntax
Operation
ADDW dst,src dst <= dst + src e.g. ADDW X,#$1000
Description The source (16-bit) is added to the contents of the destination, which is an index register (X/Y) and the result is stored in the same index register. The source is a 16-bit memory or data word. The ADDW instruction can also be used to add an immediate value to the stack pointer (SP).
Instruction overview dst
Y
Y
Y
SP
X
X
X
Affected condition flags mnem dst src
V I1 H I0 N Z
ADDW
ADDW
ADDW
V
⇒
X
Y
SP
Mem
Mem
Imm
V
V
-
-
-
-
H
H
-
-
-
-
N
N
-
(A15.M15 + M15.R15 + R15.A15)
⊕
(A14.M14 + M14.R14 + R14.A14)
Set if the signed operation generates an overflow, cleared otherwise.
Z
Z
-
H
⇒
X7.M7 + M7.R7 + R7.X7
Set if a carry occurred from bit 7 of the result, cleared otherwise.
N
⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z
⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
C
⇒
X15.M15 + M15.R15 + R15.X15
Set if a carry occurred from bit 15 of the result, cleared otherwise.
Detailed description src
#word longmem
(shortoff,SP)
#word longmem
(shortoff,SP)
#byte
Asm
ADDW X,#$1000
ADDW X,$1000
ADDW X,($10,SP)
ADDW Y,#$1000
ADDW Y,$1000
ADDW Y,($10,SP)
ADDW SP,#$9
See also: ADD, ADC, SUB, SBC, MUL, DIV cy
2
2
2
2
2
2
2 lgth
3
2
4
4
3
4
3
Op-code(s)
1C MS LS
72 BB MS LS
72 FB XX
72 A9 MS LS
72 B9 MS LS
72 F9 XX
5B XX
C
C
C
-
ST7
78/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
AND Logical AND AND
Syntax
Operation
Description
Truth table :
AND
0
1
AND A,src
A <= A AND src
e.g. AND A,#%00110101
The source byte, is ANDed with the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte.
0
0
0
1
0
1
Instruction overview
Affected condition flags mnem dst src
N
⇒
AND A Mem
V
-
I1
-
H
-
I0
-
Z
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
N
N
Z
Z dst
A
A
A
A
A
A
A
A
A
A
A
A
A
A src Asm
#byte shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
AND A,#$55
AND A,$10
AND A,$1000
AND A,(X)
AND A,($10,X)
AND A,($1000,X)
AND A,(Y)
AND A,($10,Y)
AND A,($1000,Y)
AND A,($10,SP)
[shortptr.w]
[longptr.w]
AND A,[$10.w]
AND A,[$1000.w]
([shortptr.w],X) AND A,([$10.w],X)
([longptr.w],X)
AND
A,([$1000.w],X)
([shortptr.w],Y) AND A,([$1000],Y) A
See also: OR, XOR, CPL, NEG
4
4 cy
1
1
1
1
1
1
4
4
4
1
1
1
1 lgth
2
3
4
2
2
3
3
4
3
2
2
3
1
4
3
Op-code(s)
A4 XX
B4 XX
C4 MS LS
F4
E4 XX
D4 MS LS
90 F4
90 E4 XX
90 D4 MS LS
14 XX
92 C4 XX
72 C4 MS LS
92 D4 XX
72 D4 MS LS
91 D4 XX
C
-
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 79/162
STM8 instruction set PM0044
BCCM Copy Carry Bit to Memory BCCM
Syntax
Operation
BCCM dst, #pos (pos=0..7) dst(pos) <= CC.C
e.g. BCCM $1234,#1
Description Copies the Carry flag of the Condition Code (CC) register in the bit position of the memory location given by the destination address.
M(longmem).bit <- CC.C
Instruction overview mnem dst bit position
#pos
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
BCCM Mem
Detailed description
C
dst pos = 0..7
Asm longmem n =1+2*pos BCCM $1000,#2
See also: LD, RCF, SCF cy
1 lgth
4
Op-code(s)
90 1n MS LS
ST7
80/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
BCP Logical Bit Compare BCP
Syntax
Operation
BCP A,src
{N, Z} <= A AND src
Description The source byte, is ANDed to the contents of the accumulator. The result is lost but condition flags N and Z are updated accordingly. The source is a memory or data byte. This instruction can be used to perform bit tests on
A.
Instruction overview dst
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Affected condition flags mnem dst src
N
⇒
BCP A Mem
V
-
I1
-
H
-
I0
-
Z
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
N
N
Z
Z src Asm
#byte shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
BCP A,#$55
BCP A,$10
BCP A,$1000
BCP A,(X)
BCP A,($10,X)
BCP A,($1000,X)
BCP A,(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
BCP A,($10,Y)
BCP A,($1000,Y)
BCP A,($10,SP)
BCP A,[$10.w]
[longptr.w] BCP A,[$1000.w]
([shortptr.w],X) BCP A,([$10.w],X)
([longptr.w],X) BCP A,([$1000.w],X)
([shortptr.w],Y) BCP A,([$10.w],Y)
See also: CP, TNZ cy
4
4
4
4
1
1
1
4
1
1
1
1
1
1
1 lgth
4
3
4
3
3
4
2
3
1
2
3
2
2
2
3
Op-code(s)
A5 XX
B5 XX
C5 MS LS
F5
E5 XX
D5 MS LS
90 F5
90 E5 XX
90 D5 MS LS
15 XX
92 C5 XX
72 C5 MS LS
92 D5 XX
72 D5 MS LS
91 D5 XX
C
-
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 81/162
STM8 instruction set
BCPL
PM0044
Bit Complement BCPL
Syntax
Operation
Description
BCPL dst, #pos (pos=0..7) e.g. BCPL PADR,#4 dst(pos) <= 1 - dst(pos)
Complements the bit position in destination location. Leaves all other bits unchanged.
M(longmem).bit <- -M(longmem).bit
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
BCPL
Detailed description
Mem dst longmem pos = 0..7
Asm n = 2*pos BCPL $1000,#2
See also: CPL, BRES, BSET cy
1 lgth
4
Op-code(s)
90 1n MS LS
ST7
82/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
BREAK
Syntax
Software break BREAK
Operation
Description In debug mode, the CPU is stalled and can be restarted by the debugger.
This instruction equals a NOP when the debugger is not connected.
Instruction overview mnem
SIM
Detailed description
V
-
Addressing mode
Inherent
Asm
BREAK
I1
1 cy
1
Affected condition flags
H
-
I0
1
N
lgth
1 8B
Z
-
Op-code(s)
C
-
ST7
✗
Doc ID 13590 Rev 3 83/162
STM8 instruction set PM0044
BRES
Syntax
Bit Reset BRES
Operation
Description
BRES dst,#pos pos = [0..7] e.g. BRES PADR,#6 dst <= dst AND COMPLEMENT (2**pos)
Read the destination byte, reset the corresponding bit (bit position), and write the result in destination byte. The destination is a memory byte. The bit position is a constant. This instruction is fast, compact, and does not affect any register. Very useful for boolean variable manipulation.
Instruction overview mnem dst bit position
#pos
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
BRES Mem
Detailed description dst longmem pos = 0..7
n=1+2*pos
Asm
BRES $1000,#7 cy lgth
1 4
Op-code(s)
72 1n MS LS
ST7
See also: BSET
84/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
BSET Bit Set BSET
Syntax
Operation
BSET dst,#pos pos = [0..7] dst <= dst OR (2**pos) e.g. BSET PADR,#7
Description Read the destination byte, set the corresponding bit (bit position), and write the result in destination byte. The destination is a memory byte. The bit position is a constant. This instruction is fast, compact, and does not affect any register. Very useful for boolean variable manipulation.
Instruction overview mnem dst bit position
#pos
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
BSET Mem
Detailed description dst longmem pos = 0..7
n=2*pos
Asm
BSET $1000,#1 cy lgth
1 4
Op-code(s)
72 1n MS LS
ST7
See also: BRES
Doc ID 13590 Rev 3 85/162
STM8 instruction set
BTJF
PM0044
Bit Test and Jump if False BTJF
Syntax e.g.:
Operation
BTJF dst,#pos,rel
BTJFPADR,#3,skip pos = [0..7], rel is relative jump label
PC = PC+lgth
PC = PC + rel IF (dst AND (2**pos)) = 0
Description Read the destination byte, test the corresponding bit (bit position), and jump to 'rel' label if the bit is false (0), else continue the program to the next instruction. The tested bit is saved in the C flag. The destination is a memory byte. The bit position is a constant. The jump label represents a signed offset to be added to the current PC/instruction address (relative jump). This instruction is used for boolean variable manipulation, hardware register flag tests, or I/O polling. This instruction is fast, compact, and does not affect any registers. Very useful for boolean variable manipulation.
Instruction overview mnem dst bit position jump label
V
-
Affected condition flags
I1
-
H
-
I0
-
N
-
Z
-
C
C BTJF Mem #pos
C
⇒
Tested bit is saved in the C flag.
Detailed description rel dst longmem pos = 0..7
n = 1+2*pos
Asm
BTJF
$1000,#1,loop cy lgth
2/3 5
Op-code(s)
72 0n MS LS XX
ST7
See also : BTJT
86/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
BTJT Bit Test and Jump if True BTJT
Syntax e.g.:
Operation
BTJT dst,#pos,rel
BTJT PADR,#7,skip pos = [0..7], rel is relative jump label
PC = PC+lgth
PC = PC + rel IF (dst AND (2**pos)) <> 0
Description Read the destination byte, test the corresponding bit (bit position), and jump to 'rel' label if the bit is true (1), else continue the program to the next instruction. The tested bit is saved in the C flag. The destination is a memory byte. The bit position is a constant. The jump label represents a signed offset to be added to the current PC/instruction address (relative jump). This instruction is used for boolean variable manipulation, hardware register flag tests, or I/O polling.
Instruction overview mnem dst bit position jump label
BTJT Mem #pos rel
C
⇒
Tested bit is saved in the C flag.
Detailed description dst pos = 0..7
longmem n= 2*pos
Asm
BTJT
$1000,#1,loop
V
cy lgth
2/3 5
Affected condition flags
I1
-
H
-
I0
-
N
-
Z
-
Op-code(s)
72 0n MS LS XX
C
C
ST7
See also: BTJF
Doc ID 13590 Rev 3 87/162
STM8 instruction set PM0044
CALL
CALL Subroutine
(Absolute)
CALL
Operation
Description
PC = PC+lgth
(SP--) = PCL
(SP--) = PCH
PC = dst
The current PC register value is pushed onto the stack, then PC is loaded with the destination address in same section of memory. The CALL destination and the instruction following the CALL should be in the same section as PCE is not stacked. The corresponding RET instruction should be executed in the same section. This instruction should be used versus
CALLR when developing a program.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
CALL
Detailed description
Mem dst Asm longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
CALL $1000
CALL(X)
CALL($10,X)
CALL($1000,X)
CALL(Y)
CALL($10,Y)
CALL($1000,Y)
[shortptr.w]
[longptr.w]
CALL[$10.w]
CALL[$1000.w]
([shortptr.w],X) CALL([$10.w],X)
([longptr.w],X) CALL([$1000.w],X)
([shortptr.w],Y) CALL([$10.w],Y) lgth
3
2
3
4
3
1
2
3
4
3
3
4 cy
4
4
4
4
4
4
4
6
6
6
6
6
Op-code(s)
CD MS LS
FD
ED XX
DD MS LS
90 FD
90 ED XX
90 DD MS LS
92 CD XX
72 CD MS LS
92 DD XX
72 DD MS LS
91 DD XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: RET, CALLR, CALLF
88/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
CALLF CALL Far Subroutine CALLF
Syntax
Operation
CALLF dst
PC = PC+lgth
(SP--) = PCL
(SP--) = PCH
(SP--) = PCE
PC = dst e.g. CALLF label
Description The current PC register value is pushed onto the stack, then PC is loaded with the destination address.This instruction is used with extended memory addresses. For safe memory usage, a function which crosses sections must be called by CALLF.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
CALLF
Detailed description
Mem dst Asm extmem CALLF $35AA00
[longptr.e] CALLF [$2FFC.e] cy
5
8 lgth
4
4
Op-code(s)
8D ExtB MS
92 8D MS LS
LS
ST7
See also: RETF, JPF
Doc ID 13590 Rev 3 89/162
STM8 instruction set
CALLR
PM0044
CALL Subroutine Relative CALLR
Syntax
Operation
CALLR dst
PC = PC+lgth
(SP--) = PCL
(SP--) = PCH
PC = PC + dst e.g. CALLR chk_pol
Description The current PC register value is pushed onto the stack, then PC is loaded with the relative destination address. This instruction is used, once a program is debugged, to shrink the overall program size. The CALLR destination and the corresponding RET instruction address must be in the same section, as PCE is not stacked.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
CALLR
Detailed description
Mem dst shortmem
Asm
CALLR $10 cy
4 lgth
2
Op-code(s)
AD XX
ST7
✗
See also: CALL, RET
90/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
CCF
Syntax
Complement Carry Flag
Operation
Description
CCF
CC.C <- CC.C
Complements the Carry flag of the Condition Code (CC) register.
Instruction overview mnem
CCF
V
-
I1
-
C = C ,
Complements the carry flag of the CC register.
Detailed description
Affected condition flags
H
-
I0
-
N
-
Addressing mode
Inherent CCF
Asm cy
1 lgth
1 8C
Op-code(s)
Z
-
CCF
C
C
ST7
See also: RCF, SCF
Doc ID 13590 Rev 3 91/162
STM8 instruction set PM0044
CLR Clear CLR
Syntax
Operation
CLR dst dst <= 00 e.g. CLR A
Description The destination byte is forced to 00 value. The destination is either a memory byte location or the accumulator. This instruction is compact, and does not affect any register when used with RAM variables.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
0
0
Z
1
1
C
CLR
CLR
N: 0
Cleared
Z: 1
Set
Detailed description
Mem
A dst Asm
A CLR A shortmem CLR $10 longmem
(X)
CLR $1000
CLR (X)
(shortoff.X) CLR ($10,X)
(longoff,X) CLR ($1000,X)
(Y) CLR (Y)
(shortoff,Y) CLR ($10,Y)
(longoff,Y) CLR ($1000,Y)
(shortoff,SP) CLR ($10,SP)
[shortptr.w] CLR [$10]
[longptr.w] CLR [$1000].w
([shortptr.w],X) CLR ([$10],X)
([longptr.w].X]
CLR
([$1000.w],X)
([shortptr.w],Y) CLR ([$10],Y)
4
4 cy lgth
1
1
1
1
1
1
1
1
1
1
4
4
4
2
3
4
2
4
1
1
2
2
4
3
4
3
4
3
72
92
72
92
72
91
72
90
90
90
7F
6F
4F
0F
4F
3F
5F
7F
6F
4F
3F
3F
6F
Op-code(s)
XX
MS
XX
MS
XX
MS
XX
XX
MS
XX
LS
LS
LS
LS
LS 6F
6F
MS
XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: LD
92/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
CLRW
Syntax
Clear word CLRW
Operation
Description
CLRW dst dst <= 00 e.g. CLRW X
The destination is forced to 0000 value. The destination is an index register.
Instruction overview mnem dst
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
0
0
Z
1
1
C
-
CLRW
CLRW
N: 0
Cleared
Z: 1
Set
Detailed description dst
X
Y
Asm
CLRW X
CLRW Y
X
Y cy lgth
1
1
1
2 90
5F
5F
Op-code(s) ST7
See also: LD
Doc ID 13590 Rev 3 93/162
STM8 instruction set PM0044
CP
Syntax
Compare CP
Operation
Description
CP dst,src
{N, Z, C} = Test (dst - src) e.g. CP A,(tbl,X)
The source byte is subtracted from the destination byte and the result is lost.
However, N, Z, C flags of Condition Code (CC) register are updated according to the result.The destination is a register, and the source is a memory or data byte. This instruction generally is used just before a conditional jump instruction.
Instruction overview
V
N
Z
C mnem
⇒
⇒
⇒
⇒
CP
Affected condition flags dst src
V I1 H I0 N Z C
Reg Mem V N Z C
(A7.M7 + A7.R7 + A7.M7.R7)
⊕
(A6.M6 + A6.R6 + A6.M6.R6)
Set if the signed subtraction of the destination (dst) value from the source (src) value generates a signed overflow (signed result cannot be represented on 8 bits).
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
(A7.M7 + A7.R7 + A7.M7.R7)
Set if the unsigned value of the contents of source (src) is larger than the unsigned value of the destination (dst), cleared otherwise.
Detailed description dst src Asm
A #byte
A shortmem
A longmem
A (X)
A (shortoff,X)
A (longoff,X)
A (Y)
CP A,#$10
CP A,$10
CP A,$1000
CP A,(X)
CP A,($10,X)
A (shortoff,Y)
A (longoff,Y)
A (shortoff,SP)
A [shortptr.w]
CP A,(Y)
CP A,($10,Y)
CP A,($1000,Y)
CP A,($10,SP)
CP A,[$10.w]
A [longptr.w] CP A,[$1000.w]
A ([shortptr.w],X) CP A,([$10.w],X)
A ([longptr.w],X) CP A,([$1000.w],X)
A ([shortptr.w],Y) CP A,([$10.w],Y) cy lgth
4
4
4
4
1
1
1
4
1
1
1
1
1
1
1
4
3
4
3
3
4
2
3
1
2
3
2
2
2
3
92
72
92
72
91
90
90
90
Op-code(s)
A1 XX
B1 XX
C1 MS LS
F1
E1 XX
D1 MS LS
F1
E1 XX
D1 MS LS
11 XX
C1 XX
C1 MS LS
D1 XX
D1 MS LS
D1 XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: CPW, TNZ, BCP
94/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
CPW
Syntax
Compare word CPW
Operation
Description
CPW dst,src
{N, Z, C} = Test (dst - src) e.g. CPW Y,(tbl,X)
The source byte is subtracted from the destination byte and the result is lost. However, N, Z, C flags of Condition Code (CC) register are updated according to the result. The destination is an index register, and the source is a memory or data word. This instruction generally is used just before a conditional jump instruction.
Instruction overview
V mnem
⇒
CPW
Affected condition flags dst src
V I1 H I0 N Z C
Reg Mem V N Z C
(X15.M15 + X15.R15 + X15.M15.R15)
⊕
(X14.M14 + X14.R14 + X14.M14.R14)
Set if the signed subtraction of the destination (dst) value from the source (src) value generates a signed overflow (signed result cannot be represented on 16 bits).
N
⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
(X15.M15 + X15.R15 + X15.M15.R15)
Set if the unsigned value of the contents of source (src) is larger than the unsigned value of the destination (dst), cleared otherwise.
Detailed description dst src Asm
X
X
X
#word shortmem longmem
CPW X,#$10
CPW X,$10
CPW X,$1000
X
X
(Y)
(shortoff,Y)
CPW X,(Y)
CPW X,($10,Y)
X
X
X (longoff,Y)
X
X
(shortoff,SP)
[shortptr.w]
[longptr.w]
CPW X,($10,SP)
CPW X,[$10.w]
CPW X,[$1000.w]
([shortptr.w],Y) CPW X,([$10.w],Y) cy
2
2
2
2
2
2
2
5
5
5 lgth
2
3
4
2
3
2
3
3
4
3
Op-code(s)
A3 MS LS
B3 XX
C3 MS LS
90 F3
90 E3 XX
90 D3 MS LS
13 XX
92 C3 XX
72 C3 MS LS
91 D3 XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 95/162
STM8 instruction set
Note:
PM0044
CPW detailed description (Continued) dst
Y
Y
Y
Y
Y
Y
Y
Y
Y src Asm
#word shortmem longmem
(X)
(shortoff,X)
(longoff,X)
CPW Y,#$10
CPW Y,$10
CPW Y,$1000
CPW Y,(X)
CPW Y,($10,X)
CPW Y,($1000,X)
[shortptr.w] CPW Y,[$10.w]
([shortptr.w],X) CPW Y,([$10.w],X)
([longptr.w],X) CPW Y,([$1000.w],X) cy
5
5
5
2
2
2
2
2
2 lgth
3
3
4
4
1
4
3
2
3
Op-code(s)
90 A3 MS LS
90 B3 XX
90 C3 MS LS
F3
E3 XX
D3 MS LS
91 C3 XX
92 D3 XX
72 D3 MS LS
CPW Y, (shortoff, SP) is not implemented, but can be emulated through a macro using
EXGW X,Y
&
CPW X, (shortoff, SP)
See also: CP, TNZW, BCP
ST7
✗
✗
✗
✗
✗
✗
✗
✗
96/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
CPL
Syntax
Logical 1’s Complement CPL
Operation
Description
CPL dst e.g. CPL (X) dst <= dst XOR FF, or FF - dst
The destination byte is read, then each bit is toggled (inverted) and the result is written to the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any registers when used with RAM variables.
Instruction overview
Affected condition flags mnem dst
CPL
CPL
Mem
Reg
V
-
-
I1
-
-
H
-
-
I0
-
-
N
N
N
N
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
1
Set.
Detailed description dst Asm
A shortmem longmem
(X)
(shortoff.X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
CPL A
CPL$10
CPL$1000
CPL(X)
CPL($10,X)
CPL($1000,X)
CPL(Y)
CPL($10,Y)
CPL($1000,Y)
CPL($10,SP)
[shortptr.w]
[longptr.w]
CPL[$10]
CPL[$1000].w
([shortptr.w],X) CPL([$10],X)
([longptr.w].X] CPL([$1000.w],X)
([shortptr.w],Y) CPL([$10],Y) cy lgth
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
2
3
4
2
4
1
1
2
2
4
3
4
3
3
4
72
92
72
92
72
91
72
90
90
90
73
63
43
03
43
33
53
73
63
43
33
33
63
63
63
Op-code(s)
XX
MS
XX
MS
XX
MS
XX
XX
MS
XX
MS
XX
LS
LS
LS
LS
LS
Z
Z
Z
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
C
1
1
See also: NEG, XOR, AND, OR
Doc ID 13590 Rev 3 97/162
STM8 instruction set PM0044
CPLW
Syntax
Logical 1’s Complement Word CPLW
Operation
Description
CPLW dst e.g. CPLW X dst <= dst XOR FFFF, or FFFF - dst
The destination index register is read, then each bit is toggled (inverted) and the result is written back to the destination index register.
Instruction overview
Affected condition flags mnem dst
CPLW Reg
V
-
I1
-
H
-
I0
-
N
N
N
⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
1
Set
Detailed description dst
X
Y
Asm
CPLW X
CPWL Y cy lgth
2
2
1
2 90
53
53
Op-code(s)
Z
Z
C
1
ST7
✗
✗
See also: CPL, NEGW, XOR, AND, OR
98/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
DEC
Syntax
Decrement DEC
Operation
Description
DEC dst dst <= dst - 1
The destination byte is read, then decremented by one, and the result is written to the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any registers when used with RAM variables.
Instruction overview
V
N
⇒
⇒ mnem
DEC
DEC
Affected condition flags dst
V I1 H I0 N Z C
Mem
Reg
V
V -
-
-
-
-
N
N
Z
Z
(A7.M7 + M7.R7 + R7.A7)
⊕
(A6.M6 + M6.R6 + R6.A6)
Set if the signed operation generates an overflow, cleared otherwise.
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
-
-
Z
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description dst Asm
A DEC A shortmem DEC $10 longmem
(X)
DEC $1000
DEC(X)
(shortoff.X) DEC($10,X)
(longoff,X) DEC($1000,X)
(Y) DEC(Y)
(shortoff,Y) DEC($10,Y)
(longoff,Y) DEC($1000,Y)
(shortoff,SP) DEC($10,SP)
[shortptr.w] DEC[$10]
[longptr.w] DEC[$1000].w
([shortptr.w],X) DEC([$10],X)
([longptr.w].X] DEC([$1000.w],X)
([shortptr.w],Y) DEC([$10],Y) cy
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4 lgth
2
3
4
2
4
1
1
2
2
4
3
4
3
3
4
72
92
72
92
72
91
72
90
90
90
Op-code(s)
7A
6A
4A
0A
4A
3A
5A
7A
6A
4A
3A
3A
6A
6A
6A
XX
MS
XX
MS
XX
LS
LS
MS LS
XX
XX
MS
XX
MS
XX
LS
LS
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: DECW, INC
Doc ID 13590 Rev 3 99/162
STM8 instruction set PM0044
DECW
Syntax
Decrement word
Operation
Description
DECW dst dst <= dst - 1
The value of the destination index register is decremented by one.
Instruction overview
DECW
V
⇒ mnem
DECW
Affected condition flags dst
Reg
V
V
I1
-
H
-
I0
-
N
N
Z
Z
(A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)
Set if the signed operation generates an overflow, cleared otherwise.
C
-
N
Z
⇒
⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description dst
X
Y
Asm
DECW X
DECW Y cy
1
1 lgth
1
2 90
Op-code(s)
5A
5A
ST7
See also: INCW, DEC
100/162 Doc ID 13590 Rev 3
PM0044
Note:
STM8 instruction set
DIV
Syntax
Operation
Description
Divide (unsigned) DIV
DIV dst,A e.g. DIV X,A dst <= dst / A (Quotient) A <= dst%A (Remainder)
Divides a 16-bit unsigned value, dividend, contained in an index register (X or Y) by an 8-bit value, divisor, contained in A. The quotient is placed in the same index register and the remainder is placed in A.
The register values are unchanged in the case of a division by zero.
Note: This instruction is interruptible, generating a latency of 1 cycle only.
Instruction overview
Affected condition flags mnem dst src
DIV
DIV
X
Y
A
A
V
0
0
I1
-
-
H
0
0
I0
-
-
N
0
0
V
⇒
0
Reset.
H
⇒
0
Reset.
N
⇒
0
Reset.
Z
C
⇒
⇒
Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0
Set if the quotient is zero (0x0000), cleared otherwise.
A7.A6.A5.A4.A3.A2.A1.A0
Set if division by 0, cleared otherwise.
Detailed description
Z
Z
Z dst
X
Y src
A
A
Asm
DIV X,A
DIV Y,A cy
2 to 17
2 to 17 lgth
1
2 90
Op-code(s)
62
62
C
C
C
ST7
See also: DIVW, ADD, ADC, SUB, SBC, MUL
Doc ID 13590 Rev 3 101/162
STM8 instruction set
Note:
PM0044
DIVW
Operation
Description
Divide word (unsigned) DIVW
X <= X / Y (Quotient) Y <= X%Y (Remainder)
Divides a 16-bit unsigned value, dividend, contained in X register by a
16-bit value, divisor, contained in Y. The quotient is placed in the X register and the remainder is placed in Y register.
The quotient and remainder values are indeterminate in the case of a division by zero.
This instruction is interruptible, generating a latency of 1 cycle only.
Instruction overview
Affected condition flags mnem dst src
V
⇒
DIV X Y
V
0
I1
-
H
0
I0
-
N
0
0
Reset
H
⇒
0
Reset
N
⇒
0
Reset
Z
C
⇒
⇒
Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0
Set if the quotient is zero (0x0000), cleared otherwise.
Y15.Y14.Y13.Y12.Y11.Y10.Y9.Y8.Y7.Y6.Y5.Y4.Y3.Y2.Y1.Y0
Set if division by 0, cleared otherwise.
Detailed description
Z
Z dst
X src
Y
Asm
DIV X,Y cy lgth
2 to 17 1
Op-code(s)
65
C
C
ST7
See also: ADD, ADC, SUB, SBC, MUL, DIV
102/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
EXG Exchange register contents
e.g. EXG A, XL
EXG
Syntax
Operation
EXG dst, src dst <=> src src <= dst dst<= src
Description Exchanges the contents of registers specified in the instruction as shown below.
Instruction overview mnem dst
EXG
EXG
EXG
Detailed description
A
A
A dst
A
A
A src
XL
YL longmem src
XL
YL
Mem
Asm
EXG A,XL
EXG A,YL
EXG A,$1000
V
-
-
cy lgth
1
1
3
1
1
3
I1
-
-
-
Affected condition flags
H
-
-
-
I0
-
-
-
N
-
-
-
Z
-
-
-
Op-code(s)
41
61
31 MS LS
C
-
-
-
ST7
See also: EXGW, LD
Doc ID 13590 Rev 3 103/162
STM8 instruction set PM0044
EXGW
EXG dst, src
Exchange Index register contents
e.g. EXGW X, Y
EXGW
Syntax
Operation dst <=> src src <= dst dst<= src
Description Exchanges the contents of registers specified in the instruction as shown below.
Instruction overview mnem dst src
Y
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
EXGW X
Detailed description dst
X src
Y
Asm
EXGW X,Y cy lgth
1 1
Op-code(s)
51
ST7
See also: EXG, LDW
104/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
HALT
Syntax
Operation
HALT Oscillator
(CPU + Peripherals)
HALT
I1 = 1, I0 = 0, The oscillator is stopped till an interrupt occurs.
HALT
Description The interrupt mask is reset, allowing interrupts to be fetched. Then the oscillator is stopped thus stopping the CPU and all internal peripherals, reducing the microcontroller to its lowest possible power consumption. The microcontroller resumes program execution after an external interrupt or
reset, by restarting the oscillator, and then, fetching the corresponding external interrupt, which is an I/O interrupt, a specific peripheral interrupt, or the reset vector.
Instruction overview
I1
1
Affected condition flags
H
-
I0
0
N
-
Z
-
C
mnem
HALT
I1: 1
Set.
I0: 0
Cleared.
Detailed description
V
-
Addressing mode
Inherent
Asm
HALT cy
10 lgth
1 8E
Op-code(s) ST7
✗
See also: WFI
Doc ID 13590 Rev 3 105/162
STM8 instruction set PM0044
INC
Syntax
Increment INC
Operation
Description
INC dst dst <= dst + 1 e.g. INC counter
The destination byte is read, then incremented by one, and the result is written to the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any registers when used with RAM variables.
Instruction overview
Affected condition flags mnem dst
INC
INC
Mem
A
V
V
V
I1
-
-
H
-
-
I0
-
-
N
N
N
Z
Z
Z
V
N
⇒
⇒
(A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)
Set if the signed operation generates an overflow, cleared otherwise.
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
C
-
dst Asm
A shortmem longmem
(X)
(shortoff.X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
INC A
INC $10
INC $1000
INC (X)
INC ($10,X)
INC ($1000,X)
INC (Y)
INC ($10,Y)
INC ($1000,Y)
INC ($10,SP)
[shortptr.w]
[longptr.w]
INC [$10]
INC [$1000].w
([shortptr.w],X) INC ([$10],X)
([longptr.w].X] INC ([$1000.w],X)
([shortptr.w],Y) INC ([$10],Y) cy
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4 lgth
2
3
4
2
4
1
1
2
2
4
3
4
3
3
4
72
92
72
92
72
91
72
90
90
90
Op-code(s)
7C
6C
4C
0C
4C
3C
5C
7C
6C
4C
3C
3C
6C
6C
6C
XX
MS
XX
MS
XX
LS
LS
MS LS
XX
XX
MS
XX
MS
XX
LS
LS
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: INCW, DEC
106/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
INCW
Syntax
Increment word
Operation
Description
INCW dst dst <= dst + 1 e.g. INCW X
The destination index register value is incremented by one.
Instruction overview
INCW
V
⇒ mnem
INCW
Affected condition flags dst
Reg
V
V
I1
-
H
-
I0
-
N
N
Z
Z
(A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)
Set if the signed operation generates an overflow, cleared otherwise.
C
-
N
Z
⇒
⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description dst
X
Y
Asm
INCW X
INCW Y cy
1
1 lgth
1
2 90
Op-code(s)
5C
5C
ST7
See also: INC, DECW
Doc ID 13590 Rev 3 107/162
STM8 instruction set PM0044
INT
Syntax
Interrupt
Operation
Description
INT dst
PC <= dst
This instruction is used only in the interrupt vector table.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
INT
Detailed description
Mem dst Asm extmem INT $2FFFFC cy
2 lgth
4 82
Op-code(s)
ExtB MS LS
Z
-
See also: JP, JPF, CALLF
INT
C
-
ST7
108/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
IRET
Syntax
Interrupt Return IRET
Operation
IRET
CC = (++SP)
A = (++SP)
XH = (++SP)
XL = (++SP)
YH = (++SP)
YL = (++SP)
PCE = (++SP)
PCH = (++SP)
PCL = (++SP)
Description Placed at the end of an interrupt routine, returns to the original program context before the interrupt occurred. All registers, which have been saved/pushed onto the stack are restored/popped. The I bit will be reset if the corresponding bit stored on the stack is zero.
Instruction overview
Affected condition flags mnem
IRET
V
V
I1
I1
H
H
I0
I0
N
N
Z
Z
Condition flags set or reset according to the first byte pulled from the stack.
Detailed description
Addressing mode
Inherent
Asm
IRET cy
11 lgth
1 80
Op-code(s)
C
C
ST7
✗
See also: Interrupts, TRAP
Doc ID 13590 Rev 3 109/162
STM8 instruction set PM0044
JP
Syntax
Jump (absolute) JP
Operation
Description
JP dst
PC <= dst e.g. JP test
The unconditional jump, simply replaces the content of PC by destination address in same section of memory. Control then passes to the statement addressed by the program counter. This instruction should be used instead of JRA during S/W development.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
JP
Detailed description
Mem dst Asm longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
JP $1000
JP(X)
JP($10,X)
JP($1000,X)
JP(Y)
(shortoff,Y)
(longoff,Y)
[shortptr.w]
[longptr.w]
JP($10,Y)
JP($1000,Y)
JP[$10.w]
JP[$1000.w]
([shortptr.w],X) JP([$10.w],X)
([longptr.w],X) JP([$1000.w],X)
([shortptr.w],Y) JP([$10.w],Y) lgth
3
4
3
3
4
3
4
3
1
2
3
2 cy
5
5
5
2
2
5
5
1
1
1
1
1
Op-code(s)
CC MS LS
FC
EC XX
DC MS LS
90 FC
90 EC XX
90 DC MS LS
92 CC XX
72 CC MS LS
92 DC XX
72 DC MS LS
91 DC XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: JRT
110/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
JPF
Syntax
Jump far JPF
Operation
Description
JPF dst
PC <= dst e.g.:JPF test
The unconditional jump simply replaces the content of the PC by a destination with an extended address. Control then passes to the statement addressed by the program counter. For safe memory usage, this instruction must be used, when the operation crosses a memory section.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
JPF
Detailed description
Mem dst Asm extmem JPF $2FFFFC
[longptr.e] JPF [$2FFC.e] cy
2
6 lgth
4
4 92
AC
AC
Op-code(s)
ExtB
MS
MS
LS
LS
ST7
See also: JP, CALLF
Doc ID 13590 Rev 3 111/162
STM8 instruction set PM0044
JRA
Syntax
Jump Relative Always JRA
Operation
JRA dst
PC = PC+lgth e.g. JRA loop
Description
PC <= PC + dst, if Condition is True
Unconditional relative jump. PC is updated by the signed addition of PC and dst. Control then passes to the statement addressed by the program counter. Else, the program continues normally.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
JRA
Detailed description
Mem dst shortoff
Asm
JRA $2B cy
2 lgth
2 20
Op-code(s)
XX
ST7
✗
See also: JP
112/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
JRxx Conditional Jump
Relative Instruction
e.g. JRxx loop
JRxx
Syntax
Operation
JRxx dst
PC = PC+lgth
Description
PC <= PC + dst, if Condition is True
Conditional relative jump. PC is updated by the signed addition of PC and dst, if the condition is true. Control, then passes to the statement addressed by the program counter. Else, the program continues normally.
Instruction overview mnem dst
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
JRxx
Instruction List mnem
JRC
JREQ
JRF
JRH
JRIH
JRIL
JRM
JRMI
JRNC
JRNE
JRNH
JRNM
JRNV
JRPL
JRSGE
JRSGT
JRSLE
JRSLT
JRT
JRUGE
JRUGT
JRULE
JRC
JRULT
JRV
Mem meaning
Carry
Equal
False
Half-Carry
Interrupt Line is High
Interrupt Line is Low
Interrupt Mask
Minus
Not Carry
Not Equal
Not Half-Carry
Not Interrupt Mask
Not Overflow
Plus
Signed Greater or Equal
Signed Greater Than
Signed Lower or Equal
Signed Lower Than
True
Unsigned Greater or Equal
Unsigned Greater Than
Unsigned Lower or Equal
Carry
Unsigned Lower Than
Overflow sym
=
< 0
<> 0
>= 0
>=
>
<=
<
>
<=
Condition
C = 1
Z = 1
False
H = 1
I = 1
N = 1
C = 0
Z = 0
H = 0
I = 0
V = 0
N = 0
(N XOR V) = 0
(Z OR (N XOR V)) = 0
(Z OR (N XOR V)) = 1
(N XOR V) = 1
True
C = 0
C = 0 and Z = 0
C = 1 or Z = 1
C = 1
C = 1
V = 1
Op-code (OC)
90
90
90
90
90
90 2C
28
2A
2E
2B
24
26
28
25
27
21
29
2F
2E
2D
24
22
23
25
25
29
2C
2D
2F
20
Detailed description dst shortoff shortoff
Asm
JRxx $15
JRxx $15 cy lgth
1/2
1/2
2
3
Op-code(s)
Op-code XX
90 Op-code XX
ST7
✗
✗
Doc ID 13590 Rev 3 113/162
STM8 instruction set PM0044
LD
Syntax
Load LD
Operation
Description dst <= src
Load the destination byte with the source byte. The dst and src can be a register, a byte (low/high) of an index register or a memory/data byte. When half of an index register is loaded, the other half remains unchanged.
Instruction overview
Affected condition flags mnem dst src
LD
LD
LD
Reg
Mem
Reg
Mem
Reg
Reg
V
-
-
-
I1
-
-
-
H
-
-
-
I0
-
-
-
N
Z
⇒
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
N
N
N
-
Z
Z
Z
dst src Asm
A #byte
A shortmem
A longmem
A (X)
A (shortoff,X)
LD A,#$55
LD A,$50
LD A,$5000
LD A,(X)
LD A,($50,X)
A (longoff,X)
A (Y)
A (shortoff,Y)
A (longoff,Y)
LD A,($5000,X)
LD A,(Y)
LD A,($50,Y)
LD A,($5000,Y)
A (shortoff,SP)
A [shortptr.w]
LD A,($50,SP)
LD A,[$50.w]
A [longptr.w] LD A,[$5000.w]
A ([shortptr.w],X) LD A,([$50.w],X)
A ([longptr.w],X) LD A,([$5000.w],X)
A ([shortptr.w],Y) LD A,([$50.w],Y) cy lgth
1
4
4
4
4
4
1
1
1
1
1
1
1
1
1
2
3
4
3
4
3
3
2
3
4
3
1
2
2
2
Op-code(s)
A6 XX
B6 XX
C6 MS
F6
E6 XX
D6 MS
90 F6
90 E6 XX
90 D6 MS
7B XX
92 C6 XX
72 C6 MS
92 D6 XX
72 D6 MS
91 D6 XX
LS
LS
LS
LS
LS
✗
✗
✗
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
C
-
-
-
114/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
LD detailed description (Continued) dst shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],
X) src Asm
A LD $50,A
A LD $5000,A
A LD (X),A
A LD ($50,X),A
A LD ($5000,X),A
A LD (Y),A
A LD ($50,Y),A
A LD ($5000,Y),A
A LD ($50,SP),A
A LD [$50.w],A
A LD [$5000.w],A
A LD ([$50.w],X),A
([longptr.w],X) A
([shortptr.w],
Y)
A
LD
([$5000.w],X),A
LD ([$50.w],Y),A cy lgth
1
4
4
1
1
1
1
1
1
1
1
2
3
4
3
4
1
2
2
3
3
2
4 3
4
4
4
3
B7
C7
F7
E7
D7
90 F7
90 E7
90 D7
6B
92 C7
72 C7
Op-code(s)
XX
MS LS
XX
MS
XX
MS
XX
XX
MS
LS
LS
LS
92 D7 XX
72 D7
91 D7
MS
XX
LS dst
XL
A
YL
A
XH
A
YH
A src
A
XL
A
YL
A
XH
A
YH
See also: LDW, LDF, CLR
Asm
LD XL,A
LD A,XL
LD YL,A
LD A,YL
LD XH,A
LD A,XH
LD YH,A
LD A,YH cy lgth
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
2
90
90
90
90
Op-code(s)
97
9F
97
9F
95
9E
95
9E
✗
✗
ST7
✗
✗
✗
✗
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 115/162
STM8 instruction set PM0044
LDF
Syntax
Load Far LDF
Operation
Description
LDF dst,src dst <= src e.g. LDF A,($555555,X)
Load the destination byte with the source byte. The dst and src can be a memory location or accumulator register.
Instruction overview
Affected condition flags mnem dst src
N
⇒
LDF
LDF
A
Mem
Mem
A
V
-
-
I1
-
-
H
-
-
I0
-
-
N
N
N
Z
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
Z
Z
Z dst src Asm
A extmem
A (extoff,X)
LDF A, $500000
LDF A,($500000,X)
A (extoff,Y) LDF A,($500000,Y)
A ([longptr.e],X) LDF A,([$5000.e],X)
A ([longptr.e],Y) LDF A,([$5000.e],Y)
A [longptr.e] LDF A,[$5000.e] cy
1
5
1
1
5
5 lgth
5
4
4
4
4
4
Op-code(s)
BC ExtB MS LS
AF ExtB MS LS
90 AF ExtB MS LS
92 AF MS LS
91 AF MS
92 BC MS
LS
LS
ST7
C
-
dst extmem
(extoff,X)
(extoff,Y)
([longptr.e],X)
([longptr.e],Y)
[longptr.e]
See also: LD, CALLF src
A
A
A
A
A
A
Asm
LDF $500000,A
LDF ($500000,X),A
LDF ($500000,Y),A
LDF ([$5000.e],X),A
LDF ([$5000.e],Y),A
LDF [$5000.e],A cy lgth
4
4
4
1
1
1
4
4
4
4
4
5
Op-code(s)
BD ExtB MS LS
A7 ExtB MS LS
90 A7 ExtB MS LS
92 A7 MS
91 A7 MS
92 BD MS
LS
LS
LS
ST7
116/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
LDW
Syntax
Load word LDW
Operation dst <= src
Description Load the destination word (16-bit value) with the source word. The dst and src can be a 16-bit register (X, Y or SP) or a memory/data 16-bit value.
Instruction overview
Affected condition flags mnem dst src
LD
LD
LD
LD
LD
Reg
Mem
Reg
SP
Reg
Mem
Reg
Reg
Reg
SP
V
-
-
-
-
-
I1
-
-
-
-
-
H
-
-
-
-
-
I0
-
-
-
-
-
N
-
-
-
N
N
N
Z
⇒
⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
Z
-
-
-
Z
Z dst src Asm
X #word
X shortmem
X longmem
X (X)
X (shortoff,X)
X (longoff,X)
X (shortoff,SP)
LDW X,#$55AA
LDW X,$50
LDW X,$5000
LDW X,(X)
LDW X,($50,X)
LDW X,($5000,X)
LDW X,($50,SP)
X [shortptr.w]
X [longptr.w]
LDW X,[$50.w]
LDW X,[$5000.w]
X ([shortptr.w],X) LDW X,([$50.w],X)
X ([longptr.w],X)
LDW
X,([$5000.w],X) cy lgth
2
2
2
2
2
2
2
5
5
5
1
2
3
2
3
2
3
3
4
3
5 4
92
72
92
72
AE
BE
CE
FE
EE
DE
1E
CE
CE
DE
Op-code(s)
MS LS
XX
MS LS
XX
MS LS
XX
XX
MS LS
XX
DE MS LS
✗
✗
ST7
✗
✗
✗
✗
✗
✗
C
-
-
-
-
dst shortmem longmem
(X)
(shortoff,X)
(longoff,X) src Asm
X LDW $50,X
X LDW $5000,X
Y LDW (X),Y
Y LDW ($50,X),Y
Y LDW ($5000,X),Y cy lgth
2
2
2
2
2
1
2
3
2
3
Op-code(s)
BF XX
CF MS LS
FF
EF XX
DF MS LS
ST7
✗
✗
Doc ID 13590 Rev 3 117/162
STM8 instruction set
Note:
PM0044
LDW detailed description (Continued) dst src Asm
(shortoff,SP)
[shortptr.w]
X LDW ($50,SP),X
X LDW [$50.w],X
[longptr.w] X LDW [$5000.w],X
([shortptr.w],X) Y LDW ([$50.w],X),Y
([longptr.w],X) Y LDW ([$5000.w],X),Y cy lgth
5
5
2
5
5
4
3
2
3
4
Op-code(s)
1F
92 CF XX
72 CF MS LS
92 DF XX
72 DF MS LS
ST7
✗
✗ dst src Asm
Y #word
Y shortmem
Y longmem
Y (Y)
LDW Y,#$55AA
LDW Y,$50
LDW Y,$5000
LDW Y,(Y)
Y (shortoff,Y)
Y (longoff,Y)
LDW Y,($50,Y)
LDW Y,($5000,Y)
Y (shortoff,SP)
Y [shortptr.w]
LDW Y,($50,SP)
LDW Y,[$50.w]
Y ([shortptr.w],Y) LDW Y,([$50.w],Y) dst shortmem longmem
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
([shortptr.w],Y) src
X
X
Y
Y
X
Y
Y
X
Asm
LDW $50,Y
LDW $5000,Y
LDW (Y),X
LDW ($50,Y),X
LDW ($5000,Y),X
LDW ($50,SP),Y
LDW [$50.w],Y
LDW ([$50.w],Y),X cy
2
5
5
2
2
2
2
2
2 lgth
2
3
3
3
4
4
3
4
2
Op-code(s)
90 AE MS LS
90 BE XX
90 CE MS LS
90 FE
90 EE XX
90 DE MS LS
16 XX
91 CE XX
91 DE XX cy lgth
2
2
2
2
2
2
5
5
2
3
3
4
4
2
3
3
Op-code(s)
90 BF XX
90 CF MS LS
90 FF
90 EF XX
90 DF MS LS
17 XX
91 CF XX
91 DF XX dst
Y
X
X
SP
Y
SP src
X
Y
SP
X
SP
Y
LDW Y,X
LDW X,Y
LDW X,SP
LDW SP,X
LDW Y,SP
LDW SP,Y cy
1
1
1
1
1
1 lgth
1
1
2
2
2
1
Op-code(s)
90 93
93
96
94
90 96
90 94
ST7
✗
✗
✗
✗
✗
✗
LDW Y,[longptr.w] and LDW [longptr.w],Y are not implemented. They can be emulated using
EXGW X,Y.
See also: LD, CLRW
ST7
✗
✗
✗
✗
✗
✗
✗
✗
ST7
✗
✗
✗
✗
✗
✗
✗
118/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
MOV
Syntax
Move MOV
Operation
Description
MOV dst,src dst<= src e.g. MOV $80,#$AA
●
●
Moves a byte of data from a source address to a destination address. Data is examined as it is moved. The accumulator is not affected.
There are 3 addressing modes for the MOV instruction:
An immediate byte to a direct memory location
●
A direct memory location to another direct memory location (from $00 to $FF)
A direct memory location to another direct memory location (from
$0000 to $FFFF)
Instruction overview mnem dst src
MOV
MOV
Mem
Mem
Detailed description
Imm
Mem dst src Asm longmem #byte MOV $8000, #$AA 1 shortmem shortmem MOV $80,$10 1 longmem longmem
MOV
$8000,$1000
1 cy lgth
4
3
5
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
-
-
Z
-
-
C
-
-
Op-code(s)
35 XX MS LS
45 XX2 XX1
55 MS2 LS2 MS1 LS1
ST7
See also: LD, EXG
Doc ID 13590 Rev 3 119/162
STM8 instruction set PM0044
MUL
Syntax
Multiply (unsigned) MUL
Operation
Description
MUL dst,src dst:src <= dst x src e.g. MUL X,A
Multiplies the 8-bit value in index register, low byte, (XL or YL) by the 8-bit value in the accumulator to obtain a 16-bit unsigned result in the index register. After the operation, index register contains the 16-bit result. The accumulator remains unchanged. The initial value of the high byte of the index register (XH or YH) is ignored.
Instruction overview mnem
MUL
MUL
C: 0
Cleared.
dst
X
Y src
XL,A
YL,A
V
-
-
I1
-
-
Affected condition flags
H
0
0
I0
-
-
N
-
-
Z
-
-
C
0
0
Detailed description dst
X
Y src
A
A
Asm
MUL X,A
MUL Y,A
See also: ADD, ADC, SUB, SBC cy lgth
4
4
1
2 90
42
42
Op-code(s) ST7
120/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
NEG Negate (Logical 2’s complement) NEG
Syntax
Operation
NEG dst e.g. NEG (X) dst <= (dst XOR FF) + 1, or 00 - dst
Description The destination byte is read, then each bit is toggled (inverted), and the result is incremented before it is written at the destination byte. The destination is either a memory byte or a register. The Carry is cleared if the result is zero. This instruction is used to negate signed values. This instruction is compact, and does not affect any register when used with
RAM variables.
Instruction overview
Affected condition flags mnem dst
NEG
NEG
Mem
A
V
V
V
I1
-
-
H
-
-
I0
-
-
N
N
N
Z
Z
Z
C
C
C
V
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if there is an arithmetic overflow on the 8-bit representation of the result. The V bit will set when the content of "dst" was $80 (-128) prior to the NEG operation, cleared otherwise.
N
Z
⇒
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
R7+R6+R5+R4+R3+R2+R1+R0
Set if a borrow in the implied subtraction from zero, cleared otherwise. The
C bit will be set in all cases except when the contents of "dst" was $00 prior to the NEG operation.
Detailed description dst Asm cy lgth Op-code(s)
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
NEG A
NEG $F5
NEG $F5C2
NEG(X)
NEG($F5,X)
NEG($F5C2,X)
1
1
1
1
1
1
1
2
4
1
2
4
72
72
40
30
50
70
60
40
XX
MS
XX
MS
LS
LS
ST7
✗
✗
✗
✗
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
NEG(Y)
NEG($F5,Y)
NEG($F5C2,Y)
NEG($F5,SP)
1
1
1
1
2
3
4
2
90
90
90
70
60
40
00
XX
MS
XX
LS
✗
✗
[shortptr.w] NEG($F5) 4 3 92 30 XX ✗
Doc ID 13590 Rev 3 121/162
STM8 instruction set
NEG detailed description (continued) dst Asm cy lgth
[longptr.w] NEG($F5C2.w)
([shortptr.w],X) NEG([$F5],X)
([longptr.w],X) NEG([$F5C2.w],X)
([shortptr.w],Y) NEG([$F5],Y)
4
4
4
4
4
3
4
3
See also: NEGW, CPL, AND, OR, XOR
72
92
72
91
30
60
60
60
Op-code(s)
MS
XX
MS
XX
LS
LS
PM0044
ST7
✗
✗
122/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
NEGW Negate word (Logical 2’s Complement) NEGW
Syntax
Operation
NEGW dst e.g. NEGW X dst <= (dst XOR FFFF) + 1, or 0000 - dst
Description The destination word is read, then each bit is toggled (inverted), and the result is incremented before it is written at the destination word. The destination is an index register.
Instruction overview
.
Affected condition flags mnem dst
V
⇒
NEGW
NEGW
X
Y
V
V
V
I1
-
-
H
-
-
I0
-
-
N
N
N
Z
Z
Z
C
C
C
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if there is an arithmetic overflow on the 16-bit representation. The V bit will set when the content of "dst" was $8000 prior to the NEGW operation, cleared otherwise.
N
Z
⇒
⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
R15+R14+R13+R12+R11+R10+R9+R8+R7+R6+R5+R4+R3+R2+R1+R0
Set if a borrow in the implied subtraction from zero, cleared otherwise. The
C bit will be set in all cases except when the contents of "dst" was $0000 prior to the NEGW operation.
Detailed description
X
Y dst Asm
NEGW X
NEGW Y cy lgth
2
2
1
2 90
50
50
Op-code(s) ST7
See also: NEG, CPLW, AND, OR, XOR
Doc ID 13590 Rev 3 123/162
STM8 instruction set PM0044
NOP
Syntax
No operation NOP
NOP
Operation
Description This is a single byte instruction that does nothing. This instruction can be used either to disable an instruction, or to build a waiting delay.No register or memory contents are affected by this instruction
Instruction overview mnem
NOP
Detailed description
V
-
Addressing mode
Inherent
Asm
NOP
I1
cy
1
Affected condition flags
H
-
I0
-
N
lgth
1 9D
Op-code(s)
Z
-
C
-
ST7
✗
See also: JRF
124/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
OR
Syntax
Operation
Description
Logical OR OR
OR A,src
A <= A OR src e.g. OR A,#%00110101
The source byte, is logically ORed with the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte.
Truth table
OR
0
1
0
0
1
1
1
1
Instruction overview
Affected condition flags mnem dst src
N
⇒
OR A Mem
V
-
I1
-
H
-
I0
-
N
N
Z
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
Z
Z dst src Asm cy lgth
A #byte
A shortmem
A longmem
A (X)
A (shortoff,X)
A (longoff,X)
A (Y)
A (shortoff,Y)
OR A,#$55
OR A,$10
OR A,$1000
OR A,(X)
OR A,($10,X)
OR A,($1000,X)
OR A,(Y)
OR A,($10,Y)
A (longoff,Y)
A (shortoff,SP)
A [shortptr.w]
A [longptr.w]
OR A,($1000,Y)
OR A,($10,SP)
OR A,[$10.w]
OR A,[$1000.w]
A ([shortptr.w],X) OR A,([$10.w],X) 4
A ([longptr.w],X) OR A,([$1000.w],X) 4
A ([shortptr.w],Y) OR A,([$1000],Y) 4
1
1
4
4
1
1
1
1
1
1
1
1
3
4
3
4
2
3
4
2
3
2
3
2
2
3
1
Op-code(s)
AA XX
BA XX
CA MS LS
FA
EA XX
DA MS LS
90 FA
90 EA XX
90 DA MS LS
1A XX
92 CA XX
72 CA MS LS
92 DA XX
72 DA MS LS
91 DA XX
See also: AND, XOR, CPL, NEG
C
-
✗
✗
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 125/162
STM8 instruction set PM0044
POP
Syntax
Pop from stack POP
Operation
Description
POP dst dst <= (++SP) e.g. POP CC
Restore from the stack a data byte which will be placed in dst location. The stack pointer is incremented by one. This instruction is used to restore a register/memory value.
Instruction overview mnem
POP
POP
POP dst
A
CC
Mem
V
-
V
-
I1
-
I1
-
Affected condition flags
H
-
H
-
I0
-
I0
-
N
-
-
N Z
-
Z
-
C
-
C
-
Detailed description dst
A
CC longmem
Asm
POP A
POP CC
POP $1000
See also: PUSH, POPW cy
1
1
1 lgth
1
1
3
84
86
32
Op-code(s)
MS LS
ST7
✗
✗
126/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
POPW
Syntax
Pop word from stack POPW
Operation
Description
POPW dst e.g. POPW X dst
H
<= (++SP) dst
L
<= (++SP)
Restore from the stack a data value which will be placed in dst location
(index register). The stack pointer is incremented by two. This instruction is used to restore an index register value.
Instruction overview mnem dst
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
-
-
Z
-
-
C
-
POPW
POPW
Detailed description dst
X
Y
Asm
POPW X
POPW Y
X
Y cy
2
2 lgth
1
2 90
85
85
Op-code(s) ST7
✗
✗
See also: PUSHW, POP
Doc ID 13590 Rev 3 127/162
STM8 instruction set PM0044
PUSH
Syntax
Push into the Stack PUSH
Operation
Description
PUSH src
(SP--) <= dst e.g.:PUSH A
Save into the stack the dst byte location. The stack pointer is decremented by one. Used to save a register value and a memory byte on to the stack.
Instruction overview mnem dst
PUSH
PUSH
PUSH
PUSH
Detailed description
A
CC
Imm
Mem dst
A
CC
#byte longmem
Asm
PUSH A
PUSH CC
PUSH #$10
PUSH $1000
-
-
-
V
cy lgth
1
1
1
1
1
1
2
3
-
-
-
I1
-
Affected condition flags
-
-
-
H
-
I0
-
-
-
-
-
-
-
N
-
88
8A
4B
3B
Op-code(s)
XX
MS LS
-
-
-
Z
-
ST7
✗
✗
-
-
-
C
-
See also: POP, PUSHW
128/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
PUSHW
Syntax
Push word onto the Stack PUSHW
Operation
Description
PUSHW src e.g. PUSHW X
(SP--) <= dst
L
(SP--) <= dst
H
Save the dst index register onto the stack. The stack pointer is decremented by two. Used to save an index register value onto the stack.
Instruction overview mnem dst
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
-
-
Z
-
-
C
-
PUSHW
PUSHW
Detailed description dst
X
Y
X
Y
Asm
PUSHW X
PUSHW Y cy lgth
2
2
1
2
89
90 89
Op-code(s) ST7
✗
✗
See also: POPW, PUSH
Doc ID 13590 Rev 3 129/162
STM8 instruction set PM0044
RCF
Syntax
Reset Carry Flag RCF
Operation
Description
RCF
C = 0
Clear the carry flag of the Condition Code (CC) register. May be used as a boolean user controlled flags.
Instruction overview
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
0 mnem
RCF
C: 0
Cleared.
Detailed description
V
-
Addressing mode
Inherent
Asm
RCF cy
1 lgth
1 98
Op-code(s) ST7
✗
See also : SCF, RVF
130/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
RET
Syntax
Return from subroutine RET
Operation
RET
MSB (PC) = (++SP)
LSB (PC) = (++SP)
Description Restore the PC from the stack. The stack pointer is incremented twice. This instruction, is the last instruction of a subroutine in same section.
Instruction overview mnem
RET
Detailed description
V
-
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
Addressing mode
Inherent
Note:
Asm
RET cy
4 lgth
1 81
Op-code(s) ST7
✗
See also: CALL, CALLR
Please note that the RET should be in the same section as the corresponding CALL.
C
-
Doc ID 13590 Rev 3 131/162
STM8 instruction set PM0044
RETF Far Return from subroutine
RETF
Syntax
Operation
RETF
PCE = (++SP)
PCH = (++SP)
PCL = (++SP)
Description Restore the PC from the stack then restore the Condition Code (CC) register. The stack pointer is incremented three times. This instruction is the last one of a subroutine in extended memory.
Instruction overview mnem
RETF
Detailed description
V
-
Addressing mode
Inherent
Asm
RETF
I1
cy
5
Affected condition flags
H
-
I0
-
N
lgth
1 87
Op-code(s)
Z
-
C
-
ST7
See also: CALLF
132/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
RIM Reset Interrupt
Mask/Enable Interrupt
RIM
Syntax
Operation
RIM
I1 = 1, I0 = 0
Description Clear the Interrupt mask of the Condition Code (CC) register, which enable interrupts. This instruction is generally put in the main program, after the reset routine, once all desired interrupts have been properly configured.
This instruction is not needed before WFI and HALT instructions.
Instruction overview
I1
1
Affected condition flags
H
-
I0
0
N
-
Z
-
C
mnem
RIM
I1: 1
Set.
I0: 0
Cleared.
Detailed description
V
-
Addressing mode
Inherent
Asm
RIM cy
1 lgth
1 9A
Op-code(s) ST7
✗
See also: SIM
Doc ID 13590 Rev 3 133/162
STM8 instruction set PM0044
RLC Rotate Left Logical through Carry
e.g. RLC (X)
RLC
Syntax
Operation
RLC dst
Description The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables.This instruction shifts all bits of the register or memory, one place to the left, through the Carry bit. Bit 0 of the result is a copy of the CC.C
value before the operation.
Instruction overview
N
⇒
Z
⇒
C
⇒ mnem
RLC
RLC dst
Reg
Mem
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
N
N
Z
Z
Z
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b7
Set if, before the shift, the MSB of register or memory was set, cleared otherwise.
C bit7 bit7
C b7
Detailed description dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
RLC A
RLC $10
RLC $1000
RLC (X)
RLC ($10,X)
RLC ($1000,X)
RLC (Y)
RLC ($10,Y)
RLC ($1000,Y)
RLC ($10,SP)
RLC [$10]
RLC [$1000].w
RLC ([$10],X)
RLC ([$1000.w],X)
RLC ([$10],Y) lgth
3
4
4
2
3
4
3
4
1
1
2
2
4
2
3 cy
4
4
1
1
4
4
4
1
1
1
1
1
1
1
1
72
72
90
90
90
92
72
92
72
91
See also: RLCW, RRC, SLL, SRL, SRA, ADC, SWAP, SLA
49
09
39
39
69
69
69
49
39
59
79
69
49
79
69
Op-code(s)
XX
MS
XX
MS
XX
MS
XX
XX
MS
XX
MS
XX
LS
LS
LS
LS
LS b0
✗
✗
✗
✗
✗
✗
ST7
✗
✗
✗
✗
134/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
RLCW Rotate Word Left Logical through Carry
e.g. RLCW X
RLCW
Syntax
Operation
RLCW dst
Description The destination is an index register. This instruction shifts all bits of the register one place to the left through Carry bit. Bit 0 of the result is a copy of CC.C value before the operation.
Instruction overview
N
⇒
RLCW
Z
⇒
C
⇒ mnem dst
Reg
V
-
I1
-
Affected condition flags
H
-
I0
-
N
N
Z
Z
C bit15
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b15
Set if, before the shift, the MSB of register or memory was set, cleared otherwise.
C b15 b0
Detailed description dst
X
Y
Asm
RLCW X
RLCW Y cy
2
2 lgth
1
2
59
90 59
Op-code(s)
See also: RLC, RRCW, SLLW, SRLW, SRAW, SWAPW, SLAW
ST7
✗
✗
Doc ID 13590 Rev 3 135/162
STM8 instruction set PM0044
RLWA
Syntax
Rotate Word Left through A RLWA
Operation
Description
RLWA dst e.g. RLWA Y,A
A <= dst
H
<= dst
L
<= A
The destination index register and Accumulator are rotated left by 1-byte.
Instruction overview
Affected condition flags mnem dst src
RLWA
RLWA
N
⇒
X
Y
A
A
V
-
-
I1
-
-
H
-
-
I0
-
-
N
N
N
Z
⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
Z
Z
Z dst
X
Y src
A
A
Asm
RLWA X
RLWA Y cy lgth
1
1
1
2 90
02
02
Op-code(s) ST7
C
-
-
See also: RRWA, SWAPW
136/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
RRC Rotate Right Logical through Carry RRC
Syntax
Operation
RRC dst e.g. RRC (X)
Description The destination is either a memory byte location or a register. This instruction is compact, and does not affect any register when used with
RAM variables.This instruction shifts all bits of the register or memory, one place to the right. Bit 7 of the result is a copy of the CC.C bit value before the operation.
Instruction overview
N
⇒
RRC
RRC
Z
⇒
C
⇒ mnem dst
Reg
Mem
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
N
N
Z
Z
Z
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b0
Set if, before the shift, the LSB of register or memory was set, cleared otherwise.
C bit0 bit0 b0 C b7
Detailed description dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
RRC A
RRC $10
RRC $1000
RRC (X)
RRC ($10,X)
RRC ($1000,X)
RRC (Y)
RRC ($10,Y)
RRC ($1000,Y)
RRC ($10,SP)
RRC [$10]
RRC [$1000].w
RRC ([$10],X)
RRC ([$1000.w],X)
RRC ([$10],Y) lgth
2
3
3
4
4
3
4
3
4
1
1
2
2
4
2 cy
1
4
1
1
4
4
4
4
1
1
1
1
1
1
1
See also: RLC, SRL, SLL, SRA, SWAP, ADC, SLA
72
72
90
90
90
92
72
92
72
91
66
46
06
36
36
66
66
66
46
36
56
76
66
46
76
Op-code(s)
XX
MS
XX
MS
XX
MS
XX
XX
MS
XX
MS
XX
LS
LS
LS
LS
LS
✗
✗
✗
✗
✗
✗
ST7
✗
✗
✗
✗
Doc ID 13590 Rev 3 137/162
STM8 instruction set PM0044
RRCW Rotate Word Right Logical through Carry RRCW
Syntax
Operation
RRCW dst e.g. RRCWX
Description The destination is an index register. This instruction shifts all bits of the register or memory, one place to the right, through the Carry bit. Bit 15 of the result is a copy of the CC.C bit value before the operation.
Instruction overview
N
⇒
RRCW
Z
⇒
C
⇒ mnem dst
Reg
V
-
I1
-
Affected condition flags
H
-
I0
-
N
N
Z
Z
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b0
Set if, before the shift, the MSB of register or memory was set, cleared otherwise.
C bit0
C b15 b0
Detailed description dst
X
Y
Asm
RRCW X
RRCW Y cy
2
2 lgth
1
2
56
90 56
Op-code(s)
See also: RRC, RLCW, SRLW, SLLW, SRAW, SWAPW, SLAW
ST7
✗
✗
138/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
RRWA Rotate Right Word through A RRWA
Syntax
Operation
Description
RRWA dst
A => dst
H
=> dst
L
=> A e.g. RRWA Y,A
The destination index register and Accumulator are rotated right by 1-byte.
Instruction overview mnem
RLWA
RLWA
N
⇒
Z
⇒ dst
X
Y src
A
A
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
N
N
Z
Z
Z
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
C
-
-
Detailed description dst
X
Y src
A
A
Asm
RRWA X
RRWA Y
See also: RLWA, SWAPW cy lgth
1
1
1
2 90
01
01
Op-code(s) ST7
Doc ID 13590 Rev 3 139/162
STM8 instruction set PM0044
RVF
Syntax
Reset overflow flag RVF
Operation
Description
RVF
V = 0
Clear the overflow flag of the Condition Code (CC) register. May be used as a boolean user controlled flags.
Instruction overview
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
mnem
RCF
V: 0
Cleared.
Detailed description
V
0
Addressing mode
Inherent
Asm
RVF cy
1 lgth
1
Op-code(s)
9C
ST7
✗
See also: RCF, SCF
140/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
SBC Subtraction with
Carry/Borrow
e.g. SBC A,#$15
SBC
Syntax
Operation
SBC A,src
A <= A- src - C
Description The source byte, along with the carry flag, is subtracted from the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte.
Instruction overview dst
A
A
A
A
A
A
A
A
A
A
A
A
V mnem
⇒
SBC
Affected condition flags dst src
A Mem
V
V
I1
-
H
-
I0
-
N
N
Z
Z
(A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6)
Set if the signed subtraction generates an overflow, cleared otherwise.
C
C
N
Z
⇒
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C
⇒
A7.M7 + A7.R7 + A7.M7.R7
Set if a borrow request occurred from bit 7 of the result, cleared otherwise.
Detailed description
A
A
A src
#byte shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
SBC A,#$55
SBC A,$10
SBC A,$1000
SBC A,(X)
SBC A,($10,X)
SBC A,($1000,X)
SBC A,(Y)
SBC A,($10,Y)
SBC A,($1000,Y)
SBC A,($10,SP)
SBC A,[$10.w]
SBC A,[$1000.w]
SBC
A,([$10.w],X)
SBC
A,([$1000.w],X)
SBC
A,([$10.w],Y)
See also: ADD,ADC,SUB, MUL
4
4 lgth
1
2
3
2
2
2
3
2
3
4
3
4
3 cy
1
1
1
1
1
1
1
1
4
4
1
1
4
4
3
Op-code(s)
A2 XX
B2 XX
C2 MS LS
F2
E2 XX
D2 MS LS
90 F2
90 E2 XX
90 D2 MS LS
12 XX
92 C2 XX
72 C2 MS LS
92 D2 XX
72 D2 MS LS
91 D2 XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 141/162
STM8 instruction set PM0044
SCF
Syntax
Set Carry Flag SCF
Operation
Description
SCF
C = 1
Set the carry flag of the Condition Code (CC) register. It may be used as user controlled flag.
Instruction overview mnem
SCF
Instruction overview
I1
-
Affected condition flags
H
-
I0
-
N
-
Z
-
C
1 mnem
SCF
C: 1
Set.
Detailed description
V
-
Addressing mode
Inherent
Asm
SCF cy
1 lgth
1 99
Op-code(s) ST7
✗
See also: RCF, RVF
142/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
SIM Set Interrupt
Mask/Disable Interrupt
SIM
Syntax
Operation sim
I1 = 1, I0 = 1
Description Set the Interrupt mask of the Condition Code (CC) register, which disables interrupts. This instruction is useless at the beginning of reset routine. It need not be used at the beginning of interrupt routines as the interrupt level is set automatically in CC.I[1:0].
Instruction overview
I1
1
Affected condition flags
H
-
I0
1
N
-
Z
-
C
mnem
SIM
I1 and I0: 1
Set.
Detailed description
V
-
Addressing mode
Inherent
Asm
SIM cy
1 lgth
1 9B
Op-code(s) ST7
✗
See also: RIM
Doc ID 13590 Rev 3 143/162
STM8 instruction set PM0044
SLL/SLA
Syntax SLL dst
SLA dst
Shift Left Logical/Shift
Left Arithmetic
e.g. SLL (X) e.g. SLA (X)
SLL/SLA
Operation
Description The destination is either a memory byte or a register.It double the affected value. This instruction is compact, and does not affect any register when used with RAM variables.
Instruction overview
SLL/SLA
SLL/SLA
N
⇒
Z
⇒
C
⇒ mnem dst
Mem
Reg
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
N
N
Z
Z
Z
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b7
Set if, before the shift, bit 7 of register or memory was set, cleared otherwise.
C b7 b0 0
C bit7 bit7
Detailed description dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
Asm
(1)
SLL A
SLL $15
SLL $1505
SLL (X)
SLL ($15,X)
SLL ($1505,X)
SLL (Y)
SLL ($15,Y)
SLL ($1505,Y)
SLL ($15,SP)
SLL [$15]
SLL [$1505].w
SLL ([$15],X) cy lgth
1
1
1
1
1
1
1
1
4
4
4
1
1
2
4
2
3
1
2
4
1
3
4
3
4
2
Op-code(s)
48
38 XX
72 58 MS
78
68 XX
72 48 MS
90 78
90 68 XX
90 48 MS
08 XX
92 38 XX
72 38 MS
92 68 XX
LS
LS
LS
LS
✗
✗
✗
✗
✗
ST7
✗
✗
✗
✗
144/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
([longptr.w],X)
([shortptr.w],Y)
SLL ([$1505.w],X)
SLL ([$15],Y)
4
4
4
3
1.
For the shift left arithmetic instruction, replace SLL by SLA.
See also: SLA, SRA, SRL, RRC, RLC, SWAP
72 68 MS
91 68 XX
LS
✗
Doc ID 13590 Rev 3 145/162
STM8 instruction set PM0044
SLLW/SLAW
Syntax SLLW dst
SLAW dst
Shift Left Logical
Word/Shift Left Arithmetic
Word
e.g. SLLW X e.g. SLAW X
SLLW/SLAW
Operation
Description The destination is an index register.It double the affected value.
Instruction overview mnem
SLLW/SLAW
N
⇒
Z
⇒ dst
Reg
V
-
I1
-
Affected condition flags
H
-
I0
-
N
N
Z
Z
R15
Set if bit 15of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C bit15
C
⇒ b15
Set if, before the shift, bit 15 of register or memory was set, cleared otherwise.
C b15 b0 0
Detailed description dst Asm
(1) cy lgth
X
Y
SLLW X
SLLW Y
2
2
1
2
1.
For the shift left arithmetic word instruction, replace SLLW by SLAW.
58
90 58
Op-code(s)
See also: SLL, SRAW, SRLW, RRCW, RLCW, SWAPW, SLAW
ST7
146/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
SRA
Syntax
Shift Right Arithmetic SRA
SRA dst e.g. SRA (X)
Operation
Description The destination is either a memory byte or a register. It performs an signed division by 2: The sign bit 7 is not modified.This instruction is compact, and does not affect any register when used with RAM variables.
Instruction overview
N
⇒
SRA
SRA
Z
⇒
C
⇒ mnem dst
Reg
Mem
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
N
N
Z
Z
Z
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b0
Set if, before the shift, the LSB of register or memory was set, cleared otherwise.
C bit0 bit0 b7 b7 b0 C
Detailed description dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
SRA A
SRA $15
SRA $1505
SRA (X)
SRA ($15,X)
SRA ($1505,X)
SRA (Y)
SRA ($15,Y)
SRA ($1505,Y)
SRA ($15,SP)
SRA [$15]
SRA [$1505].w
SRA ([$15],X)
SRA ([$1505.w],X)
SRA ([$15],Y) cy lgth
4
4
4
1
1
4
4
1
1
1
1
1
1
1
1
3
4
3
4
2
3
4
2
4
2
3
1
2
4
1
See also: SRAW, SRL, SLL, RRC, RLC, SWAP
Op-code(s)
47
37 XX
72 57 MS
77
67 XX
72 47 MS
90 77
90 67 XX
90 47 MS
07 XX
92 37 XX
72 37 MS
92 67 XX
72 67 MS
91 67 XX
LS
LS
LS
LS
LS
Doc ID 13590 Rev 3 147/162
✗
✗
✗
✗
✗
✗
ST7
✗
✗
✗
✗
STM8 instruction set PM0044
SRAW Shift Right Arithmetic
Word
SRAW
Syntax
Operation
SRAW dst e.g. SRAW X
Description The destination is an index register. It performs a signed division by 2. The sign bit (15) is not modified.
Instruction overview
N
⇒
SRAW
Z
⇒
C
⇒ mnem dst
Reg
V
-
I1
-
Affected condition flags
H
-
I0
-
N
N
Z
Z
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
b0
Set if, before the shift, the LSB of register or memory was set, cleared otherwise.
C bit0 b15 b15 b0 C
Detailed description dst
X
Y
Asm
SRAW X
SRAW Y cy lgth
2
2
1
2
57
90 57
Op-code(s)
See also: SRA, SRLW, SLLW, RRCW, RLCW, SWAPW
ST7
148/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
SRL
Syntax
Shift Right Logical SRL
SRL dst e.g. SRL (X)
Operation
Description The destination is either a memory byte or a register.It perform an unsigned division by 2.This instruction is compact, and does not affect any register when used with RAM variables.
Instruction overview
N
⇒
SRL
SRL
Z
⇒ mnem dst
Reg
Mem
V
-
-
I1
-
-
Affected condition flags
H
-
-
I0
-
-
N
N
N
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Z
Z
Z
C bit0 bit0
C
⇒ b0
Set if, before the shift, the LSB of register or memory was set, cleared otherwise.
0 b7 b0 C
Detailed description dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
SRL A
SRL $15
SRL $1505
SRL (X)
SRLL ($15,X)
SRL ($1505,X)
SRL (Y)
SRL ($15,Y)
SRL ($1505,Y)
SRL ($15,SP)
SRL [$15]
SRL [$1505].w
SRL ([$15],X)
SRL ([$1505.w],X)
SRL ([$15],Y) cy lgth
4
4
4
1
1
4
4
1
1
1
1
1
1
1
1
3
4
3
4
2
3
4
2
4
2
3
1
2
4
1
See also: RLC, RRC, SRA, SWAP, SLL, SRLW
Op-code(s)
44
34 XX
72 54 MS
74
64 XX
72 44 MS
90 74
90 64 XX
90 44 MS
04 XX
92 34 XX
72 34 MS
92 64 XX
72 64 MS
91 64 XX
LS
LS
LS
LS
LS
Doc ID 13590 Rev 3 149/162
✗
✗
✗
✗
✗
✗
ST7
✗
✗
✗
✗
STM8 instruction set PM0044
SRLW
Syntax
Shift Right Logical Word SRLW
SRLW dst e.g. SRLW X
Operation
Description The destination is an index register. It performs an unsigned division by 2.
Instruction overview
N
⇒
SRLW
Z
⇒
C
⇒ mnem dst
Reg
V
-
I1
-
Affected condition flags
H
-
I0
-
N
N
Z
Z
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
b0
Set if, before the shift, the LSB of the register was set, cleared otherwise.
C bit0
0 b15 b0 C
Detailed description dst
X
Y
Asm
SRLW X
SRLW Y cy lgth
2
2
1
2
54
90 54
Op-code(s)
See also: SRL, RLCW, RRCW, SRLW, SRAW, SWAPW, SLLW
ST7
150/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
SUB
Syntax
Subtraction SUB
Operation
Description
SUB A,src
A <= A- src e.g. SUB A,#%11001010
The source byte is subtracted from the contents of the accumulator/SP and the result is stored in the accumulator/SP. The source is a memory or data byte.
Instruction overview dst
A
A
A
A
A
A
A
A
A
A
A
A
A
Affected condition flags mnem dst src
V
⇒
SUB
SUB
A
SP
Mem
Imm
V
V
-
I1
-
-
H
-
-
I0
-
-
N
N
-
Z
Z
-
N
⇒
(A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6)
Set if the signed operation generates an overflow, cleared otherwise.
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
C
⇒
⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
A7.M7 + A7.R7 + A7.M7.R7
Set if a borrow request occurred from bit 7, cleared otherwise.
Detailed description
C
C
-
A
A
SP src Asm
#byte shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
SUB A,#$55
SUB A,$10
SUB A,$1000
SUB A,(X)
SUB A,($10,X)
SUB A,($1000,X)
SUB A,(Y)
SUB A,($10,Y)
SUB A,($1000,Y)
SUB A,($10,SP)
[shortptr.w]
[longptr.w]
SUB A,[$10.w]
SUB A,[$1000.w]
([shortptr.w],X) SUB A,([$10.w],X)
([longptr.w],X)
SUB
A,([$1000.w],X)
([shortptr.w],Y) SUB A,([$10.w],Y)
#byte SUB SP,#$9
See also: SUBW, ADD, ADC, SBC, MUL
4
3
2 lgth
2
3
4
2
3
1
2
2
2
3
3
4
3
4
4
1 cy
1
1
1
1
1
1
1
1
1
1
4
4
4
Op-code(s)
A0 XX
B0 XX
C0 MS LS
F0
E0 XX
D0 MS LS
90 F0
90 E0 XX
90 D0 MS LS
10 XX
92 C0 XX
72 C0 MS LS
92 D0 XX
72 D0 MS LS
91 D0 XX
52 XX
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
Doc ID 13590 Rev 3 151/162
STM8 instruction set PM0044
SUBW
Syntax
Word Subtraction SUBW
Operation
Description
SUBW dst,src dst <= dst - src e.g. SUBW X, #$5500
The source 16-bit word is subtracted from the contents of the destination index register and the result is stored in the same index register. The source is a memory or 16-bit data.
Instruction overview
Affected condition flags mnem dst src
SUBW
SUBW
V
⇒
X
Y
Mem
Mem
V
V
V
I1
-
-
H
H
H
I0
-
-
N
N
N
Z
Z
Z
(X15.M15 + X15.R15 + X15.M15.R15) ⊕ (X14.M14 + X14.R14 +
X14.M14.R14)
Set if the signed operation generates an overflow, cleared otherwise.
H
N
⇒
⇒
X7.M7 + X7.R7 + X7.M7.R7
Set if a carry occurred from bit 7, cleared otherwise.
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z
C
⇒
⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
X15.M15 + X15.R15 + X15.M15.R15
Set if a borrow request occurred from bit 15, cleared otherwise.
Detailed description
C
C
C dst
X
Y
X
X
Y
Y src Asm
#word longmem
SUBW X,#$5500
SUBW X,$1000
(shortoff, SP) SUBW X,($10,SP)
#word SUBW Y,#$5500 longmem SUBW Y,$1000
(shortoff, SP) SUBW Y,($10,SP)
See also: SUB, ADDW, ADC, SBC, MUL cy
2
2
2
2
2
2 lgth
3
4
3
4
4
3
Op-code(s)
1D MS LS
72 B0 MS LS
72 F0 XX
72 A2 MS LS
72 B2 MS LS
72 F2 XX
ST7
152/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
SWAP
Syntax
Swap nibbles SWAP
SWAP dst e.g. SWAP counter
Operation
Description The destination byte upper and low nibbles are swapped over. The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables.
Instruction overview
Affected condition flags mnem dst
SWAP
SWAP
Reg
Mem
V
-
-
I1
-
-
H
-
-
I0
-
-
N
N
N
N
Z
⇒
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
Z
Z
Z dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
SWAP A
SWAP $15
SWAP $1505
SWAP (X)
SWAPL ($15,X)
SWAP ($1505,X)
SWAP (Y)
SWAP ($15,Y)
SWAP ($1505,Y)
SWAP ($15,SP)
SWAP [$15]
SWAP [$1505].w
SWAP ([$15],X)
SWAP ([$1505.w],X)
SWAP ([$15],Y) cy lgth
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
2
3
4
2
4
1
1
2
2
4
3
4
3
3
4
Op-code(s)
4E
3E XX
72 5E MS LS
7E
6E XX
72 4E MS LS
90 7E
90 6E XX
90 4E MS LS
0E XX
92 3E XX
72 3E MS LS
92 6E XX
72 6E MS LS
91 6E XX
C
-
-
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: SWAPW, RRC, RLC, SLL, SRL, SRA
Doc ID 13590 Rev 3 153/162
STM8 instruction set PM0044
SWAPW
Syntax
Swap bytes SWAPW
SWAPW dst e.g. SWAPW Y
Operation
Description The destination index register upper and low bytes are swapped over.
Instruction overview
Affected condition flags mnem dst
N
⇒
SWAP Reg
V
-
I1
-
H
-
I0
-
N
N
Z
Z
Z
⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
X
Y dst Asm
SWAPW X
SWAPW Y cy lgth
1
1
1
2
5E
90 5E
Op-code(s)
C
-
ST7
✗
✗
See also: SWAP, RRC, RLC, SLL, SRL, SRA
154/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
TNZ
Syntax
Test for Negative or Zero TNZ
Operation
Description
TNZ dst
{N, Z} = Test(dst) e.g. TNZ A
The destination byte is tested and both N and Z flags of the Condition Code
(CC) register are updated accordingly. This instruction is compact, and does not affect any register when used with RAM variables.
Instruction overview
Affected condition flags mnem dst
TNZ
TNZ
Reg
Mem
V
-
-
I1
-
-
H
-
-
I0
-
-
N
N
N
N
Z
⇒
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
Z
Z
Z dst
A shortmem longmem
(X)
(shortoff,X)
(longoff,X)
(Y)
(shortoff,Y)
(longoff,Y)
(shortoff,SP)
[shortptr.w]
[longptr.w]
([shortptr.w],X)
([longptr.w],X)
([shortptr.w],Y)
Asm
TNZ A
TNZ $15
TNZ $1505
TNZ (X)
TNZL ($15,X)
TNZ ($1505,X)
TNZ (Y)
TNZ ($15,Y)
TNZ ($1505,Y)
TNZ ($15,SP)
TNZ [$15]
TNZ [$1505].w
TNZ ([$15],X)
TNZ ([$1505.w],X)
TNZ ([$15],Y) cy lgth
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
2
3
4
2
4
1
1
2
2
4
3
4
3
3
4
Op-code(s)
4D
3D XX
72 5D MS LS
7D
6D XX
72 4D MS LS
90 7D
90 6D XX
90 4D MS LS
0D XX
92 3D XX
72 3D MS LS
92 6D XX
72 6D MS LS
91 6D XX
C
-
-
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
See also: TNZW, CP, BCP
Doc ID 13590 Rev 3 155/162
STM8 instruction set PM0044
TNZW
Syntax
Operation
Word Test for Negative or
Zero
TNZW dst
{N, Z} = Test(dst) e.g. TNZW X
TNZW
Description The destination 16-bit word, index register, is tested and both N and Z flags of the Condition Code (CC) register are updated accordingly.
Instruction overview
Affected condition flags mnem dst
N
⇒
TNZW Reg
V
-
I1
-
H
-
I0
-
N
N
Z
Z
Z
⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
X
Y dst Asm
TNZW X
TNZW Y cy lgth
2
2
1
2
5D
90 5D
Op-code(s)
C
-
ST7
See also: TNZ, CPW
156/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
TRAP
Syntax
Operation
Software interrupt
TRAP
PC = PC + 1
(SP--) = LSB (PC)
(SP--) = MSB (PC)
(SP--) = Ext(PC)
(SP--) = YL
(SP--) = YH
(SP--) = XL
(SP--) = XH
(SP--) = A
(SP--) = CC
PC = TRAP Interrupt Vector Contents
TRAP
Description When processed, this instruction forces the trap interrupt to occur and to be processed. It cannot be masked by the I0 or I1 flags.
Instruction overview mnem
TRAP
I1 and I0: 1
Set.
Detailed description
V
-
I1
1
Affected condition flags
H
-
I0
1
N
-
Z
-
C
-
Addressing mode
Inherent
Asm
TRAP cy
9 lgth
1 83
Op-code(s) ST7
✗
See also: IRET
Doc ID 13590 Rev 3 157/162
STM8 instruction set PM0044
WFE Wait for Event
(CPU stopped, low power mode)
WFE
Syntax
Operation
WFE
The CPU Clock is stopped till an external event occurs. Internal peripherals are still running. It is used for synchronization with other computing resources (e.g coprocessor).
Description The state of the CPU is frozen, waiting for synchronization with an external event. The CPU clock also is stopped, reducing the power consumption of the microcontroller. Interrupt requests during this period are served normally, depending on the CC.I[1:0] value.
Instruction overview mnem
WFE
Detailed description
V
-
Addressing mode
Inherent
Asm
WFE
I1
cy
1
Affected condition flags
H
-
I0
-
N
lgth
2 72 8F
Op-code(s)
Z
-
C
-
ST7
See also: HALT
158/162 Doc ID 13590 Rev 3
PM0044 STM8 instruction set
WFI Wait for Interrupt
(CPU stopped, low power mode)
WFI
Syntax
Operation
WFI
CC.I1= 1, CC.I0 = 0. The CPU Clock is stopped till an interrupt occurs.
Internal peripherals are still running.
Description The interrupt flag is cleared, allowing interrupts to be fetched. Then the
CPU clock is stopped, reducing the power consumption of the microcontroller. The micro will continue the program upon an internal or external interrupt.
Instruction overview
I1
1
Affected condition flags
H
-
I0
0
N
-
Z
-
C
mnem
WFI
I1: 1
Set.
I0: 0
Cleared.
Detailed description
V
-
Addressing mode
Inherent
Asm
WFI cy
10 lgth
1 8F
Op-code(s) ST7
✗
See also: HALT
Doc ID 13590 Rev 3 159/162
STM8 instruction set PM0044
XOR
Syntax
Operation
Description
Logical Exclusive OR XOR
XOR A,src
A <= A XOR src e.g. XOR A,#%00110101
The source byte, is logically XORed with the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte.
Truth table
XOR
0
1
Instruction overview
Affected condition flags mnem dst src
N
⇒
XOR A Mem
V
-
I1
-
H
-
I0
-
N
N
Z
⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
Z
Z dst src
A #byte
A shortmem
A longmem
A (X)
A (shortoff,X)
A (longoff,X)
A (Y)
A (shortoff,Y)
A (longoff,Y)
A (shortoff,SP)
A [shortptr.w]
A [longptr.w]
A ([shortptr.w],X)
A ([longptr.w],X)
A ([shortptr.w],Y)
Asm
XOR A,#$55
XOR A,$10
XOR A,$1000
XOR A,(X)
XOR A,($10,X)
XOR A,($1000,X)
XOR A,(Y)
XOR A,($10,Y)
XOR A,($1000,Y)
XOR A,($10,SP)
XOR A,[$10.w]
XOR A,[$1000.w]
XOR
A,([$10.w],X)
XOR
A,([$1000.w],X)
XOR
A,([$1000],Y) cy lgth
1
1
1
1
1
1
1
1
1
1
4
4
2
3
2
3
2
2
3
1
4
2
3
4
4 3
4
4
4
3
E8
D8
90 F8
90 E8
A8
B8
C8
F8
90 D8
18
92 C8
72 C8
Op-code(s)
XX
XX
MS
XX
MS
XX
MS
XX
XX
MS
LS
LS
LS
LS
92 D8 XX
72
91
D8
D8
MS
XX
LS
See also: AND, OR, CPL, NEG
0
0
1
1
1
0
C
-
ST7
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
✗
160/162 Doc ID 13590 Rev 3
PM0044 Revision history
Table 43.
Document revision history
Date
14-Jan-2008
05-Jun-2008
2 0 Sep -2011
Revision
1
2
3
Changes
Initial release.
Modified
Figure 2: Context save/restore for interrupts on page 14
Changed notation for hexadecimal numbers from XXh to 0xXX.
Removed CPU register context saving from
Added LDF in Table 22: Available Extended Direct addressing mode instructions
.
Updated
Figure 2: Context save/restore for interrupts
.
Added BREAK instruction in
.
Added
Section 5: Pipelined execution
.
Table 42: Instruction set summary : updated ADDW, BCCM, BRES,
BSET, BTJF, BTJT, CALLR, DEC, DECW, DIV, EXGW, JRA, JRC,
JREQ, JRH, JRIH, JRIL, JRM, JRMI, JRNC, JRNE, JRNH, JRNM,
JRNV, JRPL, JRSGE, JRSGT, JRSLE, JRSLT, JRUGE, JRULT, LDF,
LDW, MOV, NEG, PUSH, RRCW, SBC, SLA, SLAW, SLL, SLLW,
SRA, SRAW, SRL, SRLW, SUB. Added BREAK and INT instructions.
Section 7: STM8 instruction set : updated ADD, ADDW, BCCM, BCP,
BCPL, BRES, BSET, BTJF, BTJT, CLR, CP, CPW, DEC, DECW,
HALT, INCW, INT, JP, JRxx, MOV, RLWA, RRCW, RRWA, SBC,
SRLW, SUB, and SWAPW. Added BREAK instruction. Merged JRA with JRL instructions, SLA with SLL, and SLAW with SLLW.
Doc ID 13590 Rev 3 161/162
PM0044
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