STMicroelectronics STM8S007C8 Datasheet
Oglas
Oglas
STM8S007C8
Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash, true data
EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C
Datasheet
-
production data
Features
• Core
– Max f f
CPU
≤
CPU
: up to 24 MHz, 0 wait states @
16 MHz
– Advanced STM8 core with Harvard architecture and 3-stage pipeline
– Extended instruction set
– Max 20 MIPS @ 24 MHz
• Memories
– Program: 64 Kbytes Flash; data retention
20 years at 55 °C after 100 cycles
– Data: 128 bytes true data EEPROM; endurance 100 kcycles
– RAM: 6 Kbytes
• Clock, reset and supply management
– 2.95 to 5.5 V operating voltage
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
– Clock security system with clock monitor
– Wait, active-halt, & halt low power modes
– Peripheral clocks switched off individually
– Permanently active, low consumption power-on and power-down reset
• Interrupt management
– Nested interrupt controller with 32 interrupts
– Up to 37 external interrupts on 6 vectors
• Timers
– 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization
– 8-bit basic timer with 8-bit prescaler
– Auto wakeup timer
– Window watchdog, independent watchdog
LQFP48
7 x 7mm
• Communications interfaces
– UART with clock output for synchronous operation - LIN master mode
– UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization
– SPI interface up to 10 Mbit/s
– I 2 C interface up to 400 Kbit/s
• 10-bit ADC with up to 16 channels
• I/Os
– 38 I/Os including 16 high sink outputs
– Highly robust I/O design, immune against current injection
– Development support
– Single wire interface module (SWIM) and debug module (DM)
October 2018
This is information on a product in full production.
DS8633 Rev 6
www.st.com
Contents
Contents
STM8S007C8
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 12
Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . 12
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 16
Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DS8633 Rev 6
STM8S007C8
Contents
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 56
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 58
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2 C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 88
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 90
DS8633 Rev 6
4
Contents
STM8S007C8
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DS8633 Rev 6
STM8S007C8
List of tables
List of tables
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 14
Total current consumption with code execution in run mode at V
DD
Total current consumption with code execution in run mode at V
DD
Total current consumption in wait mode at V
DD
Total current consumption in wait mode at V
DD
= 5 V . . . . . . . . . . . . 49
= 3.3 V . . . . . . . . . . . 50
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Total current consumption in active halt mode at V
DD
Total current consumption in active halt mode at V
DD
= 5 V, T
A
-40 to 85° C . . . . . . . . . . 52
= 3.3 V . . . . . . . . . . . . . . . . . . . . . 52
Total current consumption in halt mode at V
Total current consumption in halt mode at V
= 5 V, T
A
-40 to 85° C . . . . . . . . . . . . . . . 53
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
< 10 k Ω , V
< 10 k Ω R
DDA
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AIN
, V
DDA
= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DS8633 Rev 6
6
List of tables STM8S007C8
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 84
DS8633 Rev 6
STM8S007C8
List of figures
List of figures
CPUmax
versus V
DD(RUN)
DD(WFI)
vs V
DD
vs V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
, HSI RC osc, f
, HSI RC osc, f
CPU
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CPU
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical HSI frequency variation vs V
Typical LSI frequency variation vs V
DD
Typical pull-up resistance vs V
DD
OL
OL
OL
OL
OL
OL
DD
DD
DD
DD
and V
@ V
DD
@ V
DD
@ V
DD
@ V
DD
@ V
DD
@ V
- V
- V
- V
DD
OH
OH
OH
- V
OH
IH
vs V
DD
at 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 59
@ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
= 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
= 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
= 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
= 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
= 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
= 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
@ V
@ V
@ V
@ V
DD
DD
DD
DD
= 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
= 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
= 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
= 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
and V
IH
vs V
DD
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical NRST pull-up resistance vs V
DD
Typical NRST pull-up current vs V
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . 71
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SPI timing diagram - master mode
(1)
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . 85
STM8S007C8 value line ordering information scheme
. . . . . . . . . . . . . . . . . . . . . . . . . . 89
DS8633 Rev 6
7
Introduction
1 Introduction
STM8S007C8
This datasheet contains the description of the STM8S007C8 value line features, pinout, electrical characteristics, mechanical data and ordering information.
• For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).
• For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM).
• For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
• For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
DS8633 Rev 6
STM8S007C8
2 Description
Description
The STM8S007C8 value line 8-bit microcontrollers offer 64 Kbytes of Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual (RM0016).
The STM8S007C8 value line devices provide the following benefits: reduced system cost, performance, robustness, short development cycles, and product longevity.
The system cost is reduced thanks to a true data EEPROM for up to 100 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.
Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
Table 1. STM8S007C8 value line features
Features STM8S007C8
Pin count
Max. number of GPIOs (I/O)
External interrupt pins
Timer CAPCOM channels
Timer complementary outputs
A/D converter channels
High-sink I/Os
High-density Flash program memory
Data EEPROM
RAM
48
38
35
9
3
10
16
64 Kbyte
128 bytes
6 Kbytes
DS8633 Rev 6
25
Block diagram STM8S007C8
Figure 1. STM8S007C8 value line block diagram
Single wire debug interface
400 Kbit/s
10 Mbit/s
LIN master
SPI emul.
Master/slave autosynchro
16 channels
1/2/4 kHz beep
Reset block
Reset
POR BOR
Clock controller
XTAL 1-24 MHz
RC int. 16 MHz
Detector
RC int. 128 kHz
STM8 core
Debug / SWIM
I2C
Clock to peripherals and core
Window WDG
Independent WDG
64 Kbyte high density program Flash
128 byte data EEPROM
6 Kbyte RAM
SPI
UART1
UART3
ADC2
Beeper
Boot ROM
16-bit advanced control timer (TM1)
16-bit general purpose timers
(TIM2, TIM3)
8-bit basic timer
(TIM4)
AWU timer
Up to 4
CAPCOM channels + 3 complementary outputs
Up to 5
CAPCPOM channels
MS61103V1
DS8633 Rev 6
STM8S007C8 Product overview
The following section intends to give an overview of the basic features of the STM8S007C8 value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
The 8-bit STM8 core is designed for code efficiency and performance.
It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus - single cycle fetching for most instructions
• X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter - 16-Mbyte linear memory space
• 16-bit stack pointer - access to a 64 K-level stack
• 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for look-up tables located anywhere in the address space
• Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
DS8633 Rev 6
25
Product overview
4.2
STM8S007C8
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
• R/W to RAM and peripheral registers in real-time
• R/W access to all resources by stalling the CPU
• Breakpoints on all program-memory instructions (software breakpoints)
• Two advanced breakpoints, 23 predefined configurations
4.4
• Nested interrupts with three software priority levels
• 32 interrupt vectors with hardware priority
• Up to 33 external interrupts on six vectors including TLI
• Trap and reset interrupts
Flash program memory and data EEPROM
• 64 Kbyte of high-density Flash program single voltage Flash memory
• 128 byte true data EEPROM
• Read while write: Writing in data memory possible while executing code in program memory.
• User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to
DS8633 Rev 6
STM8S007C8 Product overview
The size of the UBC is programmable through the UBC option byte ( Table 12
), in increments of 1 page (512 byte) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
• Main program memory: 64 Kbyte minus UBC
• User-specific boot code (UBC): Configurable up to 64 Kbyte
The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.
Figure 2. Flash memory organization
Data
EEPROM memory
Data memory area (up to 2 Kbyte)
Option bytes
UBC area
Remains write protected during IAP
Programmable area from 1 Kbyte
(2 first pages) up to 64 Kbytes
(1 page steps)
64 Kbytes
Flash program memory
Program memory area
Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
DS8633 Rev 6
25
Product overview STM8S007C8
The clock controller distributes the system clock (f
MASTER)
coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
Features
• Clock prescaler : To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
• Safe clock switching : Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.
• Clock management : To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• Master clock sources : Four different clock sources can be used to drive the master clock:
– 1-24 MHz high-speed external crystal (HSE)
– Up to 24 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
• Startup clock : After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
• Clock security system (CSS) : This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.
• Configurable main clock output (CCO) : This outputs an external clock for use by the application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit
Peripheral clock
Bit
Peripheral clock
Bit
Peripheral clock
Bit
Peripheral clock
PCKEN17
PCKEN16
PCKEN15
PCKEN14
TIM1
TIM3
TIM2
TIM4
PCKEN13 UART3 PCKEN27 Reserved PCKEN23 ADC
PCKEN12 UART1 PCKEN26 Reserved PCKEN22
PCKEN11
PCKEN10
SPI
I
2
C
PCKEN25
PCKEN24
Reserved
Reserved
PCKEN21
PCKEN20
AWU
Reserved
Reserved
DS8633 Rev 6
STM8S007C8 Product overview
For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources.
• Wait mode : In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
• Active halt mode with regulator on : In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
• Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.
• Halt mode : In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.
The watchdog system is based on two independent timers providing maximum security to the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application perfectly.
The application software must refresh the counter before time-out and during a limited time window.
A reset is generated in two situations:
1.
Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.
2. Refresh out of window: the down-counter is refreshed before its value is lower than the one stored in the window register.
DS8633 Rev 6
25
Product overview STM8S007C8
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter
• Used for auto wakeup from active halt mode
• Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
• LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
4.10 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.
• 16-bit up, down and up/down autoreload counter with 16-bit prescaler
• Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output
• Synchronization module to control the timer with external signals
• Break input to force the timer outputs into a defined state
• Three complementary outputs with adjustable dead time
• Encoder mode
• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM2, TIM3 - 16-bit general purpose timers
• 16-bit autoreload (AR) up-counter
• 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
• Timers with 3 or 2 individually configurable capture/compare channels
• PWM mode
• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
DS8633 Rev 6
STM8S007C8 Product overview
4.12 TIM4 - 8-bit basic timer
• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
• Clock source: CPU clock
• Interrupt source: 1 x overflow/update
Table 3. TIM timer features
Timer
Counter size
(bits)
Prescaler
Counting mode
CAPCOM channels
Complem. outputs
Ext. trigger
Timer synchronization/ chaining
TIM1
TIM2
TIM3
TIM4
16
16
16
8
Any integer from 1 to 65536
Any power of 2 from 1 to 32768
Any power of 2 from 1 to 32768
Any power of 2 from 1 to 128
Up/down
Up
Up
Up
2
0
4
3
0
0
3
0
Yes
No
No
No
No
4.13 Analog-to-digital converter (ADC2)
STM8S007C8 value line products contain a 10-bit successive approximation A/D converter
(ADC2) with up to 10 multiplexed input channels and the following main features:
• Input voltage range: 0 to V
DDA
• Conversion time: 14 clock cycles
• Single and continuous modes
• External trigger input
• Trigger from TIM1 TRGO
• End of conversion (EOC) interrupt
The following communication interfaces are implemented:
• UART1: full feature UART, SPI master mode, SmartCard mode, IrDA mode, LIN2.1 master capability, single-wire mode
• UART3: full feature UART, LIN2.1 master/slave capability
• SPI: full and half-duplex, 10 Mbit/s
• I²C: up to 400 Kbit/s
DS8633 Rev 6
25
Product overview STM8S007C8
4.14.1 UART1
Main features
• 1 Mbit/s full duplex SCI
• SPI emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• LIN master mode
• Single wire half duplex mode
Asynchronous communication (UART mode)
• Full duplex communication - NRZ standard format (mark/space)
• Programmable transmit and receive baud rates up to 1 Mbit/s (f
CPU following any standard baud rate regardless of the input frequency
/16) and capable of
• Separate enable bits for transmitter and receiver
• Two receiver wakeup modes:
– Address bit (MSB)
– Idle line (interrupt)
• Transmission error detection with interrupt generation
• Parity control
Synchronous communication
• Full duplex synchronous transfers
• SPI master operation
• 8-bit data communication
• Maximum speed: 1 Mbit/s at 16 MHz (f
CPU
/16)
LIN master mode
• Emission: generates 13-bit synch. break frame
• Reception: detects 11-bit break frame
4.14.2 UART3
Main features
• 1 Mbit/s full duplex SCI
• LIN master capable
• High precision baud rate generator
DS8633 Rev 6
STM8S007C8 Product overview
Asynchronous communication (UART mode)
• Full duplex communication - NRZ standard format (mark/space)
• Programmable transmit and receive baud rates up to 1 Mbit/s (f
CPU following any standard baud rate regardless of the input frequency
/16) and capable of
• Separate enable bits for transmitter and receiver
• Two receiver wakeup modes:
– Address bit (MSB)
– Idle line (interrupt)
• Transmission error detection with interrupt generation
• Parity control
LIN master capability
• Emission: Generates 13-bit synch break frame
• Reception: Detects 11-bit break frame
LIN slave mode
• Autonomous header handling - one single interrupt per valid message header
• Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
• Synch delimiter checking
• 11-bit LIN synch break detection - break detection always active
• Parity check on the LIN identifier field
• LIN error management
• Hot plugging support
4.14.3 SPI
• Maximum speed: 10 Mbit/s (f
MASTER
/2) both for master and slave
• Full duplex synchronous transfers
• Simplex synchronous transfers on two lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• CRC calculation
• 1 byte Tx and Rx buffer
• Slave/master selection input pin
DS8633 Rev 6
25
Product overview
4.14.4 I
2
C
• I 2 C master features
– Clock generation
– Start and stop generation
• I 2 C slave features
– Programmable I 2 C address detection
– Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and general call
• Supports different communication speeds
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)
STM8S007C8
DS8633 Rev 6
STM8S007C8
5 Pinouts and pin descriptions
Figure 3. LQFP 48-pin pinout
Pinouts and pin descriptions
NRST
OSCIN/PA1
OSCOUT/PA2
V
SSIO_1
V
SS
VCAP
V
DD
V
DDIO_1
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/(HS) PA4
UART1_TX/(HS) PA5
UART1_CK/(HS) PA6
1
2
48 47 46 45 44 43 42 41 40 39 38 37
36
3
4
35
34
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23
33
32
31
30
29
28
27
26
24
25
PG1
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
V
DDIO_2
V
SSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
P C2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to V
DD
not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).
DS8633 Rev 6
25
Pinouts and pin descriptions STM8S007C8
Type
Input
Output
Table 4. Legend/abbreviations for STM8S007C8 pin description table
I = input, O = output, S = power supply
Reset state floating wpu = weak pull-up
Ext. interrupt = external interrupt
HS = high sink
Speed
O1 = Slow (up to 2 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
OD = open drain
PP = push pull
Bold X (pin state after internal reset release)
Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.
Table 5. STM8S007C8 pin description
Input Output
Pin name
Default alternate function
Alternate function after remap
[option bit]
1
2
3
NRST
PA1/OSCIN
PA2/OSCOUT
I/O X - Reset
I/O X X O1 X X Port A1
Resonator/ crystal in
I/O X X X O1 X X Port A2
Resonator/ crystal out
-
-
-
4 V
SSIO_1
5 V
SS
6 VCAP
S
S
-
-
-
-
-
-
-
-
-
-
-
-
- I/O ground
- Digital ground
7 V
DD
8 V
DDIO_1
S
S -
-
-
-
-
-
-
-
-
-
-
- Digital power supply
- I/O power supply
9 PA3/TIM2_CH3 I/O X X X O1 X X Port A3
Timer 2 - channel3
10
PA4/UART1_RX
(1)
S - 1.8 V regulator capacitor
I/O X X X HS O3 X X Port A4
UART1 receive
-
-
-
-
-
TIM3_CH1
[AFR1]
-
11 PA5/UART1_TX I/O X X X HS O3 X X Port A5
UART1 transmit
12 PA6/UART1_CK I/O X X X HS O3 X X Port A6
UART1 synchronous clock
-
-
DS8633 Rev 6
STM8S007C8 Pinouts and pin descriptions
Pin name
Table 5. STM8S007C8 pin description (continued)
Input Output
Default alternate function
Alternate function after remap
[option bit]
13
14 V
15
16
17
18
19
20
21
22
V
DDA
SSA
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
PB2/AIN2
PB1/AIN1
PB0/AIN0
S - Analog power supply
S - Analog ground
I/O X X X O1 X X Port B7
Analog input 7
I/O X X X O1 X X Port B6
Analog input 6
I/O X X X O1 X X Port B5
Analog input 5
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
O1 X
O1 X
O1 X
O1 X
O1 X
X
X
X
X
X
Port B4
Port B3
Port B2
Port B1
Port B0
Analog input 4
Analog input 3
Analog input 2
Analog input 1
Analog input 0
I/O X X X O1 X X Port E7 Analog input 8
I/O X X X O1 X X Port E6 Analog input 9
-
-
-
-
I
2
C_SDA
[AFR6]
I
2
C_SCL
[AFR6]
TIM1_ETR
[AFR5]
TIM1_
CH3N
[AFR5]
TIM1_
CH2N
[AFR5]
TIM1_
CH1N
[AFR5]
-
23 PE7/AIN8
24 PE6/AIN9
25 PE5/SPI_NSS I/O X X X O1 X X Port E5
SPI master/slave select
26 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1
Timer 1 - channel 1
27 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2
Timer 1- channel 2
28 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3
Timer 1 - channel 3
29 PC4/TIM1_CH4 I/O X X X HS O3 X X Port C4
Timer 1 - channel 4
30 PC5/SPI_SCK I/O X X X HS O3 X X Port C5 SPI clock
31 V
SSIO_2
32 V
DDIO_2
S - I/O ground
S - I/O power supply -
-
-
-
-
-
-
-
DS8633 Rev 6
25
Pinouts and pin descriptions STM8S007C8
Pin name
Table 5. STM8S007C8 pin description (continued)
Input Output
Default alternate function
Alternate function after remap
[option bit]
33 PC6/SPI_MOSI I/O X X X HS O3 X X Port C6
SPI master out/ slave in
34 PC7/SPI_MISO I/O X X X HS O3 X X Port C7
SPI master in/ slave out
35 PG0 I/O X X O1 X X Port G0
36 PG1 I/O X X O1 X X Port G1
-
-
37 PE3/TIM1_BKIN I/O X X X O1 X X Port E3
Timer 1 - break input
38 PE2/I
2
C_SDA
39 PE1/I
2
C_SCL
I/O X X O1 T
(2)
I/O X X O1 T
Port E2 I
2
C data
Port E1 I
2
C clock
40 PE0/CLK_CCO I/O X X X HS O3 X X Port E0
Configurable clock output
-
-
-
-
-
-
-
-
41 PD0/TIM3_CH2 I/O X X X HS O3 X X Port D0
Timer 3 - channel 2
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
42 PD1/SWIM
(3)
I/O X X X HS O4 X X Port D1
SWIM data interface
43 PD2/TIM3_CH1 I/O X X X HS O3 X X Port D2
Timer 3 - channel 1
44 PD3/TIM2_CH2 I/O X X X HS O3 X X Port D3
Timer 2 - channel 2
45
PD4/TIM2_CH1/B
EEP
I/O X X X HS O3 X X Port D4
Timer 2 - channel 1
46 PD5/ UART3_TX I/O X X X O1 X X Port D5
UART3 data transmit
47
PD6/
UART3_RX
I/O X X X O1 X X Port D6
UART3 data receive
48 PD7/TLI I/O X X X O1 X X Port D7
Top level interrupt
TIM2_CH3
[AFR1]
ADC_ETR
[AFR0]
BEEP output
[AFR7]
-
-
-
-
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
DD
are not implemented).
3. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
DS8633 Rev 6
STM8S007C8
Note:
Pinouts and pin descriptions
The slope control of true open drain pins cannot be programmed and by default is limited to
2 MHz.
As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to
Section 8: Option bytes . When the remapping option is active,
the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
DS8633 Rev 6
25
Memory and register map
6 Memory and register map
Figure 4. Memory map
0x00 0000
RAM
(6 Kbytes)
0x00 17FF
0x00 1800
1024 bytes stack
Reserved
0x00 3FFF
0x00 4000
128 bytes data EEPROM
0x00 407F
0x00 4080
0x00 47FF
0x00 4800
0x00 487F
0x00 4900
Reserved
Option bytes
Reserved
0x00 4FFF
0x00 5000
GPIO and peripheral registers
(see Table 8 and Table 9 )
0x00 57FF
0x00 5800
Reserved
0x00 5FFF
0x00 6000
2 Kbytes boot ROM
0x00 67FF
0x00 6800
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
CPU/SWIM/debug/ITC register (see Table 10
32 interrupt vectors
)
Flash program memory
(64 bytes)
0x01 7FFF
DS8633 Rev 6
STM8S007C8
MS19412V2
STM8S007C8 Memory and register map
Table 6 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 6. Flash, Data EEPROM and RAM boundary addresses
Memory area Size (byte) Start address End address
Flash program memory
RAM
64 K
6 K
0x00 8000
0x00 0000
0x01 7FFF
0x00 17FF
Data EEPROM 128 0x00 4000 0x00 407F
Address
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
Block
Table 7. I/O port hardware register map
Register label Register name
Port A
Port B
Port C
Port D
PA_ODR
PA_IDR
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D control register 2
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
DS8633 Rev 6
37
Memory and register map
Address
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
0x00 5023
0x00 5024
0x00 5025
0x00 5026
0x00 5027
0x00 5028
0x00 5029
0x00 502A
0x00 502B
0x00 502C
Table 7. I/O port hardware register map (continued)
Block Register label Register name
Port E
Port F
Port G
Port H
Port I
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
PI_DDR
PI_CR1
PI_CR2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E control register 2
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
Port F control register 2
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
Port G control register 2
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
Port H control register 2
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
Port I control register 2
STM8S007C8
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DS8633 Rev 6
STM8S007C8
Address
0x00 5050 to
0x00 5059
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
0x00 505F
0x00 5060 to
0x00 5061
0x00 5062
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 5063
0x00 5064
0x00 5065 to
0x00 509F
0x00 50A0
0x00 50A1
0x00 50A2 to
0x00 50B2
0x00 50B3
0x00 50B4 to
0x00 50BF
0x00 50C0
Memory and register map
Block
Flash
Flash
Flash
ITC
RST
CLK
CLK
Table 8. General hardware register map
Register label Register name
Reset status
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH _FPR
FLASH _NFPR
FLASH _IAPSR
Reserved area (10 byte)
Flash control register 1
Flash control register 2
Flash complementary control register 2
Flash protection register
Flash complementary protection register
Flash in-application programming status register
FLASH _PUKR
FLASH _DUKR
EXTI_CR1
EXTI_CR2
Reserved area (2 byte)
Flash Program memory unprotection register
Reserved area (1 byte)
Data EEPROM unprotection register
Reserved area (59 byte)
External interrupt control register 1
External interrupt control register 2
RST_SR
Reserved area (17 byte)
Reset status register
CLK_ICKR
CLK_ECKR
CLK_CMSR
CLK_SWR
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK_CCOR
CLK_PCKENR2
Reserved area (12 byte)
Internal clock control register
External clock control register
Reserved area (1 byte)
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
0x00
0x00
0x00
0x00
0xXX
(1)
0x01
0x00
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
0x00
0x00
0xFF
0x00
0xFF
0x00
DS8633 Rev 6
37
Address
0x00 50CC
0x00 50CD
0x00 50CE to
0x00 50D0
0x00 50D1
0x00 50D2
0x00 50D3 to
0x00 50DF
0x00 50E0
0x00 50E1
0x00 50E2
0x00 50E3 to
0x00 50EF
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
0x00 50F4 to
0x00 50FF
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
0x00 5208 to
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
Memory and register map STM8S007C8
Table 8. General hardware register map (continued)
Block
CLK
WWDG
IWDG
AWU
BEEP
SPI
I
2
C
Register label
CLK_HSITRIMR
CLK_SWIMCCR
Register name
HSI clock calibration trimming register
SWIM clock control register
Reset status
0x00
0bXXXX
XXX0
WWDG_CR
WWDG_WR
IWDG_KR
IWDG_PR
IWDG_RLR
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
SPI_CR1
SPI_CR2
SPI_ICR
SPI_SR
SPI_DR
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
I2C_CR1
I2C_CR2
I2C_FREQR
I2C_OARL
I2C_OARH
Reserved area (3 byte)
WWDG control register
WWDR window register
Reserved area (13 byte)
IWDG key register
IWDG prescaler register
IWDG reload register
Reserved area (13 byte)
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
Reserved area (12 byte)
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
SPI data register
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
Reserved area (8 byte)
I 2 C control register 1
I
2
C control register 2
I
2
C frequency register
I
2
C own address register low
I
2
C own address register high
Reserved
0x7F
0x7F
0xXX
(2)
0x00
0xFF
0x00
0x3F
0x00
0x1F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
DS8633 Rev 6
STM8S007C8
Address
0x00 5237
0x00 5238
0x00 5239
0x00 523A
0x00 523B to
0x00 523F
0x00 5240
0x00 5241
0x00 5242
0x00 5243
0x00 5244
0x00 5245
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E to
0x00 522F
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5246
0x00 5247
0x00 5248
0x00 5249
0x00 524A to
0x00 524F
Memory and register map
Table 8. General hardware register map (continued)
Block
I
2
C
UART1
UART3
Register label
I2C_DR
I2C_SR1
I2C_SR2
I2C_SR3
I2C_ITR
I2C_CCRL
I2C_CCRH
I2C_TRISER
UART3_CR6
Register name
I 2 C data register
I
2
C status register 1
I
2
C status register 2
I
2
C status register 3
I
2
C interrupt control register
I
2
C clock control register low
I 2 C clock control register high
I
2
C TRISE register
UART1_SR
UART1_DR
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
Reserved area (18 byte)
UART1 status register
UART1 data register
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
Reserved area (5 bytes)
UART3_SR
UART3_DR
UART3_BRR1
UART3_BRR2
UART3_CR1
UART3_CR2
UART3_CR3
UART3_CR4
UART3 status register
UART3 data register
UART3 baud rate register 1
UART3 baud rate register 2
UART3 control register 1
UART3 control register 2
UART3 control register 3
UART3 control register 4
Reserved
UART3 control register 6
Reserved area (6 bytes)
0x00
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
C0h
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
DS8633 Rev 6
37
Address
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
0x00 5270 to
0x00 52FF
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
Memory and register map
Table 8. General hardware register map (continued)
Block Register label Register name
TIM1
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1_OISR
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1 control register 1
TIM1 control register 2
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1 status register 2
TIM1 event generation register
TIM1 capture/compare mode register 1
TIM1 capture/compare mode register 2
TIM1 capture/compare mode register 3
TIM1 capture/compare mode register 4
TIM1 capture/compare enable register 1
TIM1 capture/compare enable register 2
TIM1 counter high
TIM1 counter low
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
TIM1 dead-time register
TIM1 output idle state register
Reserved area (147 byte)
STM8S007C8
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DS8633 Rev 6
STM8S007C8
Address
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315 to
0x00 531F
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
0x00 530C
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5326
0x00 5327
0x00 5328
0x00 5329
0x00 532A
Memory and register map
Table 8. General hardware register map (continued)
Block Register label Register name
TIM2
TIM3
TIM2_CR1
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2_EGR
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM3_CR1
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3_EGR
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM2 control register 1
TIM2 interrupt enable register
TIM2 status register 1
TIM2 status register 2
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register 1
TIM2 capture/compare enable register 2
TIM2 counter high
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
TIM2 capture/compare register 3 low
Reserved area (11 byte)
TIM3 control register 1
TIM3 interrupt enable register
TIM3 status register 1
TIM3 status register 2
TIM3 event generation register
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM3 capture/compare enable register 1
TIM3 counter high
TIM3 counter low
TIM3 prescaler register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
DS8633 Rev 6
37
Memory and register map
Table 8. General hardware register map (continued)
Block Register label Register name Address
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 532F
0x00 5330
0x00 5331 to
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347 to
0x00 53FF
TIM3
TIM4
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
ADC2
0x00 5408 to
0x00 57FF
1. Depends on the previous reset source.
2. Write only register.
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM4_CR1
TIM4_IER
TIM4_SR
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC_TDRH
ADC_TDRL
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
Reserved area (15 bytes)
TIM4 control register 1
TIM4 interrupt enable register
TIM4 status register
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
Reserved area (185 byte)
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
ADC data register low
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
Reserved area (1016 byte)
STM8S007C8
0x00
0x00
0x00
0x00
0xXX
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
Reset status
0xFF
0xFF
0x00
0x00
0x00
0x00
DS8633 Rev 6
STM8S007C8 Memory and register map
Table 9. CPU/SWIM/debug module/interrupt controller registers
Block Register Label Register Name Address
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
0x00 7F0B to
0x00 7F5F
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
0x00 7F78 to
0x00 7F79
0x00 7F80
0x00 7F81 to
0x00 7F8F
CPU
(1)
CPU
ITC
SWIM
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
A
PCE
PCH
PCL
XH
XL
YH
YL
SPH
SPL
CCR
SWIM_CSR
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
Stack pointer low
Condition code register
Reserved area (85 byte)
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
Reserved area (2 byte)
SWIM control status register
Reserved area (15 byte)
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Reset
Status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x17
(2)
0xFF
0x28
DS8633 Rev 6
37
Memory and register map STM8S007C8
Address
Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)
Block Register Label Register Name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
0x00 7F9B to
0x00 7F9F
DM
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
1. Accessible by debug module only
2. Product dependent value, see
.
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
Reserved area (5 byte)
Reset
Status
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DS8633 Rev 6
STM8S007C8
7 Interrupt vector mapping
Interrupt vector mapping
11
20
21
22
23
24
12
13
14
15
16
17
18
19
IRQ no.
3
4
1
2
5
-
-
0
6
7
8
9
10
Source block
Table 10. Interrupt mapping
Description
Wakeup from
Halt mode
Wakeup from
Active-halt mode
RESET Reset
TRAP
TLI
Software interrupt
External top level interrupt
AWU
CLK
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
-
-
SPI
TIM1
TIM1
TIM2
TIM2
TIM3
TIM3
Auto wake up from halt
Clock controller
Port A external interrupts
Port B external interrupts
Port C external interrupts
TIM2 capture/compare
Update/overflow
Capture/compare
Yes
-
-
-
-
-
-
-
Yes
(1)
Yes
Port D external interrupts
Port E external interrupts
Yes
Yes
Yes
Reserved
Reserved
End of transfer
TIM1 update/overflow/underflow/ trigger/break
TIM1 capture/compare
TIM2 update /overflow
Yes
-
-
-
UART1
UART1
I
2
C
UART3
UART3
ADC2
Tx complete
Receive register DATA FULL
I
2
C interrupt
Tx complete
Receive register DATA FULL
ADC2 end of conversion
TIM4 TIM4 update/overflow
Flash EOP/WR_PG_DIS
-
-
-
-
-
Yes
-
-
Yes
-
Yes
-
-
Yes
-
Yes
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
-
-
Yes
Reserved
1. Except PA1
Vector address
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 806C to
0x00 807C
DS8633 Rev 6
37
Option bytes STM8S007C8
Addr.
0x4807
Clock option
0x4808
0x4809
0x480A
0x480B
0x480C
HSE clock startup
Reserved
0x480D
0x480E
Flash wait states
0x487E
0x487F
Bootloader
Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in
Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.
Option name
Option byte no.
7
Table 11. Option bytes
Option bits
6 5 4 3 2 1 0
Factory default setting
0x4800
0x4801
0x4802
0x4803
0x4804
0x4805
0x4806
Read-out protection
(ROP)
User boot code
(UBC)
OPT1
NOPT1
Alternate function remapping
(AFR)
OPT0
OPT2
NOPT2
OPT3
Watchdog option
NOPT3
OPT4
NOPT4
OPT5
NOPT5
OPT6
NOPT6
OPT7
NOPT7
OPTBL
NOPTBL
ROP[7:0]
AFR7
NAFR7
AFR6
NAFR6
AFR5
NAFR5
Reserved
Reserved
Reserved
Reserved
UBC[7:0]
NUBC[7:0]
Reserve d
AFR3
NAFR4 NAFR3
HSECNT[7:0]
NHSECNT[7:0]
Reserved
Reserved
LSI
_EN
NLSI
_EN
EXT
CLK
NEXT
CLK
AFR2 AFR1 AFR0
NAFR2 NAFR1 NAFR0
IWDG
_HW
NIWDG
_HW
CKAWU
SEL
NCKAW
USEL
WWDG
_HW
NWWDG
_HW
WWDG
_HALT
NWWDG
_HALT
PRS
C1
NPR
SC1
PRS
C0
NPR
SC0
Reserved
Reserved
Wait state
Nwait state
BL[7:0]
NBL[7:0]
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
DS8633 Rev 6
STM8S007C8 Option bytes
Option byte no.
OPT0
OPT1
OPT2
Table 12. Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Pages 0 to 1 defined as UBC, memory write-protected
0x02: Pages 0 to 3 defined as UBC, memory write-protected
0x03: Pages 0 to 4 defined as UBC, memory write-protected
...
0xFE: Pages 0 to 255 defined as UBC, memory write-protected
0xFF: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM write protection for more details.
AFR7 Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6 Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I 2 C_SDA, port B4 alternate function =
I
2
C_SCL
AFR5 Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N
AFR4 Alternate function remapping option 4
Reserved
AFR3 Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2 Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1 Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3
AFR0 Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
DS8633 Rev 6
41
Option bytes STM8S007C8
Option byte no.
OPT3
OPT4
OPT5
OPT6
OPT7
Table 12. Option byte description (continued)
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time.
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
Reserved
WAITSTATE Wait state configuration
This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory.
1 wait state is required if f
CPU
0: No wait state
1: 1 wait state
> 16 MHz.
DS8633 Rev 6
STM8S007C8 Option bytes
Option byte no.
OPTBL
Table 12. Option byte description (continued)
Description
BL[7:0] Bootloader option byte
For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details.
For STM8L products, the bootloader option bytes are on addresses
0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the
UM0560 (STM8L/S bootloader manual) for more details.
DS8633 Rev 6
41
Electrical characteristics STM8S007C8
9.1.1
Unless otherwise specified, all voltages are referred to V
SS
.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
Amax
(given by
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ ).
Unless otherwise specified, typical data are based on T
A only as design guidelines and are not tested.
= 25 °C, V
DD
= 5 V. They are given
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ )
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
For typical current consumption measurements, V
DD
together in the configuration shown in Figure 5
.
, V
DDIO
and V
DDA
are connected
Figure 5. Supply current measurement conditions
5 V or 3.3 V
A V
DD
V
DDA
V
DDIO
V
SS
V
SSA
V
SSIO
DS8633 Rev 6
STM8S007C8 Electrical characteristics
The loading conditions used for pin parameter measurement are shown in
.
Figure 6. Pin loading conditions
STM8 pin
50 pF
9.1.6 Pin input voltage
The input voltage measurement on a pin of the device is described in
Figure 7. Pin input voltage
STM8 pin
V
IN
9.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 13: Voltage characteristics
,
Table 14: Current characteristics
and
Table 15: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device’s reliability.
The device’s mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
Symbol
Table 13. Voltage characteristics
Ratings
V
DDx
V
- V
IN
SS
Supply voltage (including V
DDA and
V
DDIO
) (1)
Input voltage on true open drain pins (PE1, PE2)
(2)
Input voltage on any other pin
|V
DDx
- V
DD
| Variations between different power pins
|V
SSx
- V
SS
| Variations between all the different ground pins
V
ESD
Electrostatic discharge voltage
Min Max
-0.3
6.5
V
SS
- 0.3
6.5
V
SS
- 0.3
V
DD
+ 0.3
50
50
see Absolute maximum ratings (electrical sensitivity) on page 81
Unit
V mV
-
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
1. All power (V , V external power supply
, V
DDA
) and ground (V
SS
, V
SSIO
, V
SSA
) pins must always be connected to the
2. I
INJ(PIN)
must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I injection is induced by V
IN
>V
DD
IN
maximum is respected. If V
IN
while a negative injection is induced by V
IN
IN
<V
SS
maximum
value. A positive
. For true open-drain pads,
maximum must always be respected
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Symbol
Table 14. Current characteristics
Ratings Max.
(1)
Unit
I
I
VDD
VSS
I
IO
Total current into V
DD power lines (source)
(2)
Total current out of V
SS ground lines (sink)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
60
60
20
20
Σ I
IO
Total output current sourced (sum of all I/O and control pins) for devices with two V
DDIO
pins
(3)
Total output current sourced (sum of all I/O and control pins) for devices with one V
DDIO
pin
Total output current sunk (sum of all I/O and control pins) for devices with two V
SSIO
Total output current sunk (sum of all I/O and control pins) for devices with one V
SSIO
pin
Injected current on NRST pin
200
100
160
80
±4 mA
I
INJ(PIN)
(4)(5)
Injected current on OSCIN pin
Injected current on any other pin
(6)
Total injected current (sum of all I/O and control pins) (6)
±4
±4
Σ I
±20
1. Guaranteed by characterization results.
2. All power (V , V external supply.
DDIO
, V
DDA
) and ground (V
SS
, V
SSIO
, V
SSA
) pins must always be connected to the
3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the V
DDIO
/V
SSIO
pins.
4. I
INJ(PIN)
must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I injection is induced by V >V
DD
IN
maximum is respected. If V
IN
while a negative injection is induced by V there is no positive injection current, and the corresponding V
IN
<V
SS
maximum
value. A positive
IN
. For true open-drain pads,
maximum must always be respected
.
6. When several inputs are submitted to a current injection, the maximum with Σ I
INJ(PIN)
Σ I
INJ(PIN)
maximum current injection on four I/O port pins of the device.
is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization
Symbol
T
STG
T
J
Table 15. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Value
-65 to 150
150
Unit
°C
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
The device must be used in operating conditions that respect the parameters in
addition, full account must be taken of all physical capacitor characteristics and tolerances.
Symbol
Table 16. General operating conditions
Parameter Conditions Min Max Unit f
CPU
Internal CPU clock frequency
-
-
-
V
DD/
V
DD_IO
Standard operating voltage
C
EXT
: capacitance of external capacitor
V
CAP
(1)
ESR of external capacitor
ESL of external capacitor
At 1 MHz
(2)
P
D
(3)
Power dissipation at
T
A
= 85° C for suffix 6
-
48-pin devices, with output on eight standard ports, two high sink ports and two open drain ports simultaneously
(4)
0
0
2.95
24
16
5.5
470 3300
-
-
-
0.3
15
443
MHz
V nF ohm nH mW
T
A
Ambient temperature for 6 suffix version
Maximum power dissipation -40 85
°C
T
J
Junction temperature range -40 105
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter specifications must be respected for the full application range.
2. This frequency of 1 MHz as a condition for V
CAP
parameters is given by the design of the internal regulator.
3. To calculate P
Dmax
(T
A
), use the formula P
) with the value for T
Table 50: Thermal characteristics
.
= (T
Jmax
Jmax
- T
A
)/ Θ
(see
given in
above and the value for
Θ
JA given in
4. Refer to Section 10.2: Thermal characteristics on page 87 for the calculation method.
DS8633 Rev 6
STM8S007C8 f
CP U
[MHz]
Figure 8. f
CPUmax
versus V
DD
Electrical characteristics
24
Functionality not guaranteed in this area
16
12
Functionality guaranteed with 1 wait state
Functionality guaranteed with 0 wait state
8
4
0
2.95
4.0
5.0
Supply voltage [ V]
5. 5
MS19413V1
Symbol t
VDD t
TEMP
V
IT+
V
IT-
V
HYS(BOR)
Table 17. Operating conditions at power-up/power-down
Parameter Conditions Min Typ
V
DD
rise time rate
V
DD
fall time rate
Reset release delay
Power-on reset threshold
(2)
Brown-out reset threshold
Brown-out reset hysteresis
V
DD
rising
-
-
-
-
2
(1)
2
2.65
2.58
-
-
-
-
2.8
2.73
70
Max Unit
∞
∞
1.7
2.95
2.88
-
µs/V ms mV
1. Guaranteed by design.
2. If V is below 2.95 V, the code execution is guaranteed above the V is kept. The EEPROM programming sequence must not be initiated.
IT-
and
VIT+
thresholds. RAM content
V
V
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
9.3.2
Stabilization for the main regulator is achieved connecting an external capacitor C
EXT
V
CAP
pin. C
EXT to less than 15 nH.
to the
is specified in
Table 16 . Care should be taken to limit the series inductance
Figure 9. External capacitor C
EXT
C
ESL
ESR
RLeak
MSv36488V1
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
Supply current characteristics
The current consumption is measured as described in
Section 9.1.6: Pin input voltage
.
Total current consumption in run mode
The MCU is placed under the following conditions:
• All I/O pins in input mode with a static value at V
DD
or V
SS
(no load)
• All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except if explicitly mentioned.
• When the MCU is clocked at 24 MHz, T
A
≤ 85 °C and the WAITSTATE option bit is set.
Subject to general operating conditions for V
DD
and T
A
.
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Table 18. Total current consumption with code execution in run mode at V
DD
= 5 V
Symbol Parameter Conditions Typ Max Unit
f
CPU
= f
MASTER
= 24 MHz
HSE crystal osc. (24 MHz) 4.4
-
HSE user ext. clock (24 MHz) 3.7
7.3
(1)
Supply current in run mode, code executed from RAM
f
f
CPU
CPU
= f
= f
MASTER
MASTER
= 16 MHz
/128 = 125 kHz
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
3.3
2.7
-
5.8
HSI RC osc. (16 MHz) 2.5
3.4
HSE user ext. clock (16 MHz) 1.2
4.1
HSI RC osc. (16 MHz) 1.0
1.3
f
CPU
= f
MASTER
15.625 kHz
/128 =
f
CPU
= f
MASTER
= 128 kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.55
0.45
-
-
I
DD(RUN)
Supply current in run mode, code executed from Flash
f
CPU
= f
MASTER
= 24 MHz
HSE crystal osc. (24 MHz) 11.4
-
HSE user ext. clock (24 MHz) 10.8
f
CPU
= f
MASTER
= 16 MHz
HSE crystal osc. (16 MHz) 9.0
-
HSE user ext. clock (16 MHz) 8.2
15.2
HSI RC osc.(16 MHz)
HSI RC osc. (16 MHz/8) (2)
8.1
13.2
1.5
f
CPU
= f
MASTER
= 2 MHz
f
CPU
= f
MASTER
/128 = 125 kHz HSI RC osc. (16 MHz)
f
CPU
= f
MASTER
15.625 kHz
/128 =
HSI RC osc. (16 MHz/8)
1.1
0.6
-
-
0.55
f
CPU
= f
MASTER
= 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
LSI RC osc. (128 kHz) mA
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Table 19. Total current consumption with code execution in run mode at V
DD
= 3.3 V
Symbol Parameter Conditions Typ Max (1) Unit
Supply current in run mode, code executed from RAM
f
f
f
CPU
CPU
CPU
= f
= f
= f
MASTER
MASTER
MASTER
= 24 MHz
= 16 MHz
/128 = 125 kHz
HSE crystal osc. (24 MHz) 4.0
HSE user ext. clock (24 MHz) 3.7
HSE crystal osc. (16 MHz) 2.9
HSE user ext. clock (16 MHz) 2.7
HSI RC osc. (16 MHz) 2.5
HSE user ext. clock (16 MHz) 1.2
HSI RC osc. (16 MHz) 1.0
I
DD(RUN)
f
CPU
= f
MASTER
15.625 kHz
/128 =
f
CPU
= f
MASTER
= 128 kHz
f
CPU
= f
MASTER
= 24 MHz
HSI RC osc. (16MHz/8) 0.55
-
LSI RC osc. (128 kHz) 0.45
-
HSE crystal osc. (24 MHz) 11.0
-
HSE user ext. clock (24 MHz) 10.8
18.0
Supply current in run mode, code executed from Flash
HSE crystal osc. (16 MHz) 8.4
f
CPU
= f
MASTER
= 16 MHz HSE user ext. clock (16 MHz)
f
CPU
= f
MASTER
= 2 MHz
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
f
CPU
= f
MASTER
/128 = 125 kHz HSI RC osc. (16 MHz)
f
CPU
= f
MASTER
15.625 kHz
/128 =
HSI RC osc. (16 MHz/8)
(2)
8.2
8.1
1.5
1.1
0.6
0.55
f
CPU
= f
MASTER
= 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration.
LSI RC osc. (128 kHz)
-
15.2
13.2
-
-
-
-
3.4
4.1
1.3
-
7.3
-
5.8
mA
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Total current consumption in wait mode
Table 20. Total current consumption in wait mode at V
DD
= 5 V
Symbol Parameter Conditions Typ Max
(1)
Unit
f
CPU
= f
MASTER
= 24 MHz
HSE crystal osc. (24 MHz) 2.4
HSE user ext. clock (24 MHz) 1.8
HSE crystal osc. (16 MHz) 2.0
I
DD(WFI)
Supply current in wait mode
f
CPU
= f
MASTER
= 16 MHz HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
f
CPU
= f
MASTER
/128 = 125 kHz HSI RC osc. (16 MHz)
f
CPU
= f
MASTER
/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
(2)
f
CPU
= f
MASTER
= 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
LSI RC osc. (128 kHz)
1.4
1.2
1.0
0.55
0.5
4.4
1.6
-
-
4.7
-
-
mA
Table 21. Total current consumption in wait mode at V
DD
= 3.3 V
Symbol Parameter Conditions Typ Max
(1)
I
DD(WFI)
Supply current in wait mode
f
f
CPU
CPU
= f
= f
MASTER
MASTER
= 24 MHz
= 16 MHz
HSE crystal osc. (24 MHz) 2.0
HSE user ext. clock (24 MHz) 1.8
HSE crystal osc. (16 MHz) 1.6
HSE user ext. clock (16 MHz) 1.4
HSI RC osc. (16 MHz) 1.2
1.0
f
CPU
= f
MASTER
/128 = 125 kHz HSI RC osc. (16 MHz)
f
CPU
= f
MASTER
15.625 kHz
/128 =
HSI RC osc. (16 MHz/8)
(2)
f
CPU
= f
MASTER
15.625 kHz
/128 =
LSI RC osc. (128 kHz)
0.55
0.5
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
-
4.7
-
4.4
1.6
-
-
-
Unit mA
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Total current consumption in active halt mode
Table 22. Total current consumption in active halt mode at V
DD
= 5 V, T
A
-40 to 85° C
Conditions
Typ Max
(1)
Symbol Parameter Main voltage regulator
(MVR)
(2)
Flash mode
(3)
Clock source
I
DD(AH)
Supply current in active halt mode
On
Off
Operating mode
HSE crystal oscillator
(16 MHz)
LSI RC oscillator
(128 kHz)
Power-down mode
HSE crystal oscillator
(16 MHz)
LSI RC oscillator
(128 kHz)
Operating mode
Power-down mode
LSI RC oscillator
(128 kHz)
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
1000
200
940
140
68
11
260
-
-
-
-
45
Unit
µA
Table 23. Total current consumption in active halt mode at V
DD
= 3.3 V
Conditions
Symbol Parameter Main voltage regulator
(MVR)
(2)
Flash mode
(3)
Clock source
Operating mode
On
I
DD(AH)
Supply current in active halt mode
Power-down mode
Off
Operating mode
Power-down mode
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
HSE crystal osc. (16 MHz)
LSI RC osc. (128 kHz)
HSE crystal osc. (16 MHz)
LSI RC osc. (128 kHz)
LSI RC osc. (128 kHz)
Typ
(1)
600
200
540
140
66
9
Unit
µA
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Total current consumption in halt mode
Symbol
Table 24. Total current consumption in halt mode at V
DD
= 5 V, T
A
-40 to 85° C
Parameter Conditions Typ Max
I
DD(H)
Supply current in halt mode
Flash in operating mode, HSI clock after wakeup
Flash in power-down mode, HSI clock after wakeup
63.5
6.5
-
35
Unit
µA
Symbol
I
DD(H)
Table 25. Total current consumption in halt mode at V
DD
= 3.3 V
Parameter Conditions Typ
Supply current in halt mode
Flash in operating mode, HSI clock after wakeup
Flash in power-down mode, HSI clock after wakeup
61.5
4.5
Unit
µA
Low-power mode wakeup times
Symbol Parameter
Table 26. Wakeup times
Conditions t t t
WU(WFI)
WU(AH)
WU(H)
Wakeup time from wait mode to run mode
Wakeup time active halt mode to run mode.
(3)
f
CPU
= f
MASTER
= 16 MHz.
MVR voltage regulator on
(4)
Flash in operating mode
(5)
Flash in power-down mode
HSI (after wakeup)
Wakeup time from halt mode to run mode
MVR voltage
Flash in operating mode
Flash in power-down mode
1. Data guaranteed by design.
2. t
WU(WFI)
= 2 x 1/f master
+ 7 x 1/f
CPU
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
Typ Max
(1)
Unit
-
(2)
0.56
-
1
(6)
3
48
50
52
54 -
-
-
-
-
µs
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Total current consumption and timing in forced reset state
Symbol
I
DD(R)
Table 27. Total current consumption and timing in forced reset state
Parameter Conditions Typ Max
(1)
Unit
Supply current in reset state
V
DD
= 5 V
V
DD
= 3.3 V
1.6
0.8
-
mA t
RESETBL
Reset release to bootloader vector fetch
1. Data guaranteed by design, not tested in production.
150 µs
Current consumption of on-chip peripherals
Subject to general operating conditions for V
DD
and T
A
.
HSI internal RC/f
CPU
= f
MASTER
= 16 MHz.
Symbol
Table 28. Peripheral current consumption
Parameter Typ.
Unit
I
DD(TIM1)
I
DD(TIM2)
I
DD(TIM3)
I
DD(TIM4)
I
DD(UART1)
I
DD(UART3)
I
DD(SPI)
I
DD(I2C)
I
DD(ADC2)
TIM1 supply current
(1)
ADC2 supply current when converting
(3)
220
100
25
UART1 supply current
(2)
UART3 supply current
I 2
90
110
40
50
1000
µA
1. Data based on a differential I
DD
measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential I tested in production.
DD
measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
3. Data based on a differential I
DD
measurement between reset configuration and continuous A/D conversions. Not tested in production.
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Current consumption curves
The following figures show the typical current consumption measured with code executing in
RAM.
Figure 10. Typ. I
DD(RUN)
vs V
DD
, HSI RC osc, f
CPU
= 16 MHz
25ºC
85ºC
4
3.5
3
2.5
2
1.5
1
0.5
0
2.5
3 3.5
4 4.5
V
DD
[V]
5 5.5
6 ai18796V2
2.5
Figure 11. Typ. I
DD(WFI)
vs V
DD
, HSI RC osc, f
CPU
= 16 MHz
25ºC
85ºC
2
1.5
1
0.5
0
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6 ai18797V2
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
HSE user external clock
Subject to general operating conditions for V
DD
and T
A
.
Symbol
Table 29. HSE user external clock characteristics
Parameter Conditions f
V
HSE_ext
HSEH
(1)
User external clock source frequency
OSCIN input pin high level voltage
V
HSEL
OSCIN input pin low level voltage
I
LEAK_HSE
OSCIN input leakage current
1. Guaranteed by characterization results.
-
V
SS
< V
IN
< V
DD
Min
V
0
0.7 x V
DD
SS
-1
Typ
-
-
-
-
Max
24
V
DD
+ 0.3 V
0.3 x V
DD
+1
Unit
MHz
V
µA
Figure 12. HSE external clock source
VHSEH
VHSEL
OSCIN fHSE
STM8
MS36489V2
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Symbol
Table 30. HSE oscillator characteristics
Parameter Conditions Min Typ Max Unit f
HSE
R
F
C (1)
External high speed oscillator frequency
Feedback resistor
Recommended load capacitance (2)
-
-
-
1
-
-
-
220
-
24
-
20
MHz k Ω pF
I
DD(HSE)
HSE oscillator power consumption f
C = 20 pF,
OSC
= 24 MHz f
C = 10 pF,
OSC
= 24 MHz
-
-
-
-
-
6 (startup)
2 (stabilized)
6 (startup)
(3)
1.5 (stabilized)
mA g m t
SU(HSE)
(4)
Oscillator transconductance
Startup time V
DD
is stabilized
5
-
-
1 -
mA/V ms
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R
Refer to crystal manufacturer for more details m
value.
3. Guaranteed by characterization results.
4. t
SU(HSE)
is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 13. HSE oscillator circuit diagram
Rm
Lm
C
O
Cm
Resonator
C
L1
OSCIN
R
F gm f
HSE
to core
Consumption control
Resonator
OSCOUT
C
L2
STM8
MS36490V3
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
HSE oscillator critical g m
formula g mcrit
= ( 2 × Π × f
HSE
) 2 × R m
( )
2
R
L
C m m m
: Notional resistance (see crystal specification)
: Notional inductance (see crystal specification)
: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
C
L1
=C
L2
=C: Grounded external capacitance g m
>> g mcrit
9.3.4 Internal clock sources and timing characteristics
Subject to general operating conditions for V
DD
and T
A
.
High speed internal RC oscillator (HSI)
Symbol
Table 31. HSI oscillator characteristics
Parameter Conditions Min
f
HSI
ACC
HSI t su(HSI)
I
DD(HSI)
Frequency -
Accuracy of HSI oscillator
Trimmed by the
CLK_HSITRIMR register for given V
DD
and T
A conditions
Accuracy of HSI oscillator
(factory calibrated)
V
DD
= 5 V,
-40°C
≤
T
A
≤
85° C
HSI oscillator wakeup time including calibration
-
HSI oscillator power consumption
-
1. Guaranteed by design.
2. Guaranteed by characterization results.
-5
-
-
Typ
16
-
-
-
Max
-
1.0
5
1.0
(1)
170 250
(2)
Unit
MHz
%
µs
µA
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Figure 14. Typical HSI frequency variation vs V
DD
at 3 temperatures
3%
-40ºC
25ºC
85ºC
2%
1%
0%
-1%
-2%
-3%
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6 ai15067c
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V
DD
and T
A
.
Symbol
Table 32. LSI oscillator characteristics
Parameter Conditions f
LSI t su(LSI)
I
DD(LSI)
Frequency -
LSI oscillator wakeup time
LSI oscillator power consumption
1. Guaranteed by design.
-
-
Min
-
-
-
Typ
128
-
5
Figure 15. Typical LSI frequency variation vs V
DD
@ 25 °C
Max
-
7
(1)
-
Unit kHz
µs
µA
3%
2%
1%
0%
-1%
-2%
-3%
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6 ai15070V2
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
RAM and hardware registers
Table 33. RAM and hardware registers
Symbol Parameter Conditions Min Unit
V
RM
Data retention mode
(1)
Halt mode (or reset) V
IT-max
(2)
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design.
2. Refer to Table 17 on page 47
for the value of V
IT-max
.
V
Flash program memory and data EEPROM
General conditions: T
A
= -40 to 85 °C.
Symbol
Table 34. Flash program memory and data EEPROM
Parameter Conditions Min
(1)
Typ Max Unit t t t
V
N
I
DD prog erase
RW
RET
DD
Operating voltage
(all modes, execution/write/erase)
Standard programming time (including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
Fast programming time for 1 block
(128 bytes)
Erase time for 1 block (128 bytes)
Erase/write cycles
(2)
(program memory)
(data memory)
Data retention (program memory) after 100 erase/write cycles at
T
A
= 85 °C
Data retention (data memory) after
10 k erase/write cycles at T
A
= 85 °C
Data retention (data memory) after
100 k erase/write cycles at T
A
= 85 °C
Supply current (Flash programming or erasing for 1 to 128 bytes) f
CPU
T
T
T
A
≤
=
RET
RET
= 55° C
= 85° C
-
-
-
-
85 °C
2.95
-
-
-
100
100 k
20
20
1.0
-
-
6.0
3.0
3.0
-
-
-
-
-
2.0
5.5
6.6
3.3
3.3
-
-
-
-
-
-
1. Guaranteed by characterization results.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
V ms ms ms cycles years mA
DS8633 Rev 6
STM8S007C8 Electrical characteristics
9.3.6 I/O port pin characteristics
General characteristics
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.
Symbol Parameter
Table 35. I/O static characteristics
Conditions Min Typ Max Unit
V
IL
V
IH
V hys
R pu t
R
, t
F
Input low level voltage
Input high level voltage
Hysteresis
(1)
Pull-up resistor
Rise and fall time
(10% - 90%)
V
DD
= 5 V
V
DD
= 5 V, V
IN
= V
SS
Fast I/Os
Load = 50 pF
Standard and high sink I/Os
Load = 50 pF
-0.3
0.7 x V
DD
-
30
-
-
-
0.3 x V
DD
V
DD
+ 0.3 V
700 -
55 80
-
-
I
I
I lkg lkg ana lkg(inj)
Input leakage current, analog and digital
Analog input leakage current
Leakage current in adjacent I/O
V
SS
V
SS
≤
IN
≤
V
IN
≤
V
DD
≤
V
DD
Injection current ±4 mA -
-
-
-
-
-
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results.
2. Data guaranteed by design.
3. Guaranteed by characterization results.
20
(2)
V
V mV k Ω ns
125
±1
±250
(3)
±1
µA nA
µA
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Figure 16. Typical V
IL
and V
IH
vs V
DD
@ 3 temperatures
6
5
4
3
2
1
0
2.5
-40ºC
25ºC
85ºC
3 3.5
4
V
DD
[V]
4.5
5 5.5
6 ai18798V2
50
45
Figure 17. Typical pull-up resistance vs V
DD
@ 3 temperatures
60
-40ºC
25ºC
85ºC
55
40
35
30
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6 ai18799V2
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Figure 18. Typical pull-up current vs V
DD
@ 3 temperatures
140
120
100
80
60
40
20
0
0 1 2 3
V
DD
[V]
4 5
-40ºC
25ºC
85ºC
6 ai15068c
1. The pull-up is a pure resistor (slope goes through 0).
Symbol
Table 36. Output driving current (standard ports)
Parameter Conditions
V
V
OL
OH
Output low level with 8 pins sunk
Output low level with 4 pins sunk
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 4 mA, V
DD
= 3.3 V
Output high level with 8 pins sourced I
IO
= 10 mA, V
DD
= 5 V
Output high level with 4 pins sourced I
IO
= 4 mA, V
DD
= 3.3 V
1. Guaranteed by characterization results.
Min
-
-
2.8
2.1
Max
-
-
2
1
(1)
Unit
V
V
Symbol
V
OL
Table 37. Output driving current (true open drain ports)
Parameter Conditions Max
Output low level with 2 pins sunk
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 3.3 V
I
IO
= 20 mA, V
DD
= 5 V
1
1.5
(1)
1. Guaranteed by characterization results.
Unit
V
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Symbol
Table 38. Output driving current (high sink ports)
Parameter
V
V
OL
OH
Output low level with 8 pins sunk
Output low level with 4 pins sunk
Output low level with 4 pins sunk
Output high level with 8 pins sourced
Output high level with 4 pins sourced
Output high level with 4 pins sourced
1. Guaranteed by characterization results.
Conditions
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 3.3 V
I
IO
= 20 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 3.3 V
I
IO
= 20 mA, V
DD
= 5 V
Min
-
-
-
4.0
Max
0.8
1.0
(1)
-
-
-
Unit
V
Typical output level curves
show typical output level curves measured with output on a single pin.
Figure 19. Typ. V
OL
@ V
DD
= 5 V (standard ports)
1.5
1.25
-40ºC
25ºC
85ºC
1
0.75
0.5
0.25
0
0 2 4 6
I
OL
[mA]
8 10 12
MS19400V2
DS8633 Rev 6
STM8S007C8
1.5
1.25
1
0.75
0.5
0.25
0
0
Electrical characteristics
Figure 20. Typ. V
OL
@ V
DD
= 3.3 V (standard ports)
-40ºC
25ºC
85ºC
1 2 3
I
OL
[mA]
4 5 6 7
MS19401V2
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
Figure 21. Typ. V
OL
@ V
DD
= 5 V (true open drain ports)
-40ºC
25ºC
85ºC
5 10
I
OL
[mA]
15 20 25
MS19402V2
DS8633 Rev 6
82
Electrical characteristics
Figure 22. Typ. V
OL
@ V
DD
= 3.3 V (true open drain ports)
STM8S007C8
-40ºC
25ºC
85ºC
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0 2 4 6
I
OL
[mA]
8 10 12 14
MS19403V2
1.5
1.25
1
0.75
0.5
0.25
0
0
Figure 23. Typ. V
OL
@ V
DD
= 5 V (high sink ports)
-40ºC
25ºC
85ºC
5 10
I
OL
[mA]
15 20 25
MS19404V2
DS8633 Rev 6
STM8S007C8
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
Electrical characteristics
1.5
1.25
Figure 24. Typ. V
OL
@ V
DD
= 3.3 V (high sink ports)
-40ºC
25ºC
85ºC
1
0.75
0.5
0.25
0
0 2 4 6
I
OL
[mA]
8 10 12 14
MS19405V2
Figure 25. Typ. V
DD -
V
OH
@ V
DD
= 5 V (standard ports)
-40ºC
25ºC
85ºC
2 4 6
I
OL
[mA]
8 10 12
MS19406V2
DS8633 Rev 6
82
Electrical characteristics
Figure 26. Typ. V
DD -
V
OH
@ V
DD
= 3.3 V (standard ports)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
-40ºC
25ºC
85ºC
2 4 6
I OL [mA]
8 10 12
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
Figure 27. Typ. V
DD -
V
OH
@ V
DD
= 5 V (high sink ports)
-40ºC
25ºC
85ºC
2 4 6
I
OH
[mA]
8 10 12
STM8S007C8
MS19407V2
MS19408V3
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Figure 28. Typ. V
DD -
V
OH
@ V
DD
= 3.3 V (high sink ports)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0 2
-40ºC
25ºC
85ºC
4 6
I
OH
[mA]
8 10 12
MS19409V2
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified.
Table 39. NRST pin characteristics
Symbol Parameter Conditions
V
IL(NRST)
V
IH(NRST)
V
OL(NRST)
R
PU(NRST) t
IFP(NRST) t
INFP(NRST) t
OP(NRST)
NRST input low level voltage
NRST pull-up resistor
(2)
NRST input filtered pulse (3)
NRST Input not filtered pulse
NRST output pulse
(1)
I
OL
= 2 mA
-
-
-
-
-
-
1. Guaranteed by characterization results.
2. The R
PU
pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design.
Min
-0.3 V
0.7 x V
DD
-
30
-
500
15
Typ
1)
-
-
55
-
-
-
-
Max
0.3 x V
DD
V
DD
+ 0.3
0.5
80
75
-
-
Unit
V k Ω ns ns
µs
Figure 29. Typical NRST V
IL
and V
IH
vs V
DD
@ 3 temperatures
6
5
-40ºC
25ºC
85ºC
4
3
2
1
0
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6
MS19410V3
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Figure 30. Typical NRST pull-up resistance vs V
DD
@ 3 temperatures
60
-40ºC
25ºC
85ºC
55
50
45
40
35
30
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6
MS19411V3
Figure 31. Typical NRST pull-up current vs V
DD
@ 3 temperatures
140
120
100
80
60
40
20
-40ºC
25ºC
85ºC
0
0 1 2 3
V
DD
[V]
4 5 6 ai15069c
The reset network shown in Figure 32
protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V
IL
max. level specified in
Table 35 . Otherwise the reset is not taken into account internally. For power consumption
sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRST signal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device’s reset timing conditions. The minimum recommended capacity is 10 nF.
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Figure 32. Recommended reset pin protection
V
DD
STM8
R
PU
External reset circuit
(Optional)
0.1 μF
NRST Filter
MSv36491V1
9.3.8 SPI serial peripheral interface
Unless otherwise specified, the parameters given in
Table 40 are derived from tests
performed under ambient temperature, f
MASTER conditions. t
MASTER
= 1/f
MASTER
.
frequency and V
DD
supply voltage
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Symbol Parameter
Table 40. SPI characteristics
Conditions Min Max f
SCK
1/t c(SCK)
SPI clock frequency
Master mode 0 10
Slave mode 0 6 t r(SCK) t f(SCK) t su(NSS)
(1) t h(NSS)
t t w(SCKH)
w(SCKL)
t t
su(SI)
SPI clock rise and fall time Capacitive load: C = 30 pF
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Slave mode
Slave mode
Master mode
Master mode
4 x t t
SCK
-
MASTER
70
/2 - 15 t
5
SCK
25
/2 + 15
-
-
-
Slave mode 5 t t
h(SI) t a(SO)
t dis(SO)
t v(SO)
t
t h(SO)
t
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Master mode
Slave mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
7
10
-
25
-
-
31
12
3 x t
MASTER
-
-
-
-
-
75
30
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
Unit
MHz ns
DS8633 Rev 6
STM8S007C8 Electrical characteristics
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 33. SPI timing diagram - slave mode and CPHA = 0
Figure 34. SPI timing diagram - slave mode and CPHA = 1
(1)
NSS input t
SU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 t w(SCKH) t w(SCKL) t c(SCK) t h(NSS)
MISO
OUTPUT
MOSI
INPUT t a(SO) t su(SI) t v(SO)
MSB OUT t h(SI)
MSB IN t h(SO)
BIT6 OUT
BIT 1 IN t r(SCK) t f(SCK) t dis(SO)
LSB OUT
LSB IN
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
ai14135b
DS8633 Rev 6
82
Electrical characteristics
Figure 35. SPI timing diagram - master mode (1)
NSS input
High tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTPUT tsu(MI) tw(SCKH) tw(SCKL)
MSB IN th(MI)
MSB OUT tv(MO)
BIT6 IN
B I T1 OUT th(MO)
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
tr(SCK) tf(SCK)
LSB IN
LSB OUT
STM8S007C8 ai14136c
DS8633 Rev 6
STM8S007C8 Electrical characteristics
9.3.9 I
2
C interface characteristics
Symbol
Table 41. I 2 C characteristics
Standard mode I
2
C Fast mode I
2
C
(1)
Parameter
Min
(2)
Max
Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA) t su(STA) t su(STO)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time t w(STO:STA)
STOP to START condition time
(bus free)
4.7
4.0
250
0
(3)
-
-
4.0
4.7
4.0
4.7
-
-
-
-
1000
300
-
-
-
-
1.3
0.6
100
0
(4)
-
-
0.6
0.6
0.6
1.3
-
-
-
300
300
-
-
-
-
µs ns
µs
µs
µs
C b
Capacitive load for each bus line 400
1. f
MASTER
, must be at least 8 MHz to achieve max fast I
2
C speed (400kHz)
2. Data based on standard I
2
C protocol requirement, not tested in production
400
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time pF
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
SDA tf(SDA)
I²C bus
Figure 36. Typical application with I 2 C bus and timing diagram
VDD VDD
4.7 kΩ 4.7 kΩ
STM8
100 Ω
SDA
SCL
100 Ω
S TART REPEATED
S TART tsu(STA)
S TART th(STA) tr(SDA) tw(SCLL) tsu(SDA) th(SDA)
S TOP tsu(STA:STO)
SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai17490V2
1. Measurement points are made at CMOS levels: 0.3 x V
DD
and 0.7 x V
DD
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Subject to general operating conditions for V
DDA specified.
, f
MASTER
, and T
A
unless otherwise
Symbol Parameter
Table 42. ADC characteristics
Conditions Min Typ Max Unit
V
DDA
= 3 to 5.5 V 1 4 f
ADC
ADC clock frequency MHz
V
DDA
= 4.5 to 5.5 V 1 6
V
DDA
Analog supply 3 5.5
V
V
V
C
REF+
V
REF-
AIN
ADC
Positive reference voltage
Negative reference voltage
Conversion voltage range
(2)
Internal sample and hold capacitor
-
-
-
-
2.75
V
V
SSA
REF-
-
(1)
-
-
-
3
V
DDA
0.5
V
-
REF+
V
V
V pF t
Sampling time f
ADC
= 4 MHz f
ADC
= 6 MHz
-
-
0.75
0.5
-
-
µs t
STAB
Wakeup time from standby 7 µs t
CONV
Total conversion time (including sampling time, 10-bit resolution) f
ADC
= 4 MHz f
ADC
= 6 MHz
-
3.5
2.33
µs
µs
14 1/f
ADC
1. Guaranteed by design.
2. During the sample time the input capacitance C
AIN
(3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t
S.
After the end of the sample time t
S
, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t
S
depend on programming.
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Symbol
Table 43. ADC accuracy with R
AIN
< 10 k Ω , V
DDA
= 5 V
Parameter Conditions Typ Max Unit
|E
|E
|E
|E
|E
T
O
G
D
L
|
|
|
|
| Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
(1)
f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz
1.0
1.4
1.6
0.6
1.1
1.2
0.2
0.6
0.8
0.7
0.7
0.8
0.6
0.6
0.6
2.5
3
3.5
2.0
2.5
2.5
2
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
LSB
1. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I
Σ I
INJ(PIN)
in
does not affect the ADC accuracy.
INJ(PIN)
and
Symbol
Table 44. ADC accuracy with R
AIN
< 10 k Ω R
AIN
, V
DDA
= 3.3 V
Parameter Conditions Typ Max Unit
|E
|E
|E
|E
|E
T
O
G
D
L
|
|
|
|
| Total unadjusted error
Offset error
Gain error
(1)
f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz
1.1
1.6
0.7
1.3
0.2
0.5
0.7
0.7
0.6
0.6
2.0
2.5
1.5
2.0
1.5
2.0
1.0
1.0
1.5
1.5
LSB
1. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I
Σ I
INJ(PIN)
in
does not affect the ADC accuracy.
INJ(PIN)
and
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Figure 37. ADC accuracy characteristics
E
G
1023
1022
1021
1LSBIDEAL =
1024
7
6
5
4
3
2
1
E
O
E
T
1 LSB
E
L
IDEAL
0
V
SSA
1 2 3 4 5 6 7
(2)
E
D
(3)
(1)
1021102210231024
V
DDA
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
E
E
E
E
E
O
G
= Differential linearity error: maximum deviation between actual steps and the ideal one.
= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.
T
= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
D
= Offset error: deviation between the first actual transition and the first ideal one.
= Gain error: deviation between the last ideal transition and the last actual one.
Figure 38. Typical application with ADC
V
DD
V
T
0.6V
STM8
R
AIN AINx
V
AIN
10-bit A/D conversion
C
AIN
V
T
0.6V
I
L
±1µA
C
ADC
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.
• FTB : A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Symbol
V
FESD
V
EFTB
Parameter
Table 45. EMS data
Conditions
Voltage limits to be applied on any I/O pin to induce a functional disturbance f
V
DD
= 5 V, T
MASTER
A
= 25 °C,
= 16 MHz, conforming to IEC 61000-4-2
Fast transient voltage burst limits to be applied through 100pF on V
DD
and V
SS pins to induce a functional disturbance f
V
DD
= 5 V, T
MASTER
A
= 25 °C,
= 16 MHz, conforming to IEC 61000-4-4
Level/class
2B
4A
DS8633 Rev 6
STM8S007C8 Electrical characteristics
Electromagnetic interference (EMI)
Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading.
Table 46. EMI data
Conditions
Symbol Parameter
General conditions
Monitored frequency band
S
EMI
Peak level
V
T
DD
A
= 5 V
= 25 °C
LQFP48 package conforming to IEC
61967-2
0.1MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
EMI level
1. Data based on characterization results, not tested in production.
-
Max f
HSE
/f
CPU
(1)
16 MHz/
8 MHz
16 MHz/
16 MHz
24 MHz/
24 MHz
14
19
-4
1.5
13
23
-4
2
24
17
7
2.5
Unit dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (three positive then three negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Symbol
Table 47. ESD absolute maximum ratings
Ratings Conditions Class
Maximum value
(1)
Unit
V
V
ESD(HBM)
ESD(CDM)
Electrostatic discharge voltage
(Human body model)
Electrostatic discharge voltage
(Charge device model)
1. Guaranteed by characterization results.
T
A
= 25°C, conforming to
JESD22-A114
T
A
= 25°C, conforming to
JESD22-C101
A
IV
2000
1000
V
V
DS8633 Rev 6
82
Electrical characteristics STM8S007C8
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance:
• A supply overvoltage (applied to each power supply pin)
• A current injection (applied to each input, output and configurable I/O pin) is performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
Symbol Parameter
Table 48. Electrical sensitivities
Conditions Class
(1)
LU Static latch-up class
T
A
= 25 °C
T
A
= 85 °C
A
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).
DS8633 Rev 6
STM8S007C8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
10.1 LQFP48 package information
Figure 39. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
SEATING
PLANE
C ccc C b
37
36
D
D1
D3
25
24
0.25 mm
GAUGE PLANE
K
L1
L
48
PIN 1
IDENTIFICATION
1
1. Drawing is not to scale.
12 e
13
5B_ME_V2
DS8633 Rev 6
88
Package information STM8S007C8
Table 49. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max e
L
L1
D3
E
E1
E3 k ccc b c
D
D1
A
A1
A2
-
0.050
1.350
0.170
0.090
8.800
6.800
-
8.800
6.800
-
-
0.450
-
0°
-
-
-
1.400
0.220
-
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
9.200
7.200
-
-
0.750
-
7°
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
0.3465
0.2677
-
-
0.0177
-
0°
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
-
-
-
0.0551
0.0087
-
0.3543
0.2756
-
0.3622
0.2835
-
-
0.0295
-
7°
0.0031
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
DS8633 Rev 6
STM8S007C8 Package information
Figure 40. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint
0.50
1.20
0.30
37
36 25
24
0.20
7.30
9.70
5.80
7.30
48
1 12
13
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
DS8633 Rev 6
88
Package information STM8S007C8
Device marking for LQFP48
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.
Figure 41. LQFP48 marking example (package top view)
Product identification
(1)
STM8S007
C8T6
Standard ST logo
Date code
Y WW
Revision code
Pin 1 identifier
R
MS37489V1
1. 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS8633 Rev 6
STM8S007C8 Package information
The maximum chip junction temperature (T
Jmax
Table 16: General operating conditions .
) must never exceed the values given in
The maximum chip-junction temperature, T
Jmax using the following equation:
, in degrees Celsius, may be calculated
T
Jmax
= T
Amax
+ (P
Dmax
x Θ
JA
)
Where:
• T
Amax
is the maximum ambient temperature in ° C
• Θ
JA
is the package junction-to-ambient thermal resistance in ° C/W
• P
Dmax
is the sum of P
INTmax
and P
I/Omax
(P
Dmax
= P
INTmax
+ P
I/Omax
)
• P
INTmax
is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
• P
I/Omax
P
I/Omax
V
OH
/I
OH
represents the maximum power dissipation on output pins, where:
= Σ (V
OL
*I
OL
) + Σ ((V
DD
-V
OH)
*I
OH
), and taking account of the actual V of the I/Os at low and high level in the application.
OL
/I
OL and
Symbol
Table 50. Thermal characteristics (1)
Parameter Value
Θ
JA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
57
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
Unit
°C/W
JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.
DS8633 Rev 6
88
Package information STM8S007C8
10.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 42: STM8S007C8 value line ordering information scheme
).
The following example shows how to calculate the temperature range needed for a given application.
Assuming the following application conditions:
• Maximum ambient temperature T
Amax
= 82 °C (measured according to JESD51-2)
• I
DDmax
= 15 mA, V
DD
= 5.5 V
• Maximum eight standard I/Os used at the same time in output at low level with I
OL mA, V
OL
= 2 V
= 10
• Maximum four high sink I/Os used at the same time in output at low level with I
OL mA, V
OL
= 1.5 V
= 20
• Maximum two true open drain I/Os used at the same time in output at low level with
I
OL
= 20 mA, V
OL
= 2 V
P
INTmax =
15 mA x 5.5 V = 82.5 mW
P
IOmax =
(10 mA x 2 V x 8 ) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW
This gives: P
INTmax
= 82.5 mW and P
IOmax
360 mW:
P
Dmax
= 82.5 mW + 360 mW
Thus: P
Dmax
= 443 mW
Using the values obtained in Table 50: Thermal characteristics on page 87 T
Jmax calculated as follows for LQFP64 10 x 10 mm = 46 °C/W:
is
T
Jmax
= 82 °C + (46 °C/W x 443 mW) = 82 °C + 20 °C = 102 °C
This is within the range of the suffix 6 version parts (-40 < T
J
< 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
DS8633 Rev 6
STM8S007C8 Ordering information
Figure 42. STM8S007C8 value line ordering information scheme (1)
Example: STM8 S 007 C 8 T 6 TR
Product class
STM8 microcontroller
Family type
S = standard
Sub-family type
(2)
00x = Value line sub-family
007 = high density
Pin count
C = 48 pins
Program memory size
8 = 64 Kbyte
Package type
T = LQFP
Temperature range
6 = -40 °C to 85 °C
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (such as memory size and package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com
or contact the ST Sales Office nearest to you.
2. Refer to Table 1: STM8S007C8 value line features for detailed description.
DS8633 Rev 6
89
STM8 development tools
12 STM8 development tools
STM8S007C8
Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.
The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.
STice key features
• Occurrence and time profiling and code coverage (new features)
• Advanced breakpoints with up to 4 levels of conditions
• Data breakpoints
• Program and data trace recording up to 128 KB records
• Read/write on the fly of memory during emulation
• In-circuit debugging/programming via SWIM protocol
• 8-bit probe analyzer
• 1 input and 2 output triggers
• Power supply follower managing application voltages between 1.62 to 5.5 V
• Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements
• Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
DS8633 Rev 6
STM8S007C8 STM8 development tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available.
STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com
. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
• Seamless integration of C and ASM toolsets
• Full-featured debugger
• Project management
• Syntax highlighting editor
• Integrated programming interface
• Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify the user STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.
12.2.2 C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface.
Available toolchains include:
• Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code is available. For more information, see www.cosmic-software.com.
• Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of code. For more information, see www.raisonance.com.
• STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows users to assemble and link the user application source code.
During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8.
For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.
DS8633 Rev 6
91
Revision history STM8S007C8
Date
31-Oct-2011
06-Jan-2012
26-Apr-2012
10-Mar-2015
20-Mar-2015
16-Oct-2018
Revision
Table 51. Document revision history
Changes
1
2
3
4
5
6
Initial release.
Table 34: Flash program memory/data EEPROM memory : updated
V
DD
condition; updated t
RET
parameters.
Table 39: NRST pin characteristics : updated typ and max values of the NRST Pull-up resistor.
Added the document status on the cover page (datasheet-production data).
Modified temperature range and ACC
HSI
values in Table 31: HSI oscillator characteristics on page 58 (ACC
HSI
parameter).
Modified Figure 35: SPI timing diagram - master mode(1) on page 74
(SCK output instead of SCK input).
Updated the disclaimer.
Added Figure 41: LQFP48 marking example (package top view) .
Updated:
– Figure 27: Typ. VDD - VOH @ VDD = 5 V (high sink ports) ,
– Figure 29: Typical NRST VIL and VIH vs VDD @ 3 temperatures ,
– Figure 30: Typical NRST pull-up resistance vs VDD @ 3 temperatures .
Added a note to Power-on reset threshold parameter in Table 17:
Operating conditions at power-up/power-down .
Updated:
–
Figure 1: STM8S007C8 value line block diagram
– Title of Section 4.4: Flash program memory and data EEPROM
–
Section 4.14: Communication interfaces
–
Table 5: STM8S007C8 pin description
–
Table 8: General hardware register map
–
– Table’s footnotes standardized on Section 9: Electrical characteristics
–
Section 9.2: Absolute maximum ratings
–
Table 31: HSI oscillator characteristics
–
–
Section : Device marking for LQFP48
–
Section 11: Ordering information
DS8633 Rev 6
STM8S007C8
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS8633 Rev 6
93
Preuzimanje
Javna poveznica ažurirana
Javna poveznica na vaš razgovor je ažurirana. You may view and manage your chat links after registration here.
Javna poveznica dokumenta
Oglas