• For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).

• For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM).

• For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

• For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

8/84 DS12129 Rev 4

STM8S001J3

2 Description

Description

The STM8S001J3 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. It is referred to as low-density device in the STM8S microcontroller family reference manual (RM0016).

The STM8S001J3 device provides the following benefits: performance, robustness and reduced system cost.

Device performance and robustness are ensured by true data EEPROM supporting up to

100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art technology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog, and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Table 1. STM8S001J3 features

Features STM8S001J3

Pin count

Max. number of GPIOs (I/O)

External interrupt pins

Timer CAPCOM channels

Timer complementary outputs

A/D converter channels

High-sink I/Os

Low-density Flash program memory

(byte)

RAM (byte)

True data EEPROM (byte)

Peripheral set

8 K

1 K

128

(1)

Multi purpose timer (TIM1), SPI unidirectional, I2C, UART,

Window WDG, independent WDG, ADC, PWM timer (TIM2), 8-bit timer

(TIM4)

1. Without read-while-write capability.

DS12129 Rev 4 9/84

Block diagram STM8S001J3

Single wire debug interface

400 Kbit/s

8 Mbit/s

LIN master

Up to 3 channels

Figure 1. STM8S001J3 block diagram

Reset block

Reset

POR BOR

Clock controller

Ext. Clock input

1 – 16 MHz

RC int. 16 MHz

Detector

RC int. 128 kHz

STM8 core

Clock to peripherals and core

Window WDG

Independent WDG

Debug / SWIM

8 Kbyte program Flash

I2C

Unidirectional SPI

UART1

ADC1

128 byte data EEPROM

1 Kbyte RAM

16-bit advanced control timer (TM1)

16-bit general purpose timer

(TIM2)

8-bit basic timer

(TIM4)

AWU timer

Up to 2

CAPCPOM channels

Up to 3

CAPCPOM channels

MSv44651V1

10/84 DS12129 Rev 4

STM8S001J3 Functional overview

The following section intends to give an overview of the basic features of the STM8S001J3 functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual

(RM0016).

The 8-bit STM8 core is designed for code efficiency and performance.

It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

• Harvard architecture

• 3-stage pipeline

• 32-bit wide program memory bus - single cycle fetching for most instructions

• X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

• 8-bit accumulator

• 24-bit program counter - 16-Mbyte linear memory space

• 16-bit stack pointer - access to a 64 K-level stack

• 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

• 20 addressing modes

• Indexed indirect addressing mode for look-up tables located anywhere in the address space

• Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

• 80 instructions with 2-byte average instruction size

• Standard data movement and logic/arithmetic functions

• 8-bit by 8-bit multiplication

• 16-bit by 8-bit and 16-bit by 16-bit division

• Bit manipulation

• Data transfer between stack and accumulator (push/pop) with direct stack access

• Data transfer using the X and Y registers or direct memory-to-memory transfers

DS12129 Rev 4 11/84

Functional overview

4.2

STM8S001J3

Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

• R/W to RAM and peripheral registers in real-time

• R/W access to all resources by stalling the CPU

• Breakpoints on all program-memory instructions (software breakpoints)

• Two advanced breakpoints, 23 predefined configurations

Recommendation for SWIM pin (pin #8) sharing

As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever.

This initial delay can be removed in the final (locked) code.

If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for device debug/programming.

4.4

• Nested interrupts with three software priority levels

• 32 interrupt vectors with hardware priority

• Up to 5 external interrupts including TLI

• Trap and reset interrupts

Flash program memory and data EEPROM

• 8 Kbytes of Flash program single voltage Flash memory

• 128 byte true data EEPROM

• User option byte area

12/84 DS12129 Rev 4

STM8S001J3 Functional overview

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to

Figure 2 .

The size of the UBC is programmable through the UBC option byte ( Table 12

), in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

• Main program memory: 8 Kbyte minus UBC

• User-specific boot code (UBC): Configurable up to 8 Kbyte

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2. Flash memory organization

Option bytes

Data EEPROM (128 bytes)

UBC area

Remains write protected during IAP

Programmable area from 64 bytes

(1 page) up to

8 Kbytes

(in 1 page steps)

Low density

Flash program memory

(8 Kbytes)

Program memory area

Write access possible for IAP

MS36408V1

DS12129 Rev 4 13/84

Functional overview STM8S001J3

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data

EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory.

Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Recommendation for the device's programming:

The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space).

If the device's program memory is empty (0x00 content), it displays the behavior described below:

• After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG

(0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF).

It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz

HSI clock.

• Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed.

The reading of non-existing memory is a random content which can lead to the execution of invalid instructions.

The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more.

Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device.

The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts).

Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop.

14/84 DS12129 Rev 4

STM8S001J3 Functional overview

The clock controller distributes the system clock (f

MASTER)

coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

• Clock prescaler : To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching : Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

• Clock management : To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• Master clock sources : Three different clock sources can be used to drive the master clock:

– Up to 16 MHz high-speed user-external clock (HSE user-ext)

– 16 MHz high-speed internal RC oscillator (HSI)

– 128 kHz low-speed internal RC (LSI)

• Startup clock : After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS) : This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

• Configurable main clock output (CCO) : This outputs an external clock for use by the application.

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit

Peripheral clock

Bit

Peripheral clock

Bit

Peripheral clock

Bit

Peripheral clock

PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC

PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22

PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21

AWU

Reserved

PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved

DS12129 Rev 4 15/84

Functional overview STM8S001J3

For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources.

• Wait mode : In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.

• Active halt mode with regulator on : In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster.

Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

• Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

• Halt mode : In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2. Refresh out of window: the down-counter is refreshed before its value is lower than the one stored in the window register.

16/84 DS12129 Rev 4

STM8S001J3 Functional overview

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

4.8

4.9 Auto wakeup counter

• Used for auto wakeup from active halt mode

• Clock source: internal 128 kHz internal low frequency RC oscillator or external clock

• LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to lighting and half-bridge driver.

• 16-bit up, down and up/down autoreload counter with 16-bit prescaler

• Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output

• Synchronization module to control the timer with external signals

• Break input to force the timer outputs into a defined state

• One complementary output (CH1 with CH1N option) with adjustable dead time

• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.10 TIM2 - 16-bit general purpose timer

• 16-bit autoreload (AR) up-counter

• 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

• 3 individually configurable capture/compare channels

• PWM mode

• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

4.11 TIM4 - 8-bit basic timer

• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

• Clock source: CPU clock

• Interrupt source: 1 x overflow/update

DS12129 Rev 4 17/84

Functional overview STM8S001J3

Timer

Counter size

(bits)

Table 3. TIM timer features

Prescaler

Counting mode

CAPCOM channels

Complem. outputs

Ext. trigger

Timer synchronization/ chaining

TIM1

TIM2

TIM4

Any integer from 1 to 65536

Any power of 2 from 1 to 32768

Any power of 2 from 1 to 128

1. TIM1_CH2N with TIM1_CH1

Up/down

1 (1)

4.12 Analog-to-digital converter (ADC1)

STM8S001J3 contains a 10-bit successive approximation A/D converter (ADC1) with up to three external and one internal multiplexed input channels and the following main features:

• Input voltage range: 0 to V

DDA

• Conversion time: 14 clock cycles

• Single and continuous, buffered continuous conversion modes

• Buffer size (10 x 10 bits)

• Scan mode for single and continuous conversion of a sequence of channels

• Analog watchdog capability with programmable upper and lower thresholds

• Analog watchdog interrupt

• Internal reference voltage on channel AIN7

• External trigger input

• Trigger from TIM1 TRGO

• End of conversion (EOC) interrupt next paragraph :

Internal bandgap reference voltage

Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal bandgap reference is constant and can be used, for example, to monitor V

or to determine the absolute voltage on external input channels. It is independent of variations in

and ambient temperature T

The following communication interfaces are implemented:

• UART1: full feature UART, synchronous mode, SmartCard mode, IrDA mode, LIN2.1 master capability

• SPI: master mode transmit/receive only, slave mode receive only, 8 Mbit/s

• I²C: up to 400 Kbit/s

18/84 DS12129 Rev 4

STM8S001J3 Functional overview

4.13.1 UART1

Main features

• 1 Mbit/s full duplex SCI

• High precision baud rate generator

• Smartcard reader emulation

• IrDA SIR encoder decoder

• LIN master mode

• Single wire half duplex mode

Asynchronous communication (UART mode)

• Full duplex communication - NRZ standard format (mark/space)

• Programmable transmit and receive baud rates up to 1 Mbit/s (f

CPU following any standard baud rate regardless of the input frequency

/16) and capable of

• Separate enable bits for transmitter and receiver

• Two receiver wakeup modes:

– Address bit (MSB)

– Idle line (interrupt)

• Transmission error detection with interrupt generation

• Parity control

LIN master mode

• Emission: generates 13-bit synch. break frame

• Reception: detects 11-bit break frame

4.13.2 SPI

• Maximum speed: 8 Mbit/s (f

MASTER

/2) both for master and slave

• Unidirectional transfer: SPI master mode transmit/receive only, SPI slave mode receive only

• Simplex master synchronous transfers on two lines with a possible bidirectional data line

• Master or slave operation - selectable by software

• CRC calculation

• 1 byte Tx and Rx buffer

DS12129 Rev 4 19/84

Functional overview

4.13.3 I2C

• I2C master features

– Clock generation

– Start and stop generation

• I2C slave features

– Programmable I2C address detection

– Stop bit detection

• Generation and detection of 7-bit/10-bit addressing and general call

• Supports different communication speeds

– Standard speed (up to 100 kHz)

– Fast speed (up to 400 kHz)

STM8S001J3

20/84 DS12129 Rev 4

STM8S001J3

5 Pinouts and pin descriptions

Pinouts and pin descriptions

This section presents the pinouts and pin descriptions for STM8S001J3.

Table 4 introduces

the legends and abbreviations that are used in the upcoming subsections.

Type

Level

Table 4. Legend/abbreviations for STM8S001J3 pin description tables

I = input, O = output, S = power supply

Output speed

Port and control configuration

Reset state

Input

Output

CM = CMOS

HS = high sink

O1 = slow (up to 2 MHz)

O2 = fast (up to 10 MHz)

O3 = fast/slow programmability with slow as default state after reset

O4 = fast/slow programmability with fast as default state after reset

Input

Output float = floating, wpu = weak pull-up

T = true open drain, OD = open drain, PP = push pull

Bold x (pin state after internal reset release)

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

5.1 STM8S001J3 SO8N pinout and pin description

Figure 3 presents the STM8S001J3 pinout image and

Table 5 below presents the device’s

pins description.

Figure 3. STM8S001J3 SO8N pinout

PD6/AIN6/UART1_RX/

PA1/OSCIN

VSS/VSSA 2

VCAP 3

VDD/VDDA 4

STM8S

PD5/AIN5/UART1_TX/

PD3/AIN4/TIM2_CH2/ADC_ETR/

PD1/SWIM/

PC6/SPI_MOSI/[TIM1_CH1]

PC5/SPI_SCK/[TIM2_CH1]/

PC4/CLK_CCO/TIM1_CH4/[AIN2]/[TIM1_CH2N]

PC3/TIM1_CH3/[TLI]/[TIM1_CH1N]

PB4/I2C_SCL/[ADC_ETR]

5 PB5/I2C_SDA/[TIM1_BKIN]/

PA3/TIM2_CH3/[SPI_NSS]/[UART1_TX]

MSv44652V2

1. [ ] Alternative function option (if the same alternate function is shown twice, it indicated an exclusive choice and not a duplication of the function).

DS12129 Rev 4 21/84

Pinouts and pin descriptions STM8S001J3

Pin no.

SO8N

Pin name Type

Table 5. STM8S001J3 pin description

Input Output

High sink

(1)

OD PP

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

PD6/ AIN6/

UART1 _RX

PA1/ OSCIN

VSS/VSSA

VDD/VDDA

PC3/ TIM1_CH3

[TLI]

[TIM1_ CH1N]

PC4/ CLK_CCO/

TIM1_

CH4/[AIN2]/

[TIM1_ CH2N]

PC5/ SPI_SCK

[TIM2_ CH1]

(2)

(3)

VCAP

PA3/ TIM2_ CH3

[SPI_ NSS]\

[UART1_TX]

(2)

PB5/ I2C_ SDA

[TIM1_ BKIN]

PB4/ I2C_ SCL

/[ADC_ETR]

I/O X

I/O

O3 X

O1 X

Port D6

Port A1

Analog input

6/ UART1 data receive

External clock input

(HSE clock)

S - -

Ground

1.8 V regulator capacitor

Power supply

I/O

X -

O3 X

O1 T

(4)

X Port A3

Port B5

Timer 2 channel 3

I2C data

SPI master/ slave select

[AFR1]

UART1 data transmit

[AFR1 and

AFR0]

Timer 1 - break input

[AFR4]

I/O

(4)

O3 X

Port B4 I2C clock

X Port C3

Timer 1 - channel 3

ADC external trigger

[AFR4]

Top level interrupt

[AFR3]

Timer 1 - inverted channel 1

[AFR7]

I/O

O3 X

X Port C4

Configurable clock output/Timer

1 - channel 4

Analog input

2 [AFR2],

Timer 1 - inverted channel 2

[AFR7]

X Port C5 SPI clock

Timer 2 - channel 1

[AFR0]

22/84 DS12129 Rev 4

STM8S001J3 Pinouts and pin descriptions

Pin no.

SO8N

Pin name

Table 5. STM8S001J3 pin description (continued)

Input Output

Type

High sink

(1)

OD PP

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

PC6/ SPI_MOSI

[TIM1_ CH1]

I/O X

(5)

X X HS O3 X X Port C6

SPI master out/slave in

Timer 1 - channel 1

[AFR0]

PD1/ SWIM

PD3/ AIN4/

TIM2_ CH2/

ADC_ ETR

PD5/ AIN5/

(5)

UART1 _TX

I/O

(5)

X HS O4 X X Port D1

O3 X

X Port D3

X Port D5

SWIM data interface

Analog input

4/ Timer 2 - channel

2/ADC external trigger

Analog input

5/ UART1 data transmit

1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings.

2. By remapping UART1_TX (AFR0=1 and AFR1=1) to PA3 the UART1_RX alternate function on PD6 becomes unavailable.

UART1 can be then used only in Single wire half-duplex mode or in Smartcard-reader emulation mode.

3. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode if halt/active-halt is used in the application.

4. In the open-drain output column, “T” defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). Although PB5 itself is a true open drain GPIO with its respective internal circuitry and characteristics, V maximum of the pin number 5 is limited by the standard GPIO PA3 which is also bonded to pin number 5.

5. The PD1 pin is in input pull-up during the reset phase and after internal reset release. This PD1 default state influences all

GPIOs connected in parallel on pin# 8 (PC6, PD3, PD5).

Note:

The PA2, PB0, PB1, PB2, PB3, PB6, PB7, PC1, PC2, PC7, PD0, PD2, PD4, PD7, PE5 and

PF4 GPIOs should be configured after device reset in output push-pull mode with output low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and they are in input-floating mode after a device reset.

As several pins provide a connection to multiple GPIOs, the mode selection for any of those

GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PD1 is also seen on PC6, PD3 and PD5. Push-pull configuration of PC3 is also seen on PC4 and

PC5, etc.

DS12129 Rev 4 23/84

Pinouts and pin descriptions STM8S001J3

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to

Section 8: Option bytes . When the remapping option is active,

the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the

GPIO section of the family reference manual, RM0016).

24/84 DS12129 Rev 4

STM8S001J3

6 Memory and register map

0x00 0000

Figure 4. Memory map

RAM

(1 Kbyte)

513 byte stack

0x00 03FF

0x00 0800

Reserved

0x00 4000

0x00 407F

0x00 47FF

0x00 4800

0x00 480A

0x00 480B

Data EEPROM

Reserved

Option bytes

Reserved

0x00 4FFF

0x00 5000

0x00 57FF

0x00 5800

GPIO and periph. reg.

Reserved

0x00 7EFF

0x00 7F00

0x00 7FFF

0x00 8000

0x00 807F

0x00 8080

0x00 9FFF

0x00 A000

CPU/SWIM/debug/ITC registers

32 interrupt vectors

Flash program memory

(8 Kbyte)

Reserved

0x02 7FFF

Memory and register map

MS36410V1

DS12129 Rev 4 25/84

Memory and register map STM8S001J3

Table 6 lists the boundary addresses for each memory size. The top of the stack is at the

RAM end address in each case.

Table 6. Flash, Data EEPROM and RAM boundary addresses

Memory area Size (byte) Start address End address

Flash program memory

RAM

8 K

1 K

0x00 8000

0x00 0000

0x00 9FFF

0x00 03FF

Data EEPROM 128 0x00 4000 0x00 407F

6.2.1 I/O port hardware register map

Address Block

Table 7. I/O port hardware register map

Register label Register name

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

Port A

Port B

Port C

Port D

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Reset status

0x00

0xXX

(1)

0x00

0xXX

(1)

0x00

0xXX (1)

0x00

0xXX

(1)

0x00

0x02

0x00

26/84 DS12129 Rev 4

STM8S001J3 Memory and register map

Table 7. I/O port hardware register map (continued)

Block Register label Register name Address

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5018

0x00 5019

0x00 501A

0x00 501B

0x00 501C

0x00 501D

Port E

Port F

1. Depends on the external circuitry.

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

Reset status

0x00

0xXX

(1)

0x00

0xXX (1)

0x00

DS12129 Rev 4 27/84

Memory and register map STM8S001J3

28/84

Address

0x00 501E to

0x00 5059

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

0x00 505F

0x00 5060 to

0x00 5061

0x00 5062

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 5063

0x00 5064

0x00 5065 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2 to

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

0x00 50C0

Block

Flash

ITC

RST

CLK

Table 8. General hardware register map

Register label Register name

Reset status

FLASH_CR1

FLASH_CR2

FLASH_NCR2

FLASH _FPR

FLASH _NFPR

FLASH _IAPSR

Reserved area (60 byte)

Flash control register 1

Flash control register 2

Flash complementary control register 2

Flash protection register

Flash complementary protection register

Flash in-application programming status register

FLASH _PUKR

FLASH _DUKR

EXTI_CR1

EXTI_CR2

Reserved area (2 byte)

Flash Program memory unprotection register

Reserved area (1 byte)

Data EEPROM unprotection register

Reserved area (59 byte)

External interrupt control register 1

External interrupt control register 2

RST_SR

Reserved area (17 byte)

Reset status register

CLK_ICKR

CLK_ECKR

CLK_CMSR

CLK_SWR

CLK_SWCR

CLK_CKDIVR

CLK_PCKENR1

CLK_CSSR

CLK_CCOR

CLK_PCKENR2

Reserved area (12 byte)

Internal clock control register

External clock control register

Reserved area (1 byte)

Clock master status register

Clock master switch register

Clock switch control register

Clock divider register

Peripheral clock gating register 1

Clock security system register

Configurable clock control register

Peripheral clock gating register 2

0x00

0xXX

(1)

0x01

0x00

0xE1

0xXX

0x18

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

DS12129 Rev 4

STM8S001J3

Address

0x00 50CB

0x00 50CC

0x00 50CD

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 50CE to

0x00 50D0

0x00 50D1

0x00 50D2

0x00 50D3 to

0x00 50DF

0x00 50E0

0x00 50E1

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 50F2

0x00 50F3 to

0x00 50FF

Memory and register map

Table 8. General hardware register map (continued)

Block

CLK

WWDG

IWDG

AWU

SPI

I2C

Register label Register name

Reset status

CLK_HSITRIMR

CLK_SWIMCCR

Reserved area (1 byte)

HSI clock calibration trimming register

SWIM clock control register

0x00

0bXXXX

XXX0

WWDG_CR

WWDG_WR

IWDG_KR

IWDG_PR

IWDG_RLR

AWU_CSR1

AWU_APR

AWU_TBR

SPI_CR1

SPI_CR2

SPI_ICR

SPI_SR

SPI_DR

SPI_CRCPR

SPI_RXCRCR

SPI_TXCRCR

I2C_CR1

I2C_CR2

I2C_FREQR

I2C_OARL

I2C_OARH

Reserved area (3 byte)

WWDG control register

WWDR window register

Reserved area (13 byte)

IWDG key register

IWDG prescaler register

IWDG reload register

Reserved area (13 byte)

AWU control/status register 1

AWU asynchronous prescaler buffer register

AWU timebase selection register

Reserved area (13 byte)

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

SPI data register

SPI CRC polynomial register

SPI Rx CRC register

SPI Tx CRC register

Reserved area (8 byte)

I2C control register 1

I2C control register 2

I2C frequency register

I2C own address register low

I2C own address register high

Reserved

0x7F

0xXX

(2)

0x00

0xFF

0x00

0x3F

0x00

0x02

0x00

0x07

0x00

DS12129 Rev 4 29/84

Address

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 521E

0x00 521F to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

0x00 523B to

0x00 523F

0x00 523B to

0x00523F

Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

I2C

UART1

I2C_DR

I2C_SR1

I2C_SR2

I2C_SR3

I2C_ITR

I2C_CCRL

I2C_CCRH

I2C_TRISER

I2C_PECR

UART1_SR

UART1_DR

UART1_BRR1

UART1_BRR2

UART1_CR1

UART1_CR2

UART1_CR3

UART1_CR4

UART1_CR5

UART1_GTR

UART1_PSCR

I2C data register

I2C status register 1

I2C status register 2

I2C status register 3

I2C interrupt control register

I2C clock control register low

I2C clock control register high

I2C TRISE register

I2C packet error checking register

Reserved area (17 byte)

UART1 status register

UART1 data register

UART1 baud rate register 1

UART1 baud rate register 2

UART1 control register 1

UART1 control register 2

UART1 control register 3

UART1 control register 4

UART1 control register 5

UART1 guard time register

UART1 prescaler register

Reserved area (5 bytes)

Reserved area (21 byte)

STM8S001J3

0x00

0xC0

0xXX

0x00

Reset status

0x00

0x02

0x00

30/84 DS12129 Rev 4

STM8S001J3

Address

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C

0x00 526D

0x00 526E

0x00 526F

0x00 5270 to

0x00 52FF

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

TIM1

TIM1_PSCRL

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1_CCR1H

TIM1_CCR1L

TIM1_CCR2H

TIM1_CCR2L

TIM1_CCR3H

TIM1_CCR3L

TIM1_CCR4H

TIM1_CCR4L

TIM1_BKR

TIM1_DTR

TIM1_OISR

TIM1_CR1

TIM1_CR2

TIM1_SMCR

TIM1_ETR

TIM1_IER

TIM1_SR1

TIM1_SR2

TIM1_EGR

TIM1_CCMR1

TIM1_CCMR2

TIM1_CCMR3

TIM1_CCMR4

TIM1_CCER1

TIM1_CCER2

TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1 control register 1

TIM1 control register 2

TIM1 slave mode control register

TIM1 external trigger register

TIM1 Interrupt enable register

TIM1 status register 1

TIM1 status register 2

TIM1 event generation register

TIM1 capture/compare mode register 1

TIM1 capture/compare mode register 2

TIM1 capture/compare mode register 3

TIM1 capture/compare mode register 4

TIM1 capture/compare enable register 1

TIM1 capture/compare enable register 2

TIM1 counter high

TIM1 counter low

TIM1 prescaler register high

TIM1 prescaler register low

TIM1 auto-reload register high

TIM1 auto-reload register low

TIM1 repetition counter register

TIM1 capture/compare register 1 high

TIM1 capture/compare register 1 low

TIM1 capture/compare register 2 high

TIM1 capture/compare register 2 low

TIM1 capture/compare register 3 high

TIM1 capture/compare register 3 low

TIM1 capture/compare register 4 high

TIM1 capture/compare register 4 low

TIM1 break register

TIM1 dead-time register

TIM1 output idle state register

Reserved area (147 byte)

Reset status

0x00

0xFF

0x00

DS12129 Rev 4 31/84

Address

0x00 5311

0x00 5312

0x00 5313

0x00 5314

0x00 5315

0x00 5316

0x00 5317 to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307

0x00 5308

0x00 5309

0x00 530A

0x00 530B

0x00 530C

0x00 530D

0x00 530E

0x00 530F

0x00 5310

Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

TIM2

TIM4

TIM2_CR1

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2_EGR

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCMR3

TIM2_CCER1

TIM2_CCER2

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_CCR3H

TIM2_CCR3L

TIM4_CR1

TIM4_IER

TIM4_SR

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM2 control register 1

Reserved

TIM2 interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare mode register 3

TIM2 capture/compare enable register 1

TIM2 capture/compare enable register 2

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare reg. 2 high

TIM2 capture/compare register 2 low

TIM2 capture/compare register 3 high

TIM2 capture/compare register 3 low

Reserved area (43 byte)

TIM4 control register 1

Reserved

TIM4 interrupt enable register

TIM4 status register

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register

STM8S001J3

Reset status

0x00

0xFF

0x00

0xFF

32/84 DS12129 Rev 4

STM8S001J3 Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name Address

0x00 5349 to

0x00 53DF

0x00 53E0 to

0x00 53F3

0x00 53F4 to

0x00 53FF

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 5406

0x00 5407

0x00 5408

0x00 5409

0x00 540A

0x00 540B

0x00 540C

0x00 540D

0x00 540E

0x00 540F

0x00 5410 to

0x00 57FF

ADC1

1. Depends on the previous reset source.

2. Write only register.

ADC_DBxR

ADC _CSR

ADC_CR1

ADC_CR2

ADC_CR3

ADC_DRH

ADC_DRL

ADC_TDRH

ADC_TDRL

ADC_HTRH

ADC_HTRL

ADC_LTRH

ADC_LTRL

ADC_AWSRH

ADC_AWSRL

ADC_AWCRH

ADC_AWCRL

Reserved area (153 byte)

ADC data buffer registers

Reserved area (12 byte)

ADC control/status register

ADC configuration register 1

ADC configuration register 2

ADC configuration register 3

ADC data register high

ADC data register low

ADC Schmitt trigger disable register high

ADC Schmitt trigger disable register low

ADC high threshold register high

ADC high threshold register low

ADC low threshold register high

ADC low threshold register low

ADC analog watchdog status register high

ADC analog watchdog status register low

ADC analog watchdog control register high

ADC analog watchdog control register low

Reserved area (1008 byte)

Reset status

0x00

0xXX

0x00

0x03

0xFF

0x00

DS12129 Rev 4 33/84

Memory and register map STM8S001J3

Address

Table 9. CPU/SWIM/debug module/interrupt controller registers

Block Register Label Register Name

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

CPU

(1)

CPU

ITC

SWIM

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

PCE

PCH

PCL

SPH

SPL

CCR

SWIM_CSR

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 byte)

Global configuration register

Interrupt software priority register 1

Interrupt software priority register 2

Interrupt software priority register 3

Interrupt software priority register 4

Interrupt software priority register 5

Interrupt software priority register 6

Interrupt software priority register 7

Interrupt software priority register 8

Reserved area (2 byte)

SWIM control status register

Reserved area (15 byte)

0x00

0xFF

0x00

Reset

Status

0x00

0xFF

0x28

34/84 DS12129 Rev 4

STM8S001J3 Memory and register map

Address

Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)

Block Register Label Register Name

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

0x00 7F9B to

0x00 7F9F

1. Accessible by debug module only

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM debug module control register 1

DM debug module control register 2

DM debug module control/status register 1

DM debug module control/status register 2

DM enable function register

Reserved area (5 byte)

Reset

Status

0xFF

0x00

0x10

0x00

0xFF

DS12129 Rev 4 35/84

Interrupt vector mapping

7 Interrupt vector mapping

STM8S001J3

IRQ no.

Source block

Table 10. Interrupt mapping

Description

Wakeup from

Halt mode

Wakeup from

Active-halt mode

RESET Reset

TRAP

TLI

Software interrupt

External top level interrupt

AWU

CLK

EXTI0

EXTI1

EXTI2

EXTI3

EXTI4

SPI

TIM1

TIM2

Auto wake up from halt

Clock controller

Port A external interrupts

Port B external interrupts

Port C external interrupts

Yes

(1)

Yes

Port D external interrupts

Port E external interrupts

Reserved

End of transfer

TIM1 update/overflow/underflow/ trigger/break

TIM1 capture/compare

TIM2 update /overflow

Yes

TIM2 capture/compare -

Reserved

Yes

UART1

I2C

Tx complete

Receive register DATA FULL

I2C interrupt

ADC1

ADC1 end of conversion/analog watchdog interrupt

TIM4 TIM4 update/overflow

Flash EOP/WR_PG_DIS

Reserved

Yes

(1)

Yes

Reserved

1. Except PA1

Vector address

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

0x00 8050

0x00 8054

0x00 8058

0x00 805C

0x00 8000

0x00 8004

0x00 8008

0x00 800C

0x00 8010

0x00 8014

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8060

0x00 8064

0x00 806C to

0x00 807C

36/84 DS12129 Rev 4

STM8S001J3 Option bytes

Addr.

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in

Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the

application in IAP mode, except the ROP option that can only be modified in ICP mode (via

SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Option name

Option byte no.

Table 11. Option bytes

Option bits

6 5 4 3 2 1 0

Factory default setting

0x4800

Read-out protection

(ROP)

OPT0

0x4801

User boot code

(UBC)

0x4802

0x4803 Alternate function

0x4804 remapping

(AFR)

OPT1

NOPT1

OPT2

NOPT2

0x4805 OPT3

Misc. option

0x4806 NOPT3

0x4807

Clock option

0x4808

0x4809

0x480A

HSE clock startup

OPT4

NOPT4

OPT5

NOPT5

ROP[7:0]

AFR7

NAFR7

AFR6

NAFR6

Reserved

AFR5

NAFR5

Reserved

UBC[7:0]

NUBC[7:0]

AFR4 AFR3

NAFR4 NAFR3

HSITRIM

NHSI

TRIM

LSI

_EN

NLSI

_EN

EXT

CLK

HSECNT[7:0]

NHSECNT[7:0]

AFR2

NAFR2

AFR1

NAFR1

AFR0

NAFR0

IWDG

_HW

NIWDG

_HW

CKAWU

SEL

NCKAW

USEL

WWDG

_HW

NWWDG

_HW

WWDG

_HALT

NWWDG

_HALT

PRS

NPR

SC1

PRS

NPR

SC0

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

OPT0

Option byte no.

Table 12. Option byte description

Description

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.

DS12129 Rev 4 37/84

Option bytes STM8S001J3

Option byte no.

OPT1

OPT2

OPT3

OPT4

OPT5

Table 12. Option byte description (continued)

Description

UBC[7:0] User boot code area

0x00: no UBC, no write-protection

0x01: Pages 0 defined as UBC, memory write-protected

0x02: Pages 0 to 1 defined as UBC, memory write-protected

Page 0 and page 1 contain the interrupt vectors.

...

0x7F: Pages 0 to 126 defined as UBC, memory write-protected

Other values: Pages 0 to 127 defined as UBC, memory-write protected.

Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details.

AFR[7:0]

Refer to the following section for alternate function remapping descriptions of bits [7:2] and [1:0] respectively.

HSITRIM : high-speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilization time.

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

38/84 DS12129 Rev 4

STM8S001J3 Option bytes

Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices

Option byte number Description

OPT2

AFR7 Alternate function remapping option 7

0: AFR7 remapping option inactive: default alternate function

(1)

1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function =

TIM1_CH2N.

AFR6 Alternate function remapping option 6

Reserved.

AFR5 Alternate function remapping option 5

Reserved.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: default alternate function

(1)

1: Port B4 alternate function = ADC_ETR; port B5 alternate function =

TIM1_BKIN.

AFR3 Alternate function remapping option 3

0: AFR3 remapping option inactive: default alternate function

(1)

1: Port C3 alternate function = TLI.

AFR2 Alternate function remapping option 2

0: AFR2 remapping option inactive: default alternate function

(1)

1: Port C4 alternate function = AIN2.

AFR1 Alternate function remapping option 1

(2)

0: AFR1 remapping option inactive: default alternate function (1)

1: If AFR0=0: Port A3 alternate function = SPI_NSS.

If AFR0=1: Port A3 alternate function = UART_TX; port D6 alternate function UART_RX unavailable.

AFR0 Alternate function remapping option 0

(2)

0: AFR0 remapping option inactive: Default alternate functions (1)

1: Port C5 alternate function = TIM2_CH1; port C6 alternate function =

TIM1_CH1.

1. Refer to the pinout description.

2. Do not use more than one remapping option in the same port.

DS12129 Rev 4 39/84

Electrical characteristics STM8S001J3

9.1.1

Unless otherwise specified, all voltages are referred to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

Amax

(given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 σ ).

Unless otherwise specified, typical data are based on T

A only as design guidelines and are not tested.

= 25 °C, V

= 5 V. They are given

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 5

Figure 5. Pin loading conditions

STM8 pin

50 pF

40/84 DS12129 Rev 4

STM8S001J3

9.1.5

Electrical characteristics

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 6 .

Figure 6. Pin input voltage

STM8 pin

9.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 14: Voltage characteristics

Table 15: Current characteristics

, and

Table 16: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47

Qualification Standard, extended mission profiles are available on demand.

Symbol

DDx

- V

ESD

Table 14. Voltage characteristics

Ratings

Supply voltage

(1)

Input voltage on true open drain pins

(2)

Input voltage on any other pin

(2)

Electrostatic discharge voltage

Min

-0.3

Max

6.5

- 0.3

6.5

- 0.3

+ 0.3

see Absolute maximum ratings (electrical sensitivity) on page 73

Unit

1. All power (V

) and ground (V

) pins must always be connected to the external power supply

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I injection is induced by V >V

maximum is respected. If V

while a negative injection is induced by V there is no positive injection current, and the corresponding V

maximum

value. A positive

. For true open-drain pads,

maximum must always be respected

DS12129 Rev 4 41/84

Electrical characteristics STM8S001J3

Symbol

Table 15. Current characteristics

Ratings Max.

(1)

Unit

VDD

VSS

Total current into V

DD power lines (source)

(2)

Total current out of V

SS ground lines (sink)

(2)

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

100

-20 mA

INJ(PIN)

(3)(4)

Injected current on OSCIN pin

Injected current on any other pin

(5)

Total injected current (sum of all I/O and control pins)

(5)

±4

Σ I

INJ(PIN)

(3)

±20

1. Guaranteed by characterization results.

2. All power (V

) and ground (V

) pins must always be connected to the external supply.

3. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I injection is induced by V >V

maximum is respected. If V

while a negative injection is induced by V there is no positive injection current, and the corresponding V

maximum

value. A positive

. For true open-drain pads,

maximum must always be respected

4. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I

Σ I

INJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.

INJ(PIN) and

5. When several inputs are submitted to a current injection, the maximum with Σ I

INJ(PIN)

Σ I

INJ(PIN)

maximum current injection on four I/O port pins of the device.

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization

Symbol

STG

Table 16. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

-65 to 150

150

Unit

°C

42/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

The device must be used in operating conditions that respect the parameters in

Table 17 . In

addition, full account must be taken of all physical capacitor characteristics and tolerances.

Symbol

Table 17. General operating conditions

Parameter Conditions Min Max Unit f

CPU

CAP

(1)

Internal CPU clock frequency

Standard operating voltage

EXT

: capacitance of external capacitor

ESR of external capacitor

At 1 MHz

(2)

ESL of external capacitor

2.95

5.5

470 3300

0.3

MHz

V nF ohm

15 nH

(3)

Power dissipation at

= 125° C

Ambient temperature

SO8N 49 mW

Junction temperature range

Maximum power dissipation -40

-40

125

130

°C

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter must be respected for the full application range.

2. This frequency of 1 MHz as a condition for V

CAP

parameters is given by the design of the internal regulator.

3. To calculate P

Dmax

), use the formula P

Dmax

= (T

Jmax

characteristics on page 78

) with the value for T

Table 49: Thermal characteristics

Jmax

- T

)/ Θ

(see

Section 10.2: Thermal

given in

Table 17

above and the value for Θ

JA given in

Figure 7. f

CPUmax

versus V

DD f

CPU

(MHz)

Functionality not guaranteed in this area

2.95

Functionality guaranteed

@T A -40 to 125 °C

4.0

Supply voltage

5.0

5.5

MSv46305V1

DS12129 Rev 4 43/84

Electrical characteristics STM8S001J3

Symbol

Table 18. Operating conditions at power-up/power-down

Parameter Conditions Min Typ Max Unit

V t t

VDD

TEMP

IT+

IT-

HYS(BOR)

rise time rate

fall time rate

(1)

Reset release delay

Power-on reset threshold

Brown-out reset threshold

Brown-out reset hysteresis

rising

2.6

2.5

2.7

2.65

∞

1.7

2.85

2.8

1. Reset is always generated after a t minimum operating voltage (V

delay. The application must ensure that V

min) when the t

TEMP delay has elapsed.

is still above the

µs/V ms

V mV

9.3.2

Stabilization for the main regulator is achieved connecting an external capacitor C

EXT

CAP

pin. C

EXT to less than 15 nH.

to the

is specified in

Table 17 . Care should be taken to limit the series inductance

Figure 8. External capacitor C

EXT

ESL

ESR

RLeak

MSv36488V1

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

Supply current characteristics

The current consumption is measured as described in

Section 9.1.5: Pin input voltage

Total current consumption in run mode

The MCU is placed under the following conditions:

• All I/O pins in input mode with a static value at V

or V

(no load)

• All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except if explicitly mentioned.

Subject to general operating conditions for V

and T

44/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Table 19. Total current consumption with code execution in run mode at V

= 5 V

Symbol Parameter Conditions Typ Max

(1)

Unit

Supply current in run mode, code executed from RAM

CPU

= f

MASTER

= 16 MHz

CPU

= f

MASTER

/128 = 125 kHz

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

1.7

0.86

0.7

CPU

= f

MASTER

15.625 kHz

/128 =

HSI RC osc. (16 MHz/8) 0.46

0.58

DD(RUN)

Supply current in run mode, code executed from Flash

CPU

= f

MASTER

= 128 kHz LSI RC osc. (128 kHz) 0.41

0.55

CPU

= f

MASTER

= 16 MHz HSE user ext. clock (16 MHz)

CPU

= f

MASTER

= 2 MHz

HSI RC osc.(16 MHz)

HSI RC osc. (16 MHz/8)

CPU

= f

MASTER

/128 = 125 kHz HSI RC osc. (16 MHz)

CPU

= f

MASTER

15.625 kHz

/128 =

HSI RC osc. (16 MHz/8)

(2)

4.3

3.7

0.84

0.72

0.46

4.75

4.5

1.05

0.9

0.58

LSI RC osc. (128 kHz) 0.42

0.57

CPU

= f

MASTER

= 128 kHz

1. Guaranteed by characterization results.

2. Default clock configuration measured with all peripherals off.

2.35

0.87

Table 20. Total current consumption with code execution in run mode at V

= 3.3 V

Symbol Parameter Conditions Typ Max

(1)

Unit

DD(RUN)

Supply current in run mode, code executed from RAM

Supply current in run mode, code executed from Flash

CPU

= f

MASTER

= 16 MHz

CPU

= f

MASTER

/128 = 125 kHz

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

1.5

0.81

0.7

2.3

0.87

CPU

= f

MASTER

15.625 kHz

/128 =

HSI RC osc. (16MHz/8) 0.46

0.58

CPU

= f

MASTER

= 128 kHz LSI RC osc. (128 kHz) 0.41

0.55

CPU

= f

MASTER

= 16 MHz

HSE user ext. clock (16 MHz)

CPU

= f

MASTER

= 2 MHz

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

CPU

= f

MASTER

/128 = 125 kHz HSI RC osc. (16 MHz)

CPU

= f

MASTER

15.625 kHz

/128 =

HSI RC osc. (16 MHz/8)

(2)

3.9

3.7

0.84

0.72

0.46

4.7

4.5

1.05

0.9

0.58

LSI RC osc. (128 kHz) 0.42

0.57

CPU

= f

MASTER

= 128 kHz

1. Guaranteed by characterization results.

2. Default clock configuration, measured with all peripherals off.

DS12129 Rev 4 45/84

Electrical characteristics STM8S001J3

Total current consumption in wait mode

Table 21. Total current consumption in wait mode at V

= 5 V

Symbol Parameter Conditions Typ Max

(1)

Unit

DD(WFI)

Supply current in wait mode

HSE user ext. clock (16 MHz) 1.1

CPU

= f

MASTER

= 16 MHz

HSI RC osc. (16 MHz)

CPU

= f

MASTER

/128 = 125 kHz HSI RC osc. (16 MHz)

CPU

= f

MASTER

/128 =

15.625 kHz

HSI RC osc. (16 MHz/8)

(2)

0.89

0.7

0.45

CPU

= f

MASTER

= 128 kHz

1. Guaranteed by characterization results.

2. Default clock configuration measured with all peripherals off.

LSI RC osc. (128 kHz) 0.4

1.3

1.1

0.88

0.57

0.54

Table 22. Total current consumption in wait mode at V

= 3.3 V

Symbol Parameter Conditions Typ Max

(1)

DD(WFI)

Supply current in wait mode

HSE user ext. clock (16 MHz) 1.1

CPU

= f

MASTER

= 16 MHz

CPU

= f

MASTER

15.625 kHz

/128 =

HSI RC osc. (16 MHz)

CPU

= f

MASTER

/128 = 125 kHz HSI RC osc. (16 MHz)

CPU

= f

MASTER

15.625 kHz

/128 =

HSI RC osc. (16 MHz/8)

(2)

LSI RC osc. (128 kHz)

0.89

0.7

0.45

0.4

1.3

1.1

0.88

0.57

0.54

1. Guaranteed by characterization results.

2. Default clock configuration measured with all peripherals off.

Unit mA

46/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Total current consumption in active halt mode

Symbol

DD(AH)

Table 23. Total current consumption in active halt mode at V

= 5 V

Conditions

Parameter

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Typ

Max at

85 ° C

(1)

Max at

125 ° C

(1)

Supply current in active halt mode

Operating mode

Power-down mode

Off

Operating mode

Power-down mode

1. Guaranteed by characterization results.

2. Configured by the REGAH bit in the CLK_ICKR register.

3. Configured by the AHALT bit in the FLASH_CR1 register.

HSE user external clock

(16 MHz)

LSI RC oscillator

(128 kHz)

HSE user external clock

(16 MHz)

LSI RC oscillator

(128 kHz)

1030

200

970

150

LSI RC oscillator

(128 kHz)

260

200

300

230

110

Unit

µA

Table 24. Total current consumption in active halt mode at V

= 3.3 V

Conditions

Symbol Parameter Main voltage regulator

(MVR) (2)

Flash mode

(3)

Clock source

Typ

Max at

85°

(1)

Max at

125°

(1)

Unit

Operating mode

DD(AH)

Supply current in active halt mode

Power-down mode

Off

Operating mode

Power-down mode

1. Guaranteed by characterization results.

2. Configured by the REGAH bit in the CLK_ICKR register.

3. Configured by the AHALT bit in the FLASH_CR1 register.

HSE user external clock

(16 MHz)

LSI RC osc. (128 kHz)

HSE user external clock(16 MHz)

LSI RC osc. (128 kHz)

550

970

150 200 230

66 80 105

200 260 290

µA

DS12129 Rev 4 47/84

Electrical characteristics STM8S001J3

Total current consumption in halt mode

Symbol

Table 25. Total current consumption in halt mode at V

= 5 V

Parameter Conditions Typ

Max at

85 ° C (1)

Max at

125 °

C (1)

DD(H)

Supply current in halt mode

1. Guaranteed by characterization results.

Flash in operating mode,

HSI clock after wakeup

Flash in power-down mode,

HSI clock after wakeup

6.0

105

Unit

µA

Symbol

Table 26. Total current consumption in halt mode at V

= 3.3 V

Parameter Conditions Typ

Max at

85° C

(1)

Max at

125°

(1)

DD(H)

Supply current in halt mode

Flash in operating mode, HSI clock after wakeup

Flash in power-down mode, HSI clock after wakeup

1. Guaranteed by characterization results.

4.5

100

Unit

µA

Low-power mode wakeup times

Symbol Parameter

Table 27. Wakeup times

Conditions t t t

WU(WFI)

WU(AH)

WU(H)

Wakeup time from wait mode to run mode

(3)

Wakeup time active halt mode to run mode.

(3)

0 to 16 MHz f

CPU

= f

MASTER

= 16 MHz.

MVR voltage regulator on

(4)

Flash in operating mode

(5)

Flash in power-down mode

(5)

HSI (after wakeup)

Wakeup time from halt mode to run mode

(3)

MVR voltage regulator off

(4)

Flash in operating mode

(5)

Flash in power-down mode

(5)

Flash in operating mode

(5)

Flash in power-down mode

(5)

1. Guaranteed by design.

2. t

WU(WFI)

= 2 x 1/f master

+ 7 x 1/f

CPU

3. Measured from interrupt event to interrupt vector fetch.

4. Configured by the REGAH bit in the CLK_ICKR register.

5. Configured by the AHALT bit in the FLASH_CR1 register.

6. Plus 1 LSI clock depending on synchronization.

(6)

Typ Max

(1)

Unit

0.56

(2)

(6)

µs

48/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Total current consumption and timing in forced reset state

Symbol

DD(R)

Table 28. Total current consumption and timing in forced reset state

Parameter Conditions Typ Max

(1)

Unit

Supply current in reset state

(2)

= 5 V

= 3.3 V

400

300

µA

µs t

RESETBL

Reset release to vector fetch

1. Guaranteed by design.

2. Characterized with all I/Os tied to V

150

Current consumption of on-chip peripherals

Subject to general operating conditions for V

and T

HSI internal RC/f

CPU

= f

MASTER

= 16 MHz, VDD = 5 V.

Symbol

Table 29. Peripheral current consumption

Parameter Typ.

Unit

DD(TIM1)

DD(TIM2)

TIM1 supply current

(1)

TIM2 supply current

(1)

210

130

DD(TIM4)

DD(UART1)

TIM4 timer supply current

UART1 supply current (1)

(1)

120

DD(SPI)

DD(I2C)

DD(ADC1)

SPI supply current

(1)

I2C supply current

(1)

ADC1 supply current when converting

(1)

1000

µA

1. Data based on a differential I

measurement between reset configuration and timer counter running at

16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

DS12129 Rev 4 49/84

Electrical characteristics STM8S001J3

Current consumption curves

The following figures show the typical current consumption measured with code executing in

RAM.

Figure 9. Typ. I

DD(RUN)

vs V

, HSE user external clock, f

CPU

= 16 MHz

Figure 10. Typ. I

DD(RUN)

vs f

CPU

, HSE user external clock, V

= 5 V

50/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 11. Typ. I

DD(RUN)

vs V

, HSI RC osc, f

CPU

= 16 MHz

Figure 12. Typ. I

DD(WFI)

vs. V

HSE user external clock, f

CPU

= 16 MHz

DS12129 Rev 4 51/84

Electrical characteristics STM8S001J3

Figure 13. Typ. I

DD(WFI)

vs. f

CPU

, HSE user external clock, V

= 5 V

Figure 14. Typ. I

DD(WFI)

vs V

, HSI RC osc, f

CPU

= 16 MHz

52/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

HSE user external clock

Subject to general operating conditions for V

and T

Symbol

Table 30. HSE user external clock characteristics

Parameter Conditions f

HSE_ext

HSEH

(1)

User external clock source frequency

OSCIN input pin high level voltage

HSEL

(1)

OSCIN input pin low level voltage

LEAK_HSE

OSCIN input leakage current

1. Guaranteed by characterization results.

< V

Min

0.7 x V

-1

Typ

Max

+ 0.3 V

0.3 x V

Unit

MHz

µA

Figure 15. HSE external clock source

VHSEH

V HSEL

External clock source

OSCIN fHSE

STM8

MS36489V2

DS12129 Rev 4 53/84

Electrical characteristics

9.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for V

and T

High speed internal RC oscillator (HSI)

Symbol

Table 31. HSI oscillator characteristics

Parameter Conditions

ACC

HSI t f

HSI su(HSI)

Frequency -

Accuracy of HSI oscillator

User-trimmed with the

CLK_HSITRIMR register for given V and T

A conditions

Accuracy of HSI oscillator

(factory calibrated)

= 5 V, T

= 25 °C

= 5 V,

-40 °C ≤ T

≤ 125 °C

HSI oscillator wakeup time including calibration

DD(HSI)

HSI oscillator power consumption

1. See the application note.

2. Guaranteed by design.

3. Guaranteed by characterization results.

Min

-2.0

(2)

-7.5

(3)

-5

Typ

STM8S001J3

170 250

(3)

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for V

and T

Symbol

Table 32. LSI oscillator characteristics

Parameter Conditions f

LSI t su(LSI)

DD(LSI)

Frequency -

LSI oscillator wakeup time

LSI oscillator power consumption

1. Guaranteed by design.

Min

Typ

128

Max

3.25

(2)

7.5

(3)

1.0

(2)

Max

(1)

Unit

MHz

µs

µA

Unit kHz

µs

µA

54/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 16. Typical LSI frequency variation vs V

@ 4 temperatures

DS12129 Rev 4 55/84

Electrical characteristics STM8S001J3

RAM and hardware registers

Table 33. RAM and hardware registers

Symbol Parameter Conditions Min Unit

Data retention mode

(1)

Halt mode (or reset) V

IT-max

(2)

1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design.

2. Refer to Table 18 on page 44

for the value of V

IT-max

Flash program memory and data EEPROM

General conditions: T

= -40 to 85 °C.

Symbol

Table 34. Flash program memory and data EEPROM

Parameter Conditions Min

(1)

Typ Max Unit t t t

DD prog erase

RET

Operating voltage

(all modes, execution/write/erase)

Standard programming time (including erase) for byte/word/block

(1 byte/4 bytes/64 bytes)

Fast programming time for 1 block (64 bytes)

Erase time for 1 block (64 bytes)

Erase/write cycles

(2)

(program memory)

Erase/write cycles

(2)

(data memory)

Data retention (program memory) after 100 erase/write cycles at

= 85 °C

Data retention (data memory) after

10 k erase/write cycles at T

= 85 °C

Data retention (data memory) after

100 k erase/write cycles at

= 125 °C

Supply current (Flash programming or erasing for 1 to 128 bytes) f

CPU

≤ 16 MHz

RET

85 °C

= 55° C

= 85° C

2.95

100

100 k

1.0

6.0

3.0

2.0

5.5

6.6

3.3

1. Guaranteed by characterization results.

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

V ms ms ms cycles years mA

56/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

9.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

and T

unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Symbol Parameter

Table 35. I/O static characteristics

Conditions Min Typ Max Unit

V hys

R pu t

, t

Input low level voltage

Input high level voltage

Hysteresis

(1)

Pull-up resistor

Rise and fall time

(10% - 90%)

= 5 V

= 5 V, V

= V

Fast I/Os

Load = 50 pF

Standard and high sink I/Os

Load = 50 pF

-0.3

0.7 x V

0.3 x V

+ 0.3 V

700 -

55 80

(2)

V mV k Ω ns

125

(2)

I lkg lkg ana lkg(inj)

Input leakage current, analog and digital

Analog input leakage current

Leakage current in adjacent I/O

≤

Injection current ±4 mA -

1. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

2. Guaranteed by design.

3. Guaranteed by characterization results.

±1

±250

±1

(3)

µA nA

µA

DS12129 Rev 4 57/84

Electrical characteristics

Figure 17. Typical V

and V

vs V

@ 4 temperatures

STM8S001J3

Figure 18. Typical pull-up resistance vs V

@ 4 temperatures

58/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 19. Typical pull-up current vs V

@ 4 temperatures

1. The pull-up is a pure resistor (slope goes through 0).

Symbol

Table 36. Output driving current (standard ports)

Parameter Conditions

Output low level with 8 pins sunk I

= 10 mA, V

= 5 V

Output low level with 4 pins sunk I

= 4 mA, V

= 3.3 V

Output high level with 8 pins sourced I

= 10 mA, V

= 5 V

Output high level with 4 pins sourced I

= 4 mA, V

= 3.3 V

1. Guaranteed by characterization results.

Min

2.8

2.1

(1)

Symbol

Table 37. Output driving current (true open drain ports)

Parameter Conditions Max

Output low level with 2 pins sunk

= 10 mA, V

= 5 V

= 10 mA, V

= 3.3 V

= 20 mA, V

= 5 V

1.5

(1)

1. Guaranteed by characterization results.

Max

(1)

Unit

DS12129 Rev 4 59/84

Electrical characteristics STM8S001J3

Symbol

Table 38. Output driving current (high sink ports)

Parameter

Output low level with 8 pins sunk

Output low level with 4 pins sunk

Output high level with 8 pins sourced

Output high level with 4 pins sourced

1. Guaranteed by characterization results.

Conditions

= 10 mA, V

= 5 V

= 10 mA, V

= 3.3 V

= 20 mA, V

= 5 V

= 10 mA, V

= 5 V

= 10 mA, V

= 3.3 V

= 20 mA, V

= 5 V

Min

4.0

2.1

(1)

3.3

(1)

Max

0.8

1.0

(1)

1.5

(1)

Unit

Typical output level curves

Figure 21

to Figure 28

show typical output level curves measured with output on a single pin.

Figure 20. Typ. V

@ V

= 5 V (standard ports)

60/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 21. Typ. V

@ V

= 3.3 V (standard ports)

Figure 22. Typ. V

@ V

= 5 V (true open drain ports)

DS12129 Rev 4 61/84

Electrical characteristics

Figure 23. Typ. V

@ V

= 3.3 V (true open drain ports)

STM8S001J3

Figure 24. Typ. V

@ V

= 5 V (high sink ports)

62/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 25. Typ. V

@ V

= 3.3 V (high sink ports)

Figure 26. Typ. V

DD -

@ V

= 5 V (standard ports)

DS12129 Rev 4 63/84

Electrical characteristics

Figure 27. Typ. V

DD -

@ V

= 3.3 V (standard ports)

STM8S001J3

Figure 28. Typ. V

DD -

@ V

= 5 V (high sink ports)

64/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 29. Typ. V

DD -

@ V

= 3.3 V (high sink ports)

9.3.7 SPI serial peripheral interface

Unless otherwise specified, the parameters given in

Table 39 are derived from tests

performed under ambient temperature, f

MASTER conditions. t

MASTER

= 1/f

MASTER

frequency and V

supply voltage

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 39. SPI characteristics

Conditions f

SCK

1/t c(SCK) t r(SCK) t f(SCK) t su(NSS)

(1) t h(NSS)

(1) t t w(SCKH)

(1) w(SCKL)

(1) t t su(MI)

(1) su(SI)

(1)

SPI clock frequency

Master mode

Slave mode

SPI clock rise and fall time Capacitive load: C = 30 pF

NSS setup time

NSS hold time

SCK high and low time

Data input setup time t t h(MI)

(1)

(1) h(SI) t a(SO)

(1)(2) t dis(SO)

(1)(3) t v(SO)

(1)

Data input hold time

Data output access time

Data output disable time

Data output valid time

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Slave mode (after enable edge)

Min

4 x t

MASTER

Max

5 t

SCK

/2 - 15 t

SCK

/2 + 15

3 x t

MASTER

Unit

MHz ns

DS12129 Rev 4 65/84

Electrical characteristics STM8S001J3

Symbol Parameter

Table 39. SPI characteristics (continued)

Conditions Min Max Unit t v(MO)

(1) t h(SO)

(1) t h(MO)

(1)

Data output valid time

Data output hold time

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

1. Values based on design simulation and/or characterization results, and not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Figure 30. SPI timing diagram - slave mode and CPHA = 0

Figure 31. SPI timing diagram - slave mode and CPHA = 1 (1)

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

DD.

ai14135b

66/84 DS12129 Rev 4

STM8S001J3

Figure 32. SPI timing diagram - master mode

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

DD.

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

9.3.8 I2C interface characteristics

Symbol

Table 40. I2C characteristics

Parameter t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA) t su(STA) t su(STO)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

Repeated START condition setup time

STOP condition setup time

Standard mode I2C

Min

(2)

4.7

4.0

250

0 (3)

Max

(2)

1000

Fast mode

I2C

(1)

Min

(2)

Max

(2)

1.3

0.6

100

0 (4)

900 (3)

Unit

µs

300 ns

4.0

4.7

4.0

300

0.6

300

µs

DS12129 Rev 4 67/84

Electrical characteristics STM8S001J3

Table 40. I2C characteristics (continued)

Symbol Parameter

Standard mode I2C

Fast mode

I2C

(1)

Min

(2)

Max

(2)

Unit

Min

(2)

Max

(2) t w(STO:STA)

STOP to START condition time

(bus free)

4.7

1.3

µs

C b

Capacitive load for each bus line 400 400

1. f

MASTER

, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)

2. Data based on standard I2C protocol requirement, not tested in production

3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL pF

I²C bus

Figure 33. Typical application with I2C bus and timing diagram

VDD VDD

4.7 kΩ 4.7 kΩ

STM8

100 Ω

SDA

SCL

100 Ω

S TART REPEATED

S TART tsu(STA)

S TART

SDA tf(SDA) th(STA) tr(SDA) tw(SCLL) tsu(SDA) th(SDA)

S TOP tsu(STA:STO)

SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai17490V2

1. Measurement points are made at CMOS levels: 0.3 x V

and 0.7 x V

68/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Subject to general operating conditions for V

DDA specified.

, f

MASTER

, and T

unless otherwise

Symbol Parameter

Table 41. ADC characteristics

Conditions Min Typ Max Unit

DDA

= 3 to 5.5 V 1 4 f

ADC

ADC clock frequency MHz

AIN

BGREF

Conversion voltage range

(1)

Internal bandgap reference voltage

DDA

= 4.5 to 5.5 V

DDA

2.95 to 5.5 V

1.19

1.22

1.25

ADC

Internal sample and hold capacitor

3 pF t

(1)

Sampling time f

ADC

= 4 MHz f

ADC

= 6 MHz

0.75

0.5

µs t

STAB

Wakeup time from standby 7 µs t

CONV

Total conversion time (including sampling time, 10-bit resolution) f

ADC

= 4 MHz f

ADC

= 6 MHz

3.5

2.33

µs

14 1/f

ADC

1. During the sample time the input capacitance C

AIN

(3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t

After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t

depend on programming.

DS12129 Rev 4 69/84

Electrical characteristics

70/84

STM8S001J3

Symbol

Table 42. ADC accuracy with R

AIN

< 10 k Ω , V

= 5 V

Parameter Conditions Typ Max

(1)

Unit

| Total unadjusted error

Offset error

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2) f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz

1.6

2.2

2.4

1.1

1.5

1.8

1.5

2.1

2.2

0.7

0.6

0.8

3.5

4.5

2.5

1.5

LSB

1. Guaranteed by characterization results.

2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I

Σ I

INJ(PIN)

Section 9.3.6

does not affect the ADC accuracy.

INJ(PIN)

and

Symbol

Table 43. ADC accuracy with R

AIN

< 10 k Ω R

AIN

, V

= 3.3 V

Parameter Conditions Typ Max

(1)

Unit

| Total unadjusted error

Offset error

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2) f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz

1.6

1.9

1.5

1.3

0.7

0.6

0.8

3.5

2.5

1.0

1.5

LSB

1. Guaranteed by characterization results.

Σ I

INJ(PIN)

Section 9.3.6

does not affect the ADC accuracy.

INJ(PIN)

and

DS12129 Rev 4

STM8S001J3 Electrical characteristics

Figure 34. ADC accuracy characteristics

1023

1022

1021

1LSBIDEAL =

1024

1 LSB

IDEAL

SSA

1 2 3 4 5 6 7

(2)

(3)

(1)

1021102210231024

DDA

1. Example of an actual transfer curve.

2. The ideal transfer curve

3. End point correlation line

= Differential linearity error: maximum deviation between actual steps and the ideal one.

= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

= Offset error: deviation between the first actual transition and the first ideal one.

= Gain error: deviation between the last ideal transition and the last actual one.

Figure 35. Typical application with ADC

0.6V

STM8

AIN AINx

AIN

10-bit A/D conversion

AIN

0.6V

±1µA

ADC

DS12129 Rev 4 71/84

Electrical characteristics STM8S001J3

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Parameter

Table 44. EMS data

Symbol Conditions Level/class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance f

= 3.3 V, T

MASTER

= 25 °C,

= 16 MHz, conforming to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100pF on V

and V

SS pins to induce a functional disturbance f

= 3.3 V, T

MASTER

= 25 °C,

= 16 MHz, conforming to IEC 61000-4-4

TBD

1. Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 -

EMC guidelines for STM8Smicrocontrollers.

(1)

72/84 DS12129 Rev 4

STM8S001J3 Electrical characteristics

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. Emission tests conform to the IEC

61967-2 standard for test software, board layout and pin loading.

Table 45. EMI data

Conditions

Symbol Parameter

General conditions

EMI

Peak level

= 5 V

25 °C

SO8N package conforming to IEC

61967-2

EMI level

1. Guaranteed by characterization results.

Monitored frequency band

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

Max f

HSE

CPU

(1)

16 MHz/

8 MHz

16 MHz/

16 MHz

TBD

Unit dBµV

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (one positive then one negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: the Human Body Model (HBM). This test conforms to the JESD22-

A114A/A115A standard. For more details, refer to the application note AN1181.

Symbol

Table 46. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(Human body model)

Electrostatic discharge voltage

(Charge device model)

1. Guaranteed by characterization results.

= 25°C, conforming to

JESD22-A114

= 25°C, conforming to

JESD22-C101

TBD

DS12129 Rev 4 73/84

Electrical characteristics STM8S001J3

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance:

• A supply overvoltage (applied to each power supply pin)

• A current injection (applied to each input, output and configurable I/O pin) is performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter

Table 47. Electrical sensitivities

Conditions Class

(1)

LU Static latch-up class

= 25 °C

= 85 °C

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

74/84 DS12129 Rev 4

STM8S001J3 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

ECOPACK is an ST trademark.

Failure analysis and guarantee

The small number of pins available induces limitations on failure analysis depth in case of isolated symptoms, typically with an impact lower than 0.1%. Please contact your sales office for additional information for any failure analysis. STMicroelectronics makes a feasibility study for investigation based on failure rate and symptom description prior to responsibility endorsement.

10.1 SO8N package information

Figure 36. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline

1. Drawing not to scale.

Table 48. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

A2 b c

0.100

1.250

0.280

0.170

1.750

0.250

0.480

0.230

0.0039

0.0492

0.0110

0.0067

0.0689

0.0098

0.0189

0.0091

DS12129 Rev 4 75/84

Package information STM8S001J3

Table 48. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

L e h

L1 ccc

4.800

5.800

3.800

0.250

0°

0.400

4.900

6.000

3.900

1.270

1.040

5.000

6.200

4.000

0.500

8°

1.270

0.100

1. Values in inches are converted from mm and rounded to four decimal digits.

0.1890

0.2283

0.1496

0.0098

0°

0.0157

0.1929

0.2362

0.1535

0.0500

0.0409

0.1969

0.2441

0.1575

0.0197

8°

0.0500

0.0039

Figure 37. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint

0.6 (x8)

76/84

1.27

O7_FP_V1

DS12129 Rev 4

STM8S001J3 Package information

Device marking for SO8N

– 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width

The following figure gives an example of topside marking orientation versus pin 1/ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 38. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, marking example

Product identification

8S001J3

R Y WW

Date code

Unmarkable surface

PIN1 reference

Additional information

MSv17033v1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS12129 Rev 4 77/84

Package information STM8S001J3

The maximum chip junction temperature (T

Jmax

Table 17: General operating conditions .

) must never exceed the values given in

The maximum chip-junction temperature, T

Jmax using the following equation:

, in degrees Celsius, may be calculated

Jmax

= T

Amax

+ (P

Dmax

x Θ

)

Where:

• T

Amax

is the maximum ambient temperature in ° C

• Θ

is the package junction-to-ambient thermal resistance in ° C/W

• P

Dmax

is the sum of P

INTmax

and P

I/Omax

Dmax

= P

INTmax

+ P

I/Omax

)

• P

INTmax

is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

• P

I/Omax

represents the maximum power dissipation on output pins, where:

= Σ (V

-V

OH)

*I ) + Σ ((V

DD OH

), and taking account of the actual V of the I/Os at low and high level in the application.

OL and

Symbol

Table 49. Thermal characteristics (1)

Parameter Value

Thermal resistance junction-ambient

SO8N

102

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

Unit

°C/W

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.

10.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 39: STM8S001J3 ordering information scheme

(1)

The following example shows how to calculate the temperature range needed for a given application.

Assuming the following application conditions:

• Maximum ambient temperature T

Amax

= 75 °C (measured according to JESD51-2)

• I

DDmax

= 8 mA, V

= 5.0 V

• Maximum 4 I/Os used at the same time in output at low level with

= 8 mA, V

= 0.4 V

INTmax =

8 mA x 5.0 V = 40 mW

Dmax

= 40 mW + (8 x 0.4 x 4) mW

Thus: P

Dmax

= 52.8 mW

78/84 DS12129 Rev 4

STM8S001J3 Package information

Using the values obtained in Section Table 49.: Thermal characteristics

Jmax as follows for SO8N package 102 °C/W :

is calculated

Jmax

= 75 °C + (102 °C/W x 52.8 mW) = 75 °C + 5.4 °C = 80.4 °C.

Above information is within the range (-40 < T

< 130 °C)

DS12129 Rev 4 79/84

Ordering information STM8S001J3

Example:

Figure 39. STM8S001J3 ordering information scheme (1)

STM8 S 001 J 3 M 3

Product class

STM8 microcontroller

Family type

S = standard

Sub-family type

001 = low density

Pin count

J = 8 pins

Program memory size

3 = 8 Kbyte

Package type

M =SO8N

Temperature range

3 = -40°C to 125°C

Packing

No character = tube

TR = Tape and reel

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com

or contact the nearest ST Sales Office.

80/84 DS12129 Rev 4

STM8S001J3

12 STM8 development tools

STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the

STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition,

STM8 application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.

STice key features

• Occurrence and time profiling and code coverage (new features)

• Advanced breakpoints with up to 4 levels of conditions

• Data breakpoints

• Program and data trace recording up to 128 KB records

• Read/write on the fly of memory during emulation

• In-circuit debugging/programming via SWIM protocol

• 8-bit probe analyzer

• 1 input and 2 output triggers

• Power supply follower managing application voltages between 1.62 to 5.5 V

• Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements

• Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

DS12129 Rev 4 81/84

STM8 development tools STM8S001J3

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual

Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to Kbytes of code is available.

STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com

. This package includes:

ST Visual Develop – Full-featured integrated development environment from ST, featuring

• Seamless integration of C and ASM toolsets

• Full-featured debugger

• Project management

• Syntax highlighting editor

• Integrated programming interface

• Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify the user STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface.

Available toolchains include:

• Cosmic C compiler for STM8 – One free version that outputs up to Kbytes of code is available. For more information, see www.cosmic-software.com.

• Raisonance C compiler for STM8 – One free version that outputs up to Kbytes of code. For more information, see www.raisonance.com.

• STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows users to assemble and link the user application source code.

82/84

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8.

For production environments, programmers include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

DS12129 Rev 4

STM8S001J3 Revision history

Date

24-May-2017

29-Jun-2017

28-Jun-2018

26-Aug-2020

Revision

Table 50. Document revision history

Changes

Initial release.

Updated:

– Section 10: Package information

– Figure 3: STM8S001J3 SO8N pinout

– Table 5: STM8S001J3 pin description

– Table 13: STM8S001J3 alternate function remapping bits for 8-pin devices

Added:

Device marking for SO8N – 8-lead 4.9 x 6 mm, plastic small outline,

150 mils body width

Updated:

– Analog to digital converter (ADC) on cover page

– Recommendation for SWIM pin (pin #8) sharing on Section 4.2

– Section 4.12: Analog-to-digital converter (ADC1)

– Table 5: STM8S001J3 pin description

– Table 13: STM8S001J3 alternate function remapping bits for 8-pin devices

– Table 41: ADC characteristics

Updated:

–

Table 47: Electrical sensitivities

–

Table 31: HSI oscillator characteristics

Removed figure Typical HSI frequency variation vs V temperatures.

at four

DS12129 Rev 4 83/84

STM8S001J3

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84/84 DS12129 Rev 4

16 MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data

EEPROM, 10-bit ADC, 3 timers, UART, SPI, I2C

Features

Core

Memories

Clock, reset and supply management

Interrupt management

Timers

Communications interfaces

Analog to digital converter (ADC)

I/Os

Development support

Contents

List of tables

List of figures

1 Introduction

2 Description

Architecture and registers

Addressing

Instruction set

4.2

Single wire interface module (SWIM) and debug module (DM)

SWIM

Debug module

Recommendation for SWIM pin (pin #8) sharing

4.4

Flash program memory and data EEPROM

Write protection (WP)

Read-out protection (ROP)

Recommendation for the device's programming:

Features

Window watchdog timer

Independent watchdog timer

4.8

4.9

Auto wakeup counter

TIM1 - 16-bit advanced control timer

4.10 TIM2 - 16-bit general purpose timer

4.11 TIM4 - 8-bit basic timer

4.12 Analog-to-digital converter (ADC1)

Internal bandgap reference voltage

Main features

Asynchronous communication (UART mode)

LIN master mode

5 Pinouts and pin descriptions

5.1 STM8S001J3 SO8N pinout and pin description

6 Memory and register map

7 Interrupt vector mapping

9.2 Absolute maximum ratings

Total current consumption in run mode

Total current consumption in wait mode

Total current consumption in active halt mode

Total current consumption in halt mode

Low-power mode wakeup times

Total current consumption and timing in forced reset state

Current consumption of on-chip peripherals

Current consumption curves

HSE user external clock

High speed internal RC oscillator (HSI)

Low speed internal RC oscillator (LSI)

RAM and hardware registers

Flash program memory and data EEPROM

General characteristics

Typical output level curves

Functional EMS (electromagnetic susceptibility)

Designing hardened software to avoid noise problems

Electromagnetic interference (EMI)

Absolute maximum ratings (electrical sensitivity)

Electrostatic discharge (ESD)

Static latch-up

Failure analysis and guarantee

10.1 SO8N package information

Device marking for SO8N

12 STM8 development tools

STice key features

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