STMicroelectronics STA380WS Datasheet
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STA380WS
Sound Terminal
®
2-channel high-efficiency digital audio system
Datasheet
-
production data
VQFN48 package with exposed pad down (EPD)
Thermal-overload and short-circuit protection embedded
Video application: 576 * f
S
input mode support
Applications
Features
LCDs
Wide-range supply voltage (4.5 V - 20 V)
2 channels of ternary PWM (stereo mode)
2 channels of 24-bit FFX
100-dB SNR and dynamic range
DVDs
Cradles
Digital speakers
Wireless-speaker cradles
Selectable 32- to 192-kHz input sample rates
I
2
C control with selectable device address
Description
Digital gain -80 dB to +48 dB in 0.5-dB steps
Software volume update
Individual channel and master gain/attenuation
The STA380WS is an integrated circuit comprising digital audio processing, digital amplifier control and FFX power output stage to create a high-power, single-chip FFX solution for all-digital amplification with high quality and high efficiency.
Individual channel and master software and hardware mute
Independent channel volume bypass The STA380WS power section can provide up to
20 W + 20 W BTL output power.
Automatic zero-detect mute
Automatic invalid input detect mute
2-channel I
2
S input data Interface
Selectable clock input ratio
Also provided in the STA380WS are new advanced AM radio interference reduction modes. The serial audio data input interface
I accepts all possible formats, including the popular
2 S format.
Input channel mapping
The STA380WS is part of the 2-channel high Automatic volume control for limiting maximum
power
Obsolete Product(s) - Obsolete Product(s) precision efficiency digital audio system family that provides full digital audio streaming to the speaker offering cost effectiveness, low power dissipation and sound enrichment.
Advanced AM interference frequency switching and noise suppression modes
Table 1. Device summary
Package Order code Packaging
STA380WS
STA380WS13TR
VQFN48 EPD
VQFN48 EPD
Tray
Tape and reel
April 2013
This is information on a product in full production.
DocID024426 Rev 1 1/48 www.st.com
48
STA380WS
Contents
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/48 DocID024426 Rev 1
STA380WS
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 23
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Volume control registers (addr 0x06 to 0x09) . . . . . . . . . . . . . . . . . . . . . . 33
Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 33
Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel volume (addr 0x08, 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Automode register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Channel configuration registers (addr 0x0E, 0x0F) . . . . . . . . . . . . . . . . . 36
Variable max power correction registers (addr 0x27, 0x28) . . . . . . . . . . . 36
Variable distortion compensation registers (addr 0x29, 0x2A) . . . . . . . . . 37
Fault detect recovery constant registers (addr 0x2B, 0x2C) . . . . . . . . . . 37
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) . . . . . . . . . . . . . . . . . 38
Postscale registers (addr 0x32, 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Output limit register (addr 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal and overcurrent warning output limit register . . . . . . . . . . . . . . 39
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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STA380WS
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4/48 DocID024426 Rev 1
List of tables STA380WS
List of tables
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DocID024426 Rev 1 5/48
List of figures
List of figures
STA380WS
S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
= 12 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
= 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CC
= 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
= 18 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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6/48 DocID024426 Rev 1
STA380WS
I
2
S interface
PLL
Digital DSP
I
2
C
Figure 1. Block diagram
Protection current/thermal
Channel
1A
Volume control
FFX
Power control
Logic
Channel
1B
Channel
2A
Regulators
Bias
Channel
2B
Power
Block diagram
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Pin description
2.1 Pinout
Figure 2. Pin connections (package top view)
STA380WS
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A 10
GND_REG 11
VDD_REG 12
7
8
9
5
6
3
4
1
2
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36 SCL
35 SDA
34 INT_LINE
33 RESET
32 SDI
31 LRCKI
30
29
BICKI
XTI
28 GND_PLL
27 FILTER_PLL
26 VDD_PLL
25 PWRDN
8/48 DocID024426 Rev 1
STA380WS Pin description
26
27
28
29
30
31
Number
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
21
22
23
24
17
18
19
20
Type
-
-
-
-
PWR
O
PWR
PWR
I/O
I/O
O
PWR
PWR
O
O
PWR
-
-
-
PWR
-
-
PWR
PWR
I
I
I
I
PWR
I
PWR
Name
Table 2. Pin description
Description
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
N.C.
N.C.
N.C.
N.C.
GND1
OUT1A
GND_REG
VDD_REG
N.C.
GND_DIG
N.C.
N.C.
N.C.
N.C.
VDD_DIG
GND_DIG
PWRDN
VDD_PLL
FILTER_PLL
GND_PLL
XTI
BICKI
LRCKI
Internal reference at V
CC
- 3.3 V
Internal V
CC
reference
Output half-bridge 2B
Power negative supply
Power positive supply
Output half-bridge 2A
Output half-bridge 1B
Power positive supply
Power negative supply
Output half-bridge 1A
Internal ground reference
Internal 3.3-V reference voltage
No internal connection
No internal connection
No internal connection
No internal connection
No internal connection
Digital ground
No internal connection
No internal connection
No internal connection
No internal connection
Positive supply digital
Digital ground
Power down:
0: power stage is switched off then the PLL is also switched off (this operation takes 13 million clock cycles)
1: normal operation
Positive supply for PLL
Connection to PLL filter
Negative supply for PLL
PLL input clock, 256 * f
S
, or 384 * f
S
I
2
S serial clock
I
2
S left/right clock
DocID024426 Rev 1 9/48
Pin description STA380WS
-
45
46
47
48
41
42
43
44
37
38
39
40
34
35
36
-
-
-
-
-
-
-
I
I
O
I
I/O
PWR
PWR
-
PWR
Number
32 I
Type
33 I
INT_LINE
SDA
SCL
GND_DIG
VDD_DIG
N.C.
GND_SUB
N.C.
N.C.
N.C.
N.C.
SA
TEST_MODE
N.C.
N.C.
SDI
EP
Table 2. Pin description (continued)
Name Description
RESET
I
2
S serial data channel
Reset:
0: reset state, power stage is switched off, all registers are set to default value
1: normal operation
Fault interrupt
I
2
C serial data
I
2
C serial clock
Digital ground
Digital supply
No internal connection
Substrate ground
I
2
C select address
This pin must be connected to ground
No internal connection
No internal connection
No internal connection
No internal connection
No internal connection
No internal connection
Exposed pad for ground-plane heatsink, to be connected to GND
Note: To increase thermal dissipation, all N.C. (no internal connection) pins must be connected to
GND.
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10/48 DocID024426 Rev 1
STA380WS Electrical specifications
3.1 Absolute maximum ratings
Symbol
V
CC
V
DD
I
L
T op
T stg
Table 3. Absolute maximum ratings
Parameter
Analog supply voltage (pins VCCx)
Digital supply voltage (pins VDD_DIG)
Logic input interface
Operating junction temperature
Storage temperature
Min Typ Max Unit
-
-
-0.3
-
0 -
-40 -
-
23
4.0
4.0
150
150
V
V
V
°C
°C
Warning: Stresses beyond those listed in
Table 3: Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
Table 5: Recommended operating conditions are not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, a power supply with nominal value rated within the limits of the recommended operating conditions, may rise beyond the maximum operating conditions for a short time when no or very low current is being sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.
Table 4. Thermal data
Symbol
R
Th(j-case)
Parameter
Thermal resistance junction to case (thermal pad) -
Min Typ Max Unit
- 1.5
°C/W
T sd
Thermal-shutdown junction temperature 140 150 160 °C
T w
T hsd
Thermal-warning temperature
Thermal-shutdown hysteresis
-
18
130 -
20 22
°C
°C
DocID024426 Rev 1 11/48
Electrical specifications
3.3 Recommended operating conditions
STA380WS
Symbol
V
CC
V
DD
I
L
T amb
Table 5. Recommended operating conditions
Parameter
Analog supply voltage (VCCx)
Digital supply voltage (VDD_DIG)
Logic input interface
Ambient temperature
Min Typ Max Unit
4.5
20.0
V
2.7
3.3
3.6
V
2.7
3.3
3.6
V
0 70 °C
3.4 Electrical specifications - digital section
Table 6. Electrical characteristics for digital section
Symbol Parameter Conditions Min Typ Max Unit
I il
I ih
V il
Input current, no pull-up or pull-down resistor
V i
= 0 V
V i
= V
DD
= 3.6 V
Low-level input voltage -
-
-
-
-
±10 μ A
±10 μ A
0.2 *
V
DD
V
V ih
High-level input voltage -
0.8 *
V
DD
V
V ol
Low-level output voltage I ol
= 2 mA -
0.4 *
V
DD
V
V oh
I pu
R pu
High-level output voltage
Pull-up current
Equivalent pull-up resistance
-
-
I oh
= 2 mA
-
0.8 *
V
DD
25
-
66
50 -
V
125 μ A k
3.5 Electrical specifications - power section
f
The specifications in
Table 7 below are given for the conditions V
CC
SW
= 384 kHz, T amb
= 25 °C and R
L
= 18 V, V
= 8 , unless otherwise specified.
DD
= 3.3 V,
Symbol
Po
R
l dsON dss
Parameter Conditions
Output power BTL
THD = 1%
THD = 10%
Power P-channel/N-channel
MOSFET (total bridge) ld = 1 A
Power P-channel/N-channel leakage
V
CC
= 18 V -
-
-
-
Min Typ Max Unit
16
20
-
-
W
180 250 m
10 μ A
12/48 DocID024426 Rev 1
STA380WS Electrical specifications
Symbol
Table 7. Electrical specifications for power section (continued)
Parameter Conditions Min Typ Max Unit gP gN
I
LDT
I
HDT
Power P-channel R dsON matching
Power N-channel R dsON matching
Low-current dead time
(static)
High-current dead time
(dynamic) ld = 1 A ld = 1 A
Resistive load, refer to
-
-
95
95 -
-
5
10
-
-
10
20
%
% ns ns t r t f
Rise time
Fall time
-
Resistive load, refer to
Resistive load, refer to
-
8
8
10
10 ns ns
V
CC
Supply voltage
Supply current from V
CC power down
in
PWRDN = 0
4.5
-
30 60
20 V
200 μ A
I
VCC
Supply current from V
CC operation
in
PCM input signal = -60 dBfs
Switching frequency =
384 kHz
No LC filters
30 50 mA
I
VDD_DI
G
I
LIM
I
SCP
V
OVP
V
UVP
Supply current for FFX processing (reference only)
Supply current in standby
Overcurrent limit
Short-circuit protection
Overvoltage protection threshold
Undervoltage protection threshold
-
Internal clock = 49.152 MHz 10
8 11 25 mA
Non-linear output
(1)
2.2
3.5
4.3
A
High-impedance output
(2)
2.7
3.8
5.0
A
-
30
22.9
50
3.5
4.3
V t min
THD+N -
20 30 60 Output minimum pulse width No load
Total harmonic distortion and noise
)) X stereo mode, Po = 1 W, f = 1 kHz
DR Dynamic range
Signal-to-noise ratio in ternary mode
-
A-weighted
-
-
100 Obsolete Product(s) - Obsolete Product(s)
100 dB
SNR dB
Signal-to-noise ratio in binary
A-weighted 90 mode ns
0.05
0.2
%
PSRR Power supply rejection ratio
)) X stereo mode, < 5 kHz,
V
RIPPLE
= 1 V RMS audio input = dither only
80 dB mA
V
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Electrical specifications STA380WS
Symbol
Table 7. Electrical specifications for power section (continued)
Parameter Conditions Min Typ Max Unit
X
TALK
Crosstalk
)) X stereo mode, < 5 kHz,
One channel driven at 1 W the other channel measured
80 dB
Peak efficiency in )) X mode
Po = 2 x 20 W into 8 90 %
1. The I
LIM
data is for 1 channel of BTL configuration, thus, 2 * I
on page 29 . When OCRB = 1 then I
SC
applies.
LIM
drives the 2-channel BTL configuration.
The current limit is active when OCRB = 0 (see
Table 23: Overcurrent warning detect adjustment bypass
2. The I
SCP
current limit data is for 1 channel of BTL configuration, thus, 2 * I
detect adjustment bypass on page 29 .
SCP
drives the 2-channel BTL
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14/48 DocID024426 Rev 1
STA380WS Electrical specifications
The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn-
on and turn-off.
Figure 3. Power-on sequence
No specific VCC and VDD_DIG turn-on sequence is required
VCC
VDD_DIG
XTI
RESET
PWRDN
Bit EAPD
Register 0x05
TR = minimum time between XTI master clock stable and reset removal: 1 ms
TC = minimum time between reset removal and I
2
C program sequence start: 1 ms
Clock stable means: fmax - fmin < 1 MHz
Figure 4. Power-off sequence
No specific VCC and VDD_DIG turn-off sequence is required
VCC
VDD_DIG
XTI
Register 0x07
Bit EAPD
Register 0x05
DocID024426 Rev 1 15/48
Electrical specifications
3.7 Testing
Duty cycle = 50%
INxY
M58
M57
Figure 5. Test circuit
OUTxY
Low current dead time = MAX(DTr,DTf) gnd
+Vcc
OUTxY t
DTr
R 8
Ω
DTf
+
-
V67 = vdc = Vcc/2
D03AU1458
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
STA380WS
Dut c c e=A
DTin(A)
INA
Figure 6. Current dead-time test circuit igh Current Dead ti e or Br idge app ication = ABS(DTout(A) DTin(A)) ABS(DTOUT (B) DTin(B))
V
CC
M58
M57
DTout(A)
Q1
OUTA
Q3
L67 22
C69
470nF
R oad=8
C71 470nF
L68 22
DTout(B)
OUTB
Q2
C70
470nF
Q4
M64
M63
Dut c c e A and B Fix ed to have DC output current o 4A in the direction shown in igure
Dut c c e=B
DTin(B)
INB
D0 3 AU1517
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16/48 DocID024426 Rev 1
STA380WS Functional description
Pin PWRDN (23) is used to power down the STA380WS.
PWRDN = 0 (0 V): power-down state
PWRND = 1 (V
DD
): normal operation
During the power-down sequence the output begins to mute. After the mute condition is reached, the power stage is switched off and the output becomes high impedance. Then the master clock to all internal hardware blocks is gated off. The PLL is also switched off. The complete power-down sequence takes 13 million cycles.
Note:
Pin RESET (31) is used to reset the STA380WS.
RESET = 0 (0 V): reset state
RESET = 1 (V
DD
): normal operation
When pin RESET is forced to 0, the power stage is switched off (with high-impedance output) and the master clock to all internal hardware blocks is gated off.
Reset has a higher priority than power-down.
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Functional description
4.2
4.2.1
Serial audio interface description
STA380WS
Serial audio interface protocols
The STA380WS serial audio input was designed to interface with standard digital audio components and to accept serial data formats. The STA380WS always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30).
The available formats are shown in
Table 7 and Table 8 , and set through
Configuration register B (addr 0x01) on page 25 .
Figure 7. I
2
S
LRCLKI
BICKI
SDI 1 2 3
Figure 8. Left justified n
-1 n
LRCLKI
BICKI
SDI 2 3 n 1 2 3 n
18/48 DocID024426 Rev 1
STA380WS
5 I
2
C bus specification
I 2 C bus specification
The STA380WS supports the I 2 C protocol via the input ports SCL and SDA. This protocol defines any device that sends data to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA380WS is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate).
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition.
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between the
STA380WS and the bus master.
During the data input the STA380WS samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
To start communication between the master and the STA380WS, the master must initiate a start condition. Following this, the master sends to the SDA line 8 bits (MSB first) Obsolete Product(s) - Obsolete Product(s)
The 7 most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In the STA380WS the I
2
C interface has two device addresses depending on the
SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and
0 for write mode. After a START condition the STA380WS identifies the device address on the SDA bus and if a match is found, acknowledges the identification during the 9th bit time.
The byte following the device identification byte is the internal space address.
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I 2 C bus specification STA380WS
Following the START condition the master sends a device select code with the RW bit set to 0. The STA380WS acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA380WS again responds with an acknowledgement.
In the byte write mode the master sends one data byte which is acknowledged by the
STA380WS. The master then terminates the transfer by generating a STOP condition.
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
BYTE
WRITE
MULTIBYTE
WRITE
START
START
DEV-ADDR
DEV-ADDR
ACK
Figure 9. Write mode sequence
ACK ACK
SUB-ADDR DATA IN
RW
ACK ACK ACK
SUB-ADDR DATA IN
STOP
RW
DATA IN
ACK
STOP
5.4.1
5.4.2
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to 1. The STA380WS acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA380WS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
Random address byte read
Following the START condition the master sends a device select code with the RW bit set to 0. The STA380WS acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA380WS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA380WS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
20/48 DocID024426 Rev 1
STA380WS
5.4.4
I 2 C bus specification
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA380WS. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer.
Figure 10. Read mode sequence
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
START
START
ACK
DEV-ADDR
RW
ACK
DEV-ADDR
DEV-ADDR
RW
RW=
HIGH
ACK
DATA
SUB-ADDR
DATA
NO ACK
ACK
STOP
ACK
S T A R T
DATA
DEV-ADDR
ACK
R W
ACK
DATA
DATA
NO ACK
NO ACK
STOP
SEQUENTIAL
RANDOM
READ
START
DEV-ADDR
ACK
SUB-ADDR
ACK
DEV-ADDR
ACK
DATA
ACK
STOP
DATA
ACK
DATA
NO ACK
START RW S T A R T R W STOP
Obsolete Product(s) - Obsolete Product(s)
DocID024426 Rev 1 21/48
Register description STA380WS
Addr Name D7
Table 8. Register summary
D6 D5
0x00 CONFA
0x01 CONFB
FDRB
C2IM
0x02 CONFC
OCRB
0x03 CONFD
Reserved
0x04 CONFE
0x05 CONFF
0x06 MUTE
0x07 MVOL
SVE
EAPD
MV7
0x08 C1VOL
0x09 C2VOL
0x0C AUTO
0x0E C1CFG
0x0F C2CFG
0x27 MPCC1
0x28 MPCC2
0x29 DCC1
C1V7
C2V7
MPCC15
MPCC7
DCC15
0x2A DCC2
0x2B FDRC1
0x2C FDRC2
0x2D STATUS
0x2E BIST1
0x2F BIST2
0x30 BIST3
0x31 TSTCTL
DCC7
FDRC15
FDRC7
PLLUL
TWAB
Reserved
Reserved
C1IM
Reserved
ZDE
ZCE
PWDN
MV6
C1V6
C2V6
Reserved
MPCC14
MPCC6
DCC14
DCC6
FDRC14
FDRC6
FAULT
Reserved
TWRB
Reserved
CSZ3
DCCV
ECLE
Reserved
MV5
C1V5
C2V5
Reserved
Reserved
MPCC13
MPCC5
DCC13
DCC5
FDRC13
FDRC5
UVFAULT
RO1BACT
R01BEND
D4
IR1
SAIFB
CSZ2
PWMS
LDTE
MV4
C1V4
C2V4
MPCC4
DCC12
DCC4
FDRC12
FDRC4
R5BACT
Reserved
D3
IR0
SAI3
CSZ1
Reserved
AME
BCLE
MV3
C1V3
C2V3
AMAM2
MPCC3
DCC11
DCC3
FDRC11
FDRC3
R4BACT
D2
MCS2
SAI2
CSZ0
NSBW
IDE
C2M
MV2
C1V2
C2V2
AMAM1
C1VBP
C2VBP
MPCC12 MPCC11 MPCC10
MPCC2
DCC10
DCC2
FDRC10
FDRC2
D1
MCS1
SAI1
OM1
MPC
MCS0
SAI0
OM0
MPCV
Reserved
C1M
MV1
C1V1
C2V1
AMAM0
MMUTE
MV0
C1V0
C2V0
AMAME
Reserved
Reserved
MPCC9
MPCC1
DCC9
DCC1
FDRC9
FDRC1
Reserved OCFAULT OCWARN TFAULT
D0
MPCC8
MPCC0
DCC8
DCC0
FDRC8
FDRC0
TWARN
R3BACT R2BACT R1BACT
R5BEND R4BEND R3BEND R2BEND R1BEND
R5BBAD R4BBAD R3BBAD R1BBAD R1BBAD
C1PS7 C1PS6 C1PS5 C1PS4 C1PS3 C1PS2 C1PS1 C1PS0
0x33 C2PS
0x34 OLIM
C2PS7
OLIM7
C2PS6
OLIM6
C2PS5
OLIM5
C2PS4
OLIM4
C2PS3
OLIM3
C2PS2
OLIM2
C2PS1
OLIM1
C2PS0
OLIM0
22/48 DocID024426 Rev 1
STA380WS
6.1
6.1.1
Register description
Configuration registers (addr 0x00 to 0x05)
Configuration register A (addr 0x00)
0
1
2
D7
FDRB
0
D6
TWAB
1
Master clock select
Bit R/W
R/W
R/W
R/W
D5
TWRB
1
D4
IR1
0
D3
IR0
0
D2
MCS2
0
D1
MCS1
1
D0
MCS0
1
1
1
0
RST
MCS0
MCS1
MCS2
Table 9. Master clock select
Name Description
Master clock select: Selects the ratio between the input I
2
S sample frequency and the input clock.
The STA380WS supports sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f
S
).
The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.
Input sample rate f
S
(kHz)
32, 44.1, 48
88.2, 96
00
01
IR
Table 10. MCS bits
101
576 * f
S
NA
100
128 * f
S
64 * f
S
MCS[2:0]
011
256 * f
S
128 * f
S
64 * f
S
010 001 000
384 * f
S
192 * f
S
96 * f
S
512 * f
S
256 * f
S
128 * f
S
768 * f
S
384 * f
S
192 * f
S
DocID024426 Rev 1 23/48
Register description STA380WS
Interpolation ratio select
4:3
Bit R/W
R/W 00
RST
Table 11. Interpolation ratio select
Name Description
IR [1:0]
Interpolation ratio select: Selects internal interpolation ratio based on input I
2
S sample frequency.
The STA380WS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.
Table 12. IR bit settings as a function of input sample rate
Input sample rate f
S
(kHz) IR 1 st
stage interpolation ratio
32
44.1
48
88.2
96
176.2
192
01
10
10
00
00
00
01
2-times oversampling
2-times oversampling
2-times oversampling
Pass-through
Pass-through
2-times downsampling
2-times downsampling
Thermal warning recovery bypass
5
Bit R/W
R/W 1
RST
Table 13. Thermal warning recovery
Name Description
TWRB
Thermal warning recovery bypass:
0: thermal warning recovery enabled
1: thermal warning recovery disabled
If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when the thermal warning is negative. is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears, the -3 dB output limit remains until TWRB is changed to zero or the device is reset.
24/48 DocID024426 Rev 1
STA380WS Register description
Thermal warning adjustment bypass
6
Bit R/W
R/W 1
RST
Table 14. Thermal warning adjustment
Name Description
TWAB
Thermal warning adjustment bypass:
0: thermal warning adjustment enabled
1: thermal warning adjustment disabled
The on-chip STA380WS power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block will force a -3 dB output limit (determined by TWOCL in coefficient
RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.
Fault detect recovery bypass
7
Bit R/W
R/W 0
RST
Table 15. Fault detect recovery
Name Description
FDRB
Fault detect recovery bypass:
0: fault detect recovery enabled
1: fault detect recovery disabled
The on-chip STA380WS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holding it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault detect recovery constant register (FDRC registers 0x2B, 0x2C), then toggling it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
6.1.2 Configuration register B (addr 0x01)
D7
C2IM
D6
C1IM
D5
Reserved
D4
SAIFB
D3
SAI3
D2
SAI2
D1
SAI1
D0
SAI0
1 0 0 0 0 0 0 0
DocID024426 Rev 1 25/48
Register description STA380WS
Serial audio input interface format
0
1
2
3
Bit R/W
R/W
R/W
R/W
R/W
0
0
0
0
Table 16. Serial audio input interface format
RST Name Description
SAI0
SAI1
SAI2
SAI3
Determines the interface format of the input serial digital audio interface.
Serial data interface
The STA380WS audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA380WS always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI.
Bits SAI and bit SAIFB are used to specify the serial data format. The default serial data format is I
2
S, MSB first. Available formats are shown in the tables and figure that follow.
Serial data first bit
0
1
SAIFB
MSB-first
LSB-first
Table 17. Serial data first bit
Format
32 * f
S
Table 18. Support serial audio input formats for MSB first (SAIFB = 0)
BICKI SAI [3:0]
0000
0001
0000
0001
0
0
0
0
SAIFB Interface format
I
2
S 15-bit data
Left/right justified 16-bit data
I
2
S 16- to 23-bit data
Left-justified 16- to 24-bit data
0010 0 Right-justified 24-bit data
48* f
S
0110
1010
0
0
Right-justified 20-bit data
Right-justified 18-bit data
1110 0 Right-justified 16-bit data
I
2
S 16- to 24-bit data 0000 0
64* f
S
0001
0010
0110
1010
1110
0
0
0
0
0
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
26/48 DocID024426 Rev 1
STA380WS Register description
32* f
S
48* f
S
48* f
S
64* f
S
Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI[3:0] SAIFB Interface format
1001
1101
0010
0110
1010
1110
0000
0100
1100
1110
0100
0100
1000
1100
0001
0101
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
2
S 15-bit data
Left/right justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB-first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB-first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
Obsolete Product(s) - Obsolete Product(s)
DocID024426 Rev 1 27/48
Register description STA380WS
6.1.3
Channel input mapping
6
7
Bit R/W
R/W
R/W
0
0
RST
Table 20. Channel input mapping
C1IM
C2IM
Name Description
0: processing channel 1 receives left I
2
1: processing channel 1 receives right I
S input
2
S input
0: processing channel 2 receives left I
2
1: processing channel 2 receives right I
S input
2
S input
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
Configuration register C (addr 0x02)
D7
OCRB
1
D6
Reserved
0
FFX power output mode
D5
CSZ3
0
0
1
Bit R/W
R/W
R/W
1
RST
1
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
OM1
1
D0
OM0
1
Table 21. FFX power output mode
Name Description
OM0
OM1
The FFX power output mode selects the configuration of the FFX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
FFX compensation pulse size register
RST
Table 22. FFX compensating pulse size
Name Description Bit R/W
2 R/W 1 CSZ0 When OM[1:0] = 11, this register determines the size of
3
4
R/W
R/W
0
1
CSZ1
CSZ2 the FFX compensating pulse from 0 to 15 clock periods:
Obsolete Product(s) - Obsolete Product(s) size
.....
5 R/W 0 CSZ3
1111: 300 ns (15 ticks) clock period compensating pulse size
28/48 DocID024426 Rev 1
STA380WS Register description
Overcurrent warning detect adjustment bypass
7
Bit R/W
Table 23. Overcurrent warning detect adjustment bypass
RST Name Description
R/W 1 OCRB
0: overcurrent warning adjustment enabled
1: overcurrent warning adjustment disabled
6.1.4
The status bit OCWARN warns that an overcurrent condition is present. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning volume adjustment is applied, it remains applied until the device is reset. The overcurrent limit can be changed via register OLIM (
Configuration register D (addr 0x03)
D7
Reserved
0
D6
ZDE
1
D5
Zero-detect mute enable
0
6
Bit R/W
R/W 1
RST
D4
0
D3
Reserved
D2
0 0
D1
0
Table 24. Zero detect mute enable
Name Description
ZDE 1: enable the automatic zero-detect mute
D0
0
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of f
S that individual channel is muted if this function is enabled.
), then
6.1.5 Configuration register E (addr 0x04)
D7
SVE
1
D6
ZCE
1
D5
DCCV
0
D4
PWMS
0
D3
AME
0
D2
NSBW
0
D1
MPC
1
D0
MPCV
0
0
Bit R/W
R/W 0
RST
Table 25. Max power correction variable
Name Description
MPCV
0: use standard MPC coefficient
1: use MPCC bits for MPC coefficient
DocID024426 Rev 1 29/48
Register description STA380WS
Max power correction
1
Bit R/W
R/W 1
RST
Table 26. Max power correction
Name Description
MPC
1: enable power bridge correction for THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA380WS power device at high power. This mode lowers the THD+N of a full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1:0] = 01) and binary. When OCFG = 00, MPC does not affect channels 3 and 4, the line-out channels.
Noise-shaper bandwidth selection
2
Bit R/W
R/W 0
Table 27. Noise-shaper bandwidth selection
RST Name Description
NSBW
1: 3 rd
order NS
0: 4 th
order NS
AM mode enable
3
Bit R/W
R/W 0
RST
AME
Table 28. AM mode enable
Name Description
0: normal FFX operation
1: AM reduction mode FFX operation
The STA380WS features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
PWM speed mode
Table 29. PWM speed mode
Bit R/W RST Name Description
Obsolete Product(s) - Obsolete Product(s)
4 R/W 0 PWMS
0: normal speed (384 kHz) all channels
1: odd speed (341.3 kHz) all channels
Distortion compensation variable enable
5
Bit R/W
R/W 0
Table 30. Distortion compensation variable enable
RST Name Description
DCCV
0: uses preset DC coefficient
1: uses DCC coefficient
30/48 DocID024426 Rev 1
STA380WS Register description
Zero-crossing volume enable
6
Bit R/W
R/W 1
RST
Table 31. Zero-crossing volume enable
Name Description
ZCE
1: volume adjustments will only occur at digital zero-crossings
0: volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings, no clicks will be audible.
Soft volume update enable
7
Bit R/W
R/W 1
RST
Table 32. Soft volume update enable
Name Description
SVE
1: volume adjustments ramp according to SVR settings
0: volume adjustments will occur immediately
6.1.6 Configuration register F (addr 0x05)
D7
EAPD
0
D6
PWDN
1
D5
ECLE
0
Invalid input detect mute enable
D4
LDTE
1
2
Bit
D3
BCLE
1
D2
IDE
1
D1
0
Reserved
D0
0
R/W
R/W 1
RST
Table 33. Invalid input detect mute enable
Name Description
IDE 1: enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I
2
S data and will automatically mute if the signals are perceived as invalid.
Binary output mode clock loss detection
3
Bit R/W
R/W 1
RST Name
BCLE
Description
Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and outputs 50% of the duty cycle.
DocID024426 Rev 1 31/48
Register description
LRCK double trigger protection
4
Bit R/W
R/W 1
RST
Table 35. LRCK double trigger protection
Name Description
LDTE LRCLK double trigger protection enable
STA380WS
Actively prevents double triggering of LRCLK.
Auto EAPD on clock loss
5
Bit R/W
R/W 0
RST
Table 36. Auto EAPD on clock loss
Name Description
ECLE Auto EAPD on clock loss
When active, will issue a power stage device power-down signal (EAPD) on clock loss detection.
IC power-down
6
Bit R/W
R/W 1
RST
PWDN
Table 37. Power-down
Name Description
0: power-down, low-power condition
1: normal operation
The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power stage, then the master clock to all internal hardware except the I
2
C block is gated.
This puts the IC in a very low power consumption state.
External amplifier power-down
Bit R/W RST
Table 38. External amplifier power-down
Name Description
7 R/W 1 EAPD
0: external power stage power-down active
1: normal operation
Obsolete Product(s) - Obsolete Product(s)
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled).
32/48 DocID024426 Rev 1
STA380WS
6.2
6.2.1
Register description
Volume control registers (addr 0x06 to 0x09)
Mute/line output configuration register (addr 0x06)
D7 D6 D5
Reserved
0
D4 D3 D2
C2M
0
D1
C1M
0 0
Master mute
0
0
Bit R/W
R/W
0 0
0
RST
MMUTE
Table 39. Master mute
Name Description
0: normal operation
1: all channels are in mute condition
D0
MMUTE
0
Channel mute
1
2
Bit R/W
R/W
R/W
0
0
RST
Table 40. Channel mute
Name Description
C1M
C2M
Channel 1 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
Channel 2 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
Obsolete Product(s) - Obsolete Product(s)
DocID024426 Rev 1 33/48
Register description STA380WS
6.2.2 Master volume register (addr 0x07)
D7
MV7
1
D6
MV6
1
D5
MV5
1
D4
MV4
1
D3
MV3
1
D2
MV2
1
D1
MV1
1
D0
MV0
1
6.2.3 Channel volume (addr 0x08, 0x09)
D7
C1V7
0
D6
C1V6
1
D5
C1V5
1
D4
C1V4
0
D3
C1V3
0
D2
C1V2
0
D1
C1V1
0
D0
C1V0
0
D7
C2V7
0
D6
C2V6
1
Volume setting
D5
C2V5
1
D4
C2V4
0
D3
C2V3
0
D2
C2V2
0
D1
C2V1
0
D0
C2V0
0
The volume structure of the STA380WS consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to
-80 dB. As an example, if C2V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 2 = +36 dB.
The master mute, when set to 1, will mute all channels at once, whereas the individual channel mutes (CxM) mute only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (about 96 kHz). A hard mute can be obtained by commanding a value of all 1’s (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel that whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F) on a per-channel basis as this creates the smoothest possible volume transitions. When
ZCE = 0, volume updates will occur immediately.
Table 41. Master volume offset as a function of MV
MV[7:0] Volume offset from channel value
00000000 (0x00) 0 dB
00000001 (0x01)
00000010 (0x02)
-0.5 dB Obsolete Product(s) - Obsolete Product(s)
… …
01001100 (0x4C) -38 dB
…
11111110 (0xFE)
11111111 (0xFF)
…
-127.5 dB
Hard master mute
34/48 DocID024426 Rev 1
STA380WS Register description
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
01100001 (0x61)
…
11010111 (0xD7)
11011000 (0xD8)
11011001 (0xD9)
11011010 (0xDA)
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
Table 42. Channel volume as a function of CxV
CxV[7:0] Volume
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
…
-59.5 dB
-60 dB
-61 dB
-62 dB
…
-80 dB
Hard channel mute
…
Hard channel mute
6.3 Automode register (0x0C)
D7 D6 D5 D4
Reserved
0 0 0 0
AM interference frequency switching
0
Bit R/W
R/W
D3
AMAM2
0
D2
AMAM1
0
D1
AMAM0
0
D0
AMAME
0
0
Table 43. AM interference frequency switching
RST Name Description
AMAME
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM setting
AMAM bits
000
001
010
011
100
101
110
AMAM[2:0] 48 kHz / 96 kHz input f
S
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
DocID024426 Rev 1
44.1 kHz / 88.2 kHz input f
S
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
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Register description
6.4 Channel configuration registers (addr 0x0E, 0x0F)
STA380WS
D7
0
D6
0
D5
Reserved
0
D4
0
D3
0
D2
C1VBP
0
D1
0
Reserved
D0
0
D7 D6 D5
Reserved
0
D4 D3 D2
C2VBP
0
D1
Reserved
D0
0 0
Volume bypass
0 0 0 0
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting. The master volume setting will not affect that channel.
6.5 Variable max power correction registers (addr 0x27, 0x28)
The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.
D7
MPCC15
0
D7
MPCC7
1
D6
MPCC14
0
D6
MPCC6
1
D5
MPCC13
0
D5
MPCC5
0
D4
MPCC12
1
D4
MPCC4
0
D3
MPCC11
1
D3
MPCC3
0
D2
MPCC10
0
D2
MPCC2
0
D1
MPCC9
1
D1
MPCC1
0
D0
MPCC8
0
D0
MPCC0
0
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STA380WS
6.6
Register description
Variable distortion compensation registers (addr 0x29, 0x2A)
D7
DCC15
1
D6
DCC14
1
D5
DCC13
1
D4
DCC12
1
D3
DCC11
0
D2
DCC10
0
D1
DCC9
1
D0
DCC8
1
D7
DCC7
0
D6
DCC6
0
D5
DCC5
1
D4
DCC4
1
D3
DCC3
0
D2
DCC2
0
D1
DCC1
1
The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.
D0
DCC0
1
6.7
Note:
Fault detect recovery constant registers (addr 0x2B, 0x2C)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
0
D4
FDRC12
0
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
The FDRC bits specify the 16-bit fault detect recovery time delay. When status register bit
FAULT is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. A value of 0x0001 in this register is approximately
0.083 ms. The default value of 0x000C gives approximately 0.1 ms.
0x0000 is a reserved value for this register pair. This value must not be used.
6.8 Device status register (addr 0x2D)
D7
PLLUL
D6
FAULT
D5
UVFAULT
D4
Reserved
D3
OCFAULT
D2
OCWARN
D1
TFAULT
D0
TWARN
This read-only register provides the fault, warning and PLL status from the power control block.
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Register description STA380WS
0
1
2
3
4
5
6
7
Bit
-
R/W
RO
RO
RO
RO
RO
RO
RO
-
-
-
-
-
-
-
-
RST
-
Table 45. Status bits description
Name Description
TWARN
TFAULT
OCWARN
OCFAULT
UVFAULT
FAULT
PLLUL
Thermal warning:
0: junction temperature is close to the fault condition
1: normal operation
Thermal fault:
0: junction temperature limit detection
1: normal operation
Overcurrent warning:
0: warning
1: normal operation
Overcurrent fault:
0: fault detected
1: normal operation
Reserved
Undervoltage warning:
0: VCCx below lower voltage threshold
1: normal operation
Power bridge fault:
0: fault detected
1: normal operation
PLL lock:
0: locked
1: not locked
6.9 Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31)
These registers are not to be used.
6.10 Postscale registers (addr 0x32, 0x33)
D7
C1PS7
D6
C1PS6
D5
C1PS5
D4
C1PS4
D3
C1PS3
D2
C1PS2
D1
C1PS1
D0
C1PS0
0 1 1 1 1 1 1 1 Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
C2PS7
0
C2PS6
1
C2PS5
1
C2PS4
1
C2PS3
1
C2PS2
1
C2PS1
1
C2PS0
1
Postscale
The STA380WS provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel, which can be used to limit the maximum modulation index and therefore the peak current through the power device. The register values represent an 8-bit signed fractional number. This number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on that
38/48 DocID024426 Rev 1
STA380WS Register description channel. An independent postscale is provided for each channel but all channels can use channel 1 postscale factor by setting the postscale link bit. By default, all postscale factors are set to 0x7F (pass-through).
6.11 Output limit register (addr 0x34)
6.11.1 Thermal and overcurrent warning output limit register
D7
OLIM7
0
D6
OLIM6
1
D5
OLIM5
0
D4
OLIM4
1
D3
OLIM3
1
D2
OLIM2
0
D1
OLIM1
1
D0
OLIM0
0
The STA380WS provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. When the TWARN or OCWARN status bit is asserted, the output is limited to the OLIM setting. The limit can be adjusted by modifying the thermal warning/overcurrent output limit value. As for the normal postscale, the register value represents an 8-bit signed fractional number. This number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on both channels. The scaling value range is from 0x80 = -1 to 0x7F = 0.992. To avoid phase changes in the output signal, only the positive range is used (0x00 to 0x7F). The default setting of 0x5A provides a
-3-dB limit.
If the cause of the limiting is a thermal warning, the output limiting is removed when the thermal warning situation disappears. If the cause of the limiting is an overcurrent warning, output limiting remains in effect until the device is reset.
Table 46. Output limit values for thermal and overcurrent warnings
OLIM [7:0] Attenuation (dB)
0x7F
0x7E
....
0x5A
....
0x40
....
3.0
....
6.0
....
0.06
0.13
....
0x28
....
10 Obsolete Product(s) - Obsolete Product(s)
0x01 42
0x00 Inf
DocID024426 Rev 1 39/48
Application information STA380WS
7.1 Application scheme for power supplies
Figure 11 below shows a typical application scheme for the STA380WS.
Special care has to be taken with regard to the power supplies when laying out the PCB. In particular the 3.3 resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This prevents unwanted oscillation on the digital parts of the device due to the inductive effects of the PCB tracks. The same rule also applies to all the decoupling capacitors; they should be placed as close as possible to the device in order to limit the effect of spikes on the supplies.
Figure 11. Application diagram
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It is recommended to use the circuit in
for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter has to be connected to the ground of the PLL without any resistive path.
For the component values, it should be remembered that the greater the filter bandwidth, the shorter the lock time, but the higher the PLL output jitter.
DocID024426 Rev 1
STA380WS
Figure 12. PLL filter circuit
Application information
7.3 Typical output configuration
below shows a typical output configuration used for BTL stereo mode.
Figure 13. Typical BTL configuration
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Characterization data STA380WS
The following characterizations were made with R
L stated.
= 8 and f = 1 kHz unless otherwise
Figure 14. Output power vs. supply voltage (THD = 1%)
4
Ω
Supply voltage, V
Figure 15. FFT 0 dBfs (V
CC
= 12 V)
6
Ω
8
Ω
16
Ω d
B
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STA380WS
Figure 16. FFT -60 dBfs (V
CC
= 12 V)
Characterization data d
B r r
-150
20
1
0.5
0.2
% 0.1
0.05
0.02
0.01
20
Figure 17. THD vs. frequency (V
CC
= 12 V, Po = 1 W)
50 100 200
6ohm
6
Ω
8 Ω
4
Ω
5k 10k 20k 500
Hz
1k 2k
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Characterization data STA380WS
Figure 18. FFT 0 dBfs (V
CC
= 18 V)
B r
-150
20
Figure 19. FFT -60 dBfs (V
CC
= 18 V) d
B r r
-150
20
Figure 20. THD vs. frequency (V
CC
= 18 V, Po = 1 W)
6 Ω 4 Ω Obsolete Product(s) - Obsolete Product(s)
8 Ω
44/48 DocID024426 Rev 1
STA380WS
9 Package mechanical data
Package mechanical data
The STA380WS comes in a 48-pin VQFN package with exposed pad down (EPD).
Figure 21. VQFN48 (7 x 7 x 0.9 mm) package dimensions
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Package mechanical data STA380WS
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
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STA380WS
Date
03$SU -2013
Revision
Table 47. Document revision history
Changes
1 Initial release.
Revision history
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STA380WS
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