STMicroelectronics STA339BW Datasheet
STMicroelectronics STA339BW is a 2.1-channel high-efficiency digital audio system with dedicated LFE processing for bass boosting and a wide range of audio presets. It features advanced AM interference frequency switching and noise suppression modes, ensuring high audio quality even in noisy environments. With its versatile power output configurations, you can tailor the device to your specific needs, whether it's for stereo or multi-channel audio setups. The STA339BW's comprehensive processing capabilities, including EQ, DRC, and user-programmable biquads, provide you with exceptional control over your audio experience. Its I2C control interface allows for seamless integration with other devices in your system.
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STA339BW
2.1-channel high-efficiency digital audio system
PowerSSO-36 (slug down)
Features
Wide voltage supply range
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
3 power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 20 W into 8 at 18 V)
– 3 channels - left, right using binary and LFE using ternary PWM (2.1 mode) (2 x 9 W +
1 x 20 W into 2 x 4 , 1 x 8 at 18 V)
– 2 channels of ternary PWM (2 x 20 W) + stereo lineout ternary
2.1 channels of 24-bit FFX ® 100 dB SNR and dynamic range
Selectable 32 to 192 kHz input sample rates
I 2 C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB with
0.5 dB/step resolution
Soft volume update with programmable ratio
Individual channel and master gain/attenuation
Two independent DRC configurable as a dual-band anti-clipper (B 2 DRC) or as independent limiters/compressors
EQ-DRC for DRC based on filtered signals
Order code
STA339BWTR
Table 1. Device summary
Package
PowerSSO-36 slug down
Datasheet
-
production data
Dedicated LFE processing for bass boosting with 0.5 dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel and master soft/hard mute
Independent channel volume and DSP bypass
Automatic zero-detect mute
Automatic invalid input-detect mute
2-channel I 2 S input data interface
Input and output channel mapping
Up to 8 user-programmable biquads per channel with 28-bit resolution
3 coefficient banks for EQ presets storing with fast recall via I 2 C interface
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency switching and noise suppression modes
Selectable high- or low-bandwidth noise-shaping topologies
Variable max power correction for lower full-power THD
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Thermal overload and short-circuit protection embedded
Video apps: 576 * f
S
input mode supported
Fully compatible with STA339BWS.
Packaging
Tape and reel
January 2015
This is information on a product in full production.
DocID15251 Rev 8 1/78 www.st.com
Contents
Contents
STA339BW
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 16
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/78 DocID15251 Rev 8
STA339BW
Contents
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 35
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 36
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Contents STA339BW
Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 38
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 45
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 46
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 48
Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 50
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4/78 DocID15251 Rev 8
STA339BW Contents
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 52
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Limiter 1 Extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 56
Limiter 1 Extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 56
Limiter 2 Extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 57
Limiter 2 Extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 57
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 57
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 64
Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 64
Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 65
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 66
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Contents
STA339BW
Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 67
Extended post scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 70
DRC RMS filter coefficients (addr 0x39 - 0x3E) . . . . . . . . . . . . . . . . . . . . 71
Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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STA339BW
List of figures
List of figures
DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DocID15251 Rev 8 7/78
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List of tables
List of tables
STA339BW
8/78 DocID15251 Rev 8
STA339BW List of tables
DocID15251 Rev 8 9/78
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Description
1 Description
STA339BW
The STA339BW is an integrated solution of digital audio processing, digital amplifier control, and FFX-power output stage, thereby creating a high-power single-chip FFX ® solution comprising high-quality, high-efficiency, all digital amplification.
STA339BW is based on FFX (fully flexible amplification) processor, an STMicroelectronics proprietary technology. FFX is the evolution and the enlargement of the ST ternary technology: the new processor can be configured to work in ternary, binary, binary differential and phase shift PWM modulation schemes.
STA339BW contains the ternary, binary and binary differential implementations, a subset of the full capability of the FFX processor.
The STA339BW is part of the Sound Terminal ® family that provides full digital audio streaming to the speaker, offering cost effectiveness, low power dissipation and sound enrichment.
The STA339BW power section consists of four independent half bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half bridges and a single full bridge, providing up to 2 x 9 W + 1 x 20 W of power output.
Two channels can be provided by two full bridges, providing up to 2 x 20 W of power. The IC can also be configured as 2.1 channels with 2 x 20 W provided by the device and external power for FFX power drive.
Also provided in the STA339BW are a full assortment of digital processing features. This includes up to 8 programmable 28-bit biquads (EQ) per channel and bass/treble tone control. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. Dual-band DRC dynamically equalizes the system to provide speaker linear frequency response regardless of the output power level. This feature independently processes the two bands, controlling dynamically the output power level in each band and so providing better sound quality.
The serial audio data input interface accepts all possible formats, including the popular I 2 S format. Three channels of FFX processing are provided. This high-quality conversion from
PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic range.
10/78 DocID15251 Rev 8
STA339BW
I 2 S interface
PLL
Digital DSP
I 2 C
Figure 1. Block diagram
Protection current/thermal
Channel
1A
Volume control
FFX
Power control
Logic
Channel
1B
Channel
2A
Regulators
Bias
Power
Channel
2B
Description
DocID15251 Rev 8 11/78
78
Pin connections STA339BW
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD
CONFIG
OUT3B / FFX3B
OUT3A / FFX3A
Figure 2. Pin connection PowerSSO-36 (top view)
15
16
17
18
10
11
12
13
14
5
6
7
8
9
3
4
1
2
29
28
27
26
25
36
35
34
33
32
31
30
21
20
19
24
23
22
D05AU1638
VDD_DIG
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
GND_PLL
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
VDD_DIG
TWARN / OUT4A
EAPD / OUT4B
12/78
6
7
4
5
1
2
3
8
9
10
Pin Type
I
I
GND
I/O
I/O
O
GND
Power
O
O
Name
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
Table 2. Pin description
Description
Substrate ground
I
2
C select address (pull-down)
This pin must be connected to ground (pull-down)
Internal reference at V
CC
- 3.3 V
Internal V
CC
reference
Output half bridge 2B
Power negative supply
Power positive supply
Output half bridge 2A
Output half bridge 1B
DocID15251 Rev 8
STA339BW Pin connections
20
32
33
34
35
36
28
29
30
31
24
25
26
27
21
22
23
15
16
17
18
19
11
12
13
14
Pin
I/O
I
I
I
I
O
I/O
I
GND
Power
Power
I
GND
I
Power
I
GND
Type
Power
GND
O
GND
O
O
I
Power
O
Table 2. Pin description (continued)
Name Description
VCC1
GND1
OUT1A
GND_REG
Power positive supply
Power negative supply
Output half bridge 1A
Internal ground reference
VDD
CONFIG
OUT3B / FFX3B PWM out Ch3B / external bridge driver
OUT3A / FFX3A PWM out Ch3A / external bridge driver
EAPD / OUT4B
Internal 3.3 V reference voltage
Paralleled mode command
TWARN / OUT4A
VDD_DIG
Power down for external bridge / PWM out Ch4B
Thermal warning from external bridge (pull-up when input)
/ PWM out Ch4A
Digital supply voltage
GND_DIG
PWRDN
VDD_PLL
FILTER_PLL
GND_PLL
XTI
BICKI
LRCKI
SDI
RESET
INT_LINE
SDA
SCL
GND_DIG
VDD_DIG
Digital ground
Power down (pull-up)
Positive supply for PLL
Connection to PLL filter
Negative supply for PLL
PLL input clock
I
2
S serial clock
I
2
S left/right clock
I
2
S serial data channels 1 and 2
Reset (pull-up)
Fault interrupt
I
2
C serial data
I
2
C serial clock
Digital ground
Digital supply voltage
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Electrical specifications STA339BW
3.1 Absolute maximum ratings
Symbol
Table 3. Absolute maximum ratings
Parameter
V
CC
Power supply voltage (VCCxA, VCCxB)
VDD_DIG Digital supply voltage
VDD_PLL PLL supply voltage
T op
T stg
Operating junction temperature
Min
-0.3
-0.3
-0.3
-20 -
-
-
-
Typ Max
30
4
4
150
Unit
V
V
V
°C
Warning: Stresses beyond those listed in
permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.
14/78
Symbol
Table 4. Thermal data
Parameter
R th j-case
R th j-amb
T th-sdj
T th-w
T th-sdh
Thermal resistance junction-case (thermal pad)
Thermal resistance junction-ambient (1)
Thermal shut-down junction temperature
Thermal warning temperature
Thermal shut-down hysteresis -
-
-
-
-
1. See
Section 9: Package thermal characteristics on page 74 for details.
Min Typ
-
-
150
130
20
Max
-
-
-
-
1.5
Unit
°C/W
°C/W
°C
°C
°C
DocID15251 Rev 8
STA339BW
3.3
Electrical specifications
Recommended operating conditions
Table 5. Recommended operating condition
3.4
V
CC
Power supply voltage (VCCxA, VCCxB)
VDD_PLL PLL supply voltage
T amb
5 26 V
2.7 3.3 3.6 V
2.7
3.3
-20 -
3.6
V
70 °C
Electrical specifications for the digital section
Table 6. Electrical specifications - digital section
Symbol Parameter Conditions Min Typ
I il
I ih
Low-level input current without pull-up/down device
High-level input current without pull-up/down device
Vi = 0 V
Vi = VDD_DIG
= 3.6 V
-10
-10
1
1
V il
Low-level input voltage -
V ih
V ol
V oh
I pu
R pu
High-level input voltage
Low-level output voltage
High-level output voltage
Pull-up/down current
Equivalent pull-up/down resistance
-
Iol = 2 mA
-
-
Ioh = 2 mA
-
-
0.8 *
VDD_DIG
-
-
-
-
0.8 *
VDD_DIG
-
25 66
50
Max
10
Unit
μA
-
10 μA
0.2 *
VDD_DIG
V
V
-
-
0.4 *
VDD_DIG
V
V
125 μA k
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Electrical specifications STA339BW
3.5 Electrical specifications for the power section
The specifications given in this section are valid for the operating conditions: V
CC f = 1 kHz, f sw
= 384 kHz, T amb
= 25° C and R
L
= 8 , unless otherwise specified.
= 18 V,
I vdd
I lim
I sc
UVL t min
DR
R dsON gP gN
Idss t r t f
I
LDT
I
HDT
V
CC
Symbol
Po
I vcc
SNR
PSSR
Table 7. Electrical specifications - power section
Parameter Conditions
Output power BTL
Output power SE
THD = 1%
THD = 10%
THD = 1%
THD = 10%
Power Pchannel/Nchannel MOSFET
(total bridge)
Power Pchannel RdsON matching
Power Nchannel RdsON matching
Power Pchannel/Nchannel leakage
Low current dead time (static)
High current dead time (dynamic)
Rise time
Fall time l d
= 1.5 A l d
= 1.5 A l d
= 1.5 A
V
CC
= 20 V
Resistive load
(1)
I load
= 1.5 A
(1)
Resistive load
(1)
Resistive load
(1)
Supply voltage operating voltage -
Supply current from V
CC
in power down PWRDN = 0
Supply current from V
CC
in operation
PCM input signal =
-60 dBfs,
Switching frequency
= 384 kHz,
No LC filters
Supply current FFX processing (reference only)
Overcurrent limit
Internal clock =
49.152 MHz
(2)
Short-circuit protection
Undervoltage protection
Output minimum pulse width
Dynamic range
Signal-to-noise ratio, ternary mode
Signal-to-noise ratio binary mode
Power supply rejection ratio
-
-
Hi-Z output
No load
-
A-weighted
FFX stereo mode,
<5 kHz
V
RIPPLE
= 1 V RMS
Audio input = dither only
-
-
-
-
-
-
-
-
-
-
-
-
-
5
95
-
95
-
-
-
20
3.0
-
3.8
16
20
4
5
180 250
52 60
55
3.8
(3)
4.8
3.5
30
100
100
90
%
-
-
10
%
A
8 15 ns
15 30 ns
10 18 ns
10 18 ns
-
0.1
26
1
V mA
80 -
70
-
-
-
60
-
-
4.3
-
-
-
-
W
W m mA mA ns dB dB dB
A
A
V dB
16/78 DocID15251 Rev 8
STA339BW Electrical specifications
Symbol
Table 7. Electrical specifications - power section (continued)
Parameter Conditions
THD+N
X
TALK
Total harmonic distortion + noise
Crosstalk
Peak efficiency, FFX mode
Peak efficiency,binary modes
FFX stereo mode,
Po = 1 W f = 1 kHz
FFX stereo mode,
<5 kHz
One channel driven at 1 W
Other channel measured
Po = 2 x 20 W into 8
Po = 2 x 9 W into 4
+ 1 x 20 W into 8
-
-
-
-
0.2
80
90
87 -
-
-
% dB
%
1. Refer to Figure 5: Test circuit 1 .
2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled, refer to I sc
.
3. I lim
typical value is 0.8*I sc
.
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78
Electrical specifications
3.6 Power on/off sequence
Figure 3. Power-on sequence
Note: no specific VCC and
VDD_DIG turn −on sequence is required
STA339BW
Note:
TR = minimum time between XTI master clock stable and Reset removal: 1 ms
TC = minimum time between Reset removal and I
2
C program, sequence start: 1ms
The definition of a stable clock is when f max
- f min
< 1 MHz.
Section 7.2.3 on page 31 gives information on setting up the I
2 S interface.
Figure 4. Power-off sequence for pop-free turn-off
Note: no specific VCC and
VDD_DIG turn −off sequence is required
18/78 DocID15251 Rev 8
STA339BW Electrical specifications
3.7 Testing
3.7.1 Functional pin definition
Table 8. Functional pin definition
Pin name Number Logic value IC status
PWRDN 23
TWARN 20
0
A temperature warning is indicated by the external power stage
EAPD 19
0
Low consumption for power stage
All internal regulators are switched off
Duty cycle=A
DTin(A)
INxA
Low current dead time = MAX(DTr, DTf)
Duty cycle = 50%
INxY
Figure 5. Test circuit 1
OUTxY
+Vcc
OUTxY t
DTr DTf
Rload = 8
vdc = Vcc/2
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc gnd
Figure 6. Test circuit 2
High current dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
DTout(A)
Q1
OUTxA
Iout
Q3
10
470nF
Rload = 4
470nF
10
470nF
Q2
DTout(B)
OUTxB
Iout
Q4
Duty cycle=B
DTin(B)
INxB
Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure D06AU1651_00
DocID15251 Rev 8 19/78
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Serial audio interface
4 Serial audio interface
STA339BW
The STA339BW audio serial input interface was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA339BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock
BICKI, and serial data SDI12.
The SAI bit and the SAIFB bit are used to specify the serial data format. The default serial data format is I 2 S, MSB-first.
4.0.1 Timings
In the STA339BW the BICKI and LRCKI pins are configured as inputs and they must be supplied by the external peripheral.
Figure 7. Timing diagram for SAI interface
4.0.2
4.0.3
Symbol t
BCy t
BCH t
BCL t
LRSU t
LRH t
LRJT
Table 9. Timing parameters for slave mode
Parameter
BICK cycle time
BICK pulse width high
BICK pulse width low
LRCKI setup time to BICKI strobing edge
LRCKI hold time to BICKI strobing edge
LRCKI Jitter Tolerance
Min
80
40
40
40
40
Typ Max Unit
-
-
-
-
-
-
-
-
-
-
40 ns ns ns ns ns ns
Delay serial clock enable
To tolerate anomalies in some I 2 S master devices, a PLL clock cycle delay can be added to the BICKI signal before the SAI interface.
Channel input mapping
Each channel received via I 2 S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I 2 S input channel to its corresponding processing channel.
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STA339BW
5 Processing data paths
Processing data paths
The whole processing chain is composed of two consecutive sections. In the first one dual-channel processing is implemented, as described below. Then each channel is fed into the post-mixing block where there is a choice of processing, either the dual-band DRC is disabled or it is enabled. When B 2 DRC is disabled a third channel, typically used in 2.1 output configuration and with cross-over filters enabled, is used. When B 2 DRC is enabled the 2.0 output configuration with cross-over filters for defining the cutoff frequency of the two bands is used.
The first section,
Figure 8 , begins with a 2x oversampling FIR filter allowing a 2 * fs audio
processing. Then a selectable high-pass filter removes the DC level (enabled if HFB = 0).
The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]).
By default, four independent filters per channel are enabled, plus the preconfigured deemphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).
If the coefficient sets are linked (BQL = 1) then it is possible to use the de-emphasis, bass and treble filter in a user defined configuration (provided the relevant BQx bits are set to 1).
In other words both channels use the same processing coefficients and can have up to 7 filters each. Note that if BQL = 0 the BQx bits are ignored and the 5th, 6th and 7th filters are configured as de-emphasis, bass and treble controls, respectively.
Moreover the common 8th filter, from the subsequent processing section, can be available on both channels (provided the pre-defined cross-over frequencies are not used,
XO[3:0] = 0, and the dual-band DRC is not used).
In the second section, mixing and crossover filters are available. If B 2 DRC is not enabled
(lower schematic in Figure 9 ) they are fully user-programmable and allow a third channel
(2.1 outputs) to be generated. Alternatively, in B 2 DRC mode (upper schematic in
those blocks will be used to split the sub-band and define the cutoff frequencies of the two bands. A prescaler and a final post scaler allow full control over the signal dynamics before and after, respectively, the filtering stages. A mixer function is also available.
Figure 8. Left and right processing part 1
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Processing data paths
Figure 9. Processing part 2
Dual-band DRC enabled
STA339BW
Dual-band DRC disabled
22/78 DocID15251 Rev 8
STA339BW
6 I
2
C bus specification
I 2 C bus specification
The STA339BW supports the I 2 C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA339BW is always a slave device in all of its communications. It can operate at up to 400 kb/s (fast-mode bit rate). The STA339BW I 2 C interface is a slave only interface.
6.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA339BW and the bus master.
During the data input the STA339BW samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
To start communication between the master and the STA339BW, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode.
The seven most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In the STA339BW the I
2
C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and to 0 for write mode. After a START condition the STA339BW identifies on the bus the device address and if a match is found, acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
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I 2 C bus specification STA339BW
Following the START condition the master sends a device select code with the RW bit set to 0. The STA339BW acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA339BW again responds with an acknowledgement.
In the byte write mode the master sends one data byte, this is acknowledged by the
STA339BW. The master then terminates the transfer by generating a STOP condition.
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
6.4.1
6.4.2
6.4.3
6.4.4
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to 1. The STA339BW acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA339BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
Random address byte read
Following the START condition the master sends a device select code with the RW bit set to 0. The STA339BW acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA339BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA339BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA339BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
24/78 DocID15251 Rev 8
STA339BW
6.4.5 Write mode sequence
Figure 10. Write mode sequence
I 2 C bus specification
6.4.6 Read mode sequence
Figure 11. Read mode sequence
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Register description STA339BW
Addr Name
0x10 C3CFG
0x11 TONE
0x12 L1AR
0x13 L1ATRT
0x14 L2AR
0x15 L2ATRT
0x16 CFADDR
0x17 B1CF1
0x18 B1CF2
0x19 B1CF3
0x1A B2CF1
0x1B B2CF2
0x1C B2CF3
0x1D A1CF1
0x1E A1CF2
0x1F A1CF3
0x00 CONFA
0x01 CONFB
0x02 CONFC
0x03 CONFD
0x04 CONFE
0x05 CONFF
0x06 MUTE/LOC
0x07 MVOL
0x08 C1VOL
0x09 C2VOL
0x0A C3VOL
0x0B AUTO1
0x0C AUTO2
0x0D AUTO3
0x0E C1CFG
0x0F C2CFG
C1OM1
C2OM1
C3OM1
TTC3
L1A3
L1AT3
L2A3
L2AT3 L2AT2
Reserved
C1B23
C1B15
C1B22
C1B14
C1B7
C2B23
C2B15
C2B7
C1B6
C2B22
C2B14
C2B6
C3B23
C3B15
C3B7
C1OM0
C2OM0
C3OM0
TTC2
L1A2
L1AT2
L2A2
C3B22
C3B14
C3B6
D7 D6
FDRB
C2IM
OCRB
SME
SVE
EAPD
LOC1
MV7
C1V7
C2V7
C3V7
XO3
Reserved
XO2
MV6
C1V6
C2V6
C3V6
TWAB
C1IM
Reserved
ZDE
ZCE
PWDN
LOC0
Table 10. Register summary
D5 D4 D3 D2 D1 D0
L2AT1
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
C2B5
C1LS1
C2LS1
C3LS1
TTC1
L1A1
L1AT1
L2A1
MV5
C1V5
C2V5
C3V5
AMGC1
XO1
TWRB
DSCKE
CSZ3
IR1
SAIFB
CSZ2
DRC
DCCV
BQL
PWMS
ECLE
Reserved
LDTE
IR0
SAI3
CSZ1
PSL
AME
BCLE
C3M
MCS2
SAI2
CSZ0
DSPB
IDE
C2M
MCS1
SAI1
OM1
DEMP
NSBW MPC MPCV
OCFG1
C1M
MCS0
SAI0
OM0
HPB
OCFG0
MMUTE
MV4
C1V4
C2V4
C3V4
MV3
C1V3
C2V3
C3V3
MV2
C1V2
C2V2
C3V2
MV1
C1V1
C2V1
C3V1
MV0
C1V0
C2V0
C3V0
AMGC0
XO0 AMAM2
Reserved
AMAM1 AMAM0
Reserved
C1LS0 C1BO C1VBP C1EQBP
C2LS0
C3LS0
C2BO
C3BO
C2VBP
C3VBP
AMAME
C1TCB
C2EQBP C2TCB
Reserved
TTC0
L1A0
L1AT0
L2A0
L2AT0
CFA4
C1B20
C1B12
BTC3
L1R3
L1RT3
L2R3
L2RT3
CFA3
C1B19
C1B11
BTC2
L1R2
L1RT2
L2R2
L2RT2
CFA2
C1B18
C1B10
BTC1
L1R1
L1RT1
L2R1
L2RT1
CFA1
C1B17
C1B9
BTC0
L1R0
L1RT0
L2R0
L2RT0
CFA0
C1B16
C1B8
C3B21
C3B13
C3B5
C1B4
C2B20
C2B12
C2B4
C3B20
C3B12
C3B4
C1B3
C2B19
C2B11
C2B3
C3B19
C3B11
C3B3
C1B2
C2B18
C2B10
C2B2
C3B18
C3B10
C3B2
C1B1
C2B17
C2B9
C2B1
C3B17
C3B9
C3B1
C1B0
C2B16
C2B8
C2B0
C3B16
C3B8
C3B0
26/78 DocID15251 Rev 8
STA339BW Register description
Addr Name
0x30 Reserved
0x31 EQCFG
0x32 EATH1
0x33 ERTH1
0x34 EATH2
0x35 ERTH2
0x36 CONFX
0x37 SVCA
0x38 SVCB
0x39 RMS0A
0x3A RMS0B
0x3B RMS0C
0x3C RMS1A
0x3D RMS1B
0x3E RMS1C
0x20 A2CF1
0x21 A2CF2
0x22 A2CF3
0x23 B0CF1
0x24 B0CF2
0x25 B0CF3
0x26 CFUD
0x27 MPCC1
0x28 MPCC2
0x29 DCC1
0x2A DCC2
0x2B FDRC1
0x2C FDRC2
0x2D STATUS
0x2E Reserved
0x2F Reserved
D7
Table 10. Register summary (continued)
D6 D5
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
C4B22
C4B14
C4B6
C4B21
C4B13
C4B5
C5B22
C5B14
C5B21
C5B13
C5B6 C5B5
Reserved
MPCC15
MPCC7
DCC15
DCC7
MPCC14
MPCC6
DCC14
DCC6
MPCC13
MPCC5
DCC13
DCC5
FDRC15
FDRC7
PLLUL
FDRC14
FDRC6
FAULT
Reserved
FDRC13
FDRC5
UVFAULT
RO1BACT
R01BEND Reserved
Reserved
XOB
EATHEN1
Reserved
EATH1[6] EATH1[5]
ERTHEN1
EATHEN2
ERTHEN2
MDRC[1]
ERTH1[6]
EATH2[6]
ERTH2[6]
MDRC[0]
R_C0[23]
R_C0[15]
Reserved
Reserved
R_C0[22]
R_C0[14]
R_C0[7]
R_C1[23]
R_C1[15]
R_C1[7]
R_C0[6]
R_C1[22]
R_C1[14]
R_C1[6]
ERTH1[5]
EATH2[5]
ERTH2[5]
PS48DB
SVUPE
SVDWE
R_C0[21]
R_C0[13]
R_C0[5]
R_C1[21]
R_C1[13]
R_C1[5]
D4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
D3
R5BEND
R5BBAD
AMGC3
EATH1[4]
ERTH1[4]
EATH2[4]
ERTH2[4]
XAR1
MPCC12
MPCC4
DCC12
DCC4
FDRC12
FDRC4
OVFAULT
R5BACT
SVUP[4]
SVDW[4]
R_C0[20]
R_C0[12]
R_C0[4]
R_C1[20]
R_C1[12]
R_C1[4]
SVUP[3]
SVDW[3]
R_C0[19]
R_C0[11]
R_C0[3]
R_C1[19]
R_C1[11]
R_C1[3]
R4BEND
R4BBAD
AMGC2
EATH1[3]
ERTH1[3]
EATH2[3]
ERTH2[3]
XAR2
MPCC11
MPCC3
DCC11
DCC3
FDRC11
FDRC3
OCFAULT
R4BACT
C4B19
C4B11
C4B3
C5B19
C5B11
C5B3
RA
D2
SVUP[2]
SVDW[2]
R_C0[18]
R_C0[10]
R_C0[2]
R_C1[18]
R_C1[10]
R_C1[2]
R3BEND
R3BBAD
Reserved
EATH1[2]
ERTH1[2]
EATH2[2]
ERTH2[2]
BQ5
MPCC10
MPCC2
DCC10
DCC2
FDRC10
FDRC2
OCWARN
R3BACT
C4B18
C4B10
C4B2
C5B18
C5B10
C5B2
R1
D0
SVUP[0]
SVDW[0]
R_C0[16]
R_C0[8]
R_C0[0]
R_C1[16]
R_C1[8]
R_C1[0]
R1BEND
R1BBAD
SEL0
EATH1[0]
ERTH1[0]
EATH2[0]
ERTH2[0]
BQ7
MPCC8
MPCC0
DCC8
DCC0
FDRC8
FDRC0
TWARN
R1BACT
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
D1
SVUP[1]
SVDW[1]
R_C0[17]
R_C0[9]
R_C0[1]
R_C1[17]
R_C1[9]
R_C1[1]
R2BEND
R2BBAD
SEL1
EATH1[1]
ERTH1[1]
EATH2[1]
ERTH2[1]
BQ6
MPCC9
MPCC1
DCC9
DCC1
FDRC9
FDRC1
TFAULT
R2BACT
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
WA
DocID15251 Rev 8 27/78
78
Register description
7.1
7.1.1
Configuration register A (addr 0x00)
D7
FDRB
0
D6
TWAB
1
D5
TWRB
1
D4
IR1
0
D3
IR0
0
D2
MCS2
0
D1
MCS1
1
STA339BW
D0
MCS0
1
Master clock select
0
1
2
Bit R/W
R/W
R/W
R/W
1
1
0
RST
Table 11. Master clock select
Name Description
MCS0
MCS1
MCS2
Selects the ratio between the input I
2
S sample frequency and the input clock.
The STA339BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f s
).
The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.
Table 12. Input sampling rates
Input sample rate
fs (kHz)
-
32, 44.1, 48
88.2, 96
176.4, 192
IR
00
01
1X
-
MCS[2:0]
101 100 011 010 001 000
576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs
NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
28/78 DocID15251 Rev 8
STA339BW
7.1.2
Register description
Interpolation ratio select
Bit
4:3
R/W
R/W 00
RST
Table 13. Internal interpolation ratio
Name Description
IR [1:0]
Selects internal interpolation ratio based on input I
2
S sample frequency
The STA339BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.
32
44.1
48
88.2
96
176.4
192
Table 14. IR bit settings as a function of input sample rate
Input sample rate fs (kHz) IR 1st stage interpolation ratio
01
10
10
00
00
00
01
2 times oversampling
2 times oversampling
2 times oversampling
Pass-through
Pass-through
2 times downsampling
2 times downsampling
7.1.3
7.1.4
Thermal warning recovery bypass
5
Bit R/W
R/W 1
RST
Table 15. Thermal warning recovery bypass
Name Description
TWRB
0: Thermal warning recovery enabled
1: Thermal warning recovery disabled
If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative.
If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset.
Thermal warning adjustment bypass
6
Bit R/W
R/W 1
Table 16. Thermal warning adjustment bypass
RST Name Description
TWAB
0: Thermal warning adjustment enabled
1: Thermal warning adjustment disabled
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Register description
7.1.5
STA339BW
The on-chip STA339BW power output block provides feedback to the digital controller using inputs to the power control block. Input TWARN is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in the coefficient
RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.
Fault detect recovery bypass
7
Bit R/W
R/W 0
RST
Table 17. Fault detect recovery bypass
Name Description
FDRB
0: fault detect recovery enabled
1: fault detect recovery disabled
The on-chip STA339BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x2B-0x2C), then toggles it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
7.2
7.2.1
Configuration register B (addr 0x01)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
Serial audio input interface format
0
1
2
3
Bit R/W
R/W
R/W
R/W
R/W
0
0
0
0
RST
Table 18. Serial audio input interface
Name Description
SAI0
SAI1
SAI2
SAI3
Determines the interface format of the input serial digital audio interface.
30/78 DocID15251 Rev 8
STA339BW
7.2.2
7.2.3
Register description
Serial data interface
The STA339BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA339BW always acts as slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.
The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I
2
S, MSB-first. Available formats are shown in the tables and figure that follow.
Serial data first bit
0
1
SAIFB
Table 19. Serial data first bit
Format
MSB-first
LSB-first
32 * fs
Table 20. Supported serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
0000 0 I
2
S 15-bit data
0001
0000
0
0
Left/right-justified 16-bit data
I
2
S 16 to 23-bit data
48 * fs
64 * fs
0001
0010
0110
1010
1110
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
Left-justified 16 to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16 to 24-bit data
Left-justified 16 to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
DocID15251 Rev 8 31/78
78
Register description STA339BW
32 * fs
48 * fs
64 * fs
Table 21. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
1001
1101
0010
0110
1010
1110
0000
0100
1100
1110
0100
0100
1000
1100
0001
0101
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
To make the STA339BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that:
the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in
the PLL must be locked.
If these two conditions are not met, and bit IDE of register address 0x05 is set to 1, the
STA339BW immediately mutes the I 2 S PCM data out (provided to the processing block) and it freezes any active processing task.
32/78 DocID15251 Rev 8
STA339BW
Note:
7.2.4
Register description
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any audio streams flowing into STA339BW data path before the desynchronization event happens. At the same time any processing related to the I 2 C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I 2 C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization.
Delay serial clock enable
5
Bit R/W
R/W 0
RST
Table 22. Delay serial clock enable
Name Description
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
7.2.5 Channel input mapping
6
7
Bit R/W
R/W
R/W
0
1
RST
Table 23. Channel input mapping
C1IM
C2IM
Name Description
0: Processing channel 1 receives Left I
2
1: Processing channel 1 receives Right I
S Input
2
S Input
0: Processing channel 2 receives Left I
2
1: Processing channel 2 receives Right I
S Input
2
S Input
Each channel received via I
2
S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
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78
Register description
7.3
7.3.1
Configuration register C (addr 0x02)
D7
OCRB
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
1
D2
CSZ0
1
D1
OM1
1
FFX power output mode
0
1
Bit R/W
R/W
R/W
1
1
RST
OM0
OM1
Table 24. FFX power output mode
Name Description
Selects configuration of FFX output.
STA339BW
D0
OM0
1
00
01
10
11
The FFX power output mode selects how the FFX output timing is configured.
Different power devices use different output modes.
OM[1,0]
Table 25. Output modes
Output stage mode
Drop compensation
Discrete output stage - tapered compensation
Full power mode
Variable drop compensation (CSZx bits)
7.3.2 FFX compensating pulse size register
2
3
4
5
Bit R/W
R/W
R/W
R/W
R/W
1
1
1
0
RST
Table 26. FFX compensating pulse size bits
Name Description
CSZ0
CSZ1
CSZ2
CSZ3
When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to
15 clock periods.
0000
0001
…
1111
CSZ[3:0]
Table 27. Compensating pulse size
Compensating pulse size
0 ns (0 tick) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 tick) clock period compensating pulse size
34/78 DocID15251 Rev 8
STA339BW
7.3.3
Register description
Overcurrent warning detect adjustment bypass
7
Bit R/W
R/W 1
RST
Table 28. Overcurrent warning bypass
Name Description
OCRB
0: overcurrent warning adjustment enabled
1: overcurrent warning adjustment disabled
The OCWARN input is used to indicate an overcurrent warning condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default is -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning volume adjustment is applied, it remains in this state until reset is applied. The level of adjustment can be changed via the TWOCL (thermal warning / overcurrent limit) setting which is address 0x37 of the user defined coefficient RAM.
7.4
7.4.1
Configuration register D (addr 0x03)
D7
SME
0
D6
ZDE
1
D5
DRC
0
D4
BQL
0
D3
PSL
0
D2
DSPB
0
D1
DEMP
0
D0
HPB
0
High-pass filter bypass
0
Bit R/W
R/W 0
RST
HPB
Table 29. High-pass filter bypass
Name Description
Setting of one bypasses internal AC coupling digital high-pass filter
The STA339BW features an internal digital high-pass filter for the purpose of AC coupling.
The purpose of this filter is to prevent DC signals from passing through a FFX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled.
7.4.2 De-emphasis
1
Bit R/W
R/W 0
RST
DEMP
Table 30. De-emphasis
Name Description
0: No de-emphasis
1: Enable de-emphasis on all channels
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78
Register description STA339BW
2
Bit R/W
R/W 0
RST
DSPB
Table 31. DSP bypass
Name Description
0: Normal operation
1: Bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the EQ function of the STA339BW.
7.4.5
7.4.6
3
Bit R/W
R/W 0
RST
PSL
Table 32. Post-scale link
Name Description
0: Each channel uses individual post-scale value
1: Each channel uses channel 1 post-scale value
Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster.
Biquad coefficient link
4
Bit R/W
R/W 0
RST
BQL
Table 33. Biquad coefficient link
Name Description
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
Dynamic range compression/anti-clipping bit
5
Bit R/W
R/W
Table 34. Dynamic range compression/anti-clipping bit
RST Name Description
0 DRC
0: Limiters act in anti-clipping mode
1: Limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.
36/78 DocID15251 Rev 8
STA339BW
7.4.7
Register description
Zero-detect mute enable
6
Bit R/W
R/W 1
RST
Table 35. Zero-detect mute enable
Name Description
ZDE Setting of 1 enables the automatic zero-detect mute
7.4.8
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.
Submix mode enable
7
Bit R/W
R/W 0
RST
SME
Table 36. Submix mode enable
Name Description
0: Sub Mix into Left/Right disabled
1: Sub Mix into Left/Right enabled
7.5
7.5.1
7.5.2
Configuration register E (addr 0x04)
D7
SVE
1
D6
ZCE
1
D5
DCCV
0
D4
PWMS
0
D3
AME
0
D2
NSBW
0
D1
MPC
1
Max power correction variable
0
Bit R/W
R/W 0
RST
Table 37. Max power correction variable
Name Description
MPCV
0: Use standard MPC coefficient
1: Use MPCC bits for MPC coefficient
D0
MPCV
0
Max power correction
1
Bit R/W
R/W 1
RST
MPC
Table 38. Max power correction
Name Description
Setting of 1 enables Power Bridge correction for
THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA339BW power device at high power. This mode should lower the THD+N of a full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the lineout channels.
DocID15251 Rev 8 37/78
78
Register description
7.5.3 Noise-shaper bandwidth selection
2
Bit R/W
R/W 0
RST
Table 39. Noise-shaper bandwidth selection
Name Description
NSBW
1: Third order NS
0: Fourth order NS
7.5.4
7.5.5
STA339BW
AM mode enable
3
Bit R/W
R/W 0
RST
AME
Table 40. AM mode enable
Name Description
0: Normal FFX operation.
1: AM reduction mode FFX operation
STA339BW features aFFX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an AM tuner active. The SNR of the FFX processing is reduced to approximately
83 dB in this mode, which is still greater than the SNR of AM radio.
PWM speed mode
4
Bit R/W
R/W 0
RST
Table 41. PWM speed mode
Name Description
PWMS
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels
7.5.6
7.5.7
38/78
Distortion compensation variable enable
5
Bit R/W
R/W 0
Table 42. Distortion compensation variable enable
RST Name Description
DCCV
0: Use preset DC coefficient
1: Use DCC coefficient
Zero-crossing volume enable
6
Bit R/W
R/W 1
RST
Table 43. Zero-crossing volume enable
Name Description
ZCE
1: Volume adjustments only occur at digital zerocrossings
0: Volume adjustments occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible.
DocID15251 Rev 8
STA339BW
7.5.8
Register description
Soft volume update enable
7
Bit R/W
R/W 1
RST
SVE
Table 44. Soft volume update enable
Name Description
1: Volume adjustments ramp according to SVR settings
0: Volume adjustments occur immediately
7.6 Configuration register F (addr 0x05)
D7
EAPD
0
D6
PWDN
1
D5
ECLE
0
D4
LDTE
1
D3
BCLE
1
D2
IDE
1
D1
OCFG1
0
D0
OCFG0
0
0
1
Bit R/W
R/W
R/W
0
0
RST
Table 45. Output configuration
Name Description
OCFG0
OCFG1
Selects the output configuration
00
01
10
11
OCFG[1:0]
Table 46. Output configuration engine selection
Output configuration
2 channel (full-bridge) power, 2 channel data-out:
1A/1B 1A/1B
2A/2B 2A/2B
LineOut1 3A/3B
LineOut2 4A/4B
Line Out Configuration determined by LOC register
2(Half-Bridge).1(Full-Bridge) On-Board Power:
1A 1A Binary 0 °
2A 1B Binary 90°
3A/3B 2A/2B Binary 45°
1A/B 3A/B Binary 0°
2A/B 4A/B Binary 90°
2 Channel (Full-Bridge) Power, 1 Channel FFX:
1A/1B 1A/1B
2A/2B 2A/2B
3A/3B 3A/3B
EAPDEXT and TWARNEXT Active
1 Channel Mono-Parallel:
3A 1A/1B w/ C3BO 45°
3B 2A/2B w/ C3BO 45°
1A/1B 3A/3B
2A/2B 4A/4B
0
0
0
1
DocID15251 Rev 8
Config pin
39/78
78
Register description
Note:
STA339BW
To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs.
Figure 12. OCFG = 00 (default value)
Figure 13. OCFG = 01
Figure 14. OCFG = 10
40/78 DocID15251 Rev 8
STA339BW
Figure 15. OCFG = 11
Register description
The STA339BW can be configured to support different output configurations. For each
PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries.
Figure 16. Output mapping scheme
For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage:
DocID15251 Rev 8 41/78
78
Register description STA339BW
2.0 channels, two full bridges (OCFG = 00)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as lineout ternary
FFX4A/4B configured as lineout ternary
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, volume control or EQ have no effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in
Figure 17. 2.0 channels (OCFG = 00) PWM slots
42/78 DocID15251 Rev 8
STA339BW Register description
2.1 channels, two half bridges + one full bridge (OCFG = 01)
FFX1A -> OUT1A
FFX2A -> OUT1B
FFX3A -> OUT2A
FFX3B -> OUT2B
FFX1A -> OUT3A
FFX1B -> OUT3B
FFX2A -> OUT4A
FFX2B -> OUT4B
FFX1A/1B configured as binary
FFX2A/2B configured as binary
FFX3A/3B configured as binary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in
Figure 18. 2.1 channels (OCFG = 01) PWM slots
DocID15251 Rev 8 43/78
78
Register description STA339BW
2.1 channels, two fullbridge + one external full bridge (OCFG = 10)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
EAPD -> OUT4A
TWARN -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as ternary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in
Figure 19. 2.1 channels (OCFG = 10) PWM slots
44/78 DocID15251 Rev 8
STA339BW
7.6.2
7.6.3
Register description
Invalid input detect mute enable
2
Bit R/W
R/W 1
RST
Table 47. Invalid input detect mute enable
Name Description
IDE
Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I 2 S data and automatically mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
3
Bit R/W
R/W 1
Table 48. Binary output mode clock loss detection
RST Name Description
BCLE Binary output mode clock loss detection enable
7.6.4
7.6.5
7.6.6
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
4
Bit R/W
R/W 1
RST
Table 49. LRCK double trigger protection
Name Description
LDTE LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
5
Bit R/W
R/W 0
RST
Table 50. Auto EAPD on clock loss
Name Description
ECLE Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
7
Bit R/W
R/W 1
RST
PWDN
Table 51. IC power down
Name Description
0: IC power down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
DocID15251 Rev 8 45/78
78
Register description
7.6.7
STA339BW
I to power down the power-stage, then the master clock to all internal hardware expect the
2 C block is gated. This places the IC in a very low power consumption state.
External amplifier power down
7
Bit R/W
R/W 0
RST
Table 52. External amplifier power down
Name Description
EAPD
0: External power stage power down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register also controls the FFX4B/EAPD output pin when OCFG = 10.
7.7
7.7.1
7.7.2
7.7.3
Volume control registers (addr 0x06 - 0x0A)
Mute/line output configuration register
00
01
10
D7
LOC1
0
LOC[1:0]
D6
LOC0
0
D5
0
Reserved
D4
0
D3
C3M
0
D2
C2M
0
Table 53. Line output configuration
Line output configuration
Line output fixed - no volume, no EQ
Line output variable - CH3 volume effects line output, no EQ
Line output variable with EQ - CH3 volume effects line output
D1
C1M
0
D0
MMUTE
0
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.
Master volume register
D7
MV7
1
D6
MV6
1
D5
MV5
1
D4
MV4
1
D3
MV3
1
D2
MV2
1
D1
MV1
1
D0
MV0
1
Channel 1 volume
D7
C1V7
0
D6
C1V6
1
D5
C1V5
1
D4
C1V4
0
D3
C1V3
0
D2
C1V2
0
D1
C1V1
0
D0
C1V0
0
46/78 DocID15251 Rev 8
STA339BW
7.7.4
7.7.5
Register description
Channel 2 volume
D7
C2V7
0
D6
C2V6
1
D5
C2V5
1
D4
C2V4
0
D3
C2V3
0
D2
C2V2
0
D1
C2V1
0
D0
C2V0
0
Channel 3 / line output volume
D7
C3V7
0
D6
C3V6
1
D5
C3V5
1
D4
C3V4
0
D3
C3V3
0
D2
C3V2
0
D1
C3V1
0
D0
C3V0
0
The Volume structure of the STA339BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -
80 dB.
As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel mutes (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (
(addr 0x04) on page 37 ) on a per channel basis as this creates the smoothest possible
volume transitions. When ZCE = 0, volume updates occur immediately.
Table 54. Master volume offset as a function of MV[7:0]
MV[7:0] Volume offset from channel value
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01001100 (0x4C)
…
11111110 (0xFE)
11111111 (0xFF)
0 dB
-0.5 dB
-1 dB
…
-38 dB
…
-127.5 dB
Hard master mute
DocID15251 Rev 8 47/78
78
Register description
Table 55. Channel volume as a function of CxV[7:0]
CxV[7:0] Volume
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
01100001 (0x61)
…
11010111 (0xD7)
11011000 (0xD8)
11011001 (0xD9)
11011010 (0xDA)
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
…
-59.5 dB
-60 dB
-61 dB
-62 dB
…
-80 dB
Hard channel mute
…
Hard channel mute
STA339BW
7.8
7.8.1
48/78
Audio preset registers (addr 0x0B and 0x0C)
Audio preset register 1 (addr 0x0B)
D7
0
Reserved
D6
0
D5
AMGC[1]
0
D4
AMGC[0]
0
D3
0
D2
0
Reserved
D1
0
D0
0
Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. AMGC[3:2] is defined in register
EQ coefficients and DRC configuration register (addr 0x31) on page 66 .
The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].
When this value is 00 then bits AMGC[1:0] are defined below in Table 56
.
00
01
10
11
Table 56. Audio preset gain compression/limiters selection for AMGC[3:2] = 00
AMGC[1:0] Mode
User programmable GC
AC no clipping 2.1
AC limited clipping (10%) 2.1
DRC night-time listening mode 2.1
DocID15251 Rev 8
STA339BW
7.8.2
7.8.3
Register description
Audio preset register 2 (addr 0x0C)
D7
XO3
0
D6
XO2
0
D5
XO1
0
D4
XO0
0
D3
AMAM2
0
D2
AMAM1
0
D1
AMAM0
0
D0
AMAME
0
AM interference frequency switching
0
Bit R/W
R/W 0
Table 57. AM interference frequency switching bits
RST Name Description
AMAME
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
7.8.4
000
001
010
011
100
101
110
Table 58. Audio preset AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
Bass management crossover
4
5
6
7
Bit R/W
R/W
R/W
R/W
R/W
0
0
0
0
RST
Table 59. Bass management crossover
Name Description
XO0
XO1
XO2
XO3
Selects the bass-management crossover frequency.
A 1st-order hign-pass filter (channels 1 and 2) or a
2nd-order low-pass filter (channel 3) at the selected frequency is performed.
0000
0001
0010
0011
XO[3:0]
Table 60. Bass management crossover frequency
Crossover frequency
User-defined
80 Hz
100 Hz
120 Hz
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Register description
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 60. Bass management crossover frequency (continued)
XO[3:0] Crossover frequency
140 Hz
160 Hz
180 Hz
200 Hz
220 Hz
240 Hz
260 Hz
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
STA339BW
7.9
7.9.1
Channel configuration registers (addr 0x0E - 0x10)
D7
C1OM1
0
D7
C2OM1
0
D7
C3OM1
1
D6
C1OM0
0
D6
C2OM0
1
D6
C3OM0
0
D5
C1LS1
0
D5
C2LS1
0
D5
C3LS1
0
D4
C1LS0
0
D4
C2LS0
0
D4
C3LS0
0
D3
C1BO
0
D3
C2BO
0
D3
C3BO
0
D2
C1VPB
0
D2
C2VPB
0
D2
C3VPB
0
D1
C1EQBP
0
D1
C2EQBP
0
D0
C1TCB
0
D0
C2TCB
0
D1
0
Reserved
D0
0
Tone control bypass
Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2.
0
1
CxTCB
Table 61. Tone control bypass
Mode
Perform tone control on channel x - normal operation
Bypass tone control on channel x
50/78
EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel.
DocID15251 Rev 8
STA339BW
0
1
CxEQBP
Table 62. EQ bypass
Mode
Perform EQ on channel x - normal operation
Bypass EQ on channel x
Register description
7.9.4
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse.
0
1
CxBO
Table 63. Binary output enable registers
Mode
FFX 3-state output - normal operation
Binary output
Limiter selection can be made on a per-channel basis according to the channel limiter select bits.
.
00
01
10
Table 64. Channel limiter mapping as a function of CxLS bits
CxLS[1:0] Channel limiter mapping
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.
.
00
01
10
Table 65. Channel output mapping as a function of CxOM bits
CxOM[1:0] Channel x output source from
Channel1
Channel 2
Channel 3
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Register description
7.10 Tone control register (addr 0x11)
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
STA339BW
D2
BTC2
1
D1
BTC1
1
D0
BTC0
1
0000
0001
…
0111
0110
0111
1000
1001
…
1101
1110
1111
Table 66. Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0] Boost/Cut
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
…
+12 dB
+12 dB
+12 dB
7.11 Dynamic control registers (addr 0x12 - 0x15)
7.11.1 Limiter 1 attack/release rate
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
7.11.2 Limiter 1 attack/release threshold
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
D3
L1R3
1
D3
L1RT3
1
D2
L1R2
0
D2
L1RT2
0
7.11.3 Limiter 2 attack/release rate
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L2R3
1
D2
L2R2
0
D1
L1R1
1
D1
L1RT1
0
D1
L2R1
1
52/78 DocID15251 Rev 8
D0
L1R0
0
D0
L1RT0
1
D0
L2R0
0
STA339BW Register description
7.11.4 Limiter 2 attack/release threshold
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
The STA339BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in
Configuration register E (addr 0x04) on page 37
.
Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set to 0 else the thresholds are determined by EATHx[6:0] . It is recommended in anti-clipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a
FFX amplifier. Since gain can be added digitally within the STA339BW it is possible to exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting EATHx[7] bits to 1 selects the anti-clipping mode.
The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set to 0 else the thresholds are determined by ERTHx[6:0]. Settings to 1 ERTHx[7] bits the anti-clipping mode is selected automatically. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.
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Register description
Figure 20. Basic limiter and volume flow diagram
STA339BW
Table 67. Limiter attack rate as a function of
LxA bits
LxA[3:0] Attack Rate dB/ms
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451
3.1584
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
0.2256
Fast
Slow
Table 68. Limiter release rate as a function of LxR bits
LxR[3:0] Release Rate dB/ms
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
0.0198
0.0172
0.0147
0.0137
0.0134
0.0117
0.0110
0.0104
0.5116
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
0.0208
Fast
Slow
54/78 DocID15251 Rev 8
STA339BW Register description
Anti-clipping mode
LxAT[3:0]
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
Table 69. Limiter attack threshold as a function of LxAT bits (AC mode)
AC (dB relative to fs) LxRT[3:0]
-12
-10
-8
0000
0001
0010
-6
-4
0011
0100
-2 0101
0 0110
+2
+3
+4
+5
0111
1000
1001
1010
+6
+7
1011
1100
+8 1101
+9 1110
+10 1111
Table 70. Limiter release threshold as a function of LxRT bits (AC mode)
-29 dB
-20 dB
-16 dB
-14 dB
-12 dB
AC (dB relative to fs)
-8 dB
-7 dB
-6 dB
-5 dB
-4 dB
-3 dB
-2 dB
-0 dB
DocID15251 Rev 8 55/78
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Register description STA339BW
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Dynamic range compression mode
Table 71. Limiter attack threshold as a function of LxAT bits (DRC mode)
LxAT[3:0] DRC (dB relative to Volume)
-7
-4
-12
-10
-16
-15
-14
-13
-23
-21
-19
-17
-31
-29
-27
-25
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 72. Limiter release threshold as a as a function of LxRT bits (DRC mode)
LxRT[3:0]
DRC (db relative to Volume +
LxAT)
-24 dB
-22 dB
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
-38 dB
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
-26 dB
7.11.5 Limiter 1 Extended attack threshold (addr 0x32)
D7
EATHEN1
TBD
D6
EATH1[6]
TBD
D5
EATH1[5]
TBD
D4
EATH1[4]
TBD
D3
EATH1[3]
TBD
D2
EATH1[2]
TBD
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH1 / 4
7.11.6 Limiter 1 Extended release threshold (addr 0x33)
D7
ERTHEN1
TBD
D6
ERTH1[6]
TBD
D5
ERTH1[5]
TBD
D4
ERTH1[4]
TBD
D3
ERTH1[3]
TBD
D2
ERTH1[2]
TBD
The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4
D1
EATH1[1]
TBD
D1
ERTH1[1]
TBD
D0
EATH1[0]
TBD
D0
ERTH1[0]
TBD
56/78 DocID15251 Rev 8
STA339BW Register description
7.11.7 Limiter 2 Extended attack threshold (addr 0x34)
D7
EATHEN2
TBD
D6
EATH2[6]
TBD
D5
EATH2[5]
TBD
D4
EATH2[4]
TBD
D3
EATH2[3]
TBD
D2
EATH2[2]
TBD
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4
D1
EATH2[1]
TBD
7.11.8 Limiter 2 Extended release threshold (addr 0x35)
Note:
D7
ERTHEN2
TBD
D6
ERTH2[6]
TBD
D5
ERTH2[5]
TBD
D4
ERTH2[4]
TBD
D3
ERTH2[3]
TBD
D2
ERTH2[2]
TBD
The extended release threshold value is determined as follows: release threshold = -12 + ERTH2 / 4
Attack/release threshold step is 0.125 dB in the range -12 dB and 0 dB.
D1
ERTH2[1]
TBD
D0
EATH2[0]
TBD
D0
ERTH2[0]
TBD
7.12 User-defined coefficient control registers (addr 0x16 - 0x26)
7.12.1 Coefficient address register
D7
Reserved
0
D6 D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
7.12.2 Coefficient b1 data register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
7.12.3 Coefficient b1 data register bits 15:8
D7
C1B15
0
D6
C1B14
0
D5
C1B13
0
D4
C1B12
0
D3
C1B11
0
7.12.4 Coefficient b1 data register bits 7:0
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B18
0
D2
C1B10
0
D2
C1B2
0
D1
C1B17
0
D1
C1B9
0
D1
C1B1
0
D0
C1B16
0
D0
C1B8
0
D0
C1B0
0
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Register description
7.12.5 Coefficient b2 data register bits 23:16
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
7.12.6 Coefficient b2 data register bits 15:8
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
7.12.7 Coefficient b2 data register bits 7:0
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
7.12.8 Coefficient a1 data register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
7.12.9 Coefficient a1 data register bits 15:8
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
7.12.10 Coefficient a1 data register bits 7:0
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
7.12.11 Coefficient a2 data register bits 23:16
D7
C4B23
0
D6
C4B22
0
D5
C4B21
0
D4
C4B20
0
D3
C4B19
0
D2
C2B18
0
D2
C2B10
0
D2
C2B2
0
D2
C1B18
0
D2
C3B10
0
D2
C3B2
0
D2
C4B18
0
D1
C2B17
0
D0
C2B16
0
D1
C2B9
0
D1
C2B1
0
D1
C3B9
0
D1
C3B1
0
STA339BW
D0
C2B8
0
D0
C2B0
0
D1
C1B17
0
D0
C1B16
0
D0
C3B8
0
D0
C3B0
0
D1
C4B17
0
D0
C4B16
0
58/78 DocID15251 Rev 8
STA339BW Register description
7.12.12 Coefficient a2 data register bits 15:8
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
7.12.13 Coefficient a2 data register bits 7:0
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
7.12.14 Coefficient b0 data register bits 23:16
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C4B10
0
D2
C4B2
0
D1
C4B9
0
D1
C4B1
0
D0
C4B8
0
D0
C4B0
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
7.12.15 Coefficient b0 data register bits 15:8
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
7.12.16 Coefficient b0 data register bits 7:0
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
7.12.17 Coefficient write/read control register
D7 D6
Reserved
0
D5 D4 D3
RA
0
D2
R1
0
D1
WA
0
D0
W1
0
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA339BW via RAM. Access to this RAM is available to the user via an I 2 C register interface. A collection of I 2 C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.
Three different RAM banks are embedded in STA339BW. The three banks are managed in paging mode using EQCFG register bits. They can be used to store different EQ settings.
For speaker frequency compensation, a sampling frequency independent EQ must be implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and downloading them into the three RAM banks, it is possible to select the suitable RAM block depending from the incoming frequency with a simple I 2 C write operation on register 0x31.
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Register description
Note:
STA339BW
For example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the three RAM blocks allowing a faster operation, without any additional download from the microcontroller.
To write the coefficients in a particular RAM bank, this bank must be selected first writing bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.
Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to the coefficients stored in the active RAM block.
The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and
, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D).
Reading a coefficient from RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2. Write 6 bits of address to I
2
C register 0x16.
3. Write 1 to R1 bit in I 2 C address 0x26.
4. Read top 8 bits of coefficient in I
2
C address 0x17.
5. Read middle 8 bits of coefficient in I 2 C address 0x18.
6. Read bottom 8 bits of coefficient in I
2
C address 0x19.
Reading a set of coefficients from RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2. Write 6 bits of address to I 2 C register 0x16.
3. Write 1 to RA bit in I
2
C address 0x26.
4. Read top 8 bits of coefficient in I 2 C address 0x17.
5. Read middle 8 bits of coefficient in I
2
C address 0x18.
6. Read bottom 8 bits of coefficient in I 2 C address 0x19.
7. Read top 8 bits of coefficient b2 in I
2
C address 0x1A.
8. Read middle 8 bits of coefficient b2 in I 2 C address 0x1B.
9. Read bottom 8 bits of coefficient b2 in I
2
C address 0x1C.
10. Read top 8 bits of coefficient a1 in I 2 C address 0x1D.
11. Read middle 8 bits of coefficient a1 in I
2
C address 0x1E.
12. Read bottom 8 bits of coefficient a1 in I 2 C address 0x1F.
13. Read top 8 bits of coefficient a2 in I
2
C address 0x20.
14. Read middle 8 bits of coefficient a2 in I 2 C address 0x21.
15. Read bottom 8 bits of coefficient a2 in I
2
C address 0x22.
16. Read top 8 bits of coefficient b0 in I 2 C address 0x23.
17. Read middle 8 bits of coefficient b0 in I
2
C address 0x24.
18. Read bottom 8 bits of coefficient b0 in I 2 C address 0x25.
60/78 DocID15251 Rev 8
STA339BW Register description
Writing a single coefficient to RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2. Write 6 bits of address to I
2
C register 0x16.
3. Write top 8 bits of coefficient in I 2 C address 0x17.
4. Write middle 8 bits of coefficient in I
2
C address 0x18.
5. Write bottom 8 bits of coefficient in I 2 C address 0x19.
6. Write 1 to W1 bit in I
2
C address 0x26.
Writing a set of coefficients to RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2. Write 6 bits of starting address to I 2 C register 0x16.
3. Write top 8 bits of coefficient b1 in I
2
C address 0x17.
4. Write middle 8 bits of coefficient b1 in I 2 C address 0x18.
5. Write bottom 8 bits of coefficient b1 in I
2
C address 0x19.
6. Write top 8 bits of coefficient b2 in I 2 C address 0x1A.
7. Write middle 8 bits of coefficient b2 in I
2
C address 0x1B.
8. Write bottom 8 bits of coefficient b2 in I 2 C address 0x1C.
9. Write top 8 bits of coefficient a1 in I
2
C address 0x1D.
10. Write middle 8 bits of coefficient a1 in I 2 C address 0x1E.
11. Write bottom 8 bits of coefficient a1 in I
2
C address 0x1F.
12. Write top 8 bits of coefficient a2 in I 2 C address 0x20.
13. Write middle 8 bits of coefficient a2 in I
2
C address 0x21.
14. Write bottom 8 bits of coefficient a2 in I 2 C address 0x22.
15. Write top 8 bits of coefficient b0 in I
2
C address 0x23.
16. Write middle 8 bits of coefficient b0 in I 2 C address 0x24.
17. Write bottom 8 bits of coefficient b0 in I
2
C address 0x25.
18. Write 1 to WA bit in I 2 C address 0x26.
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA339BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
DocID15251 Rev 8 61/78
78
Register description STA339BW
The STA339BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:
Y[n] = 2 * (b
0
/ 2) * X[n] + 2 * (b
1
/ 2) * X[n-1] + b
2
* X[n-2] - 2 * (a
1
/ 2) * Y[n-1] - a
2
* Y[n-2]
= b
0
* X[n] + b
1
* X[n-1] + b
2
* X[n-2] - a
1
* Y[n-1] - a
2
* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user defined coefficient RAM are referenced in the following manner:
CxHy0 = b
1
/ 2
CxHy1 = b
2
CxHy2 = -a
1
/ 2
CxHy3 = -a
2
CxHy4 = b
0
/ 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b coefficient in the fourth biquad for channel 2.
2
Additionally, the STA339BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass-management crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in
.
By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b
0
/2 coefficient which is set to 0x400000 (representing 0.5)
7.12.19 Prescale
The STA339BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I 2 C registers as the biquad coefficients and the bass management. All channels can use the channel-1 prescale factor by setting the Biquad link bit. By default, all prescale factors are set to 0x7FFFFF.
7.12.20 Postscale
The STA339BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This postscaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. This postscale factor can be used in conjunction with an ADC equipped microcontroller to perform power-supply error correction. All channels can use the channel-1 postscale factor by setting the postscale link bit. By default, all postscale factors are set to 0x7FFFFF. When line output is being used, channel-3 postscale will affect both channels 3 and 4.
62/78 DocID15251 Rev 8
STA339BW Register description
The STA339BW provides a simple mechanism for reacting to overcurrent detection in the power block. When the ocwarn input is asserted, the overcurrent postscale value is used in place of the normal postscale value to provide output attenuation on all channels. The default setting provides 3 dB of output attenuation when ocwarn is asserted.
The amount of attenuation to be applied in this situation can be adjusted by modifying the
Overcurrent postscale value. As with the normal postscale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the overcurrent postscale factor is set to 0x5A9DF7 . Once the overcurrent attenuation is applied, it remains until the device is reset.
Table 73. RAM block for biquads, mixing, scaling and bass management
Index (decimal) Index (hex) RAM block setting Coefficient Default
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x13
0x14
0x15
…
0x27
0x28
0x29
0x2A
0x00
0x01
0x02
0x03
0x04
0x05
…
47
48
49
50
43
44
45
46
51
52
53
54
39
40
41
42
19
20
21
…
3
4
5
…
0
1
2 Channel 1 - Biquad 1
Channel 1 - Biquad 2
…
Channel 1 - Biquad 4
Channel 2 - Biquad 1
…
Channel 2 - Biquad 4
Channel 1/2 - Biquad 5 for XO = 000
High-pass 2 nd
order filter for XO 000
Channel 3 - Biquad for XO = 000
Low-pass 2 nd
order filter for XO 000
Channel 1 - Prescale
Channel 2 - Prescale
Channel 1 - Postscale
Channel 2 - Postscale
Channel 3 - Postscale
C12H3(a2)
C12H4(b0/2)
C3H0(b1/2)
C3H1(b2)
C3H2(a1/2)
C3H3(a2)
C3H4(b0/2)
C1PreS
C2PreS
C1PstS
C2PstS
C3PstS
C1H10(b1/2)
C1H11(b2)
C1H12(a1/2)
C1H13(a2)
C1H14(b0/2)
C1H20
…
C1H44
C2H10
C2H11
…
C2H44
C12H0(b1/2)
C12H1(b2)
C12H2(a1/2)
0x000000
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x000000
0x000000
0x000000
0x000000
0x400000
0x000000
…
0x400000
0x000000
0x000000
…
0x400000
0x000000
0x000000
0x000000
DocID15251 Rev 8 63/78
78
Register description STA339BW
59
60
61
62
63
55
56
57
58
Table 73. RAM block for biquads, mixing, scaling and bass management (continued)
Index (decimal) Index (hex) RAM block setting Coefficient Default
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
TWARN/OC - Limit
Channel 1 - Mix 1
Channel 1 - Mix 2
Channel 2 - Mix 1
Channel 2 - Mix 2
Channel 3 - Mix 1
Channel 3 - Mix 2
Unused
Unused
TWOCL
C1MX1
C1MX2
C2MX1
-
C2MX2
C3MX1
-
C3MX2
0x5A9DF7
0x7FFFFF
0x000000
0x000000
-
0x7FFFFF
0x400000
-
0x400000
7.13 Variable max power correction registers (addr 0x27 - 0x28)
D7
MPCC15
0
D6
MPCC14
0
D5
MPCC13
0
D4
MPCC12
1
D3
MPCC11
1
D2
MPCC10
0
D1
MPCC9
1
D0
MPCC8
0
D7
MPCC7
1
D6
MPCC6
1
D5
MPCC5
0
D4
MPCC4
0
D3
MPCC3
0
D2
MPCC2
0
D1
MPCC1
0
D0
MPCC0
0
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.
7.14 Variable distortion compensation registers (addr 0x29 -
0x2A)
D7
DCC15
1
D6
DCC14
1
D5
DCC13
1
D4
DCC12
1
D3
DCC11
0
D2
DCC10
0
D1
DCC9
1
D0
DCC8
1
D7
DCC7
0
D6
DCC6
0
D5
DCC5
1
D4
DCC4
1
D3
DCC3
0
D2
DCC2
0
D1
DCC1
1
D0
DCC0
1
DCC bits determine the 16 MSBs of the Distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.
64/78 DocID15251 Rev 8
STA339BW Register description
7.15 Fault detect recovery constant registers (addr 0x2B - 0x2C)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
0
D4
FDRC12
0
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the
TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C gives approximately 0.1 ms.
7.16 Device status register (addr 0x2D)
7
6
5
4
3
2
1
0
D7
PLLUL
D6
FAULT
D5
UVFAULT
D4
OVFAULT
D3
OCFAULT
D2
OCWARN
D1
TFAULT
D0
TWARN
This read-only register provides fault- and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning has been detected on the power bridge. The PLLUL = 1 means that the
PLL is not locked.
Bit
R
R
R
R
R
R
R
R
R/W
-
-
-
-
-
-
-
-
RST
PLLUL
FAULT
Table 74. Status register bits
Name Description
UVFAULT
OVFAULT
OCFAULT
OCWARN
TFAULT
TWARN
0: PLL locked
1: PLL not locked
0: fault detected on power bridge
1: normal operation
0: VCCxX internally detected
1: undervoltage threshold
0: VCCxX internally detected
1: overvoltage threshold
0: overcurrent fault detected
0: overcurrent warning
0: thermal fault, junction temperature over limit
0: thermal warning, junction temperature is close to fault condition
DocID15251 Rev 8 65/78
78
Register description STA339BW
7.17 EQ coefficients and DRC configuration register (addr 0x31)
00/11
01
10
D7
XOB
0
SEL[1:0]
D6
0
Reserved
D5
0
D4
AMGC[3]
0
D3
AMGC[2]
0
D2
Reserved
0
Table 75. EQ RAM select
EQ RAM bank selected
Bank 0 activated
Bank 1 activated
Bank 2 activated
D1
SEL[1]
0
D0
SEL[0]
0
Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in
00
01
10/11
AMGC[3:2]
Table 76. Anti-clipping and DRC preset
Anti-clipping and DRC preset selected
DRC/Anti-clipping behavior described in
Table 56 on page 48 (default).
DRC/Anti-clipping behavior is described in
Reserved, do not use
00
01
10
11
When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in
.
AMGC[1:0]
Table 77. Anti-clipping selection for AMGC[3:2] = 01
Mode
AC0, stereo anticlipping 0 dB limiter
AC1, stereo anticlipping +1.25 dB limiter
AC2, stereo anticlipping +2 dB limiter
Reserved do not use
AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the minimum any audio artefacts introduced by typical anti-clipping/DRC algorithms. More detailed information is available in the applications notes “Configurable output power rate using STA335BW” and “STA335BWS vs STA335BW”.
Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not active. In this case, high pass crossover filter works as a passtrough on the data path
(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have zero signal on channel-3 data processing (all the coefficients are at logic 0).
66/78 DocID15251 Rev 8
STA339BW Register description
7.18 Extended configuration register (addr 0x36)
D7
Mdrc[1]
0
D6
Mdrc[0]
0
D5
PS48DB
0
D4
XAR1
0
D3
XAR2
0
D2
BQ5
0
D1
BQ6
0
Extended configuration register provides access to B
2
DRC and biquads 5, 6 and 7.
D0
BQ7
0
The STA339BW provides a dual-band DRC (B 2 DRC) on the left- and right-channel data path, as depicted in
Figure 21 . Dual-band DRC is activated by setting MDRC[1:0] = 1x.
Figure 21. B 2 DRC scheme
The low-frequency information (LFE) is extracted from the left and right channels by removing the high frequencies with a programmable Biquad filter, so that, using the original signal, the difference signal can be computed. Limiter 1 (DRC1) is then used to control the left and right high-frequency component amplitudes while limiter 2 (DRC2) is used to control the low-frequency components (see
).
The cutoff frequency of the high-pass filters can be user defined, XO[3:0] = 0, or selected from the pre-defined values.
DRC1 and DRC2 are then used to independently limit the left- and right-channel high
frequencies and the LFE-channel amplitude (see Chapter 7.11
control. Note that, in this configuration, the dedicated channel-3 volume control can actually be used as a bass boost enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.
Sub band decomposition
The sub band decomposition for B
2
DRC can be configured specifying the cutoff frequency.
The cut off frequency can be programmed in two ways, using XO bits in register 0x0C, or using “user programmable” mode (coefficients stored in RAM adresses 0x28 to 0x31).
DocID15251 Rev 8 67/78
78
Register description STA339BW
For the user programmable mode, use the formulae below to compute the high pass filters: b0 = (1 + alpha) / 2 b1 = -(1 + alpha) / 2 a0 = 1 a1 = -alpha b2 = 0 a2 = 0 where alpha = (1-sin(
0
))/cos(
0
), and
0
is the cutoff frequency.
A first-order filter is suggested to guarantee that for every
0
the corresponding low-pass filter obtained as difference (as shown in
Figure 21 ) will have a symmetric (relative to HP
filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully choosen to provide good low pass response and minimum ripple recombination.
For second-order is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.
DRC settings
The DRC blocks used by B 2 DRC are the same as those described in
2 DRC configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14.
Band downmixing
The low-frequency band is down-mixed to the left and right channels at the B 2 DRC output.
Channel volume can be used to weight the bands recombination to fine tune the overall frequency response.
7.18.2 EQ DRC mode
Note:
Setting MDRC = 01, it is possible to add a programmable biquad (the XO biquad at RAM addresses 0x28 to 0x2C is used for this purpose) to the Limiter/compressor measure path
(side chain). Using EQDRC the peak detector input can be shaped in frequency using the programmable biquad. For example if a +2 dB bass boost is applied (using a low shelf filter for example), the effect is that the EQDRC out will limit bass frequencies to -2 dB below the selected attack treshold.
Generally speaking, if the biquad boosts frequency f with an amount of X dB, the level of a compressed sinusoid at the output will be TH - X, where TH is the selected attack threshold.
EQDRC works only if the biquad frequency response magnitude is >= 0 dB for every frequency.
68/78 DocID15251 Rev 8
STA339BW
Figure 22. EQDRC scheme
Register description
7.18.3 Extended post scale range
0
1
PS48DB
Table 78. Post scale setup
Mode
Postscale value is applied as defined in coefficient RAM
Postscale value is applied with +48-dB offset with respect to the coefficient RAM value
Post scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the configured word, so postscale can act as a gain too.
7.18.4 Extended attack rate
The attack rate shown in
Table 67 can be extended to provide up to 8 dB/ms attack rate on
both limiters.
0
1
XAR1
Table 79. Extended attack rate setup for limiter 1
Mode
Limiter1 attack rate is configured using
Limiter1 attack rate is 8 dB/ms
0
1
XAR2
Table 80. Extended attack rate setup for limiter 2
Mode
Limiter2 attack rate is configured using
Limiter2 attack rate is 8 dB/ms
DocID15251 Rev 8 69/78
78
Register description STA339BW
7.18.5 Extended BIQUAD selector
De-ephasis filter as well as bass and treble controls can be configured as user defined filters when equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.
0
1
BQ5
Table 81. De-emphasis filter setup
Mode
Preset de-emphasis filter selected
User defined biquad 5 coefficients are selected
Note:
0
1
BQ6
Table 82. Bass filter setup
Mode
Preset bass filter selected as per
User defined biquad 6 coefficients are selected
0
1
BQ7
Table 83. Treble filter setup
Mode
Preset treble filter selected as per
User defined biquad 7 coefficients are selected
When filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-
0x2E (BQ7) as in
BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for
BQ6 and BQ7).
7.19 EQ soft volume configuration registers (addr 0x37 - 0x38)
D7
0
Reserved
D6
0
D5
SVUPE
0
D4
SVUP[4]
0
D3
SVUP[3]
0
D2
SVUP[2]
0
D1
SVUP[1]
0
D0
SVUP[0]
0
D7
0
Reserved
D6
0
D5
SVDWE
0
D4
SVDW4]
0
D3
SVDW[3]
0
D2
SVDW[2]
0
D1
SVDW[1]
0
D0
SVDW[0]
0
Soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to override the default behavior allowing different volume change rates.
It is also possible to independently define the fade-in (volume is increased) and fade-out
(volume is decreased) rates according to the desired behavior.
70/78 DocID15251 Rev 8
STA339BW Register description
0
1
SVUPE
Table 84. Soft volume (increasing) setup
Mode
When volume is increased, use the default rate
When volume is increased, use the rates defined by SVUP[4:0] .
When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the formula:
Fade-in rate = 48 / (SVUP[4:0] + 1) dB/ms.
0
1
SVDWE
Table 85. Soft volume (decreasing) setup
Mode
When volume is decreased, use the default rate
When volume is decreased, use the rates defined by SVDW[4:0] .
When SVDWE = 1 the fade-out rate is defined by the SVDW[4:0] bits according to the formula:
Fade-in rate = 48 / (SVDW[4:0] + 1) dB/ms.
7.20 DRC RMS filter coefficients (addr 0x39 - 0x3E)
D7
R_C0[23]
0
D7
R_C0[15]
1
D7
R_C0[7]
1
D7
R_C1[23]
0
D7
R_C1[15]
1
D6
R_C0[22]
0
D6
R_C0[14]
1
D6
R_C0[6]
1
D6
R_C1[22]
1
D5
R_C0[21]
0
D5
R_C0[13]
1
D5
R_C0[5]
1
D5
R_C1[21]
1
D4
R_C0[20]
0
D4
R_C0[12]
0
D4
R_C0[4]
1
D4
R_C1[20]
1
D3
R_C0[19]
0
D3
R_C0[11]
1
D3
R_C0[3]
1
D3
R_C1[19]
1
D2
R_C0[18]
0
D2
R_C0[10]
1
D2
R_C0[2]
1
D2
R_C1[18]
1
D1
R_C0[17]
0
D1
R_C0[9]
1
D1
R_C0[1]
1
D1
R_C1[17]
1
D0
R_C0[16]
1
D0
R_C0[8]
0
D0
R_C0[0]
1
D0
R_C1[16]
0
D6
R_C1[14]
1
D5
R_C1[13]
0
D4
R_C1[12]
0
D3
R_C1[11]
0
D2
R_C1[10]
0
D1
R_C1[9]
0
D0
R_C1[8]
0
D7
R_C1[7]
0
D6
R_C1[6]
0
D5
R_C1[5]
1
D4
R_C1[4]
0
D3
R_C1[3]
0
D2
R_C1[2]
1
D1
R_C1[1]
1
D0
R_C1[0]
0
Signal level detection in DRC algorithm is computed usign the following formula: y(t) = c0 * abs(x(t)) + c1 * y(t-1) where x(t) represents the audio signal applied to the limiter, and y(t) the measured level.
DocID15251 Rev 8 71/78
78
Application
8 Application
8.1
STA339BW
Application scheme for power supplies
Here in
Figure 23 below is the typical application diagram for STA339BW showing the
power supply decoupling. Particular care has to be taken with the layout of the PCB. In particular the 3.3 resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This helps to prevent unwanted oscillation in the digital part of the device due to the inductive tracks of the PCB. The same rule also applies to all the decoulpling capacitors in order to limit spikes on all the supplies.
Figure 23. Application diagram
72/78
It is recommended to use the above scheme and values for the PLL filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, remember that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter.
DocID15251 Rev 8
STA339BW
8.3
Application
Typical output configuration
Here after the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other possible output configuration recommended schematics.
Figure 24. Output configuration for stereo BTL mode
DocID15251 Rev 8 73/78
78
Package thermal characteristics
9 Package thermal characteristics
STA339BW
Using a double-layer PCB the thermal resistance junction to ambient with 2 copper ground areas of 3 x 3 cm 2
and with 16 via holes (see Figure 25 ) is 24 °C/W in natural air
convection.
The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.
Thus, the maximum estimated dissipated power for the STA339BW is:
2 x 20 W @ 8 , 18 V Pd max ~ 4 W
2 x 10 W + 1 x 20 W @ 4 , 8 ,18 V Pd max < 5 W
Figure 25. Double-layer PCB with 2 copper ground areas and 16 via holes
shows the power derating curve for the PowerSSO-36 slug-down package on
PCBs with copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 .
Figure 26. PowerSSO-36 power derating curve
STA339BW
PowerSSO-36
74/78 DocID15251 Rev 8
STA339BW
10 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
shows the package outline and
Table 86 gives the dimensions of the
PowerSSO-36 package with exposed pad (slug) down (EPD).
Symbol
Min k
L
H h
F
G e e3
D
E b c
A
A2 a1
O
Q
M
N
S
T -
-
U -
X 4.10
Y 4.90
-
-
-
-
-
-
-
-
-
10.10
0
0.60
2.15
2.15
0
0.18
0.23
10.10
7.40
-
-
-
-
0.5
8.5
-
2.3
-
-
-
-
-
-
-
-
2.90
3.65
-
1.00
-
4.30
1.20
0.80
Typ
Table 86. PowerSSO-36 EPD dimensions
Dimensions in mm Dimensions in inches
Max Min
2.47
2.40
0.10
0.36
0.32
10.50
7.60
-
-
-
0.10
10.50
0.40
8 degrees
1.00
-
-
-
4.70
7.10
-
-
-
10 degrees -
-
-
-
-
-
-
0.161
0.193
-
-
-
-
-
0.398
-
0.024
0.085
0.085
0
0.007
0.009
0.398
0.291
0.047
0.031
0.114
0.144
-
-
0.039
Typ
0.020
0.335
-
0.091
-
-
-
-
0.169
-
-
-
-
-
-
-
Max
0.097
0.094
0.004
0.014
0.013
0.413
0.299
-
-
-
0.004
0.413
0.016
8 degrees
0.039
-
-
-
10 degrees
-
-
-
0.185
0.280
DocID15251 Rev 8 75/78
78
Figure 27. PowerSSO-36 EPD outline drawing h x 45°
STA339BW Revision history
Date
09-Dec-2008
16-Feb-2009
01-Apr-2009
15-May-2009
04-Aug-2010
18-Sep-2013
13-Feb-2014
05-Jan-2015
Revision
Table 87. Document revision history
Changes
1
2
3
4
5
6
7
8
Initial release
Updated names/descriptions for pins 17-20 in Chapter 2 on page 12
Added cross reference to I
2
S interface setup in
Updated text and
Figure 23: Application diagram on page 72
Updated
Section 8.2: PLL filter on page 72
Updated Y dimension in
Table 86: PowerSSO-36 EPD dimensions on page 75
Updated
to “8 programmable 28-bit biquads”
Updated I il
and I ih
in
Table 6: Electrical specifications - digital section
Updated I lim
and I sc
in
Table 7: Electrical specifications - power section on page 16
Updated register FDRC addresses in
Section 7.1.5: Fault detect recovery bypass on page 30
Updated bits 4 and 5 in
Table 74: Status register bits on page 65 .
Updated order code in Table 1: Device summary on page 1
Updated name of Chapter 10 on page 75
to
Added
Modified
Updated Company information appearing on last page of document
Updated order code in Table 1 on page 1
Updated I lim
in
Table 7: Electrical specifications - power section
DocID15251 Rev 8 77/78
78
STA339BW
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Key features
Dedicated LFE processing for enhanced bass response
Wide selection of audio presets for various listening preferences
Advanced noise suppression for pristine audio quality
Flexible power output configurations for stereo or multi-channel setups
Comprehensive processing capabilities with EQ, DRC, and biquads
I2C control interface for easy system integration
Automatic zero-detect and invalid input-detect mute for reliable operation
Frequently asked questions
The STA339BW offers three power output configurations: 2 channels of ternary PWM (stereo mode), 3 channels (left, right using binary and LFE using ternary PWM), and 2 channels of ternary PWM plus stereo lineout ternary.
Yes, the STA339BW allows for individual channel and master volume and gain control, providing precise adjustment for each audio source.
The STA339BW features dedicated LFE processing with 0.5 dB/step resolution, ensuring accurate and powerful bass enhancement for an immersive audio experience.