The STA333BW is an integrated solution of digital audio processing, digital amplifier controls and power output stages to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The

FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor.

The STA333BW is part of the Sound Terminal

family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment.

The power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes.

For example, 2.1 channels can be provided by two half-bridges and a single full-bridge, supplying up to 2 x 9 W + 1 x 20 W of output power or two channels can be provided by two full-bridges, supplying up to 2 x 20 W of output power.

The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device plus a drive for an external FFX power amplifier, such as STA533WF or STA515W.

The serial audio data input interface accepts all possible formats, including the popular I²S format. The high-quality conversion from PCM audio to FFX PWM switching provides over

100 dB of SNR and of dynamic range.

Also provided in the STA333BW are a full assortment of digital processing features. This includes up to 5 programmable biquads (EQ) per channel. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes.

The DRC dynamically equalizes the system to provide a linear frequency speaker response regardless of output power level.

Figure 1. Block diagram

I²C

Protection current / thermal

I²S interface

Channel

Volume control

FFX

Power control

PLL

Digital DSP

Logic

Regulators

Bias

Channel

Power

Channel

8/68 DocID13773 Rev 5

STA333BW Pin connections

Figure 2. Pin connection PowerSSO-36 (top view)

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B / FFX3B

OUT3A / FFX3A

EP, exposed pad

(device ground)

D05AU1638

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN / OUT4A

EAPD / OUT4B

Pin Type

GND

I/O

GND

Power

Name

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

Table 2. Pin description

Description

Substrate ground

I²C select address (pull-down)

This pin must be connected to ground (pull-down)

Internal reference at V

- 3.3 V

Internal V

reference

Output half-bridge channel 2B

Power negative supply

Power positive supply

Output half-bridge channel 2A

Output half-bridge channel 1B

DocID13773 Rev 5 9/68

Pin connections STA333BW

Pin

I/O

Power

GND

Power

GND

I/O

GND

Power

Type

Power

GND

Power

Table 2. Pin description (continued)

Name Description

FILTER_PLL

GND_PLL

XTI

BICKI

LRCKI

SDI

RESET

INT_LINE

SDA

SCL

GND_DIG

VDD_DIG

VCC1

GND1

OUT1A

Power positive supply

Power negative supply

Output half-bridge channel 1A

GND_REG

VDD

Internal ground reference

Internal 3.3 V reference voltage

CONFIG Parallel mode command

OUT3B / FFX3B PWM out channel 3B / external bridge driver

OUT3A / FFX3A PWM out channel 3A / external bridge driver

EAPD / OUT4B Power down for external bridge / PWM out channel 4B

TWARN / OUT4A

VDD_DIG

GND_DIG

PWRDN

VDD_PLL

Thermal warning from external bridge (pull-up when input)

/ PWM out channel 4A

Digital supply voltage

Digital ground

Power down (pull-up)

Positive supply for PLL

Connection to PLL filter

Negative supply for PLL

PLL input clock

I²S serial clock

I²S left / right clock

I²SI²S serial data channels 1 and 2

Reset (pull-up)

Fault interrupt

I²C serial data

I²C serial clock

Digital ground

Digital supply voltage

Exposed pad for PCB heatsink, to be connected to GND

10/68 DocID13773 Rev 5

STA333BW Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min

T op

T stg

Power supply voltage (pins VCCx)

Digital supply voltage (pins VDD_DIG)

PLL supply voltage (pin VDD_PLL)

Operating junction temperature

-0.3

-20

Typ Max

4.0

150

Unit

°C

Warning:

Stresses beyond those listed in Table 3

above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under

“Recommended operating conditions” are not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.

Table 4. Thermal data

Parameter

R th j-case

T th-sdj

Thermal resistance junction-case (thermal pad)

Thermal shut-down junction temperature -

T th-w

T th-sdh

R th j-amb

Thermal warning temperature

Thermal shut-down hysteresis

Thermal resistance junction-ambient

(1)

See

Chapter 9: Package thermal characteristics on page 64

for details.

Min Typ

150

130

Max

1.5

Unit

°C/W

°C

°C/W

DocID13773 Rev 5 11/68

Electrical specifications

3.3 Recommended operating conditions

Table 5. Recommended operating condition

DD_DIG

DD_PLL

T amb

Power supply voltage (VCCxA, VCCxB)

PLL supply voltage

STA333BW

4.5

21.5

2.7 3.3 3.6 V

2.7

3.3

3.6

-20 70 °C

The specifications given in this section are valid for T amb

= 25 °C unless otherwise specified.

Table 6. Electrical specifications - digital section

Symbol Parameter Conditions Min Typ Max Unit

I il

I ih

Low level input current without pull-up/down device

High level input current without pull-up/down device

Vi = 0 V

Vi = VDD_DIG

= 3.6 V

µA

V il

Low level input voltage -

0.2 *

VDD_DIG

V ih

High level input voltage -

0.8 *

VDD_DIG

V ol

Low level output voltage Iol = 2 mA -

0.4 *

VDD_DIG

V oh

High level output voltage Ioh = 2 mA

0.8 *

VDD_DIG

R pu

Equivalent pull-up/down resistance

50 k



12/68 DocID13773 Rev 5

STA333BW Electrical specifications

The specifications given in this section are valid for the operating conditions: V

CC f = 1 kHz, f sw

= 384 kHz, T amb

= 25 °C and R

= 8



, unless otherwise specified.

= 18 V,

Symbol

Table 7. Electrical specifications - power section

Parameter Conditions Min Typ Max Unit

I t

Po t r t f

R dsON gP gN

Idss

VCC

VDD

LIM

SCP

UVP min

THD = 1%

Output power BTL

Output power SE

THD = 10%

THD = 1%, R

= 4



THD = 10%, R

= 4



Power P-channel or N-channel MOSFET l d

= 0.75 A

Power P-channel R dsON

matching l d

= 0.75 A -

Power N-channel R dsON

matching

Power P-channel / N-channel leakage l d

= 0.75 A

= 20 V

Rise time -

Fall time

Resistive load, see

Figure 3

below

Supply current from V

in power down PWRDN = 0

Supply current from V

in operation PWRDN = 1

Supply current FFX processing

Internal clock =

49.152 MHz

Overcurrent limit

(1)

Short -circuit protection

Undervoltage protection -

= 0



100

0.3

2.2

3.0

2.7 3.6

Output minimum pulse width

Dynamic range

Signal to noise ratio, ternary mode

No load

A-Weighted -

20 40

100

250

W m





10 ns

4.3

60 ns



A mA mA

SNR

THD+N



TALK

Signal to noise ratio binary mode

Total harmonic distortion + noise

Crosstalk

Peak efficiency, FFX mode

Peak efficiency, binary modes

FFX stereo mode,

Po = 1 W f = 1 kHz

FFX stereo mode,

<5 kHz

One channel driven at 1 W, other channel measured

Po = 2 x 20 W into 8



Po = 2 x 9 W into 4



+ 1 x 20 W into 8



0.2

% dB

Limit the current if overcurrent warning detect adjustment bypass is enabled (register bit CONFC.OCRB on page 29 ).

When disabled refer to the I

SCP

ns dB dB

DocID13773 Rev 5 13/68

Electrical specifications STA333BW

Figure 3. Test circuit

OUTxY tr tf

+Vcc

Duty cycle = 50%

INxY

M58

M57 gnd

OUTxY R 8



V67 vdc = Vcc/2

VCC

(0.9)*VCC

½VCC

(0.1)*VCC t

14/68 DocID13773 Rev 5

STA333BW Electrical specifications

Note:

Figure 4. Power-on sequence

Note: no specific VCC and

VDD_DIG turn

 on sequence is required

VCC

VDD_Dig

XTI

Reset

Don’t care

I 2 C

Don’t care CMD0 CMD1 CMD2

PWDN

TR = minimum time between XTI master clock stable and Reset removal: 1 ms

TC = minimum time between Reset removal and I²C program, sequence start: 1ms

The definition of a stable clock is when f max

- f min

< 1 MHz.

Section Serial audio input interface format on page 26 gives information on setting up the

I²S interface.

Figure 5. Power-off sequence for pop-free turn-off

Note: no specific VCC and

VDD_DIG turn

 off sequence is required

DocID13773 Rev 5 15/68

Serial audio interface

4 Serial audio interface

STA333BW

The STA333BW audio serial input interface was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA333BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock

BICKI, and serial data SDI12.

The SAI bit and the SAIFB bit are used to specify the serial data format. The default serial data format is I²S, MSB-first.

4.0.1 Timings

In the STA333BW the BICKI and LRCKI pins are configured as inputs and they must be supplied by the external peripheral.

Figure 6. Timing diagram for SAI interface t

BCH t

BCL

80%

BICKI 40% t

BCy

LRCKI

SDI12 t

LRH t

LRSU

4.0.2

4.0.3

Symbol t

BCy t

BCH t

BCL t

LRSU t

LRH t

LRJT

Table 8. Timing parameters for slave mode

Parameter

BICK cycle time

BICK pulse width high

BICK pulse width low

LRCKI setup time to BICKI strobing edge

LRCKI hold time to BICKI strobing edge

LRCKI Jitter Tolerance

Min

Typ Max Unit

40 ns ns ns ns ns ns

Delay serial clock enable

To tolerate anomalies in some I²S master devices, a PLL clock cycle delay can be added to the BICKI signal before the SAI interface.

Channel input mapping

Each channel received via I²S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I²S input channel to its corresponding processing channel.

16/68 DocID13773 Rev 5

STA333BW

5 Processing data paths

Processing data paths

Figure 7 and

Figure 8

below show the data processing paths inside STA333BW. The whole processing chain is composed of two consecutive sections. In the first one, dual-channel processing is implemented and in the second section each channel is fed into the post mixing block either to generate a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the DRC block (2.0 output configuration with crossover filters used to define the cut-off frequency of the two bands).

The first section, Figure 7

, begins with a 2x oversampling FIR filter providing 2 * f

audio processing. Then a selectable high-pass filter removes the DC level (enabled if HPB = 0).

The left and right channel processing paths can include up to 8 filters, depending on the selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, four user programmable, independent filters per channel are enabled, plus the preconfigured de-emphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).

If the coefficient sets for the two channels are linked (BQL = 1) it is possible to use the de-emphasis, bass and treble filters in a user defined configuration (provided the relevant

BQx bits are set). In this case both channels use the same processing coefficients and can have up to seven filters each. If BQL = 0 the BQx bits are ignored and the fifth, sixth and seventh filters are configured as de-emphasis, bass and treble controls, respectively.

Figure 7. Left and right processing, section 1 x2

FIR

I2S input interface

FIR

FIR sampling

Hi-Pass

Filter

Biquad

Moreover, the common 8th filter can be available on both channels provided the predefined crossover frequencies are not used, XO[3:0] = 0, and the DRC is not used.

In the second section,

Figure 8 , mixing and crossover filters are available. If DRC is not

enabled they are fully user-programmable and allow the generation of a third channel

(2.1 outputs). Alternatively, in mode DRC, these blocks are used to split the sub-band and define the cut-off frequencies of the two bands. A prescaler and a final postscaler allow full control over the signal dynamics before and after the filtering stages. A mixer function is also available.

DocID13773 Rev 5 17/68

Processing data paths

Figure 8. Left and right processing, section 2

STA333BW

18/68 DocID13773 Rev 5

STA333BW

6 I²C bus specification

I²C bus specification

The STA333BW supports the I²CI²C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA333BW is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate).

For correct operation of the I²C interface ensure that the master clock generated by the PLL has a frequency at least 10 times higher than the frequency of the applied SCL clock.

6.1.1 Data transition or change

Data changes on the SDA line must only occur when the clock SCL is low. A SDA transition while the clock is high is used to identify a START or STOP condition.

START is identified by a high to low transition of the data bus, SDA, while the clock, SCL, is stable in the high state. A START condition must precede any command for data transfer.

STOP is identified by low to high transition of SDA while SCL is stable in the high state. A

STOP condition terminates communication between STA333BW and the bus master.

During the data input the STA333BW samples the SDA signal on the rising edge of SCL.

For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

To start communication between the master and the STA333BW, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode bit.

The seven most significant bits are the device address identifiers, corresponding to the I²C bus definition. In the STA333BW the I²C interface has two device addresses depending on the SA pin configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies a read or write operation (R/W); this is set to 1 for read and to

0 for write. After a START condition the STA333BW identifies the device address on the

SDA bus and if a match is found, acknowledges the identification during the 9th bit time frame. The byte following the device identification is the address of a device register.

DocID13773 Rev 5 19/68

I²C bus specification STA333BW

Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then waits for the byte of internal address.

After receiving the internal byte address the STA333BW again responds with an acknowledgment.

In the byte write mode the master sends one data byte, this is acknowledged by the

STA333BW. The master then terminates the transfer by generating a STOP condition.

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

BYTE

WRITE

MULTIBYTE

WRITE

START

DEV-ADDR

Figure 9. Write mode sequence

ACK ACK ACK

SUB-ADDR DATA IN

STOP

ACK ACK ACK

SUB-ADDR DATA IN

DATA IN

ACK

STOP

6.4.1

6.4.2

6.4.3

Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data.

The master then terminates the transfer by generating a STOP condition.

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA333BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

20/68 DocID13773 Rev 5

STA333BW

6.4.4

I²C bus specification

Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

Figure 10. Read mode sequence

CURRENT

ADDRESS

READ

START

RANDOM

ADDRESS

READ

START

SEQUENTIAL

CURRENT

READ

START

SEQUENTIAL

RANDOM

READ

START

ACK

DEV-ADDR

ACK

DEV-ADDR

RW=

ACK

DEV-ADDR

HIGH

DEV-ADDR

ACK

NO ACK

DATA

SUB-ADDR

DATA

ACK

STOP

DEV-ADDR

ACK

START

DATA

ACK

SUB-ADDR

ACK

START

DEV-ADDR

ACK

DATA

NO ACK

STOP

ACK

STOP

DATA

ACK

DATA

NO ACK

STOP

DocID13773 Rev 5 21/68

Register description STA333BW

Note:

Addr Name

0x00 CONFA

0x01 CONFB

0x02 CONFC

0x03 CONFD

0x04 CONFE

0x05 CONFF

0x06 MUTELOC

0x07 MVOL

0x08 C1VOL

0x09 C2VOL

0x0A C3VOL

0x0B AUTO1

0x0C AUTO2

0x0D AUTO3

0x0E C1CFG

0x0F C2CFG

0x10 C3CFG

0x11 TONE

0x12 L1AR

0x13 L1ATRT

0x14 L2AR

0x15 L2ATRT

0x16 CFADDR

0x17 B1CF1

0x18 B1CF2

0x19 B1CF3

0x1A B2CF1

0x1B B2CF2

0x1C B2CF3

0x1D A1CF1

0x1E A1CF2

Reserved

XO3

C1OM1

C2OM1

C3OM1

TTC3

L1A3

L1AT3

L2A3

L2AT3

Reserved

FDRB

C2IM

OCRB

SME

SVE

EAPD

LOC1

Addresses exceeding the maximum address number must not be written.

TWAB

C1IM

Reserved

ZDE

ZCE

PWDN

LOC0

C1OM0

C2OM0

C3OM0

TTC2

L1A2

L1AT2

L2A2

L2AT2

Reserved

Table 9. Register summary

Reserved

XO2

D5 D4 D3 D2 D1 D0

C2LS1

C3LS1

TTC1

L1A1

L1AT1

L2A1

L2AT1

TWRB

DSCKE

CSZ3

DRC

DCCV

ECLE

Reserved

IR1

SAIFB

CSZ2

BQL

PWMS

LDTE

Reserved

IR0

SAI3

CSZ1

PSL

AME

BCLE

C3M

MVOL[7:0]

C1VOL[7:0]

C2VOL[7:0]

C3VOL[7:0]

XO1

AMGC[1:0]

XO0

C1LS1

Reserved

AMAM2

Reserved

AMAM1

Reserved

C1LS0 C1BO C1VBP

MCS2

SAI2

CSZ0

MCS1

SAI1

OM1

MCS0

SAI0

OM0

DSPB DEMP HPB

NSBW MPC MPCV

IDE

C2M

OCFG1

C1M

OCFG0

Reserved

AMAM0

Reserved

AMAME

C2LS0

C3LS0

TTC0

L1A0

L1AT0

L2A0

L2AT0

C2BO

C3BO

BTC3

L1R3

L1RT3

L2R3

C2VBP

C3VBP

BTC2

L1R2

L1RT2

L2R2

L2RT3

CFA[5:0]

L2RT2

C1EQBP

C2EQBP

Reserved

BTC1

L1R1

L1RT1

L2R1

L2RT1

C1TCB

C2TCB

Reserved

BTC0

L1R0

L1RT0

L2R0

L2RT0

C1B[23:16]

C1B[15:8]

C1B[7:0]

C2B[23:16]

C2B[15:8]

C2B[7:0]

C3B[23:16]

C3B[15:8]

22/68 DocID13773 Rev 5

STA333BW

Addr Name

0x1F A1CF3

0x20 A2CF1

0x21 A2CF2

0x22 A2CF3

0x23 B0CF1

0x24 B0CF2

0x25 B0CF3

0x26 CFUD

0x27 MPCC1

0x28 MPCC2

0x29 DCC1

0x2A DCC2

0x2B FDRC1

0x2C FDRC2

0x2D STATUS

Register description

PLLUL

Table 9. Register summary (continued)

D6 D5 D4 D3

FAULT

Reserved

UVFAULT

C3B[7:0]

C4B[23:16]

C4B[15:8]

C4B[7:0]

C5B[23:16]

C5B[15:8]

C5B[7:0]

MPCC[15:8]

MPCC[7:0]

DCC[15:8]

DCC[7:0]

FDRC[15:8]

FDRC[7:0]

Reserved OCFAULT

OCWARN

TFAULT

TWARN

FDRB

TWAB

Master clock select

Bit R/W

R/W

TWRB

IR1

IR0

MCS2

MCS1

MCS0

RST

Table 10. Master clock select

Name Description

MCS0

MCS1

MCS2

Selects the ratio between the input I²S sample frequency and the input clock.

The STA333BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:



32.768 MHz for 32 kHz



45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz



49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f s

DocID13773 Rev 5 23/68

Register description STA333BW

The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.

Table 11. Input sampling rates

Input sample rate

fs (kHz)

IR MCS[2:0]

32, 44.1, 48

88.2, 96

176.4, 192

101 100 011 010 001 000

576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

Interpolation ratio select

Bit

4:3

R/W

R/W 00

RST

Table 12. Internal interpolation ratio

Name Description

IR [1:0]

Selects internal interpolation ratio based on input I²S sample frequency

The STA333BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.

44.1

88.2

176.4

192

Table 13. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR 1st stage interpolation ratio

2-times oversampling

Pass-through

2-times downsampling

24/68 DocID13773 Rev 5

STA333BW Register description

Thermal warning recovery bypass

Bit R/W

R/W 1

RST

Table 14. Thermal warning recovery bypass

Name Description

TWRB

0: thermal warning recovery enabled

1: thermal warning recovery disabled

This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled the device automatically restores the normal gain and output limiting is no longer active. If it is disabled the device keeps the output limit active until a reset is asserted or until TWRB set to 0. This bit works in conjunction with TWAB

Thermal warning adjustment bypass

Bit R/W

R/W 1

Table 15. Thermal warning adjustment bypass

RST Name Description

TWAB

0: thermal warning adjustment enabled

1: thermal warning adjustment disabled

Bit TWAB enables automatic output limiting when a power stage thermal warning condition persists for longer than 400ms. When the feature is active (TWAB = 0) the desired output limiting, set through bit TWOCL (-3 dB by default) at address 0x37 in the RAM coefficients bank, is applied. The way the limiting acts after the warning condition disappears is controlled by bit TWRB.

Fault detect recovery bypass

Bit R/W

R/W 0

RST

Table 16. Fault detect recovery bypass

Name Description

FDRB

0: fault detect recovery enabled

1: fault detect recovery disabled

The on-chip power block provides feedback to the digital controller which is used to indicate a fault condition (either overcurrent or thermal). When fault is asserted, the power control block attempts a recovery from the fault by asserting the 3-state output, holding it for period of time in the range of 0.1 ms to 1 second, as defined by the fault-detect recovery constant register (FDRC registers 0x2B-0x2C), then toggling it back to normal condition. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. The fault condition is also asserted by a low-state pulse of the normally high INT_LINE output pin.

C2IM

C1IM

DSCKE

SAIFB

SAI3

SAI2

SAI1

SAI0

DocID13773 Rev 5 25/68

Register description STA333BW

Serial audio input interface format

Bit R/W

R/W

Table 17. Serial audio input interface

RST

SAI0

SAI1

SAI2

SAI3

Name Description

Determines the interface format of the input serial digital audio interface.

Serial data interface

The STA333BW audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA333BW always acts as slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI.

Bits SAI and bit SAIFB are used to specify the serial data format. The default serial data format is I²S, MSB first. Available formats are shown in the tables and figure that follow.

Serial data first bit

SAIFB

Table 18. Serial data first bit

Format

MSB-first

LSB-first

32 * fs

48 * fs

64 * fs

Table 19. Support serial audio input formats for MSB-first (SAIFB = 0)

BICKI SAI [3:0] SAIFB Interface format

0110

1010

1110

0000

0001

0010

0000

0001

0000

0001

0010

0110

1010

1110

I²S 15-bit data

Left / right-justified 16-bit data

I²S 16 to 23-bit data

Left-justified 16 to 24-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

I²S 16 to 24-bit data

Left-justified 16 to 24-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

26/68 DocID13773 Rev 5

STA333BW Register description

32 * fs

48 * fs

64 * fs

Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI SAI [3:0] SAIFB Interface Format

1100

0001

0101

1001

1101

0010

0110

1010

1110

0101

1001

1101

0010

0110

1010

1110

0000

0100

1000

1100

1110

0100

1000

1100

0001

I²S 15-bit data

Left/right-justified 16-bit data

I²S 23-bit data

I²S 20-bit data

I²S 18-bit data

LSB first I²S 16-bit data

Left-justified 24-bit data

Left-justified 20-bit data

Left-justified 18-bit data

Left-justified 16-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

I²S 24-bit data

I²S 20-bit data

I²S 18-bit data

LSB first I²S 16-bit data

Left-justified 24-bit data

Left-justified 20-bit data

Left-justified 18-bit data

Left-justified 16-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

To make the STA333BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that:



N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,

where N depends on the settings in Table 13 on page 24

 the PLL must be locked.

If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the

STA333BW immediately mutes the I²S PCM data out (provided to the processing block) and it freezes any active processing task.

DocID13773 Rev 5 27/68

Register description STA333BW

Clock desynchronization can happen during STA333BW operation because of source switching or TV channel change. To avoid audio side effects, like click or pop noise, it is strongly recommended to complete the following actions:

2. I²C read / write instructions while the serial audio interface and the internal PLL are still synchronous.

Delay serial clock enable

Bit R/W

R/W 0

RST

Table 21. Delay serial clock enable

Name Description

DSCKE

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate anomalies in some I²S master devices

Channel input mapping

Bit R/W

R/W

RST

Table 22. Channel input mapping

Name Description

C1IM

C2IM

0: processing channel 1 receives left I²S Input

1: processing channel 1 receives right I²S Input

0: processing channel 2 receives left I²S Input

1: processing channel 2 receives right I²S Input

Each channel received via I²S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers maps each I²S input channel to its corresponding processing channel.

28/68

OCRB

Reserved

FFX power output mode

CSZ3

CSZ2

CSZ1

CSZ0

OM1

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

Bit R/W

R/W

1 R/W

OM0

RST

OM0

Table 23. FFX power output mode

Name Description

1 OM1

Selects configuration of FFX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

DocID13773 Rev 5

STA333BW Register description

FFX compensating pulse size register

Bit R/W

R/W

RST

Table 24. FFX compensating pulse size bits

Name Description

CSZ0

CSZ1

CSZ2

CSZ3

When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to

15 clock periods.

0000

0001

…

1111

CSZ[3:0]

Table 25. Compensating pulse size

Compensating pulse size

0 ns (0 tick) compensating pulse size

20 ns (1 tick) clock period compensating pulse size

…

300 ns (15 tick) clock period compensating pulse size

Overcurrent warning adjustment bypass

Bit R/W

R/W 1

RST

Table 26. Overcurrent warning bypass

Name Description

OCRB

0: overcurrent warning adjustment enabled

1: overcurrent warning adjustment disabled

The OCRB is used to indicate how STA333BW behaves when an overcurrent warning condition occurs. If OCRB = 0 and the overcurrent condition happens, the power control block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning clipping adjustment is applied, it remains in this state until reset is applied or OCRB is set to 1. The level of adjustment can be changed via the TWOCL (thermal warning / overcurrent limit) setting at address 0x37 of the user defined coefficient RAM (

Section 7.7.7 on page 55

). The

OCRB can be enabled when the output bridge is already on.

SME

ZDE

High-pass filter bypass

DRC

Bit R/W

R/W

BQL

PSL

DSPB

DEMP

HPB

RST

HPB

Table 27. High-pass filter bypass

Name Description

1: bypass internal AC coupling digital high-pass filter

DocID13773 Rev 5 29/68

Register description STA333BW

The STA333BW features an internal digital high-pass filter for the purpose of AC coupling.

The purpose of this filter is to prevent DC signals from passing through a FFX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled.

De-emphasis

Bit R/W

R/W 0

RST

DEMP

Table 28. De-emphasis

Name Description

0: no de-emphasis

1: enable de-emphasis on all channels

DSP bypass

Bit R/W

R/W 0

RST

DSPB

Table 29. DSP bypass

Name Description

0: normal operation

1: bypass of biquad and bass / treble functions

Setting the DSPB bit bypasses the EQ function of the STA333BW.

Postscale link

Bit R/W

R/W 0

RST

PSL

Table 30. Postscale link

Name Description

0: each channel uses individual postscale value

1: each channel uses channel 1 postscale value

Postscale function can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the postscale values can be linked to the value of channel 1 for ease of use and update the values faster.

Biquad coefficient link

Bit R/W

R/W 0

RST

BQL

Table 31. Biquad coefficient link

Name Description

0: each channel uses coefficient values

1: each channel uses channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the Channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.

30/68 DocID13773 Rev 5

STA333BW Register description

Dynamic range compression / anticlipping bit

Bit R/W

R/W

Table 32. Dynamic range compression / anticlipping bit

RST Name Description

0 DRC

0: limiters act in anticlipping mode

1: limiters act in dynamic range compression mode

Both limiters can be used in one of two ways, anticlipping or dynamic range compression.

When used in anticlipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.

Zero-detect mute enable

Bit R/W

R/W 1

RST

Table 33. Zero-detect mute enable

Name Description

ZDE

0: automatic zero-detect mute disabled

1: automatic zero-detect mute enabled

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.

Submix mode enable

Bit R/W

R/W 0

RST

SME

Table 34. Submix mode enable

Name Description

0: submix into left / right disabled

1: submix into left / right enabled

SVE

ZCE

DCCV

Max power correction variable

PWMS

Bit R/W

R/W

AME

NSBW

MPC

RST

Table 35. Max power correction variable

Name Description

MPCV

0: use standard MPC coefficient

1: use MPCC bits for MPC coefficient

MPCV

DocID13773 Rev 5 31/68

Register description STA333BW

Max power correction

Bit R/W

R/W 1

RST

MPC

Table 36. Max power correction

Name Description

0: function disabled

1: enables power bridge correction for THD reduction near maximum power output.

Setting the MPC bit turns on special processing that corrects the STA333BW power device at high power. This mode should lower the THD+N of a full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered

(OM[1,0] = 01) and binary. When OCFG = 00, MPC has no effect on channels 3 and 4, the line-out channels.

Noise-shaper bandwidth selection

Bit R/W

R/W 0

RST

Table 37. Noise-shaper bandwidth selection

Name Description

NSBW

1: third-order NS

0: fourth-order NS

AM mode enable

Bit R/W

R/W 0

RST

AME

Table 38. AM mode enable

Name Description

0: normal FFX operation.

1: AM reduction mode FFX operation

STA333BW features a FFX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an AM tuner active. The SNR of the FFX processing is reduced to approximately

83 dB in this mode, which is still greater than the SNR of AM radio.

PWM speed mode

Bit R/W

R/W 0

RST

Table 39. PWM speed mode

Name Description

PWMS

0: normal speed (384 kHz) all channels

1: odd speed (341.3 kHz) all channels

32/68 DocID13773 Rev 5

STA333BW Register description

Distortion compensation variable enable

Bit R/W

R/W 0

Table 40. Distortion compensation variable enable

RST Name Description

DCCV

0: use preset DC coefficient

1: use DCC coefficient

Zero-crossing volume enable

Bit R/W

R/W 1

RST

Table 41. Zero-crossing volume enable

Name Description

ZCE

1: volume adjustments only occur at digital zerocrossings

0: volume adjustments occur immediately

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible.

Soft volume update enable

Bit R/W

R/W 1

RST

SVE

Table 42. Soft volume update enable

Name Description

1: volume adjustments ramp according to SVUP / SVDW settings

0: volume adjustments occur immediately

EAPD

PWDN

Output configuration

ECLE

Bit R/W

R/W

LDTE

BCLE

IDE

RST

Table 43. Output configuration

Name

OCFG0

OCFG1

Description

Selects the output configuration

OCFG1

OCFG0

DocID13773 Rev 5 33/68

Register description

OCFG[1:0]

STA333BW

Table 44. Output configuration engine selection

Output configuration

2 channel (full-bridge) power, 2 channel data-out:

1A/1B



1A/1B

2A/2B



2A/2B

LineOut1



3A/3B

LineOut2



4A/4B

Line Out Configuration determined by LOC register

2 (half-bridge), 1(full-bridge) on-board power:



1A Binary 0 °



1B Binary 90°

3A/3B



2A/2B Binary 45°

1A/B



3A/B Binary 0°

2A/B



4A/B Binary 90°

2 channel (full-bridge) power, 1 channel FFX:

1A/1B



1A/1B

2A/2B



2A/2B

3A/3B



3A/3B

EAPDEXT and TWARNEXT Active

1 channel mono-parallel:



1A/1B w/ C3BO 45°



2A/2B w/ C3BO 45°

1A/1B



3A/3B

2A/2B



4A/4B

Config pin

Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs.

Figure 11. OCFG = 00 (default value)

34/68 DocID13773 Rev 5

STA333BW

Figure 12. OCFG = 01

Register description

Figure 13. OCFG = 10

Figure 14. OCFG = 11

The STA333BW can be configured to support different output configurations. For each

PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries.

DocID13773 Rev 5 35/68

Register description

Figure 15. Output mapping scheme

STA333BW

For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage:

36/68 DocID13773 Rev 5

STA333BW Register description

2.0 channels, two full-bridges (OCFG = 00)

Mapping:



FFX1A -> OUT1A



FFX1B -> OUT1B



FFX2A -> OUT2A



FFX2B -> OUT2B



FFX3A -> OUT3A



FFX3B -> OUT3B



FFX4A -> OUT4A



FFX4B -> OUT4B

Default modulation:



FFX1A / 1B configured as ternary



FFX2A / 2B configured as ternary



FFX3A / 3B configured as lineout ternary



FFX4A / 4B configured as lineout ternary

On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, volume control or EQ have no effect on channels 3 and 4.

In this configuration the PWM slot phase is the following as shown in Figure 16 .

Figure 16. 2.0 channels (OCFG = 00) PWM slots

DocID13773 Rev 5 37/68

Register description STA333BW

2.1 channels, two half-bridges + one full-bridge (OCFG = 01)

Mapping:



FFX1A -> OUT1A



FFX2A -> OUT1B



FFX3A -> OUT2A



FFX3B -> OUT2B



FFX1A -> OUT3A



FFX1B -> OUT3B



FFX2A -> OUT4A



FFX2B -> OUT4B

Modulation:



FFX1A / 1B configured as binary



FFX2A / 2B configured as binary



FFX3A / 3B configured as binary



FFX4A / 4B configured as binary

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3 / OUT4 channels the channel 1 and channel 2 PWM are replicated.

In this configuration the PWM slot phase is the following as shown in Figure 17 .

Figure 17. 2.1 channels (OCFG = 01) PWM slots

38/68 DocID13773 Rev 5

STA333BW Register description

2.1 channels, two full-bridges + one external full-bridge (OCFG = 10)

Mapping:



FFX1A -> OUT1A



FFX1B -> OUT1B



FFX2A -> OUT2A



FFX2B -> OUT2B



FFX3A -> OUT3A



FFX3B -> OUT3B



EAPD -> OUT4A



TWARN -> OUT4B

Default modulation:



FFX1A / 1B configured as ternary



FFX2A / 2B configured as ternary



FFX3A / 3B configured as ternary



FFX4A / 4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.

In this configuration the PWM slot phase is the following as shown in Figure 18 .

Figure 18. 2.1 channels (OCFG = 10) PWM slots

DocID13773 Rev 5 39/68

Register description STA333BW

Invalid input detect mute enable

Bit R/W

R/W 1

RST

Table 45. Invalid input detect mute enable

Name Description

IDE

0: disables the automatic invalid input detect mute

1: enables the automatic invalid input detect mute

Setting the IDE bit enables this function, which looks at the input I²S data and automatically mutes if the signals are perceived as invalid.

Binary output mode clock loss detection

Bit R/W

R/W 1

Table 46. Binary output mode clock loss detection

RST Name Description

BCLE

0: binary output mode clock loss detection disabled

1: binary output mode clock loss detection enable

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

LRCK double trigger protection

Bit R/W

R/W 1

RST

Table 47. LRCK double trigger protection

Name Description

LDTE

0: LRCLK double trigger protection disabled

1: LRCLK double trigger protection enabled

LDTE, when enabled, prevents double trigger of LRCLK on instable I²S input.

Auto EAPD on clock loss

Bit R/W

R/W 0

RST

Table 48. Auto EAPD on clock loss

Name Description

ECLE

0: auto EAPD on clock loss not enabled

1: auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

IC power down

Bit R/W

R/W 1

RST

PWDN

Table 49. IC power down

Name Description

0: IC power down low-power condition

1: IC normal operation

40/68 DocID13773 Rev 5

STA333BW Register description

The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, then the master clock to all internal hardware expect the

I²C block is gated. This places the IC in a very low power consumption state.

External amplifier power down

Bit R/W

R/W 0

RST

Table 50. External amplifier power down

Name Description

EAPD

0: external power stage power down active

1: normal operation

The EAPD register directly disables / enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the FFX4B / EAPD output pin when OCFG = 10.

7.2 Volume control registers (addr 0x06 - 0x0A)

The volume structure of the STA333BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB.

As an example if C3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB.

The channel mutes provide a “soft mute” with the volume ramping down to mute in

4096 samples from the maximum volume setting at the internal processing rate

(approximately 96 kHz).

A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) in any channel volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -80 dB is muted.

All changes in volume take place at zero-crossings when ZCE = 1 ( Configuration register E

(addr 0x04) ) on a per channel basis as this creates the smoothest possible volume

transitions. When ZCE = 0, volume updates occur immediately.

DocID13773 Rev 5 41/68

Register description

7.2.1

STA333BW

Mute / line output configuration register (addr 0x06)

LOC1

LOC[1:0]

LOC0

Reserved

C3M

C2M

C1M

Table 51. Line output configuration

Line output configuration

Line output fixed - no volume, no EQ

Line output variable - channel 3 volume effects line output, no EQ

Line output variable with EQ - channel 3 volume effects line output

Reserved

Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.

7.2.3

7.2.4

MVOL7

MVOL6

MVOL5

MVOL4

MVOL3

MVOL2

MVOL1

Table 52. Master volume offset as a function of MVOL

Volume offset from channel value MVOL[7:0]

00000000 (0x00) 0 dB

00000001 (0x01) -0.5 dB

00000010 (0x02) -1 dB

… …

01001100 (0x4C) -38 dB

… …

11111110 (0xFE)

11111111 (0xFF)

-127.5 dB

Default mute, not to be used during operation

Channel 1 volume (addr 0x08)

C1VOL7

C1VOL6

C1VOL5

C1VOL4

Channel 2 volume (addr 0x09)

C2VOL7

C2VOL6

C2VOL5

C2VOL4

C1VOL3

C1VOL2

C2VOL3

C2VOL2

C1VOL1

C2VOL1

MVOL0

C1VOL0

C2VOL0

42/68 DocID13773 Rev 5

STA333BW

7.2.5

Register description

Channel 3 / line output volume (addr 0x0A)

C3VOL7

C3VOL6

C3VOL5

C3VOL4

C3VOL3

C3VOL2

Table 53. Channel volume as a function of CxVOL

CxVOL[7:0]

00000000 (0x00) +48 dB

00000001 (0x01) +47.5 dB

00000010 (0x02) +47 dB

… …

01011111 (0x5F)

01100000 (0x60)

01100001 (0x61)

…

11010111 (0xD7)

+0.5 dB

0 dB

-0.5 dB

…

-59.5 dB

11011000 (0xD8) -60 dB

11011001 (0xD9) -61 dB

11011010 (0xDA) -62 dB

… …

11101100 (0xEC) -80 dB

11101101 (0xED) Hard channel mute

…

11111111 (0xFF)

…

Hard channel mute

Volume

C3VOL1

C3VOL0

DocID13773 Rev 5 43/68

Register description

7.3 Audio preset registers (addr 0x0B and 0x0C)

STA333BW

Reserved

AMGC[1]

AMGC[0]

Reserved

Using AMGC[1:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. They are defined below in Table 54

Table 54. Audio preset gain compression / limiters selection for AMGC[3:2] = 00

AMGC[1:0] Mode

User programmable GC

AC no clipping 2.1

AC limited clipping (10%) 2.1

DRC night-time listening mode 2.1

XO3

XO2

XO1

XO0

AM interference frequency switching

Bit R/W

R/W

AMAM2

AMAM1

AMAM0

AMAME

Table 55. AM interference frequency switching bits

RST Name Description

AMAME

Audio preset AM enable

0: switching frequency determined by PWMS setting

1: switching frequency determined by AMAM settings

000

001

010

011

100

101

110

AMAM[2:0]

Table 56. Audio preset AM switching frequency selection

48 kHz / 96 kHz input fs 44.1 kHz / 88.2 kHz input fs

0.535 MHz - 0.720 MHz

0.721 MHz - 0.900 MHz

0.901 MHz - 1.100 MHz

1.101 MHz - 1.300 MHz

1.301 MHz - 1.480 MHz

1.481 MHz - 1.600 MHz

1.601 MHz - 1.700 MHz

0.535 MHz - 0.670 MHz

0.671 MHz - 0.800 MHz

0.801 MHz - 1.000 MHz

1.001 MHz - 1.180 MHz

1.181 MHz - 1.340 MHz

1.341 MHz - 1.500 MHz

1.501 MHz - 1.700 MHz

44/68 DocID13773 Rev 5

STA333BW Register description

Bass management crossover

Bit R/W

R/W

Table 57. Bass management crossover

RST

XO0

XO1

XO2

XO3

Name Description

Selects the bass-management crossover frequency.

A 1st-order hign-pass filter (channels 1 and 2) or a

2nd-order low-pass filter (channel 3) at the selected frequency is performed.

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

XO[3:0]

Table 58. Bass management crossover frequency

Crossover frequency

User-defined ( Section 7.7.8 on page 56 )

80 Hz

100 Hz

120 Hz

140 Hz

160 Hz

180 Hz

200 Hz

220 Hz

240 Hz

260 Hz

280 Hz

300 Hz

320 Hz

340 Hz

360 Hz

DocID13773 Rev 5 45/68

Register description STA333BW

C1OM1

C1OM0

C1LS1

C1LS0

C1BO

C1VPB

C1EQBP

C1TCB

C2OM1

C2OM0

C2LS1

C2LS0

C2BO

C2VPB

C2EQBP

C2TCB

C3OM1

C3OM0

C3LS1

C3LS0

C3BO

C3VPB

Reserved

Tone control bypass

Tone control (bass / treble) can be bypassed on a per channel basis for channels 1 and 2.

CxTCB

Table 59. Tone control bypass

Mode

Perform tone control on channel x - normal operation

Bypass tone control on channel x

EQ bypass

EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel.

CxEQBP

Table 60. EQ bypass

Mode

Perform EQ on channel x - normal operation

Bypass EQ on channel x

Volume bypass

Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting has no effect on that channel.

CxVBP

Table 61. Volume bypass register

Mode

Normal volume operations

Volume is by-passed

46/68 DocID13773 Rev 5

STA333BW Register description

Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse.

CxBO

Table 62. Binary output enable registers

Mode

FFX output operation

Binary output

Limiter select

Limiter selection can be made on a per-channel basis according to the channel limiter select bits.

Table 63. Channel limiter mapping as a function of CxLS bits

CxLS[1:0] Channel limiter mapping

Channel has limiting disabled

Channel is mapped to limiter #1

Channel is mapped to limiter #2

Output mapping

Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.

Table 64. Channel output mapping as a function of CxOM bits

CxOM[1:0] Channel x output source from

Channel1

Channel 2

Channel 3

DocID13773 Rev 5 47/68

Register description STA333BW

TTC3

Tone control

TTC2

TTC1

TTC0

BTC3

BTC2

BTC1

0000

0001

0010

…

0101

0110

0111

1000

1001

…

1100

1101

1110

1111

Table 65. Tone control boost / cut as a function of BTC and TTC bits

BTC[3:0],

TTC[3:0]

Boost / Cut

-12 dB

-10 dB

…

-4 dB

-2 dB

0 dB

+2 dB

+4 dB

…

+10 dB

+12 dB

BTC0

7.6

7.6.1

7.6.2

Dynamic control registers (addr 0x12 - 0x15)

Limiter 1 attack / release rate (addr 0x12)

L1A3

L1A2

L1A1

L1A0

L1R3

L1R2

Limiter 1 attack / release threshold (addr 0x13)

L1AT3

L1AT2

L1AT1

L1AT0

L1RT3

L1RT2

L1R1

L1RT1

L1R0

L1RT0

48/68 DocID13773 Rev 5

STA333BW Register description

7.6.3

7.6.4

Limiter 2 attack / release rate (addr 0x14)

L2A3

L2A2

L2A1

L2A0

L2R3

L2R2

Limiter 2 attack / release threshold (addr 0x15)

L2AT3

L2AT2

L2AT1

L2AT0

L2RT3

L2RT2

L2R1

L2R0

L2RT1

L2RT0

7.6.5 Description

The STA333BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in

Configuration register E (addr 0x04) on page 31

Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0 dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison.

Figure 19. Basic limiter and volume flow diagram

GAIN / VOLUME

The limiter attack thresholds are determined by the LxAT registers.

It is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a FFX amplifier. Since gain can be added digitally within the STA333BW it is possible to exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm.

The limiter release thresholds are determined by the LxRT registers.

The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume / limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already

DocID13773 Rev 5 49/68

Register description STA333BW

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

LxA[3:0] reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.

In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.

Table 66. Limiter attack rate vs LxA bits

Attack Rate dB/ms

0.1123

0.0902

0.0752

0.0645

0.0564

0.0501

0.0451

3.1584

2.7072

2.2560

1.8048

1.3536

0.9024

0.4512

0.2256

0.1504

Fast

Slow

50/68 DocID13773 Rev 5

STA333BW Register description

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

LxR[3:0]

Table 67. Limiter release rate vs LxR bits

Release Rate dB/ms

0.0208

0.0198

0.0172

0.0147

0.0137

0.0134

0.0117

0.0110

0.0104

0.5116

0.1370

0.0744

0.0499

0.0360

0.0299

0.0264

Anticlipping mode

0111

1000

1001

1010

1011

1100

1101

0000

0001

0010

0011

0100

0101

0110

LxAT[3:0]

Table 68. Limiter attack threshold vs LxAT bits (AC mode)

AC (dB relative to fs)

-4

-2

-12

-10

-8

-6

Fast

Slow

DocID13773 Rev 5 51/68

Register description STA333BW

1110

1111

Table 68. Limiter attack threshold vs LxAT bits (AC mode) (continued)

LxAT[3:0] AC (dB relative to fs)

+10

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

LxRT[3:0]

Table 69. Limiter release threshold vs LxRT bits (AC mode)

AC (dB relative to fs)



-29

-20

-2

-1

-0

-8

-7

-6

-5

-4

-3

-16

-14

-12

-10

Dynamic range compression mode

0000

0001

0010

0011

0100

0101

0110

0111

1000

Table 70. Limiter attack threshold vs LxAT bits (DRC mode)

LxAT[3:0] DRC (dB relative to Volume)

-31

-29

-27

-25

-23

-21

-19

-17

-16

52/68 DocID13773 Rev 5

STA333BW Register description

1001

1010

1011

1100

1101

1110

1111

Table 70. Limiter attack threshold vs LxAT bits (DRC mode) (continued)

LxAT[3:0] DRC (dB relative to Volume)

-15

-14

-13

-12

-10

-7

-4

0000

0001

Table 71. Limiter release threshold vs LxRT bits (DRC mode)

LxRT[3:0] DRC (db relative to Volume + LxAT)



-38

1000

1001

1010

1011

1100

1101

1110

1111

0010

0011

0100

0101

0110

0111

-24

-22

-20

-18

-15

-12

-9

-6

-36

-33

-31

-30

-28

-26

DocID13773 Rev 5 53/68

Register description

7.7

7.7.1

STA333BW

User-defined coefficient control registers (addr 0x16 - 0x26)

Coefficient address register (addr 0x16)

Reserved

CFA5

CFA4

CFA3

CFA2

CFA1

CFA0

7.7.3

7.7.4

54/68

C1B15

C1B23

C1B7

C1B22

C1B14

C1B6

C1B21

C1B13

C1B5

C1B20

C1B12

C1B4

C1B19

C1B11

C1B3

Coefficient b2 data register bits (addr 0x1A - 0x1C)

C2B23

C2B15

C2B7

C2B22

C2B14

C2B6

C2B21

C2B13

C2B5

C2B20

C2B12

C2B4

C2B19

C2B11

C2B3

C2B18

C2B10

C2B2

C1B18

C1B10

C1B2

Coefficient a1 data register bits (addr 0x1D - 0x1F)

C3B15

C3B23

C3B7

C3B22

C3B14

C3B6

C3B21

C3B13

C3B5

C3B20

C3B12

C3B4

C3B19

C3B11

C3B3

C3B18

C3B10

C3B2

DocID13773 Rev 5

C1B17

C1B9

C1B1

C1B16

C1B8

C1B0

C2B17

C2B9

C2B1

C2B16

C2B8

C2B0

C3B17

C3B9

C3B1

C3B16

C3B8

C3B0

STA333BW

7.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22)

C4B23

C4B15

C4B7

C4B22

C4B14

C4B6

C4B21

C4B13

C4B5

C4B20

C4B12

C4B4

C4B19

C4B11

C4B3

C4B18

C4B10

C4B2

Register description

C4B17

C4B9

C4B1

C4B16

C4B8

C4B0

7.7.7

C5B15

C5B23

C5B7

C5B22

C5B14

C5B6

C5B21

C5B13

C5B5

C5B20

C5B12

C5B4

C5B19

C5B11

C5B3

Coefficient read / write control register (addr 0x26)

D7 D6

Reserved

D5 D4 D3

C5B18

C5B10

C5B2

C5B17

C5B9

C5B1

C5B16

C5B8

C5B0

DocID13773 Rev 5 55/68

Register description STA333BW

7.7.8 Description

Note:

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA333BW via RAM. Access to this RAM is available to the user via an I²C register interface. A collection of I²C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read / write of the coefficient(s) to/from RAM.

The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref.

Table 8

, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D).

Reading a coefficient from RAM

Write 6-bits of address to I²C register 0x16.

2. Write 1 to R1 bit in I²C address 0x26.

3. Read top 8-bits of coefficient in I²C address 0x17.

4. Read middle 8-bits of coefficient in I²C address 0x18.

5. Read bottom 8-bits of coefficient in I²C address 0x19.

Reading a set of coefficients from RAM

Write 6-bits of address to I²C register 0x16.

2. Write 1 to RA bit in I²C address 0x26.

3. Read top 8-bits of coefficient in I²C address 0x17.

4. Read middle 8-bits of coefficient in I²C address 0x18.

5. Read bottom 8-bits of coefficient in I²C address 0x19.

6. Read top 8-bits of coefficient b2 in I²C address 0x1A.

7. Read middle 8-bits of coefficient b2 in I²C address 0x1B.

8. Read bottom 8-bits of coefficient b2 in I²C address 0x1C.

9. Read top 8-bits of coefficient a1 in I²C address 0x1D.

10. Read middle 8-bits of coefficient a1 in I²C address 0x1E.

11. Read bottom 8-bits of coefficient a1 in I²C address 0x1F.

12. Read top 8-bits of coefficient a2 in I²C address 0x20.

13. Read middle 8-bits of coefficient a2 in I²C address 0x21.

14. Read bottom 8-bits of coefficient a2 in I²C address 0x22.

15. Read top 8-bits of coefficient b0 in I²C address 0x23.

16. Read middle 8-bits of coefficient b0 in I²C address 0x24.

17. Read bottom 8-bits of coefficient b0 in I²C address 0x25.

Writing a single coefficient to RAM

Write 6-bits of address to I²C register 0x16.

2. Write top 8-bits of coefficient in I²C address 0x17.

3. Write middle 8-bits of coefficient in I²C address 0x18.

4. Write bottom 8-bits of coefficient in I²C address 0x19.

5. Write 1 to W1 bit in I²C address 0x26.

56/68 DocID13773 Rev 5

STA333BW Register description

Writing a set of coefficients to RAM

Write 6-bits of starting address to I²C register 0x16.

2. Write top 8-bits of coefficient b1 in I²C address 0x17.

3. Write middle 8-bits of coefficient b1 in I²C address 0x18.

4. Write bottom 8-bits of coefficient b1 in I²C address 0x19.

5. Write top 8-bits of coefficient b2 in I²C address 0x1A.

6. Write middle 8-bits of coefficient b2 in I²C address 0x1B.

7. Write bottom 8-bits of coefficient b2 in I²C address 0x1C.

8. Write top 8-bits of coefficient a1 in I²C address 0x1D.

9. Write middle 8-bits of coefficient a1 in I²C address 0x1E.

10. Write bottom 8-bits of coefficient a1 in I²C address 0x1F.

11. Write top 8-bits of coefficient a2 in I²C address 0x20.

12. Write middle 8-bits of coefficient a2 in I²C address 0x21.

13. Write bottom 8-bits of coefficient a2 in I²C address 0x22.

14. Write top 8-bits of coefficient b0 in I²C address 0x23.

15. Write middle 8-bits of coefficient b0 in I²C address 0x24.

16. Write bottom 8-bits of coefficient b0 in I²C address 0x25.

17. Write 1 to WA bit in I²C address 0x26.

The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the

STA333BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.

Table 72. RAM block for biquads, mixing, scaling, bass management

Index

(Decimal)

Index (Hex) Description Coefficient Default

…

0x00

0x01

0x02

0x03

0x04

0x05

…

0x13

0x14

0x15

…

0x27

Channel 1 - Biquad 1

Channel 1 - Biquad 2

…

Channel 1 - Biquad 4

Channel 2 - Biquad 1

…

Channel 2 - Biquad 4

C1H10(b1/2)

C1H11(b2)

C1H12(a1/2)

C1H13(a2)

C1H14(b0/2)

C1H20

…

C1H44

C2H10

C2H11

…

C2H44

0x000000

0x400000

0x000000

…

0x400000

0x000000

…

0x400000

DocID13773 Rev 5 57/68

Register description STA333BW

Table 72. RAM block for biquads, mixing, scaling, bass management (continued)

Index

(Decimal)

Index (Hex) Description Coefficient Default

0x30

0x31

0x32

0x33

0x34

0x35

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

Channel 1 / 2 - Biquad 5 or 8 for XO = 000

High-pass 2 nd

order filter for XO



000

Channel 3 - Biquad for XO = 000

Low-pass 2 nd

order filter for XO



000

Channel 1 - Prescale

Channel 2 - Prescale

Channel 1 - Postscale

Channel 2 - Postscale

Channel 3 - Postscale

TWARN / OC - Limit

Channel 1 - Mix 1

Channel 1 - Mix 2

Channel 2 - Mix 1

Channel 2 - Mix 2

Channel 3 - Mix 1

Channel 3 - Mix 2

Unused

Unused -

C3PstS

TWOCL

C1MX1

C1MX2

C2MX1

C2MX2

C3MX1

C3MX2

C12H0(b1/2)

C12H1(b2)

C12H2(a1/2)

C12H3(a2)

C12H4(b0/2)

C3H0(b1/2)

C3H1(b2)

C3H2(a1/2)

C3H3(a2)

C3H4(b0/2)

C1PreS

C2PreS

C1PstS

C2PstS

0x000000

0x400000

0x000000

0x400000

0x7FFFFF

0x5A9DF7

0x7FFFFF

0x000000

0x7FFFFF

0x400000

User-defined EQ

The STA333BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:

Y[n] = 2 * (b

/ 2) * X[n] + 2 * (b

/ 2) * X[n-1] + b

* X[n-2] - 2 * (a

/ 2) * Y[n-1] - a

* Y[n-2]

= b

* X[n] + b

* X[n-1] + b

* X[n-2] - a

* Y[n-1] - a

* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF

(0.9999998808).

58/68 DocID13773 Rev 5

STA333BW Register description

Coefficients stored in the user defined coefficient RAM are referenced in the following manner:

CxHy0 = b

/ 2

CxHy1 = b

CxHy2 = -a

/ 2

CxHy3 = -a

CxHy4 = b

/ 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b

2 coefficient in the fourth biquad for channel 2.

Crossover and biquad #8

Additionally, the STA333BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and

C3Hy0-4 areas of RAM noted in

Table 72 , addresses 0x28 to 0x31.

By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b

/ 2 coefficient which is set to 0x400000 (representing 0.5)

Prescale

The STA333BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM. All channels can use the channel-1 prescale factor by setting the Biquad link bit. By default, all prescale factors (RAM addresses 0x32 to 0x33) are set to 0x7FFFFF.

Postscale

The STA333BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This postscaling is accomplished by using a

24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM. This postscale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel-1 postscale factor by setting the postscale link bit. By default, all postscale factors (RAM addresses 0x34 to 0x36) are set to 0x7FFFFF.

When line output is being used, channel-3 postscale affects both channels 3 and 4.

Thermal warning and overcurrent adjustment (TWOCL)

The STA333BW provides a simple mechanism for reacting to overcurrent or thermal warning detection in the power block. When the warning occurs, the TWOCL value is used to provide output attenuation clipping on all channels.

The amount of attenuation to be applied in this situation can be adjusted by modifying the overcurrent and thermal warning limiting value (RAM addr 0x37). By default, the overcurrent postscale adjustment factor is set to 0x5A9DF7 (that is, -3 dB). Once the limiting is applied, it remains until the device is reset or according to the TWRB and OCRB settings.

DocID13773 Rev 5 59/68

Register description

7.8

STA333BW

Variable max power correction registers (addr 0x27 - 0x28)

MPCC15

MPCC14

MPCC13

MPCC12

MPCC11

MPCC10

MPCC9

MPCC8

MPCC7

MPCC6

MPCC5

MPCC4

MPCC3

MPCC2

MPCC1

MPCC0

MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.

DCC15

DCC14

DCC13

DCC12

DCC11

DCC10

DCC9

DCC8

DCC7

DCC6

DCC5

DCC4

DCC3

DCC2

DCC1

DCC0

DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.

7.10 Fault detect recovery constant registers (addr 0x2B - 0x2C)

Note:

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C gives approximately 0.1 ms.

0x0000 is a reserved value for these registers.

60/68 DocID13773 Rev 5

STA333BW Register description

PLLUL

FAULT

UVFAULT

Reserved

OCFAULT

OCWARN

TFAULT

TWARN

This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.

Bit

R/W

RST

PLLUL

FAULT

Table 73. Status register bits

Name Description

UVFAULT

Reserved

OCFAULT

OCWARN

TFAULT

TWARN

0: PLL locked

1: PLL not locked

0: fault detected on power bridge

1: normal operation

0: VCCxX internally detected

< undervoltage threshold

0: overcurrent fault detected

0: overcurrent warning

0: thermal fault, junction temperature over limit

0: thermal warning, junction temperature is close to the fault condition

DocID13773 Rev 5 61/68

Applications

8 Applications

STA333BW

Figure 21

below shows the typical applications schematic for STA333BW. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies.

8.3

It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path. Concerning the component values, it must be taken into account that the greater the filter bandwidth, the less is the lock time but the higher is the PLL output jitter.

Typical output configuration

Figure 20

shows the typical output configuration used for BTL stereo mode. Please contact

STMicroelectronics for other recommended output configurations.

Figure 20. Output configuration for stereo BTL mode (R

= 8



22 µH

OUT1A

100 nF

22R

330 pF

100 nF

6R2

100 nF

470 nF

Left

22 µH

OUT1B

22 µH

OUT2A

100 nF

22R

330 pF

100 nF

6R2

100 nF

470 nF

Right

22 µH

OUT2B

62/68 DocID13773 Rev 5

C1 4

100µF 25V

C21 1µF 25V

C2 3

C2 9

00 nF

C1 8

100nF

OU T2 B

OU T2 A

Vc c

OU T1 B

C3 1 1 µF 25V

OU T1 A

C3 2

100nF

Figure 21. Applications circuit

STA333BW

GN D_ SU B

T EST _M OD E

VSS

VCC_REG

OU T2 B

GN D2

VCC2

OU T2 A

OU T1 B

Vc c1

GN D1

OU T1 A

GN D_ RE G

VDD

CO NFIG

OUT3B / FFX3B

OUT3A / FFX3A

VDD_DIG

GN D_ DI G

SC L

SD A

IN T_ LI NE

R ESET

SDI

LR CK I

BI CK I

XT I

GND_PLL

FILTER_PLL

VDD_PLL

PW RD N

GN D_ DI G

VDD_DIG

TWARN / OUT4A

EAPD / OUT4B

3V 3

C1 3

100nF

SC L

SD A

IN TL

R1 1

10 K

R ESET

DA TA

LR CK I

BI CK I

XT I

C2 2

1nF

C3 0

100nF R3 5

C3 3

PW DN

100nF

3V 3

2 R2

3V 3

R1 4

2K 2

R3 6 0

C3 6

4. 7n F

C3 5

680p F

Package thermal characteristics

9 Package thermal characteristics

STA333BW

Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas of 3 x 3 cm

and with 16 via holes is 24 °C/W in natural air convection.

The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.

Thus, the maximum estimated dissipated power for the STA333BW is:

2 x 20 W @ 8



, 18 V Pd max is approximately 4 W

2 x 9 W + 1 x 20 W @ 4



, 8





18 V Pd max is approximately 5 W

Figure 22

shows the power derating curve for the PowerSSO-36 package on PCBs with copper areas of 2 x 2 cm

and 3 x 3 cm

Figure 22. PowerSSO-36 power derating curve

STA333BW

PowerSSO-

20 40 60 80 100 120 140 160

64/68 DocID13773 Rev 5

STA333BW

10 Package mechanical data

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com.

ECOPACK

is an ST trademark.

Figure 23

below shows the package outline and

Table 74 gives the dimensions.

Table 74. PowerSSO-36 EPD dimensions

Dimensions in mm Dimensions in inches

Symbol

Min

H h k

M c

E e e3

A2 a1 b

1.20

0.80

X 4.10

6.50 -

2.90

3.65

1.00

10.10

0.60

2.15

0.00

0.18

0.23

10.10

7.40

4.30

0.5

8.5

2.3

Typ Max Min

2.47

2.40

0.10

0.36

0.32

10.50

7.60

0.10

10.50

0.40

8 degrees

1.00

10 degrees -

4.70

7.10

0.161

0.256

0.398

0.024

0.085

0.00

0.007

0.009

0.398

0.291

Typ

0.169

0.020

0.335

0.091

0.047

0.031

0.114

0.144

0.039

Max

0.097

0.094

0.004

0.014

0.013

0.413

0.299

0.004

0.413

0.016

8 degrees

0.039

10 degrees

0.185

0.280

DocID13773 Rev 5 65/68

Figure 23. PowerSSO-36 EPD outline drawing h x 45°

STA333BW Revision history

Date

11-Apr-2006

26-Jul-2007

26-Jan-2011

18-Sep-2013

13-Feb-2014

Revision

Table 75. Document revision history

Changes

Initial release.

Added:

Electrical specifications, digital section

Power on sequence

Processing data path

Application

Improved:

Pin description

Absolute maximum ratings

Recommended operative conditions

Output configuration

Device status register

Updated presentation

Document status updated to Datasheet

Modified layout of chapter Chapter 1: Description

Removed master mute from

Section 7.2 on page 41

Improved presentation of applications circuit in

Figure 21 on page 63

Added

Section 4 on page 16

Modified

Note:: The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref. Table 8, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D). on page 56

Updated Company information appearing on last page of document

Updated order code

Table 1 on page 1

DocID13773 Rev 5 67/68

STA333BW

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