STMicroelectronics STA335BWQS Datasheet
Διαφήμιση
Διαφήμιση
STA335BWQS
2.1-channel high-efficiency digital audio system with QSound QHD
®
Features
Wide supply voltage range (4.5 V to 24 V)
3 power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 20 W into 8 Ω at 18 V), (2 x 37 W into
8 Ω at 24 V)
– 3 channels - left, right using binary and LFE using ternary PWM (2.1 mode) (2 x 9 W +
1 x 20 W into 2 x 4 Ω , 1 x 8 Ω at 18 V)
– 2 channels of ternary PWM (2 x 20 W) + stereo line-out ternary
2.1 channels of 24-bit DDX
®
100-dB SNR and dynamic range
Selectable 32 kHz to 192 kHz input sample rates
I
2
C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB in
0.5-dB steps
Soft volume update
Individual channel and master gain/attenuation
Dual independent limiters/compressors
Dynamic range compression or anti-clipping modes
AutoModes™ settings for:
– 15 preset crossover filters
– 2 preset anti-clipping modes
– Preset night-time listening mode
mute
Independent channel volume and DSP bypass
Automatic zero-detect mute
Table 1.
Device summary
Order code
STA335BWQS
STA335BWQS13TR
PowerSSO-36 slug down
Automatic invalid input detect mute
2-channel I
2
S input data interface
Input and output channel mapping
4 x 28-bit user programmable biquads (EQ) per channel
Bass/treble tone control
DC blocking selectable high-pass filter
Selectable de-emphasis
Sub-channel mix into left and right channels
Advanced AM interference frequency switching and noise-suppression modes
Selectable high or low-bandwidth noise-shaping topologies
Variable max power correction for lower full-power THD
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Thermal overload and short-circuit protection
Video application supports 576 x f s
input mode
QSound QHD
®
– Field proven stereo soundfield enhancement technology
– Provides improved audio image width, separation and depth for stereo signals
– Synthesizes a 3-D stereo soundfield
PowerSSO-36 slug down package.
Package
PowerSSO-36 slug down
PowerSSO-36 slug down
Packaging
Tube
Tape and reel
August 2010 Rev 3 1/72 www.st.com
1
Contents
Contents
STA335BWQS
®
QHD
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pinout and thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/72
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STA335BWQS Contents
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
®
power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
®
compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . 33
Over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 34
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Obsolete Product(s) - Obsolete Product(s)
Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 35
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Contents STA335BWQS
MiamiMode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 37
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 43
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Volume control registers (addr 0x06 to 0x0A) . . . . . . . . . . . . . . . . . . . . . 44
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Auto mode registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . . . 46
AutoModes™ register 1 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AutoModes™ register 2 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Obsolete Product(s) - Obsolete Product(s)
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4/72
STA335BWQS Contents
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Dynamics control registers (addr 0x12 to 0x15) . . . . . . . . . . . . . . . . . . . . 50
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
User-defined coefficient control registers (addr 0x16 to 0x26) . . . . . . . . . 55
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Variable distortion compensation registers (addr 0x29 to 0x2A) . . . . . . . 62
Fault detect recovery constant registers (addr 0x2B to 0x2C) . . . . . . . . . 62
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Application and power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5/72
Contents STA335BWQS
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 70
Obsolete Product(s) - Obsolete Product(s)
6/72
List of tables STA335BWQS
List of tables
Obsolete Product(s) - Obsolete Product(s)
7/72
List of tables STA335BWQS
Obsolete Product(s) - Obsolete Product(s)
8/72
STA335BWQS
List of figures
List of figures
S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Obsolete Product(s) - Obsolete Product(s)
9/72
STA335BWQS Description
1 Description
The STA335BWQS is an integration of digital audio processing, digital amplifier control,
DDX
®
power-output stage and QSound QHD
®
technology to create a high-power single-chip DDX solution comprising high-quality, high-efficiency and all digital amplification.
The STA335BWQS is part of the Sound Terminal™ family that provides full digital audio streaming to the speaker offering cost effectiveness, low energy dissipation and sound enrichment.
The STA335BWQS power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 9 W + 1 x 20 W of power output.
Two channels can be provided by two full-bridges, providing up to 2 x 37 W of power. The IC can also be configured as 2.1 channels with 2 x 30 W provided by the device and external power for DDX
®
power drive.
Also provided in the STA335BWQS are a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. AutoModes™ enables a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes auto volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio-interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I
2
S format. Three channels of DDX
®
processing are provided. This high-quality conversion from PCM audio to the DDX-patented 3-state PWM switching waveform provides over 100 dB SNR and dynamic range.
1.1 QSound
®
QHD
®
Normally, reduced audio clarity is experienced due to the digital compression of music (and video-sound) combined with various audio processing techniques used in broadcast transmission. This is most apparent in products such as digital televisions and audio players. These devices are faced with a multitude of audio challenges, primarily associated with the small speakers, that are limited in location and cabinet housing, plus economized speaker drivers and components. As such, digital televisions and audio players are ideal candidates to benefit from stereo soundfield enhancement in order to deliver a full surround-like experience.
QSound QHD
®
and its industry recognized QXpander
®
technology is a field-proven stereo soundfield enhancement technology that provides a broader stereo image width with greater separation and depth for stereo signals and synthesizes a 3-D stereo soundfield. QHD
®
Obsolete Product(s) - Obsolete Product(s) hundreds of QSound and third party hardware and software products, with total shipments in the millions.
10/72
STA335BWQS
Figure 1.
Block diagram
I
2
C
I
2
S interface
Volume control
DDX
Power control
PLL
Digital signal processing
Protection current/thermal
Channel
1A
Logic
Channel
1B
Channel
2A
Regulators
Bias
Power
Channel
2B
Description
Obsolete Product(s) - Obsolete Product(s)
11/72
Pinout and thermal information
2 Pinout and thermal information
STA335BWQS
Figure 2.
Pin connection PowerSSO-36 (top view)
GND_SUB
SA
TEST MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD
CONFIG
OUT3B/DDX3B
OUT3A/DDX3A
11
12
13
14
15
16
17
18
6
7
8
9
10
1
2
3
4
5
23
22
21
20
19
28
27
26
25
24
33
32
31
30
29
36
35
34
D05AU1638
VDD_DIG
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
PLL_GND
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
VDD_DIG
TWARN/OUT4A
EAPD/OUT4B
12/72
Table 2.
Pin
1
2
9
10
7
8
4
5
6
Pin description
Type
GND
I
I
I/O
I/O
O
GND
Power
O
O
Name
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
Description
Substrate ground
I
2
C select address
This pin must be connected to ground
Internal reference at Vcc - 3.3 V
Internal Vcc reference
Output half bridge 2B
Power negative supply
Power positive supply
Output half bridge 2A
Output half bridge 1B
STA335BWQS Pinout and thermal information
Table 2.
Pin
18
19
20
21
22
23
24
25
14
15
16
17
11
12
13
26
27
28
29
30
31
32
33
34
35
36
Pin description (continued)
Type Name
O
O
I
Power
GND
I
Power
I
Power
GND
I/O
GND
Power
I
O
GND
I
I
I
I
I
VCC1
GND1
OUT1A
GND_REG
VDD
CONFIG
OUT3B/DDX3B
OUT3A/DDX3A
EAPD/OUT4B
TWARN/OUT4A
VDD_DIG
GND_DIG
PWRDN
VDD_PLL
FILTER_PLL
GND_PLL
XTI
BICKI
LRCKI
SDI
RESET
O
I/O
I
GND
Power
INT_LINE
SDA
SCL
GND_DIG
VDD_DIG
Description
Power positive supply
Power negative supply
Output half bridge 1A
Internal ground reference
Internal 3.3-V reference voltage
Paralleled mode command
PWM out CH3B - external bridge
PWM out CH3A - external bridge
Power down for external bridge
Thermal warning from external bridge
Digital supply voltage
Digital ground
Power down
Positive supply for PLL
Connection to PLL filter
Negative supply for PLL
PLL input clock
I
2
S serial clock
I
2
S left/right clock
I
2
C serial data channels 1 and 2
Reset
Fault interrupt (0 = fault detected in the power bridge, 1 = normal operation)
I
2
C serial data
I
2
C serial clock
Digital ground
Digital supply voltage
Obsolete Product(s) - Obsolete Product(s)
13/72
Pinout and thermal information STA335BWQS
Table 3.
Thermal data
Parameter Min
R th j-case
Thermal resistance junction-case (thermal pad)
T th-sdj
T th-w
T th-sdh
R th j-amb
Thermal shut-down junction temperature
Thermal warning temperature
Thermal shut-down hysteresis
Thermal resistance junction-ambient
(1)
140
18
1.
See
Section 9: Package thermal characteristics on page 66 for details.
Typ Max
150
130
20
1.5
160
22
Unit
°C/W
°C
°C
°C
Obsolete Product(s) - Obsolete Product(s)
14/72
STA335BWQS Electrical specifications
3.1
Note:
3.2
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol Parameter Min
V cc
Power supply voltage (VCC1, VCC2)
VDD_DIG Digital supply voltage
VDD_PLL PLL supply voltage
T op
Operating junction temperature
T stg temperature
-0.3
-0.3
-0.3
0
-40
Typ Max
30
4
4
150
Unit
V
V
V
°C
Stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supply with nominal value rated inside recommended operating conditions, may experience some rising beyond the maximum operating condition for short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded.
Recommended operating condition
Table 5.
Recommended operating condition
V cc
Power supply voltage (VCC1, VCC2)
VDD_DIG Digital supply voltage
VDD_PLL PLL supply voltage
T amb
4.5
2.7
2.7
0
3.3
3.3
24.0
3.6
3.6
V
V
V
Obsolete Product(s) - Obsolete Product(s)
15/72
Electrical specifications STA335BWQS
V il
V ih
V ol
V oh
I pu
R pu
Table 6.
Electrical specifications - digital section
Symbol Parameter Conditions
I il
I ih
Min Typ
Low level input current without pull device Vi = 0 V -10
High level input current without pull device
Vi = VDD_DIG =
3.6 V
-10
Low level input voltage
High level input voltage
Low level output voltage
High level output voltage
Pull current
Equivalent pull resistance
Iol = 2 mA
Ioh = 2 mA
0.8*
0.8*
-25
VDD_DIG
VDD_DIG
66
50
10
10
Max Unit
µA
µA
0.2* VDD_DIG V
V
0.4* VDD_DIG V
V
125 µA k Ω
The specifications given in this section are with the operating conditions VCC = 18 V, f = 1 kHz, f sw
= 384 kHz, T amb
= 25° C, R
L
= 8
Ω
unless otherwise specified
Table 7.
Symbol
Po
R dsON gN
I dss g
P g
N
Electrical specifications - power section
Parameter Conditions Typ
Output power BTL
Output power BTL
Output power SE
Output power SE
THD = 1%
THD = 10%
VCC = 24 V
VCC = 24 V
R1 = 4
Ω
THD = 1%
THD = 10%
THD = 1%
THD = 10%
THD = 1%
THD = 10%
16
20
29
37
6.6
8.5
7
9
W
W
W
W
Power Pchannel/Nchannel
MOSFET (total bridge)
Power Pchannel RdsON matching
Power Nchannel RdsON matching
Power Pchannel/Nchannel leakage ldss
Power Pchannel RdsON
Matching
Power Nchannel RdsON
Matching l d
= 1.5 A l d
= 1.5 A
V
CC
= 24 V l d
= 1.5 A l d
= 1.5 A
95
95
95
95
200 280
10 m Ω
%
%
µA
%
%
16/72
STA335BWQS Electrical specifications
Table 7.
Symbol
Electrical specifications - power section (continued)
Parameter Conditions Typ
I
Idss
I
LDT
HDT
V t t f r cc
Power Pchannel/Nchannel leakage
VCC = 24 V
Low current dead time (static) Resistive load
(1)
High current dead time
(dynamic)
I load
= 1.5 A
(1)
Rise time
Fall time
Resistive load
(1)
Resistive load
(1)
Supply voltage operating voltage
Supply current from Vcc in power down
PWRDN = 0
I cc
Supply current from Vcc in operation
PCM Input signal = -60 dBFS
Switching frequency = 384 kHz
No LC filters
Supply current DDX processing
(reference only)
Internal clock = 49.152 MHz
Over-current limit
(2)
Short circuit protection Hi-Z output
Ilim
Isc
UVL t min
DR
SNR
PSSR
Under voltage protection
Output minimum pulse width No load
Dynamic range
Signal to noise ratio, ternary mode
Signal to noise ratio binary mode
A-Weighted
Power supply rejection ratio
DDX stereo mode, <5 kHz
V
RIPPLE
= 1 V RMS
Audio input = dither only
THD+N
Total harmonic distortion + noise
DDX stereo mode, Po = 1 W f = 1 kHz
DDX stereo mode, <5 kHz
X
TALK
4.5 24
3.0
3.8
20
0.1
80
10
1
µ A
8 15 ns
15 30 ns
10 18 ns
10 18 ns
V mA
30 mA
3.8 A
4.8 A
3.5
30
100
4.3
60
V ns dB
100
90
80
0.2
80 mA dB dB dB
% dB
η
Peak efficiency, DDX mode
Peak efficiency,binary modes
Po = 2 x 20 W into 8 Ω
Po = 2 x 9 W into 4
Ω
,
1 x 20 W into 8 Ω
90
87
%
1.
Refer to Figure 5: Test circuit 1 .
2.
Limit current if the register (OCRB par 6.1.3.3) over-current warning detect adjustment bypass is enabled. When disabled refer to the Isc.
17/72
Electrical specifications
Figure 3.
Power-on sequence
STA335BWQS
Don’t care
I I I I I I
Don’t care CMD0 CMD1 CMD2 z z
TR = minimum time between XTI master clock stable and Reset removal: 1 ms,
TC = minimum time between RESET removal and I
2
C program, sequence start: 1 ms.
Clock stable means: fmax - fmin < 1 MHz
No specific VCC and VDD_DIG turn-on sequence is required.
Figure 4.
Power-off sequence
18/72
XTI
Soft Mute
Register addr 0x07 z z
No specific VCC and VDD_DIG turn-on sequence is required.
This sequence ensure a pop-free turn-off procedure
STA335BWQS Electrical specifications
3.6 Testing
Figure 5.
Test circuit 1
Low current dead time = MAX(DTr, DTf)
Duty cycle = 50%
INxY
M58
M57 gnd
+Vcc
OUTxY
OUTxY t
DTr
R 8
Ω
DTf
V67 vdc = Vcc/2
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
Figure 6.
Test circuit 2
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=A
DTin(A)
INA
M58
M57
DTout(A)
Q1
Q3
OUTA
Iout=1.5A
L67 10
µ
C69
470nF
Rload=4
Ω
C71 470nF
DTout(B)
L68 10
µ
Iout=1.5A
OUTB
Q2
C70
470nF
Q4
M64
M63
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
Duty cycle=B
DTin(B)
INB
D06AU1651
Obsolete Product(s) - Obsolete Product(s)
19/72
Processing data paths
4 Processing data paths
STA335BWQS
Here are some diagrams that represent the data processing paths inside STA335BWQS. A
2-times oversampling FIR filter allows a 2x fs audio processing. Then a selectable high-pass filter removes the DC level. Four biquad filters allow a full equalization system. A final
I crossover filter is present. This filter can eventually be used as a fifth biquad stage, see the
2
C registers settings for this specific usage. A prescaler and a final post scaler allow a full control over the signal dynamic respectively before and after the filtering stages. A mixer function is also available.
Figure 7.
STA335BWQS processing data flow
Obsolete Product(s) - Obsolete Product(s)
20/72
STA335BWQS Functional description
Table 8.
Pin name
Functional pin status
Pin # Logic value
RESET
RESET
31
31
PWRDN 23
0
1
0
IC status
Reset state:
Power stage is switched off
All the registers are set to default value
Normal operation
Low power mode:
Power stage is switched off then the PLL is switched off
(this operation take 13 million clock cycles)
PWRDN 23
TWARN 20
TWARN 20
1
0
1
Temperature warning indication from external power stage
EAPD 19 0
Low power mode for power stage:
All internal regulators are switched off
EAPD 19 1
Pin PWRDN (23) is used to power down the STA335BWQS.
PWRDN = 0 (GND) → Power down
PWRND = 1 (VDD) → Normal operation
During the power-down sequence the output begins a gradual (soft) mute. After the mute condition is reached the power stage is switched off (Hi-Z) then the master clock to all internal hardware blocks is gated. The PLL is also switched off. The power-down sequence takes 13 million cycles.
Pin RESET (31) is used to reset the STA335BWQS.
RESET = 0 (GND) → Reset state Obsolete Product(s) - Obsolete Product(s)
When pin RESET is forced to 0 the power stage is switched off (Hi-Z) and the master clock to all internal hardware blocks is gated.
Note: RESET condition takes priority over PWRDN condition.
21/72
Functional description
5.2
5.2.1
Serial audio interface description
STA335BWQS
Serial audio interface protocols
The STA335BWQS serial audio input interfaces with standard digital audio components and accepts serial data formats. The STA335BWQS always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28) and serial data
SDI (pin 30).
Available formats are showed in
. The format is set through
Configuration register B (address 0x01).
Figure 8.
I
2
S
Lrclki
Bicki
Sdi 1 2 3 n
-1 n
Figure 9.
Left justified
Lrclki/
Lrclko
Biclki/
Biclko
Obsolete Product(s) - Obsolete Product(s)
Sdatai/
1 2 3 n
-1 n
1 2 3 n
-1 n
Sdatao
22/72
STA335BWQS
6 I
2
C bus specification
I
2
C bus specification
The STA335BWQS supports the I
2
C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. STA335BWQS is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate). STA335BWQS I
2
C is a slave only interface.
6.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA335BWQS and the bus master.
During the data input the STA335BWQS samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
To start communication between the master and the STA335BWQS, the master must initiate
Obsolete Product(s) - Obsolete Product(s)
The seven most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In the STA335BWQS the I
2
C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA335BWQS identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
23/72
I
2
C bus specification STA335BWQS
Following the START condition the master sends a device select code with the RW bit set to 0. The STA335BWQS acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA335BWQS again responds with an acknowledgement.
In the byte write mode the master sends one data byte, this is acknowledged by the
STA335BWQS. The master then terminates the transfer by generating a STOP condition.
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
6.4.1
6.4.2
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to 1. The STA335BWQS acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA335BWQS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
Following the START condition the master sends a device select code with the RW bit set to 0. The STA335BWQS acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA335BWQS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA335BWQS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA335BWQS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
24/72
STA335BWQS I
2
C bus specification
Figure 10.
Write mode sequence
ACK
BYTE
WRITE
DEV-ADDR
START RW
ACK
MULTIBYTE
WRITE
DEV-ADDR
START RW
SUB-ADDR
SUB-ADDR
ACK
ACK
DATA IN
ACK
ACK
STOP
DATA IN DATA IN
ACK
STOP
Figure 11.
Read mode sequence
CURRENT
ADDRESS
READ
START
RANDOM
ADDRESS
READ
START
SEQUENTIAL
CURRENT
READ
START
SEQUENTIAL
RANDOM
READ
START
ACK
DEV-ADDR
RW
ACK
DEV-ADDR
DEV-ADDR
RW
RW=
HIGH
ACK
DEV-ADDR
RW
ACK
DATA
SUB-ADDR
DATA
SUB-ADDR
NO ACK
ACK
STOP
ACK
START
DATA
DEV-ADDR
ACK
START
DEV-ADDR
RW
ACK
RW
ACK
ACK
DATA
NO ACK
NO ACK
STOP
DATA
DATA
ACK
STOP
DATA
ACK
DATA
NO ACK
STOP
Obsolete Product(s) - Obsolete Product(s)
25/72
Register description STA335BWQS
You must not reprogram the register bits marked “Reserved”. It is important that these bits keep their default reset values.
Table 9.
Addr
Register summary
Name D7 D6 D5 D4 D3 D2 D1 D0
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x10
0x11
0x12
0x13
0x14
0x15
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x00
0x01
0x02
0x03
ConfA
ConfB
ConfC
ConfD
0x04
0x05
ConfE
ConfF
0x06 Mute/LOC
0x07 Mvol
C1Vol
C2Vol
C3Vol
Auto1
Auto2
Auto3
C1Cfg
C2Cfg
FDRB
C2IM
SVE
EAPD
LOC1
MV7
TWAB
C1IM
ZCE
PWDN
TWRB
DSCKE
OCRB Reserved CSZ3
MME ZDE DRC
DCCV
ECLE
IR1
SAIFB
CSZ2
BQL
PWMS
LDTE
LOC0 Reserved Reserved
MV6 MV5 MV4
IR0
SAI3
CSZ1
PSL
AME
BCLE
C3M
MV3
MCS2
SAI2
CSZ0
DSPB
IDE
C2M
MV2
MCS1
SAI1
OM1
DEMP
NSBW MPC MPCV
OCFG1
C1M
MV1
MCS0
SAI0
OM0
HPB
OCFG0
MMute
MV0
C1V7
C2V7
C1V6
C2V6
C1V5
C2V5
C1V4
C2V4
C1V3
C2V3
C1V2
C2V2
C1V1
C2V1
C1V0
C2V0
C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0
Reserved Reserved AMGC1 AMGC0 Reserved Reserved Reserved Reserved
XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
C1OM1 C1OM0
C2OM1 C2OM0
C1LS1
C2LS1
C1LS0 C1BO C1VBP
C2LS0 C2BO C2VBP
C1EQBP
C2EQBP
C1TCB
C2TCB
B1cf2
B1cf3
B2cf1
B2cf2
B2cf3
A1cf1
C3Cfg
Tone
L1ar
L1atrt
C3OM1 C3OM0
TTC3 TTC2
L1A3
L1AT3
L1A2
L1AT2
L2ar
L2atrt
L2A3
L2AT3
L2A2
L2AT2
Cfaddr Reserved Reserved
B1cf1 C1B23 C1B22
C1B15
C1B7
C2B23
C2B15
C2B7
C3B23
C1B14
C1B6
C2B22
C2B14
C2B6
C3B22
C3LS1
TTC1
L1A1
L1AT1
L2A1
L2AT1
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
C2B5
C3B21
C3LS0
TTC0
L1A0
L1AT0
L2A0
L2AT0
CFA4
C1B20
C1B12
C1B4
C2B20
C2B12
C2B4
C3B20
C3BO
BTC3
L1R3
L1RT3
L2R3
L2RT3
CFA3
C1B19
C1B11
C1B3
C2B19
C2B11
C2B3
C3B19
C3VBP Reserved Reserved
BTC2 BTC1 BTC0
L1R2
L1RT2
L1R1
L1RT1
L1R0
L1RT0
L2R2
L2RT2
CFA2
C1B18
C1B10
C1B2
C2B18
C2B10
C2B2
C3B18
L2R1
L2RT1
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C2B1
C3B17
L2R0
L2RT0
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C2B0
C3B16
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STA335BWQS Register description
Table 9.
Addr
Register summary (continued)
Name D7 D6 D5 D4 D3 D2 D1 D0
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
A1cf2
A1cf3
A2cf1
A2cf2
A2cf3
B0cf1
B0cf2
C3B15
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C3B14
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C3B13
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C3B12
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C3B11
C3B3
C4B19
C4B11
C4B3
C5B19
C5B11
C3B10
C3B2
C4B18
C4B10
C4B2
C5B18
C5B10
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
C5B9
0x25
0x26
0x27
0x28
0x29
B0cf3
Cfud
C5B7 C5B6 C5B5 C5B4
Reserved Reserved Reserved Reserved
C5B3
RA
C5B2
R1
C5B1
WA
C5B0
W1
MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
0x2A
0x2B
0x2C
DCC2
FDRC1
FDRC2
DCC7
FDRC15
FDRC7
DCC6
FDRC14
FDRC6
DCC5
FDRC13
FDRC5
DCC4
FDRC12
FDRC4
DCC3
FDRC11
FDRC3
DCC2
FDRC10
FDRC2
DCC1
FDRC9
FDRC1
DCC0
FDRC8
FDRC0
0x2D Status PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN
0x2E Reserved Reserved Reserved RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT
0x2F Reserved Reserved Reserved R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND
0x30 Reserved Reserved Reserved Reserved R5BBAD R4BBAD R3BBAD R2BBAD R1BBAD
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
C5B8
7.1 Configuration register A (addr 0x00)
D7
FDRB
0
D6
TWAB
1
D5
TWRB
1
D4
IR1
0
D3
IR0
0
D2
MCS2
0
D1
MCS1
1
D0
MCS0
1
Table 10.
MCS Obsolete Product(s) - Obsolete Product(s)
0 RW 1 MCS0
1 RW 1 MCS1
Selects the ratio between the input I
2
S sample frequency and the input clock.
2 RW 0 MCS2
27/72
Register description STA335BWQS z z
The STA335BWQS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is: z 32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f s
).
The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally
Table 11.
Input sampling rates
Input sample rate fs (kHz)
IR MCS[2:0]
32, 44.1, 48
88.2, 96
176.4, 192
101 100 011 010 001 000
00 576 x fs 128 x fs 256 x fs 384 x fs 512 x fs 768 x fs
01 NA 64 x fs 128 x fs 192 x fs 256 x fs 384 x fs
1X NA 32 x fs 64 x fs 96 x fs 128 x fs 192 x fs
7.1.2 Interpolation ratio select
Table 12.
IR
Bit R/W
4:3 RW
RST
00
Name
IR [1:0]
Description
Selects internal interpolation ratio based on input I
2
S sample frequency
The STA335BWQS has variable interpolation (oversampling) settings such that internal processing and DDX
®
output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample.
The oversampling ratio of this interpolation is determined by the IR bits.
Table 13.
IR bit settings as a function of input sample rate
Input sample rate fs (kHz) IR 1st stage interpolation ratio
32
44.1
00
00
2 times oversampling
2 times oversampling
48 00 2 times oversampling
88.2
96
176.4
192
01
01
10
10
Pass-through
Pass-through
2 times downsampling
2 times downsampling
28/72
STA335BWQS
7.1.3
7.1.4
Register description
Thermal warning recovery bypass
Table 14.
TWRB
Bit R/W RST
5 RW 1
Name
TWRB
Description
0: Thermal warning recovery enabled
1: Thermal warning recovery disabled
If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative.
If TWRB = 0 and TWAB = 0 then, when a thermal warning disappears, the -3 dB output limit is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset.
Thermal warning adjustment bypass
Table 15.
TWAB
Bit R/W RST
6 RW 1
Name
TWAB
Description
0: Thermal warning adjustment enabled
1: Thermal warning adjustment disabled
The on-chip STA335BWQS power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than
400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in coefficients RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.
Table 16.
FDRB
Bit R/W RST
7 RW 0
Name
FDRB
Description
0: fault detect recovery enabled
1: fault detect recovery disabled
The on-chip STA335BWQS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition Obsolete Product(s) - Obsolete Product(s) attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (FDRC registers
0x29, 0x2A), then toggles it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
29/72
Register description
7.2
7.2.1
STA335BWQS
Configuration register B (addr 0x01)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
Serial audio input interface format
Table 17.
SAIn
Bit R/W RST
2
3
0
1
RW
RW
RW
RW
0
0
0
0
Name
SAI0
SAI1
SAI2
SAI3
Description
Determines the interface format of the input serial digital audio interface.
7.2.3
The STA335BWQS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA335BWQS always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.
The SAI register (configuration register B (0x01), bits D3 to D0) and the SAIFB register
(configuration register B (0x01), bit D4) are used to specify the serial data format. The default serial data format is I
2
S, MSB first. Available formats are shown in the tables and figure that follow.
Serial data first bit
Table 18.
SAIFB
SAIFB
0
1
MSB first
LSB first
Format
Obsolete Product(s) - Obsolete Product(s)
30/72
STA335BWQS Register description
Table 19.
Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
0000 0 I
2
S 15-bit data
32fs
0001
0000
0
0
Left/right-justified 16-bit data
I
2
S 16 to 23-bit data
48fs
64fs
0001
0010
0110
1010
1110
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
Left-justified 16 to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16 to 24-bit data
Left-justified 16 to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
Table 20.
Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB
32fs
1100
1110
0100
0100
1000
1100
1
1
1
1
1
1
Interface Format
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
48fs
0001
0101
1001
1
1
1
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
1101 1 Left-justified 16-bit data
0010
0110
1
1
Right-justified 24-bit data
Right-justified 20-bit data
1010 1 Right-justified 18-bit data
1110 1 Right-justified 16-bit data
31/72
Register description STA335BWQS
7.2.4
Table 20.
Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)
BICKI SAI [3:0]
0000
0100
1000
1100
0001
SAIFB
1
1
1
1
1
Interface Format
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
64fs
0101
1001
1101
0010
0110
1010
1110
1
1
1
1
1
1
1
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
Delay serial clock enable
Table 21.
DSCKE
Bit R/W RST Name
5 RW 0 DSCKE
Description
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
7.2.5 Channel input mapping
Table 22.
CnIM
Bit R/W RST
6
7
RW
RW
0
1
Name
C1IM
C2IM
Description
0: Processing channel 1 receives Left I
2
S Input
1: Processing channel 1 receives Right I
2
S Input
0: Processing channel 2 receives Left I
2
S Input
1: Processing channel 2 receives Right I
2
S Input
Each channel received via I
2
S can be mapped to any internal processing channel via the Obsolete Product(s) - Obsolete Product(s) of these registers map each I
2
S input channel to its corresponding processing channel.
32/72
STA335BWQS Register description
7.3 Configuration register C (addr 0x02)
D7
OCRB
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
OM1
1
7.3.1 DDX
®
power output mode
Table 23.
OM
Bit R/W RST
0
1
RW
RW
1
1
Name
OM0
OM1
Description
Selects configuration of DDX output.
The DDX power output mode selects how the DDX output timing is configured.
Different power devices use different output modes.
Table 24.
Output modes
OM[1,0]
00
01
10
11
Output stage - mode
Drop compensation
Discrete output stage - tapered compensation
Full power mode
Variable drop compensation (CSZx bits)
D0
OM0
1
7.3.2 DDX
®
compensating pulse size register
Table 25.
CSZ
Bit R/W RST
4
5
2
3
RW
RW
RW
RW
1
0
1
0
Name
CSZ0
CSZ1
CSZ2
CSZ3
Description
When OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 15 clock periods.
Table 6:
Table 26.
Compensating pulse size
Obsolete Product(s) - Obsolete Product(s)
0000 0 ns (0 ticks) compensating pulse size
0001 20 ns (1 tick) clock period compensating pulse size
…
1111
…
300 ns (15 ticks) clock period compensating pulse size
33/72
Register description
7.3.3
STA335BWQS
Over-current warning detect adjustment bypass
Table 27.
OCRB
Bit R/W RST
7 RW 1
Name
OCRB
Description
0: Over-current warning adjustment enabled
1: Over-current warning adjustment disabled
The OCWARN input is used to indicate an over-current warning condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default is -3 dB) in an attempt to eliminate the over-current warning condition. Once the over-current warning volume adjustment is applied, it remains in this state until reset is applied. The level of adjustment can be changed via the TWOCL (thermal warning/over current limit) setting which is address 0x37 of the user defined coefficient RAM.
7.4 Configuration register D (addr 0x03)
D7
MME
0
D6
ZDE
1
D5
DRC
0
D4
BQL
0
D3
PSL
0
D2
DSPB
0
D1
DEMP
0
D0
HPB
0
Table 28.
HPB
Bit R/W RST
0 RW 0
Name
HPB
Description
Setting of one bypasses internal AC coupling digital high-pass filter
The STA335BWQS features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled.
7.4.2 De-emphasis
Table 29.
DEMP
Bit R/W RST Name Description
0: No de-emphasis
1 RW 0 DEMP
1: De-emphasis Obsolete Product(s) - Obsolete Product(s)
Setting the DEMP bit enables de-emphasis on all channels
34/72
Table 30.
DSPB
Bit R/W RST
2 RW 0
Name
DSPB
Description
0: Normal operation
1: Bypass of biquad and bass/treble function
STA335BWQS
Setting the DSPB bit bypasses the EQ function of the STA335BWQS.
Register description
7.4.5
Table 31.
PSL
Bit R/W RST
3 RW 0
Name
PSL
Description
0: Each channel uses individual post-scale value
1: Each channel uses channel 1 post-scale value
Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster.
Biquad coefficient link
Table 32.
BQL
Bit R/W RST
4 RW 0
Name
BQL
Description
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting bit BQL to 1. Therefore, any EQ updates only have to be performed once.
Table 33.
DRC
Bit R/W RST
5 RW 0
Name
DRC
Description
0: Limiters act in anti-clipping mode
1: Limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.
7.4.7 Zero-detect mute enable
Obsolete Product(s) - Obsolete Product(s)
Table 34.
ZDE
Bit R/W RST Name Description
6 RW 1 ZDE Setting of 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.
35/72
Register description STA335BWQS
Table 35.
MME
Bit R/W RST
7 RW 0
Name
MME
Description
0: Sub mix into left/right disabled
1: Sub mix into left/right enabled
7.5
7.5.1
Configuration register E (addr 0x04)
D7
SVE
1
D6
ZCE
1
D5
DCCV
0
D4
PWMS
0
D3
AME
0
Max power correction variable
Table 36.
MPCV
Bit R/W RST Name
0 RW 0 MPCV
D2
NSBW
0
D1
MPC
1
Description
0: Use standard MPC coefficient
1: Use MPCC bits for MPC coefficient
D0
MPCV
0
7.5.2 Max power correction
Table 37.
MPC
Bit R/W RST
1 RW 1
Name
MPC
Description
Setting of 1 enables Power Bridge correction for
THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA335BW power device at high power. This mode should lower the THD+N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-out channels.
7.5.3 Noise-shaper bandwidth selection
Table 38.
NSBW Obsolete Product(s) - Obsolete Product(s)
Bit R/W RST Name Description
2 RW 0 NSBW
1: Third-order NS
0: Fourth-order NS
36/72
STA335BWQS Register description
Table 39.
AME
Bit R/W RST
3 RW 0
Name
AME
Description
0: Normal DDX operation.
1: AM reduction mode DDX operation
STA335BWQS features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.
Table 40.
PWMS
Bit R/W RST
4 RW 0
Name
PWMS
Description
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels
Table 41.
DCCV
Bit R/W RST
5 RW 0
Name
DCCV
Description
0: Uses preset DC coefficient
1: Uses DCC coefficient
Table 42.
ZCE
Bit R/W RST
6 RW 1
Name
ZCE
Description
1: Volume adjustments only occur at digital zero-crossings
0: Volume adjustments occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible.
Soft volume update enable
Table 43.
SVE
Bit R/W RST Name
7 RW 1 SVE
Description
1: Volume adjustments ramp according to SVR settings
0: Volume adjustments occur immediately
37/72
Register description
7.6 Configuration register F (addr 0x05)
D7
EAPD
0
D6
PWDN
1
D5
ECLE
0
D4
LDTE
1
D3
BCLE
1
STA335BWQS
D2
IDE
1
D1
OCFG1
0
D0
OCFG0
0
Table 44.
OCFG
Bit R/W RST
0
1
RW
RW
0
0
Name
OCFG0
OCFG1
Description
Selects the output configuration
Table 45.
Output configuration engine selection
OCFG[1:0] Output configuration Config pin
00
2-channel (full-bridge) power, 2-channel data-out:
1A/1B
→
1A/1B
2A/2B → 2A/2B
LineOut1 → 3A/3B
LineOut2 → 4A/4B
Line out configuration determined by LOC register
0
01
10
2 (half-bridge), 1 (full-bridge) on-board power:
1A → 1A Binary 0 °
2A → 1B Binary 90°
3A/3B → 2A/2B Binary 45°
1A/B → 3A/B Binary 0°
2A/B
→
4A/B Binary 90°
2-channel (full-bridge) power, 1-channel DDX:
1A/1B
→
1A/1B
2A/2B → 2A/2B
3A/3B → 3A/3B
EAPDEXT and TWARNEXT Active
0
0
1-channel mono-parallel:
11
3A → 1A/1B w/ C3BO 45°
3B → 2A/2B w/ C3BO 45°
1A/1B → 3A/3B
2A/2B → 4A/4B
1
Obsolete Product(s) - Obsolete Product(s) of the three processing channel outputs can be used for any of the three inputs.
38/72
STA335BWQS
Figure 12.
OCFG = 00 (default value)
OUT1A
Half
Bridge
Channel 1
Half
Bridge
OUT1B
OUT2A
Half
Bridge
Half
Bridge
Channel 2
OUT2B
OUT3A
OUT3B LPF
LineOut 1
OUT4A
OUT4B LPF
LineOut 2
Figure 14.
OCFG = 10
OUT1A
Half
Bridge
Half
Bridge
Half
Bridge
Half
Bridge
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
Power
Device
EAPD
Channel 1
Channel 2
Channel 3
Figure 13.
OCFG = 01
Half
Bridge
Half
Bridge
Half
Bridge
Half
Bridge
OUT1A
OUT1B
OUT2A
OUT2B
Register description
Channel 1
Channel 2
Channel 3
Figure 15.
OCFG = 11
OUT1A
Half
Bridge
OUT1B
Half
Bridge
Half
Bridge
Half
Bridge
OUT2A
OUT2B
OUT3A
OUT3B
Channel 1
OUT4A
OUT4B
Channel 2
Channel 3
STA335BWQS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. The PWM slot always has a time duration of
1 / (8 * fs) seconds and defines the maximum extension for PWM rising and falling edges, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries.
Figure 16.
Output mapping scheme.
DDX1A
DDX1B
OUT1A OUT1A
DDX2A
OUT1B OUT1B
DDX™ modulator
DDX2B
DDX3A
DDX3B
DDX4A
DDX4B
OUT2A
Power
Bridge Obsolete Product(s) - Obsolete Product(s)
OUT2B
OUT2A
OUT2B
REM AP
OUT3A
OUT3B
OUT4A
OUT4B
39/72
Register description STA335BWQS
For each configuration the PWM from the digital driver is mapped in a different way to the power stage:
2.0 channels, two full bridges (OCFG = 00)
z z z z z z z z z z z z
DDX1A : OUT1A
DDX1B : OUT1B
DDX2A : OUT2A
DDX2B : OUT2B
DDX3A : OUT3A
DDX3B : OUT3B
DDX4A : OUT4A
DDX4B : OUT4B
DDX1A/1B configured as ternary
DDX2A/2B configured as ternary
DDX3A/3B configured as line-out ternary
DDX4A/4B configured as line-out ternary.
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing are sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing are sent. In this configuration, no volume control or EQ have effect on channel 3 and 4.
shows the PWM slot phases for this configuration.
Figure 17.
2.0 channels (OCFG = 00) PWM slots.
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
Obsolete Product(s) - Obsolete Product(s)
40/72
STA335BWQS Register description
2.1 channels, two half bridges + one full bridge (OCFG = 01)
z z z z z z z z z z z z
DDX1A : OUT1A
DDX2A : OUT1B
DDX3A : OUT2A
DDX3B : OUT2B
DDX1A : OUT3A
DDX1B : OUT3B
DDX2A : OUT4A
DDX2B : OUT4B
DDX1A/1B configured as binary
DDX2A/2B configured as binary
DDX3A/3B configured as binary
DDX4A/4B not used.
In this configuration, channel 3 has full control (for example, on volume, EQ). On
OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated.
shows the PWM slot phases for this configuration.
Figure 18.
2.1 channels (OCFG = 01) PWM slots.
Obsolete Product(s) - Obsolete Product(s)
41/72
Register description STA335BWQS
2.1 channels, two full bridge + one external full bridge (OCFG = 10)
z z z z z z z z z z z z
DDX1A : OUT1A
DDX1B : OUT1B
DDX2A : OUT2A
DDX2B : OUT2B
DDX3A : OUT3A
DDX3B : OUT3B
EAPD : OUT4A
TWARN : OUT4B
DDX1A/1B configured as ternary
DDX2A/2B configured as ternary
DDX3A/3B configured as ternary
DDX4A/4B not used.
In this configuration, channel 3 has full control (for example, on volume, EQ). On OUT4 channel the external bridge control signals are muxed.
shows the PWM slot phases for this configuration.
Figure 19.
2.1 channels (OCFG = 10) PWM slots.
42/72
Bit R/W RST Name Description
2 RW 1 IDE
Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I
2
S data and will automatically mute if the signals are perceived as invalid.
STA335BWQS
7.6.3
7.6.4
7.6.5
Register description
Binary output mode clock loss detection
Table 47.
BCLE
Bit R/W RST
3 RW 1
Name
BCLE
Description
Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 48.
LDTE
Bit R/W RST
4 RW 1
Name
LDTE
Actively prevents double trigger of LRCLK.
Description
LRCLK double trigger protection enable
Auto EAPD on clock loss
Table 49.
ECLE
Bit R/W RST
5 RW 0
Name
ECLE
Description
Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
Table 50.
PWDN
Bit R/W RST
7 RW 1
Name
PWDN
Description
0: IC power down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, then the master clock to all internal hardware expect the
I
2
C block is gated. This places the IC in a very low power consumption state.
Obsolete Product(s) - Obsolete Product(s)
Table 51.
EAPD
Bit R/W RST Name Description
7 RW 0 EAPD
0: External power stage power down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register also controls the DDX4B/EAPD output pin when OCFG = 10.
43/72
Register description
7.7 Volume control registers (addr 0x06 to 0x0A)
STA335BWQS
7.7.2
7.7.3
7.7.4
D7
LOC1
0
D6
LOC0
0
D5
Reserved
0
Table 52.
LOC description
LOC[1:0]
00
01
10
D4
Reserved
0
D3
C3M
0
D2
C2M
0
Line output configuration
Line output fixed - no volume, no EQ
Line output variable - CH3 volume effects line output, no EQ
Line output variable with EQ - CH3 volume effects line output
D1
C1M
0
D0
MMUTE
0
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.
Master volume register
D7
MV7
1
D6
MV6
1
D5
MV5
1
D4
MV4
1
D3
MV3
1
D2
MV2
1
D1
MV1
1
D0
MV0
1
Channel 1 volume
D7
C1V7
0
D6
C1V6
1
D5
C1V5
1
Channel 2 volume
D7
C2V7
0
D6
C2V6
1
D5
C2V5
1
D4
C1V4
0
D4
C2V4
0
D3
C1V3
0
D3
C2V3
0
D2
C1V2
0
D2
C2V2
0
D1
C1V1
0
D1
C2V1
0
D0
C1V0
0
D0
C2V0
0
Obsolete Product(s) - Obsolete Product(s)
44/72
STA335BWQS Register description
7.7.5 Channel 3 / line output volume
D7
C3V7
0
D6
C3V6
1
D5
C3V5
1
D4
C3V4
0
D3
C3V3
0
D2
C3V2
0
D1
C3V1
0
D0
C3V0
0
The volume structure of the STA335BWQS consists of separate volume registers for each channel and a master volume register to provide an offset to each channel volume setting.
The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB.
As an example if C3V = 0x00 (+48 dB) and MV = 0x18 (-12 dB) then the total gain for channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel mutes (CnM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (~96 kHz).
A “hard mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 ( Configuration register F
on a per channel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates occur immediately.
Table 53.
Master volume offset as a function of MV[7:0]
MV[7:0] Volume offset from channel value
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01001100 (0x4C)
…
11111110 (0xFE)
11111111 (0xFF)
0 dB
-0.5 dB
-1 dB
…
-38 dB
…
-127.5 dB
Hard master mute
Table 54.
Channel volume as a function of CnV[7:0]
CnV[7:0]
00000000 (0x00)
Volume
Obsolete Product(s) - Obsolete Product(s)
00000001 (0x01) +47.5 dB
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
01100001 (0x61)
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
45/72
Register description
Table 54.
Channel volume as a function of CnV[7:0] (continued)
CnV[7:0] Volume
…
11010111 (0xD7)
11011000 (0xD8)
11011001 (0xD9)
11011010 (0xDA)
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
…
-59.5 dB
-60 dB
-61 dB
-62 dB
…
-80 dB
Hard channel mute
…
Hard channel mute
STA335BWQS
7.8.1 AutoModes™ register 1 (0x0B)
D7
Reserved
0
D6
Reserved
0
D5
AMGC1
0
D4
AMGC2
0
D3
Reserved
0
D2
Reserved
0
Table 55.
AutoModes™ gain compression/limiters selection
AMGC[1:0] Mode
00
01
10
11
User programmable GC
AC no clipping 2.1
AC limited clipping (10%) 2.1
DRC nighttime listening mode 2.1
D1
Reserved
0
D0
Reserved
0
7.8.2 AutoModes™ register 2 (0x0C)
D7 D6 D5 D4 D3 D2 D1 D0
XO3
0
XO2
0
XO1
0
XO0
0
AMAM2
0
AMAM1
0
AMAM0
0
AMAME
0
46/72
STA335BWQS Register description
Table 56.
AM enable
Bit R/W RST
0 RW 0
Name
AMAME
Description
AutoModes™ AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 57.
AutoModes™ AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
000
001
010
011
100
101
110
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
Bit
6
7
4
5
R/W
RW
RW
RW
RW
RST
0
0
0
0
Name
XO0
XO1
XO2
XO3
Description
Selects the bass-management crossover frequency.
A 1st-order high-pass filtering (channels 1 and 2) or a 2nd-order low-pass filtering (channel 3) at the selected frequency is performed.
Table 58.
Bass management crossover frequency
XO[3:0] Crossover frequency
0000
0001
User-Defined
80 Hz
0010 100 Hz
0011
0100
120 Hz Obsolete Product(s) - Obsolete Product(s)
0101 160 Hz
0110
0111
180 Hz
200 Hz
1000
1001
1010
220 Hz
240 Hz
260 Hz
47/72
Register description
Table 58.
Bass management crossover frequency (continued)
XO[3:0] Crossover frequency
1011
1100
1101
1110
1111
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
STA335BWQS
7.9.1
D7
C2OM1
0
D7
C1OM1
0
D7
C3OM1
1
D6
C1OM0
0
D6
C2OM0
1
D6
C3OM0
0
D5
C1LS1
0
D5
C2LS1
0
D5
C3LS1
0
D4
C1LS0
0
D4
C2LS0
0
D4
C3LS0
0
D3
C1BO
0
D3
C2BO
0
D3
C3BO
0
D2
C1VPB
0
D2
C2VPB
0
D2
C3VPB
0
D1
C1EQBP
0
D1
C2EQBP
0
D1
Reserved
0
Tone control bypass
Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2.
CnTCB:
0: Perform tone control on channel n - normal operation
1: Bypass tone control on channel n
D0
C1TCB
0
D0
C2TCB
0
D0
Reserved
0
EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel.
CnEQBP:
Obsolete Product(s) - Obsolete Product(s)
1: Bypass EQ on channel n
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CnVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
48/72
STA335BWQS
7.9.4
Register description
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse.
CnBO:
0: DDX 3-state output - normal operation
1: Binary output
Limiter selection can be made on a per-channel basis according to the channel limiter select bits.
.
Table 59.
Channel limiter mapping as a function of CnLS bits
CnLS[1,0] Channel limiter mapping
00
01
10
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
Output mapping can be performed on a per channel basis according to the CnOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.
.
Table 60.
Channel output mapping as a function of CnOM bits
CnOM[1,0] Channel n output source from
00
01
10
Channel 1
Channel 2
Channel 3
Obsolete Product(s) - Obsolete Product(s)
49/72
STA335BWQS Register description
7.10 Tone control register (addr 0x11)
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
Table 61.
Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0] / TTC[3:0] Boost / Cut
D1
BTC1
1
0000
0001
…
0111
0110
0111
1000
1001
…
1101
1110
1111
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
…
+12 dB
+12 dB
+12 dB
D0
BTC0
1
7.11 Dynamics control registers (addr 0x12 to 0x15)
7.11.1 Limiter 1 attack/release rate
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
D3
L1R3
1
D2
L1R2
0
D1
L1R1
1
D0
L1R0
0
7.11.2 Limiter 1 attack/release threshold
Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0
0 1 1 0 1 0 0 1
7.11.3 Limiter 2 attack/release rate
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L2R3
1
D2
L2R2
0
D1
L2R1
1
D0
L2R0
0
50/72
STA335BWQS Register description
7.11.4 Limiter 2 attack/release threshold
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
The STA335BWQS includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in
Configuration register F (addr 0x05) , bit 0. Each
channel can be mapped to either limiter or not mapped, meaning that channel will clip when
0 dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LnAT registers. It is recommended in anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within STA335BWQS it is possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm.
The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past it's set value and therefore the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.
Figure 20.
Basic limiter and volume flow diagram
Obsolete Product(s) - Obsolete Product(s)
Limiter RMS
Gain, volume
Output
Input
Saturation Gain Attenuation
51/72
Register description STA335BWQS
Table 62.
Attack rate
LnA[3:0] Attack rate (dB/ms)
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
3.1584 (fast)
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
0.2256
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451 (slow)
Table 63.
Release rate
LnR[3:0] Release rate (dB/s)
0000
0001
0010
0011
0100
0101
0110
0111
3.904 (fast)
3.859
3.859
3.849
3.793
3.750
3.682
3.549
1000
1001
3.483
Obsolete Product(s) - Obsolete Product(s)
1010 3.357
1011 3.284
1100
1101
1110
1111
3.082
2.957
2.864
2.864 (slow)
52/72
STA335BWQS Register description
Table 64.
LnAT bits, anti-clipping
LnAT[3:0]
Anti-clipping (AC)
(dB relative to FS)
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
+3
+4
+5
+6
+7
+8
+9
+10
-4
-2
0
+2
-12
-10
-8
-6
Table 65.
LnRT bits, anti-clipping
LnRT[3:0]
Anti-clipping (AC)
(dB relative to FS)
0000
0001
0010
0011
0100
∞
-29 dB
-20 dB
-16 dB
-14 dB
0101 -12 dB
0110 -10 dB
0111 -8 dB Obsolete Product(s) - Obsolete Product(s)
1000 -7 dB
1001
1010
-6 dB
-5 dB
1011
1100
1101
-4 dB
-3 dB
-2 dB
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Register description STA335BWQS
Table 65.
LnRT bits, anti-clipping (continued)
LnRT[3:0]
Anti-clipping (AC)
(dB relative to FS)
1110
1111
-1 dB
-0 dB
Table 66.
LnAT bits, dynamic range compression
LnAT[3:0]
Dynamic range compression (DRC)
(dB relative to volume)
0111
1000
1001
1010
1011
1100
0000
0001
0010
0011
0100
0101
0110
1101
1110
1111
-17
-16
-15
-14
-13
-12
-31
-29
-27
-25
-23
-21
-19
-10
-7
-4
0011
0100
0101
0110
0111
1000
1001
Table 67.
LnRT bits, dynamic range compression
LnRT[3:0]
Dynamic range compression (DRC)
(dB relative to volume + LnAT)
0000
0001
∞
-38 dB
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
-26 dB
-24 dB
-22 dB
54/72
STA335BWQS Register description
Table 67.
LnRT bits, dynamic range compression (continued)
LnRT[3:0]
Dynamic range compression (DRC)
(dB relative to volume + LnAT)
1010
1011
1100
1101
1110
1111
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
7.12 User-defined coefficient control registers (addr 0x16 to 0x26)
7.12.1 Coefficient address register
D7
Reserved
0
D6
Reserved
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
7.12.2 Coefficient register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
7.12.3 Coefficient data register bits 15:8
D7
C1B15
0
D6
C1B14
0
D5
C1B13
0
D4
C1B12
0
D3
C1B11
0
D2
C1B18
0
D2
C1B10
0
D1
C1B17
0
D1
C1B9
0
D0
C1B16
0
D0
C1B8
0
7.12.4 Coefficient data register bits 7:0
D7 D6 D5 D4 D3 D2 D1 D0
C1B7
0
C1B6
0
C1B5
0
C1B4
0
C1B3
0
C1B2
0
C1B1
0
C1B0
0
7.12.5 Coefficient register bits 23:16
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
D2
C2B18
0
D1
C2B17
0
D0
C2B16
0
55/72
Register description
7.12.6 Coefficient data register bits 15:8
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
7.12.7 Coefficient data register bits 7:0
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
7.12.8 Coefficient register bits 23:16
D7
C3B23
0
D6
C3B22
0
D5
C3B21
0
D4
C3B20
0
D3
C3B19
0
7.12.9 Coefficient data register bits 15:8
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
D2
C2B10
0
D2
C2B2
0
D2
C3B18
0
D2
C3B10
0
D1
C2B9
0
D1
C2B1
0
D1
C3B17
0
D0
C3B16
0
D1
C3B9
0
STA335BWQS
D0
C2B8
0
D0
C2B0
0
D0
C3B8
0
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
D2
C3B2
0
D1
C3B1
0
D0
C3B0
0
D7
C4B23
0
D6
C4B22
0
D5
C4B21
0
D4
C4B20
0
D3
C4B19
0
D2
C4B18
0
D1
C4B17
0
D0
C4B16
0
Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
C4B15
0
C4B14
0
C4B13
0
C4B12
0
C4B11
0
C4B10
0
C4B9
0
C4B8
0
56/72
STA335BWQS Register description
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
D2
C4B2
0
D1
C4B1
0
D0
C4B0
0
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
RA
0
D2
R1
0
D1
WA
0
D0
W1
0
Coefficients for user-defined EQ, Mixing, Scaling, and Bass Management are handled internally in the STA335BWQS via RAM. Access to this RAM is available to the user via an
I
2
C register interface. A collection of I
2
C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.
Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.
Obsolete Product(s) - Obsolete Product(s)
1.
Write 6-bits of address to I
2
C register 0x16.
2. Write 1 to R1 bit in I
2
C address 0x26.
3. Read top 8-bits of coefficient in I
2
C address 0x17.
4. Read middle 8-bits of coefficient in I
2
C address 0x18.
5. Read bottom 8-bits of coefficient in I
2
C address 0x19.
57/72
Register description
Reading a set of coefficients from RAM
1.
Write 6-bits of address to I
2
C register 0x16.
2. Write 1 to RA bit in I
2
C address 0x26.
3. Read top 8-bits of coefficient in I
2
C address 0x17.
4. Read middle 8-bits of coefficient in I
2
C address 0x18.
5. Read bottom 8-bits of coefficient in I
2
C address 0x19.
6. Read top 8-bits of coefficient b2 in I
2
C address 0x1A.
7. Read middle 8-bits of coefficient b2 in I
2
C address 0x1B.
8. Read bottom 8-bits of coefficient b2 in I
2
C address 0x1C.
9. Read top 8-bits of coefficient a1 in I
2
C address 0x1D.
10. Read middle 8-bits of coefficient a1 in I
2
C address 0x1E.
11. Read bottom 8-bits of coefficient a1 in I
2
C address 0x1F.
12. Read top 8-bits of coefficient a2 in I
2
C address 0x20.
13. Read middle 8-bits of coefficient a2 in I
2
C address 0x21.
14. Read bottom 8-bits of coefficient a2 in I
2
C address 0x22.
15. Read top 8-bits of coefficient b0 in I
2
C address 0x23.
16. Read middle 8-bits of coefficient b0 in I
2
C address 0x24.
17. Read bottom 8-bits of coefficient b0 in I
2
C address 0x25.
Writing a single coefficient to RAM
1.
Write 6-bits of address to I
2
C register 0x16.
2. Write top 8-bits of coefficient in I
2
C address 0x17.
3. Write middle 8-bits of coefficient in I
2
C address 0x18.
4. Write bottom 8-bits of coefficient in I
2
C address 0x19.
5. Write 1 to W1 bit in I
2
C address 0x26.
STA335BWQS
Obsolete Product(s) - Obsolete Product(s)
58/72
STA335BWQS Register description
Writing a set of coefficients to RAM
1.
Write 6-bits of starting address to I
2
C register 0x16.
2. Write top 8-bits of coefficient b1 in I
2
C address 0x17.
3. Write middle 8-bits of coefficient b1 in I
2
C address 0x18.
4. Write bottom 8-bits of coefficient b1 in I
2
C address 0x19.
5. Write top 8-bits of coefficient b2 in I
2
C address 0x1A.
6. Write middle 8-bits of coefficient b2 in I
2
C address 0x1B.
7. Write bottom 8-bits of coefficient b2 in I
2
C address 0x1C.
8. Write top 8-bits of coefficient a1 in I
2
C address 0x1D.
9. Write middle 8-bits of coefficient a1 in I
2
C address 0x1E.
10. Write bottom 8-bits of coefficient a1 in I
2
C address 0x1F.
11. Write top 8-bits of coefficient a2 in I
2
C address 0x20.
12. Write middle 8-bits of coefficient a2 in I
2
C address 0x21.
13. Write bottom 8-bits of coefficient a2 in I
2
C address 0x22.
14. Write top 8-bits of coefficient b0 in I
2
C address 0x23.
15. Write middle 8-bits of coefficient b0 in I
2
C address 0x24.
16. Write bottom 8-bits of coefficient b0 in I
2
C address 0x25.
17. Write 1 to WA bit in I
2
C address 0x26.
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA335BWQS generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
The STA335BWQS provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:
Y[n] = 2(b
0
/2)X[n] + 2(b
1
/2)X[n-1] + b
2
X[n-2] - 2(a
1
/2)Y[n-1] - a
2
Y[n-2]
= b
0
X[n] + b
1
X[n-1] + b
2
X[n-2] - a
1
Y[n-1] - a
2
Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user defined coefficient RAM are referenced in the following
Obsolete Product(s) - Obsolete Product(s)
CnHm0 = b
1
/2
CnHm1 = b
2
CnHm2 = -a
1
/2
CnHm3 = -a
2
CnHm4 = b
0
/2 where n represents the channel and the m the biquad number. For example C2H41 is the b
2 coefficient in the fourth biquad for channel 2.
59/72
Register description STA335BWQS
Additionally, the STA335BWQS allows specification of a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass-management crossover when the XO setting is 000 (user-defined). Both of these filters, when defined by the user (rather than using the preset crossover filters), are second-order filters that use the biquad equation given above. They are loaded into the
C12H0-4 and C3Hm0-4 areas of RAM noted in
.
By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b
0
/2 coefficient which is set to 0x400000 (representing 0.5)
7.12.19 Pre-scale
The STA335BWQS provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass-management. All channels can use the channel 1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
7.12.20 Post-scale
The STA335BWQS provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF =
0.9999998808. The scale factor for this multiply is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 0x7FFFFF. When Line output is being utilized, channel 3 post-scale will affect both channels 3 and 4.
The STA335BWQS provides a simple mechanism for reacting to over-current detection in the power-block. When the OCWARN input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels.
The default setting provides 3 dB of output attenuation when OCWARN is asserted.
The amount of attenuation to be applied in this situation can be adjusted by modifying the
Over-current post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the over-current post-scale factor is set to 0x5A9DF7 . Once the over-current attenuation is applied, it remains until the device is reset.
Obsolete Product(s) - Obsolete Product(s)
Table 68.
RAM block for biquads, mixing, scaling and bass setup
Index (decimal) Index (hex) Coefficient Default
0
1
2
3
4
0x00
0x01
0x02
0x03
0x04
Channel 1 - Biquad 1
C1H10(b1/2)
C1H11(b2)
C1H12(a1/2)
C1H13(a2)
C1H14(b0/2)
0x000000
0x000000
0x000000
0x000000
0x400000
60/72
STA335BWQS Register description
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x30
0x31
0x32
0x33
0x34
0x35
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x05
…
0x13
0x14
0x15
…
0x27
Table 68.
RAM block for biquads, mixing, scaling and bass setup (continued)
Index (decimal) Index (hex) Coefficient Default
61
62
63
54
55
56
57
58
59
48
49
50
51
52
53
40
41
42
43
44
45
46
47
20
21
…
39
5
…
19
Channel 1 - Biquad 2
…
Channel 1 - Biquad 4
Channel 2 - Biquad 1
…
Channel 2 - Biquad 4
High-pass 2 nd
order filter for XO=000
Low-pass 2 nd
order filter for XO=000
Channel 1 - Pre-scale
Channel 2 - Pre-scale
Channel 1 - Post-scale
Channel 2 - Post-scale
Channel 3 - Post-scale
TWARN/OC - Limit
Channel 1 - Mix 1
Channel 1 - Mix 2
Channel 2 - Mix 1
Channel 2 - Mix 2
Channel 3 - Mix 1
Channel 3 - Mix 2
Unused
Unused
C3H3(a2)
C3H4(b0/2)
C1PreS
C2PreS
C1PstS
C2PstS
C3PstS
TWOCL
C1MX1
C1MX2
C2MX1
C2MX2
C3MX1
C3MX2
C1H20
…
C1H44
C2H10
C2H11
…
C2H44
C12H0(b1/2)
C12H1(b2)
C12H2(a1/2)
C12H3(a2)
C12H4(b0/2)
C3H0(b1/2)
C3H1(b2)
C3H2(a1/2)
0x000000
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x5A9DF7
0x7FFFFF
0x000000
0x000000
0x7FFFFF
0x400000
0x400000
0x000000
…
0x400000
0x000000
0x000000
…
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x000000
0x000000
0x000000
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Register description STA335BWQS
7.13 Variable max power correction registers (addr 0x27 to 0x28)
D7
MPCC15
0
D6
MPCC14
0
D5
MPCC13
0
D4
MPCC12
1
D3
MPCC11
1
D2
MPCC10
0
D1
MPCC9
1
D0
MPCC8
0
D7
MPCC7
1
D6
MPCC6
1
D5
MPCC5
0
D4
MPCC4
0
D3
MPCC3
0
D2
MPCC2
0
D1
MPCC1
0
D0
MPCC0
0
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.
7.14 Variable distortion compensation registers (addr 0x29 to
0x2A)
D7
DCC15
1
D6
DCC14
1
D5
DCC13
1
D4
DCC12
1
D3
DCC11
0
D2
DCC10
0
D1
DCC9
1
D0
DCC8
1
D7
DCC7
0
D6
DCC6
0
D5
DCC5
1
D4
DCC4
1
D3
DCC3
0
D2
DCC2
0
D1
DCC1
1
D0
DCC0
1
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.
7.15 Fault detect recovery constant registers (addr 0x2B to 0x2C)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
0
D4
FDRC12
0
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the
Obsolete Product(s) - Obsolete Product(s) this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 0.1 ms.
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STA335BWQS Register description
7.16 Device status register (addr 0x2D)
D7
PLLUL
D6
FAULT
D5
UVFAULT
D4
OVFAULT
D3
OCFAULT
D2
OCWARN
D1
TFAULT
D0
TWARN z z z z z z
This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
z PLLUL: 0 = PLL locked, 1= PLL not locked.
FAULT: 0 = fault detected on power bridge, 1 = normal operation
UVFAULT: 0 = VCCx internally detected < under-voltage threshold.
OVFAULT: 0 = VCCx internally detected > over-voltage threshold.
OCFAULT: 0 = over-current fault detected z
OCWARN: 0 = over-current warning.
TFAULT: 0 = thermal fault. Junction temperature over limit detection.
TWARN: 0 = thermal warning. The junction temperature is close to the fault condition.
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Application
8 Application
8.1
STA335BWQS
Application and power supplies
below shows the circuit diagram of a typical application for STA335BWQS.
Particular care has to be given to the layout of the PCB, especially the power supplies. The
3.3Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This helps to prevent unwanted oscillation on the digital portion of the device due to inductive tracks of the PCB. This same rule also applies to all the decoulpling capacitors in order to limit any kind of spikes on the supplies.
Figure 21.
Application schematic
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It is recommended to use the schematic and values in Figure 22
below for the PLL loop filter. In order to achieve the best performance from the device in general applications the filter ground (PLL_GND) must be connected as close as possible to the device pin
PLL_GND. Concerning the component values, please take into account that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter.
Component leads must be kept as short as possible
STA335BWQS Application
shows the typical output configuration used for BTL stereo mode. Please refer to the application note for other recommended output configuration schematics.
Figure 23.
Output configuration for stereo BTL mode
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Package thermal characteristics
9 Package thermal characteristics
STA335BWQS
Using a double-layer PCB the thermal resistance (junction to ambient) with 2 copper ground areas of 3 cm x 3 cm and with 16 via holes (see
Figure 24 ) is 24 °C/W in natural air
convection.
The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.
The max estimated dissipated power for the STA335BWQS is:
2 x 20 W @ 8 Ω , 18 V Pd max ~ 4 W
2 x 10 W + 1 x 20 W @ 4 Ω , 8 Ω , 18 V Pd max < 5 W
2 x 15 W @ 16 Ω , 24 V Pd max ~ 3 W
Figure 24.
Double-layer PCB with copper ground area and 16 vias
shows the power derating curves for the PowerSSO-36 package on a board with two different sizes of copper layers.
Figure 25.
PowerSSO-36 power derating curves
Pd (W)
Copper Area 3x3 cm and via holes
STA335BW
PowerSSO-36
Copper Area 2x2 cm and via holes Obsolete Product(s) - Obsolete Product(s)
80 100 120 140 160
Tamb ( °C)
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STA335BWQS Package information
shows the package outline and
gives the dimensions.
Figure 26.
PowerSSO-36 slug down outline drawing
Obsolete Product(s) - Obsolete Product(s)
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Package information STA335BWQS
Table 69.
PowerSSO-36 slug down dimensions mm
Symbol
Min Typ Max Min inch
Typ Max e3
F
G
H h k
E e c
D
A
A2 a1 b
O
Q
S
T
U
X
Y
L
M
N
-
-
-
-
8.5
2.3
-
-
-
0.5
-
-
-
-
-
-
4.30
1.20
0.80
2.90
3.65
1.00
-
-
-
-
10.10
0
2.15
2.15
0
0.18
0.23
10.10
-
7.40
-
-
-
-
-
-
-
0.60
4.10
6.50
2.47
2.40
0.10
0.36
0.32
10.50
-
7.60
-
-
0.10
10.50
0.40
8 degrees
-
-
-
-
-
-
1.00
10 degrees
4.70
7.10
0.085
0.085
0
0.007
0.009
0.398
-
0.291
-
-
-
0.398
0.024
-
-
-
-
-
-
-
0.020
-
0.335
0.091
0.169
0.047
0.031
0.114
0.144
0.039
0.097
0.094
0.004
0.014
0.013
0.413
0.299
0.004
0.413
0.016
8 degrees
0.039
10 degrees
0.161
0.256
0.185
0.280
In order to meet environmental requirements, ST offers these devices in ECOPACK
® packages. These packages have a Lead-free second level interconnect. The category of
Obsolete Product(s) - Obsolete Product(s) conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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STA335BWQS License information
Supply of this product does not convey a license under the relevant intellectual property of the companies mentioned in this chapter nor imply any right to use this intellectual property in any finished end-user or ready to use final product. An independent license for such use is required and can be obtained by contacting the company or companies concerned. Once the license is obtained, a copy must be sent to STMicroelectronics. The details of all the features requiring licenses are not provided within the datasheet and register manual. They are provided only after a copy of the license has been received by STMicroelectronics.
The feature requiring license is:
QXpander
®
, QHD
®
QHD
®
and QXpander
®
are intellectual property of QSound Labs Inc. A license can be obtained with the STA335BWQS via STMicroelectronics, please contact the HPC Audio
Division Product Manager for details.
Alternatively the license can be obtained directly from QSound Labs Inc.
For details please contact: [email protected] or
QSound Labs, Inc
400 - 3115 12th Street NE
Calgary, AB
Canada T2E 7J2
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Trademarks and other acknowledgements
12 Trademarks and other acknowledgements
STA335BWQS
DDX is a registered trademark of Apogee Technology Inc.
AutoModes is a trademark of Apogee Technology Inc
SoundTerminal is a trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
QHD and QXpander are registered trademarks of QSound Labs Inc.
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STA335BWQS Revision history
Table 70.
Document revision history
Date Revision
26-Mar-2008
15-May-2008
12-Aug-2010
1
2
3
Changes
Initial release
Updated pins 19 and 20 names (4A->4B, 4B->4A) in
Added power-off sequence,
Added
Chapter 5 on page 21 (reset, power-down, I
2
S interface description)
Updated release rate values in
Updated package information in
Removed erroneous watermark
Obsolete Product(s) - Obsolete Product(s)
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STA335BWQS
Please Read Carefully:
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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Information in this document supersedes and replaces all information previously supplied.
Obsolete Product(s) - Obsolete Product(s)
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2010 STMicroelectronics - All rights reserved
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