STMicroelectronics L99DZ100GP Datasheet
STMicroelectronics L99DZ100GP is designed to simplify the control of various electronic systems and features in automotive door zones. With its 1 half bridge for 7.5 A load, 1 configurable high-side driver for up to 1.5 A load, and a fully protected driver for external high-side MOSFETs, this device provides robust and efficient power management capabilities.
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L99DZ100G, L99DZ100GP
Automotive door module with LIN and HS-CAN (L99DZ100G) or
HS-CAN supporting selective wake up (L99DZ100GP)
Datasheet
-
production data
Features
AEC Q100 compliant qualified
1 half bridge for 7.5 A load (R
ON
= 100 m Ω )
1 half bridge for 7.5 A load (R
ON
= 150 m Ω )
2 half bridges for 0.5 A load (R
ON
= 2000 m Ω )
2 half bridges for 3 A load (R
ON
= 300 m Ω )
1 configurable high-side driver for up to 1.5 A
(R
ON load
= 500 m Ω ) or 0.35 A (R
ON
= 1600 m Ω )
1 configurable high-side driver for 0.8 A
(R
ON load
= 800 m Ω ) or 0.35 A (R
ON
= 1600 m Ω )
3 configurable high-side drivers for
0.15 A/0.35 A (R
ON
=2 Ω )
1 configurable high-side driver for 0.25 A/0.5 A
(R
ON
= 2 Ω ) to supply EC Glass MOSFET
4 configurable high-side drivers for
0.15 A/0.25 A (R
ON
= 5 Ω )
Internal 10bit PWM timer for each stand-alone high-side driver
Buffered supply for voltage regulators and 2 high-side drivers (OUT15 & OUT_HS / both
P-channel) to supply e.g. external contacts
Programmable soft-start function to drive loads with higher inrush currents as current limitation value (for OUT1-6, OUT7, OUT8 and
OUT_HS) with thermal expiration feature
All the embedded outputs come with protection and supervision features:
– Current Monitor (high-side only)
– Open-load
– Overcurrent
– Thermal warning
– Thermal shutdown
Fully protected driver for external MOSFETs in
H-bridge configuration or dual Half bridge configuration
Fully protected driver for external high-side
MOSFET
Control block for electro-chromic element
Two 5 V voltage regulators for microcontroller and peripheral supply
Programmable reset generator for power-on and undervoltage
Configurable window watchdog
LIN 2.2a compliant (SAEJ2602 compatible) transceiver
Advanced high speed CAN transceiver (ISO
11898-2:2003 /-5:2007 and SAE J2284 compliant) with local failure and bus failure diagnosis and selective wake-up functionality according to ISO 11898-6:2013
Separated (Isolated) fail-safe block with 2 LS
(R
ON
= 1 Ω ) to pull down the gates of the external HS MOSFETs
Thermal clusters
A/D conversion of supply voltages and internal temperature sensors
Embedded and programmable VS duty cycle adjustment for LED driver outputs
Applications
Door zone applications.
March 2019
This is information on a product in full production.
DS11546 Rev 5
www.st.com
L99DZ100G, L99DZ100GP
Table 1. Device summary
Package Variant
LQFP-64 epad
LQFP-64 epad
High Speed CAN Transceiver with partial networking
(ISO 11898-6:2013)
High Speed CAN Transceiver (ISO 11898-2:2003 and 11898-5:2007)
Tray
Order codes
Tape and reel
L99DZ100GP L99DZ100GPTR
L99DZ100G L99DZ100GTR
Product label
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Contents
Contents
Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LQFP64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . 38
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Gate drivers for the external Power-MOS switching times . . . . . . . . . . 45
Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . 48
Drain source monitoring external heater MOSFET . . . . . . . . . . . . . . . . 49
Open-load monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . 49
Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . 50
Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DS11546 Rev 5
7
Contents
L99DZ100G, L99DZ100GP
Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . 63
Inputs DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
S
, V
SREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SW-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Wake-up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Non-recoverable failures – forced Vbat_standby mode . . . . . . . . . . . . . 83
DS11546 Rev 5
L99DZ100G, L99DZ100GP Contents
Wake up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
High-speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
CAN transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Automatic voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Pretended networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 93
S
supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SREG
supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 97
Power outputs OUT1..15 and OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 99
PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programmable soft-start function to drive loads with higher inrush current .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . 108
H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . .111
DS11546 Rev 5
7
Contents
L99DZ100G, L99DZ100GP
Power window H-bridge safety switch off block . . . . . . . . . . . . . . . . . . . .111
Heater MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Controller of electro-chromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
S
compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . .117
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Clock and Data Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Global Status Byte GSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Control Register CR1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Control Register CR2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Control Register CR3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Control Register CR4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Control Register CR5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Control Register CR6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Control Register CR7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Control Register CR8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Control Register CR9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Control Register CR10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Control Register CR11 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Control Register CR12 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Contents
Control Register CR13 (0x0D) to CR17 (0x11) . . . . . . . . . . . . . . . . . . 167
Control Register CR18 (0x12) to CR22 (0x16) . . . . . . . . . . . . . . . . . . 168
Control Register CR23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Control Register CR24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Control Register CR25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Control Register CR26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Control Register CR27 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Control Register CR28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Control Register CR29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Control Register CR34 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Configuration Register (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . 188
Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Status Register SR12 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
LQFP-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
LQFP-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DS11546 Rev 5
7
List of tables
List of tables
L99DZ100G, L99DZ100GP
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CAN transmitter recessive output characteristics, CAN normal mode . . . . . . . . . . . . . . . . 54
CAN transmitter recessive output characteristics, CAN low-power mode, biasing active . 54
CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive 55
CAN receiver input characteristics during CAN low power mode, biasing active . . . . . . . . 55
CAN Receiver input characteristics during CAN Low power mode, biasing inactive . . . . . 56
Maximum leakage currents on CAN_H and CAN_L, unpowered . . . . . . . . . . . . . . . . . . . . 57
DS11546 Rev 5
L99DZ100G, L99DZ100GP List of tables
DS11546 Rev 5
11
List of tables L99DZ100G, L99DZ100GP
DS11546 Rev 5
L99DZ100G, L99DZ100GP List of tables
DS11546 Rev 5
11
List of figures
List of figures
L99DZ100G, L99DZ100GP
Example of long auto-recovery on OUT7. Temperature acquisition starts after t
, thermal expiration occurs after a ∆ T = 30° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Software strategy for half bridges before applying auto-recovery mode. . . . . . . . . . . . . . 104
H-bridge open-load detection (short to V
detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
< V
OUT_max
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DS11546 Rev 5
L99DZ100G, L99DZ100GP List of figures
S
compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 118
, V
S
, WU and THCL1 ..THCL6 . . . . . . . . . . . . . . . . 119
DS11546 Rev 5
13
Description
1 Description
L99DZ100G, L99DZ100GP
The L99DZ100G and L99DZ100GP are door zone systems IC providing electronic control modules with enhanced power management power supply functionality, including various standby modes, as well as LIN and HS CAN physical communication layers.
The two low-drop voltage regulators of the devices supply the system microcontroller and external peripheral loads such as sensors and provide enhanced system standby functionality with programmable local and remote wake-up capability. In addition 8 high-side drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration level.
Up to 5 DC motors and 4 external MOS transistors in H-bridge configuration can be driven.
An additional gate drive can control an external MOSFET in high-side configuration to supply a resistive load connected to GND (e.g. mirror heater). An electro-chromic mirror glass can be controlled using the integrated SPI-driven module in conjunction with an external MOS transistor. All outputs are SC protected and implement an open-load diagnosis.
The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables generic software development.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
2
Block diagram and pin descriptions
Block diagram and pin descriptions
Pin
1
2
3
4
5
6
Figure 1. Block diagram
&33 &3 96
&30
&33
&30
&KDUJH
3XPS
*+
6+
*/
[
',5+
3:0+
/6B)62
/6B)62
)DLO6DIH
[
965(*
9B
15(6(7
9B
&$16XSSO\
5['B&1,17
7['B&
&$1B+
&$1B/
5['B/1,17
7['B/
/,1
'HEXJ
1,17
:8
95(*
95(*
+6&$1
ZLWK31
/,1
[7M
&O
[7M
&O
965(*
96
%LW
$'&6$5
&61
&/.
',
'2
&0
+6
+6
+6
+6
+6
+6
+6
+6
+6
3&KDQQHO
+6
3&KDQQHO
(&*ODVV
&RQWURO%ORFN
%,763,FRQWUROOHG
*1'
6*1'
3*1'
*+
KHDWHU
6+
KHDWHU
',5
',5
(&'5
(&9
Symbol
WU
CP2M
CP2P
CP
CP1P
CP1M
*$3*&)7
Table 2. Pin definitions and functions
Function
Wake-up Input: Input pin for static or cyclic monitoring of external contacts
Charge pump pin for capacitor 2, negative side
Charge pump pin for capacitor 2, positive side
Charge pump output
Charge pump pin for capacitor 1, positive side
Charge pump pin for capacitor 1, negative side
DS11546 Rev 5
196
Block diagram and pin descriptions L99DZ100G, L99DZ100GP
13
14
15
16
Pin
7
10
11
8
9
12
17
18
19
20
21
22
23
24
Symbol
Table 2. Pin definitions and functions (continued)
Function
GHheater
SHheater
OUT14
OUT13
OUT12
OUT9
OUT10
Gate driver for external power N-Channel MOSFET in high-side configuration to control the heater
Source of high-side MOSFET to control the heater
High-side-driver output to drive LEDs
High-side-driver output to drive LEDs
High-side-driver output to drive LEDs
High-side-driver output to drive LEDs
High-side-driver-output; Important: Beside the bits OUT10_x ( CR 5 ) this output can be switched on setting the ECON bit for electro-chrome control mode with higher priority.
High-side-driver output to drive LEDs
Fail Safe low-side switch (Active low)
OUT11
LS1_FSO
LS2_FSO
VS
VS; 2nd pin
OUT7
OUT6
OUT1
Fail Safe low-side switch (Active low)
Power supply voltage for power stage outputs (external reverse battery protection required), for this input a ceramic capacitor as close as possible to GND is recommended. Important: For the capability of driving, the full current at the outputs all pins of VS must be connected externally!
Current capability (pin description see above)
High-side-driver output to drive LEDs or a 10 Watt bulb (programmable
R dson
)
Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)
Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)
OUT2
OUT5
Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)
Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to V
S from GND to output)
, low-side driver
OUT5; 2nd pin Current capability (pin description see above)
DS11546 Rev 5
L99DZ100G, L99DZ100GP Block diagram and pin descriptions
30
31
32
33
34
35
37
38
39
40
41
42
43
44
45
46
Pin
25
26
27
28
29
36
Symbol
Table 2. Pin definitions and functions (continued)
Function
V
SREG
OUT_HS
OUT3
High-side-driver output to drive LEDs or to supply contacts
OUT4
Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to V
S from GND to output)
, low-side driver
OUT4; 2 nd
pin Current capability (pin description see above)
Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to V
S from GND to output)
, low-side driver
VS; 3rd pin
OUT15
Current capability (for the pin description see above)
High-side-driver output to drive LEDs
PGND
Power supply voltage to supply the internal voltage regulators, OUT15 and the OUT_HS (external reverse battery protection required / Diode) for this input a ceramic capacitor as close as possible to GND and an electrolytic back up capacitor is recommended.
OUT8
ECDR
SGND
CM
ECV
CLK
DO
Power GND
High-side-driver output to drive LEDs or a 5 Watt bulb (programmable
R dson
)
ECDR: using the device in EC control mode this pin is used to control the gate of an external N-Channel MOSFET
Signal Ground
Current monitor output: depending on the selected multiplexer bits
CM_SEL_x ( CR 7 ) of the; Control Register this output sources an image of the instant current; through the corresponding high-side driver with a fixed ratio
ECV: using the device in EC control mode this pin is used as voltage monitor input. For fast discharge an additional low-side-switch is implemented
SPI: serial clock input
DI
CSN
TxD_L
SPI: serial data output (push pull output stage)
SPI: serial data input
SPI: chip select not input
LIN Transmit data input
RxD_L/NINT
TxD_C
RxD_C/NINT
DIR1
RxDL -> LIN receive data output; NINT -> indicates local/remote wake-up events (push pull output stage)
CAN transmit data input
CAN receive data output NINT -> indicates local/remote wake-up events
(push pull output stage)
Direct Drive Input 1
DS11546 Rev 5
196
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Block diagram and pin descriptions
Pin
47
48
49
50
L99DZ100G, L99DZ100GP
Symbol
Table 2. Pin definitions and functions (continued)
Function
PWMH
DIRH
DIR2
NRESET
5V_1
CAN Supply
NINT
CAN_L
CAN_H
Debug
LIN
5V_2
GL1
SH1
GH1
GH2
SH2
GL2
PWMH input: this input signal can be used to control the H-bridge Gate
Drivers.
Direction Input: this input controls the H-bridge Drivers for the external
MOSFETs
Direct Drive Input 2
NReset output to micro controller; (reset state = LOW) (Low-side switch with drain connected to the output pin and internal pull up resistance to
5V_1)
Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver
CAN supply input; to allow external CAN supply from V
1 or V
2 regulator
Interrupt output (low active; push-pull output stage) to indicate V
SREG early warning (Active mode); indicates wake-up events from V1_standby mode
CAN low level voltage I / O
CAN high level voltage I / O
Debug input to deactivate the window watchdog (high active)
LIN bus line
Voltage regulator 2 output: 5 V supply for external loads (potentiometer, sensors) or CAN Transceiver. V
2 is protected against reverse supply
Gate driver for PowerMOS low-side switch in half-bridge 1
Source of high-side switch in half-bridge 1
Gate driver for PowerMOS high-side switch in half-bridge 1
Gate driver for PowerMOS high-side switch in half-bridge 2
Source of high-side switch in half-bridge 2
Gate driver for PowerMOS low-side switch in half-bridge 2
DS11546 Rev 5
L99DZ100G, L99DZ100GP Block diagram and pin descriptions
Figure 2. Pin connection (top view)
:8
&30
&33
&3
&33
&30
*+KHDWHU
6+KHDWHU
287
287
287
287
287
287
/6B)62
/6B)62
',5+
3:0+
',5
5['B&1,17
7['B&
5['B/1,17
7['B/
&61
',
'2
&/.
(&9
&0
6*1'
(&'5
287
*$3*&)7
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
3.1 Absolute maximum ratings
Stressing the device above the rating listed in
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability
Symbol
V
S,
V
SREG
5V_1
Table 3. Absolute maximum ratings
Parameter / test condition Value [DC voltage] Unit
DC supply voltage / “jump start”
Load dump
Stabilized supply voltage, logic supply
-0.3 to +28
-0.3 to +40
-0.3 to 6.5
V1 < V
SREG
-0.3 to +28 (2)
V
V
V
V 5V_2 (1) Stabilized supply voltage
V
DI
, V
CLK
V
CSN
V
DO,
V
RXDL/NINT,
V
NRESET,
V
V
RXDC,
CM,
V
DIR2
, V
PWMH
V
DIRH,
V
INT
V
DIR
,
,
V
TXDC,
V
TXDL
V
Debug
Logic input / output voltage range
Multi Level Inputs
Debug input pin voltage range
V
LS1_FSO,
V
LS2_FSO
Output voltage range of Fail-Safe Low-side
Switches
DC Wake up input voltage / “jump start”
V
WU
Load dump
V
LIN
I
Input
(3)
I
OUT_INJ
V
CANSUP
V
CANH
, V
CANL
LIN bus I/O voltage range
Current injection into V
Current injection into V
CAN supply
S
S
related input pins
related outputs
CAN bus I/O voltage range
V
CANH
V
CANL
V
OUTn,
V
ECDR,
V
ECV,
V out_HS
Differential CAN-Bus Voltage
Output voltage (n = 1 to 15)
-0.3 to V1+0.3
-0.3 to 40
-0.3 to 40
-0.3 to 35
-0.3 to +28
-0.3 to +40
-20 to +40
20
20
-0.3 to +5.25
-27 to +40
-5 to +10
-0.3 to V
S
+0.3
V
V
V
V
V mA
V
V
V
V
V
V mA
V
GH1
, V
GH2
(V
Gxy
) High Voltage Signal Pins
V
GL1,
V
GL2
, (V
Gxy
) High Voltage Signal Pins
V
Sxy
-0.3 to
V
Sxy
+13; V
CP
+0.3
V
Sxy
V
Sxy
-0.3 to
+13; V
CP
-0.3V to +12V; Vcp+0.3V
V
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
V
SH1
, V
SH2
(V
Sxy
)
V
CP1P
V
CP2P
V
CP1M
, V
CP2M
V
CP
V
GH_heater
V
SH_heater
Table 3. Absolute maximum ratings (continued)
Parameter / test condition Value [DC voltage] Unit
-1 to 40 V High Voltage Signal Pins
High Voltage Signal Pins; single pulse with t max
= 200ns
High Voltage Signal Pins
High Voltage Signal Pins
High Voltage Signal Pins
High Voltage Signal Pin V
S
≤ 26 V
High Voltage Signal Pin V
S
> 26 V
-5 to 40 V
V
S
-0.3 to V
S
+14
V
S
-0.6 to V
S
+14
-0.3 to V
S
+0.3
V
S
-0.3 to V
S
+14
V
S
-0.3 to +40
V
Sheater -
V
Sheater
V
CP
0.3 to
+13;
+0.3
-0.3 to 40V
Or -0.3 to Vs+0.3
V
V
V
V
V
V
V
+/-10 mA ISH_Heater
I
I
ECV,
OUT9,
I
I
OUT2,
OUT10,
I
OUT3,
I
OUT12,
I
OUT11,
I
OUT13,
I
OUT14,
I
OUT15,
I
OUT_HS
I
OUT8
I
OUT7
I
OUT1,6
I
OUT4,5
I
VScum
Maximum cumulated current at V
S
drawn by
I
I
VScum
VScum
Maximum cumulated current at V
S
drawn by
Maximum cumulated current at V
S
drawn by
OUT4
I
I
I
I
I
VScum
VScum
VScum
VSREG
PGNDcum
Maximum cumulated current at V
S
drawn by
OUT5
Maximum cumulated current at V
S
drawn by
Maximum cumulated current at V
S
drawn by
OUT9, OUT11, OUT12, OUT13, OUT14,
OUT15 and CP
Maximum current at V
SREG and OUT_HS)
pin
(5V_1. 5V_2
Maximum cumulated current at PGND drawn
±1.25
±2.5
±5
±5
±10
±7.5
±2.5
±10
±10
±7.5
±2.5
±2.5
±7.5
A
A
A
A
A
A
A
A
A
A
A
A
A
DS11546 Rev 5
196
Electrical specifications
Note:
Note:
L99DZ100G, L99DZ100GP
Symbol
Table 3. Absolute maximum ratings (continued)
Parameter / test condition Value [DC voltage] Unit
I
I
PGNDcum
PGNDcum
I
SGND
GND pins
Maximum cumulated current at PGND drawn
Maximum cumulated current at PGND drawn by OUT3, OUT4 & ECV
Maximum current at SGND
PGND versus SGND
±12.5
±12.5
±1.25
-0.3 to 0.3
1. 5V_2 is robust against SC to 28 V only in case V
SREG
is supplied.
2. Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power dissipation or other limits.
3. Guaranteed by design.
A
A
A
V
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit!
Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current.
All pins
(1)
All power output pins
(2)
LIN
CAN_H, CAN_L
All pins
(6)
All pins
(7)
Table 4. ESD protection
Parameter
: OUT1 – OUT15, OUT_HS, ECV
Value
+/-2
+/-4
+/-8
(2)
+/-9
(3) (4)
+/-6
(5)
+/-8
+/-500
+/-750
+/- 200
Unit kV kV kV kV
1. HBM (human body model, 100 pF, 1.5 k Ω ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.
2. HBM with all none zapped pins grounded.
3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω ) and ‘Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
4. Value has been verified by an external test house; the result was equal or better than minimum requirement.
5. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω ) and ‘Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
6. Charged device model.
7. Machine model; C = 220 pF, R = 0 Ω .
V
V
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Note:
Note:
Symbol
T j
Table 5. Operating junction temperature
Parameter
Operating junction temperature
Value
-40 to 175
Unit
°C
All parameters are guaranteed in the junction temperature range -40 to 150°C (unless otherwise specified); the device is still operative and functional at higher temperatures (up to
175°C).
Parameters limits at higher junction temperatures than 150°C may change respect to what is specified as per the standard temperature range.
Device functionality at high junction temperature is guaranteed by characterization.
Symbol
Table 6. Temperature warning and thermal shutdown
Parameter
T
T
W
SD1
T
SD2
T
SD12hys
T jtft
Thermal overtemperature warning threshold T j
(1)
Thermal shutdown junction temperature 1
T
Cluster 1-4
Cluster 5-6
Thermal shutdown junction temperature 2
Thermal warning / shutdown filter time
1. Non-overlapping.
T
Hysteresis
Min. Typ.
Max.
Unit
140 150 160
165
165
175
175
185
190
175 185 195
5
32
°C
°C
°C
°C
µs
Devices belonging to L99DZxxx family embed a multitude of junctions (i.e. Outputs based on a PowerMOSFET stage) housed in a relatively small piece of silicon. The devices contain, among all the described features, 6 Half-bridges (12 N-Channel PowerMOS), 10 high-sides and two voltage regulators; all the other derivatives, even if smaller than the family super set device, still contain a significant number of junctions.
For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or major power dissipation contributor) does not allow to predict thermal behavior of the whole device and therefore it is not possible to assess if a device is thermally suitable for a given activation profile and loads characteristics.
Thermal information is provided as temperature reading by different clusters placed close to the most dissipative junctions.
Some representative and realistic worst-case thermal profiles are described in the below paragraph.
Following measurement methods can be easily implemented, by final user, for a specific activation profile.
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
L99DZ100G and L99DZ100GP thermal profiles
Profile 1
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 Ω resistor (DC activation)
OUT12: 300 Ω resistor (DC activation)
OUT13: 300 Ω resistor (DC activation)
OUT14: 300 Ω resistor (DC activation)
Cyclic activation
OUT4 – OUT5: 3,3 Ω resistor placed across those outputs
– 10 activations of Lock/Un-lock (250 ms ON Lock; 500 ms wait; 250 ms ON Unlock unlock; 500 ms wait)
OUT5 – OUT6: 10 Ω resistor placed across those outputs
– (250 ms ON Safe Lock; 500 ms wait; 250 ms ON Safe unlock; 500 ms wait)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation” sequence is applied.
Temperature reading is logged just at the end of the whole sequence.
Figure 3. Activation profile 1 ϭϰϱ ϭϯϱ ϭϮϱ ϭϭϱ ϭϬϱ ϵϱ
Ϭ ϱ dŝŵĞ;ƐͿ ϭϬ ϭϱ ůƵƐƚĞƌϮ ůƵƐƚĞƌϯ ůƵƐƚĞƌϰ ůƵƐƚĞƌϱ ůƵƐƚĞƌϲ
("1($'5
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Note:
Electrical specifications
Figure 4. Activation profile 1 (first cycle) ϭϰϱ ϭϯϱ ϭϮϱ ϭϭϱ ϭϬϱ
Ϭ
Ͳϭ
ͲϮ
Ͳϯ
Ͳϰ
Ϯ ϭ ϱ ϰ ϯ ůƵƐƚĞƌϮ ůƵƐƚĞƌϯ ůƵƐƚĞƌϰ ůƵƐƚĞƌϱ ůƵƐƚĞƌϲ
Khdͺϱ ϵϱ
Ϭ͘ϳ Ϭ͘ϵ ϭ͘ϭ ϭ͘ϯ ϭ͘ϱ dŝŵĞ;ƐͿ ϭ͘ϳ ϭ͘ϵ Ϯ͘ϭ Ϯ͘ϯ
Ͳϱ
("1($'5
All curves are plotted interpolating measured samples with 15 ms of period .
Profile 2
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 Ω resistor (DC activation)
OUT12: 300 Ω resistor (DC activation)
OUT13: 300 Ω resistor (DC activation
OUT14: 300 Ω resistor (DC activation)
Cyclic activation
OUT1 – OUT6: 6,8 Ω resistor placed across those outputs
– 2 activations of Fold/Unfold. (3s ON; 1s OFF; 2x)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation” sequence is applied.
DS11546 Rev 5
196
Electrical specifications
Note:
L99DZ100G, L99DZ100GP
Figure 5. Activation profile 2 ϭϳϬ ϭϲϬ ϭϱϬ ϭϰϬ ϭϯϬ ϭϮϬ ϭϭϬ ϭϬϬ ϵϬ
Ϭ͘ϱ ůƵƐƚĞƌϮ ůƵƐƚĞƌϯ ůƵƐƚĞƌϰ ůƵƐƚĞƌϱ ůƵƐƚĞƌϲ ϱ͘ϱ ϭϬ͘ϱ džŝƐdŝƚůĞ ϭϱ͘ϱ ϮϬ͘ϱ
("1($'5
Figure 6. Activation profile 2 (first cycle) ϭϳϬ ϭϲϬ ϭϱϬ ϭϰϬ ϭϯϬ ϭϮϬ ϭϭϬ ϭϬϬ ϵϬ
Ϭ͘ϱ Ϯ͘ϱ ϰ͘ϱ ϲ͘ϱ dŝŵĞ;ƐͿ
ϴ͘ϱ ϭϬ͘ϱ
All curves are plotted interpolating measured samples with 15 ms of period.
Ͳϭ͘ϱ
ͲϮ
ͲϮ͘ϱ
Ϭ
ͲϬ͘ϱ
Ͳϭ
Ϯ͘ϱ
Ϯ ϭ͘ϱ ϭ
Ϭ͘ϱ ůƵƐƚĞƌϮ ůƵƐƚĞƌϯ ůƵƐƚĞƌϰ ůƵƐƚĞƌϱ ůƵƐƚĞƌϲ
KhdͺϭͲϲ
("1($'5
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Figure 7. LQFP64 package and PCB thermal configuration
Note: Layout condition for Thermal Characterization (board finishing thickness 1.5 mm +/- 10%, board four layers, board dimension 77 mm x 114 mm, board material FR4, Cu thickness
0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm.
3.4.1 Supply and supply monitoring
All SPI communication, logic and oscillator parameter are working down to V
SREG and parameter are as specified in the according chapters (guaranteed by design).
= 3.5 V
SPI thresholds
Oscillator frequency (delay times correctly elapsed)
Internal register status correctly kept (reset at default values for V
SREG
< V
POR
)
Reset threshold correctly detected
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S otherwise specified.
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol
V
SUV
V hyst_UV
V
SOV
V hyst_OV
V
SREG_UV
V hyst_UV
V
SREG_OV
V hyst_OV t ovuv_filt
I
V(act)
I
V(BAT)
I
V(BAT)CS
I
V(BAT)CW
I
V(V1stby)
I
V(SW)
Table 7. Supply and supply monitoring
Parameter Test condition
V
S
undervoltage threshold
V
S
undervoltage hysteresis
V
S
increasing / decreasing
V
S
overvoltage threshold
V
S
increasing
V
S
decreasing
V
S
overvoltage hysteresis
V
SREG
undervoltage threshold
V
SREG
undervoltage hysteresis
V
SREG
increasing / decreasing
V
SREG overvoltage threshold
V
SREG
increasing
V
SREG
decreasing
V
SREG
overvoltage hysteresis
V
S
/V
SREG
over/undervoltage filter time
Current consumption in Active mode
Current consumption in
V bat
_standby mode
(1)
Current consumption in
V bat
_standby mode with cyclic sense enabled
Current consumption in
V bat
_standby mode with cyclic
Current consumption in
V
1
_standby mode
Current consumption in
V
1
_standby mode
(2)
Current consumption in
V
1
_standby mode
V
S
= V
SREG
= 12 V;
TxD CAN = high;
TxD LIN = high; V1 = ON;
V2 = ON; HS/LS Driver OFF;
CP = ON
V
S
= 12 V; Both voltage regulators deactivated; HS/LS
Driver OFF; No CAN communication; CAN automatic voltage biasing enabled
V
S
= 12 V; Both voltage regulators deactivated;
T = 50 ms, t
ON
= 100 µs
V
S
= 12 V; Both voltage regulators deactivated during standby phase
V
S
= 12 V; Voltage regulator V1 active; (I
V1
OFF
= 0); HS/LS Driver
V
S
= 12 V; Voltage regulator V1 active; (I
V1
Driver OFF
= I
CMP
); HS/LS
V
S
= 12V; Voltage regulator V1 active; (I
V1
Driver OFF
= I
PEAK
); HS/LS
Current consumption adder in standby mode if Selective
Wakeup enabled and CAN communication on the bus
TRX_BIAS mode
V
S
= 12 V
Min.
0.5
4.2
0.04
20
4.7
0.04
20
18.5
18.5
0.5
8
40
40
16
Typ.
Max.
Unit
0.1
1
0.1
1
5.4
0.2
22.5
22.5
1.5
4.9
0.2
22.5
22.5
1.5
V
V
V
V
V
V
V
V
64 µs
11
21
100
100
56
15
35
76 mA
µA
143 µA
143 µA
µA
196 µA
436 µA
1570 2000 µA
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 7. Supply and supply monitoring (continued)
Parameter Test condition Min.
Typ.
Max.
Unit
I
I
I
I qCAN qLIN
OUT_HS
OUTHS_DIR
Quiescent current adder for CAN wake up activated
Guaranteed by design
Quiescent current adder for LIN wake up activated
Guaranteed by design
Additional bias quiescent current for switched on OUT_HS or
OUT15 by DIR or Timer; value for
1 output
Guaranteed by design
Quiescent current adder if
OUT_HS and/or OUT15 are configured for Direct Drive; value during output off
Guaranteed by design
0
0
620
0
1100
5
I timer
Quiescent current adder if timer1 and/or timer 2 are active to provide interrupt on NINT upon timer expiration
Guaranteed by design 65
1. Conditions for specified current consumption:
— V
— (V
— V
LIN
> (V
CAN_H
WU
-1.5 V)
< 1 V or V
– V
CAN_L
WU
) < 0.4 V or (V
> (V
S
– 1.5 V)
CAN_H
– V
CAN_L
) > 1.2 V
2. I q
= I q0
+ 2% * I
LOAD
(see also
Figure 8: Voltage regulator V1 characteristics (quiescent current and accuracy)
110
µA
µA
µA
µA
µA
3.4.2 Oscillator
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S otherwise specified.
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Table 8. Oscillator
Symbol Parameter Test condition f
CLK1
(1) f
CLK2
Oscillation frequency OSC1
Oscillation frequency OSC2
1. OSC1: charge pump, SPI, output drivers, watchdog
OSC2: ADC, CAN-PN
Min.
1.66
30.4
Typ.
Max.
Unit
2.0
2.34
MHz
32.0
33.6
MHz
SREG
)
All outputs open; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol Parameter
Table 9. Power-on reset (V
SREG
)
Test condition Min.
V
V
POR_R
POR_F
V
V
POR
POR
threshold
threshold
V
SREG
rising
V
SREG
falling
(1)
2.45
1. This threshold is valid if V
SREG
had already reached V
POR_R(max)
previously.
Typ.
Max.
Unit
3.45
4.5
3.5
V
V
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
3.4.4 Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ V
S
≤ 28 V; 4.5 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol
V1
V1
_low_acc
V1_ hi_acc
V1_
250mA
V
DP1
I
CC1
I
CCmax1
C load1 t
TSD
I
CMP_ris
I
CMP_fal
I
CMP_hys
I
Peak_ris
(2)
I
I
Peak_hys
V
SREG_absmin
Parameter
Table 10. Voltage regulator V1
Test condition
Output voltage
V
SREG
absolute minimum value for controlling NRESET output
V
V
SREG
SREG
= 13.5V
rising/falling
Output voltage tolerance Low accuracy mode
Output voltage tolerance High accuracy mode
I
LOAD
= 0 mA to I mode) or I
LOAD
(V1stdby); V
SREG
CMP
; (Active
= 0 mA to I
PEAK
= 13.5 V
I
LOAD
= I
CMP
to 100 mA; (Active mode) or I
LOAD
= I
PEAK
100 mA (V1stdby);
to
V
SREG
= 13.5 V
Output voltage tolerance (100 to
250mA)
I
LOAD
V
= 250 mA;
SREG
= 13.5 V
Drop-out Voltage
I
LOAD
= 50 mA; V
SREG
= 5 V
I
LOAD
= 100 mA; V
SREG
= 5 V
I
LOAD
= 150 mA; V
SREG
= 5 V
Output current in Active mode
Max. continuous load current
Short circuit output current
Load capacitor1
Current limitation
Ceramic (+/- 20%)
V1 deactivation time after thermal shut-down
Current comp. rising thresh
Current comp. falling threshold
Rising current
Falling current
Current comp.
Hysteresis
Current comp. rising thresh.
Current comp. falling threshold
Current comp.
Hysteresis
Rising current
Falling current
Min.
-3
-2
-3
340
0.22
(1)
2
1.4
6
5
Typ.
5.0
0.2
0.3
0.45
600
1
4
2.8
1.2
12
10
2
Max.
Unit
V
2
3
2
3
0.4
0.5
0.6
250
900
6
4.2
18
15
V
%
%
% mA mA mA mA mA mA
V
V
V mA mA
µF sec
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 10. Voltage regulator V1 (continued)
Parameter Test condition Min.
Typ.
Max.
Unit t t t
V1
V1short t fail
V1fail
V1FS
V1off
V1 fail threshold
V1 fail filter time
V1 short filter time
V1 Fail-Safe Filter Time
V1 forced
V1 deactivation time after 8 consecutive WD failures
Tested by scan 150
2
2
4
2
200 250 ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.
2. In Active mode, V1 regulator is switched to high accuracy mode, dropping below the I low accuracy mode.
CMP
threshold regulator switches to
V
µs ms ms
Figure 8. Voltage regulator V1 characteristics (quiescent current and accuracy)
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3.4.5 Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ V
S
≤ 28 V; 4.5 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol
V2
V2
_1mA
Parameter
Output voltage
Output voltage tolerance
(0 to 1 mA)
Table 11. Voltage regulator V2
Test condition
V
SREG
= 13.5 V
I
LOAD
= 1 mA; V
SREG
= 13.5 V
Min.
-6.5
Typ.
5.0
Max.
Unit
V
6.5
%
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol Parameter
Table 11. Voltage regulator V2 (continued)
Test condition Min.
Typ.
Max.
Unit
V2
_25mA
V2_
50mA
Output voltage tolerance
(1 to 25 mA)
Output voltage tolerance
(25 to 50 mA)
I
I
LOAD
LOAD
= 25 mA; V
= 50 mA; V
SREG
SREG
= 13.5 V
= 13.5 V
-3
-4
3
4
%
%
V2_
100mA
Output voltage tolerance
(50 to 100 mA)
I
LOAD
= 100 mA; V
SREG
= 13.5 V -4 4 %
V
DP2
Drop-out voltage
I
LOAD
= 25 mA; V
SREG
= 5.25 V
I
LOAD
= 50 mA; V
SREG
= 5.25 V
I
LOAD
= 100 mA; V
SREG
= 13.5 V
0.3
0.4
1
0.4
0.8
1.6
V
V
V
I
CC2
Output current in Active mode
Max. continuous load current 50 mA
I
CCmax2
Short circuit output current
Current limitation 100 150 250 mA
C load
V2 fail t
V2fail t
V2short
Load capacitor
V2 fail threshold
V2 fail filter time
V2 short filter time
Ceramic (+/- 20%)
V2 forced
0.22 (1)
2
2
4
μ
V
µs ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.
F
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4V ≤ V
SREG
≤ 28V; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol Parameter
Table 12. Reset output
Test condition
V
RT1falling
V
V
V
V
RT2falling
RT3falling
RT4falling
V
R
RTrising
RESET
RESET
Reset threshold voltage1
Reset threshold voltage2
Reset threshold voltage3
Reset threshold voltage4
Reset threshold voltage4
V
V
V
V
V
V1
V1
V1
V1
V1
decreasing
decreasing
decreasing
decreasing
increasing
Reset Pin low output voltage
V1 > 1 V; I
RESET
= 5 mA
Reset pull up int. resistor
Min.
3.25
3.55
3.75
4.1
4.67
10
Typ.
Max.
Unit
3.5
3.8
4.0
4.3
4.8
0.2
20
3.7
4
4.2
4.5
4.87
0.4
30
V
V
V
V
V
V k Ω
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol t
RR t
UV1 t
V1R t
WDR
Parameter
Table 12. Reset output (continued)
Test condition Min.
Reset reaction time I
LOAD
= 1 mA
V1 undervoltage filter time
Reset pulse duration
(V1 undervoltage and V1 power on reset)
Reset pulse duration
(watchdog failure)
6
1.5
3
Typ.
Max.
Unit
40 µs
16 µs
2.0
4
2.5
ms
5 ms
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
4.5 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol
T
EFW3
T
LFW3
T
SW3
T
EFW4
T
LFW4
T
SW4 t
LW
T
EFW1
T
LFW1
T
SW1
T
EFW2
T
LFW2
T
SW2
Parameter
Long open window
Early Failure Window 1
Late Failure Window 1
Safe Window 1
Early Failure Window 2
Late Failure Window 2
Safe Window 2
Early Failure Window 3
Late Failure Window 3
Safe Window 3
Early Failure Window 4
Late Failure Window 4
Safe Window 4
Table 13. Watchdog timing
Test condition Min.
160
20
7.5
100
37.5
200
75
400
150
Typ.
Max.
Unit
200 240
4.5
12 ms
22.3
ms
60
45 ms ms ms ms
120
90
240 ms ms ms ms ms ms ms
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Figure 9. Watchdog timing
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DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Figure 10. Watchdog early, late and safe windows
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3.4.8 Current monitor output (CM)
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S otherwise specified
≤ 28V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Symbol
V
CM
I
CMr
Parameter
Table 14. Current monitor output (CM)
Test condition Min.
0 Functional voltage range
Current monitor output ratio:
I
CM
/I
OUT1,4,5,6 and 7
(low onresistance)
I
CM
/I
OUT8
(low on-resistance)
I
CM
/I
OUT 2,3, 7,8
(high onresistance)
I
CM
/I
OUT9,10,11,12,13,14,15 and HS
0 V ≤ V
CM
≤ (V
1
- 1 V)
Typ.
1/10000
1/6500
1/2000
1/1000
Max.
Unit
V
1
-1V V
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
I
CM acc
I
CM acc_2ol
Table 14. Current monitor output (CM) (continued)
Parameter Test condition Min.
Current monitor accuracy accI
CMOUT1,4,5,6 and 7 resistance)
(low on-
Current monitor accuracy accI
CMOUT 8
(low on-resistance)
Current monitor accuracy accI
CMOUT2,3, 9,10,11,12,13,14,15
,HS and OUT7,8
(high onresistance)
Current monitor accuracy accI
CMOUT1,4,5,6 and 7 resistance)
(low on-
Current monitor accuracy accI
CMOUT 8
(low on-resistance)
Current monitor accuracy accI
CMOUT2, 3, 9,11,12,13,14,15, HS and OUT7,8
(high on-resistance)
Current monitor accuracy accI
CMOUT10
I
I
I
0 V ≤ V
CM
OUTmin
≤ (V
1
- 1 V);
= 500 mA;
I
OUT4,5max
OUT1,6max
OUT7max
=7.4 A;
= 2.9 A;
= 1.4 A
I
0 V ≤ V
CM
OUTmin
= 100 mA;
I
OUT8max
≤ (V
1
- 1 V);
=0.9 A
0 V ≤ V
CM
≤ (V
1
- 1 V);
I
OUT.min
= 100 mA; I
OUT11,12,
15 HS
= 0.2 A; I
OUT7,8 max
= 0.3 A
I
I
I
0 V ≤ V
CM
≤ (V
1
- 1 V);
I
OUTmin
= 2 * I
OLD
OUT4,5max
OUT1,6max
OUT7max
= 1.4 A
;
= 7.4 A;
= 2.9 A;
0 V ≤ V
CM
≤ (V
1
- 1 V);
I
I
OUTmin
= 2 * I
OLD
OUT8max
= 0.9 A
;
I
0 V ≤ V
CM
≤ (V
1
- 1 V);
I
OUT.min
= 2 * I
OLD
OUT2,3max
= 0.4 A;
I
OUT9,13,14max
;
= 0.3 A;
I
I
OUT11,12,15 HS
OUT7,8 max
= 0.2 A;
= 0.3 A
0 V ≤ V
CM
≤ (V
1
- 1 V);
I
I
OUT.min
= 2 * I
OLD
OUT10max
= 0.4 A
;
Typ.
Max.
Unit
4% + 1%
FS
(1)
8% + 2%
FS
4% + 1%
FS
8% + 2%
FS
4% + 1%
FS
8% + 4%
FS
t cmb
Current monitor blanking time
1. FS (full scale) = I
OUTmax
* I
CMr
32 µs
Symbol
V
CP
I
CP
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S
≤ 28V; T j
= -40 °C to 150 °C, unless otherwise specified.
Table 15. Charge pump electrical characteristics
Parameter
Charge pump output voltage
Charge pump output current (1)
Test condition
V
S
= 6 V, I
CP
= -15 mA
V
S
≥ 10 V, I
CP
= -15 mA
V
CP
V
S
C
1
= V
S
+ 10 V;
= 13.5 V;
= C
2
= C
CP
= 100 nF
Min.
22.5
Typ.
Max.
V
S
+6 V
S
+7
V
S
+11 V
S
+12 V
S
+13.5
Unit
V
V mA
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol
Table 15. Charge pump electrical characteristics (continued)
Parameter Test condition Min.
Typ.
Max.
I
CPlim
Charge pump output current limitation
(2)
V
CP
V
S
C
1
= V
S
;
= 13.5 V;
= C
2
= C
CP
= 100 nF
70
V
CP_low
Charge pump low threshold voltage
V
S
+4.5
V
S
+5
T
CP f
CP
Charge pump low filter time
Charge Pump frequency
64
400
1. I
CP
is the minimum current the device can provide to an external circuit without V
CP
going below V
S
+ 10 V.
2. I
CPlim
is the maximum current, which flows out of the device in case of a short to V
S
.
V
S
+5.5
Unit mA
V
µs kHz
3.4.10 Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S
T j
≤ 28 V; 6 V ≤ V
= -40 °C to 150 °C, unless otherwise specified.
SREG
≤ 28 V, all outputs open;
Symbol r
ON OUT1,6 r
ON OUT2,3 r
ON OUT4 r
ON OUT5 r
ON OUT7
Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR
Parameter Test condition Min.
Typ.
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply in low resistance mode
On-resistance to supply in high resistance mode
I
V
S
= 13.5 V; T j
OUT1,6
= ±1.5A
= 25 °C;
I
V
S
= 13.5V; T
OUT1,6 j
= 130 °C
= ±1.5 A
I
V
S
= 13.5 V; T j
OUT2,3
= 25 °C;
= ±0.25 A
I
V
S
= 13.5 V; T j
= 130 °C
OUT2,3
= ±0.25 A
;
V
S
= 13.5V; T
I
OUT4
= ±3 A j
= 25 °C;
I
V
S
= 13.5 V; T j
OUT4
= ±3 A
= 130 °C ;
V
S
= 13.5 V; T
I
OUT5
= ±3 A j
= 25°C;
V
S
= 13.5 V; T
I
OUT5
= 3 A j
= 130 °C ;
V
S
= 13.5 V; T
I
OUT7
= -0.8 A j
= 25 °C;
V
S
= 13.5 V; T
I
OUT7
= -0.8 A j
= 130 °C ;
V
S
= 13.5 V; T
I
OUT7
= -0.2 A j
= 25°C;
V
S
= 13.5 V; T
I
OUT7
= -0.2 A j
= 130 °C;
300
2000
150
100
500
1600
Max.
Unit
600
4000
300
200
1000
3200 m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR (continued)
Parameter Test condition r r
ON OUT9,10,13,14 r
ON OUT11,12,15, HS r
ON OUT8
ON ECV
I
I
I
QLH
QLH
QLL
On-resistance to supply in low resistance mode
On-resistance to supply in high resistance mode
On-resistance to supply
On-resistance to supply
On-resistance to GND
Switched-off output current high-side drivers of OUT7-
15, OUT_HS
V
S
= 13.5 V; T
I
OUT8
= -0.4 A j
= 25 °C;
V
S
= 13.5 V; T
I
OUT8
= -0.4 A j
= 130 °C;
V
S
= 13.5 V; T
I
OUT8
= -0.2 A j
= 25 °C;
V
S
= 13.5 V; T
I
OUT8
= -0.2 A j
= 130 °C;
I
V
S
= 13.5 V; T j
OUT9,10,13,14
= 25 °C;
= -75 mA
I
V
S
= 13.5 V; T j
OUT9,10,13,14
= 130 °C
= -75 mA
;
V
S
= 13.5 V; T j
I
OUT11,12,15, HS
= 25 °C;
= -75 mA
V
S
= 13.5 V; T j
I
OUT11,12,15, HS
= 130 °C
= -75 mA
;
I
V
S
= 13.5 V; T j
OUTECV,ECFD
= 25 °C;
= +0.4 A
I
V
S
= 13.5 V; T j
= 130 °C
OUTECV,ECFD
= +0.4 A
;
V
OUT
= 0 V; standby mode
V
OUT
= 0 V; active mode
Switched-off output current high-side drivers of OUT1-6
Switched-off output current low-side drivers of OUT1-6
V
OUT
= 0 V; standby mode
V
OUT
= 0 V; Active mode
V
OUT
= V
S
; standby mode
V
OUT mode
= V
S
- 0.5 V; active
Switched-off output current low-side driver of ECV
V
OUT
= V
S
- 2.5 V with
ECDR = V
S
; standby mode
V
OUT
= V
S
- 2.5 V with
ECDR = V
S
; active mode
Min.
-5
-10
-5
-100
-100
-15
-10
Typ.
800
1600
2000
5
1600
2500
Max.
Unit m Ω
1600
3200
4000
10
2200
3400
165
15 m Ω m Ω m Ω m Ω m Ω
Ω
Ω m Ω
µA
µA m Ω
µA
µA
µA
µA
µA
µA
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.
≤ V
S
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Symbol t d ON H t d OFF H t d ON H t d OFF H t d ON L t d OFF L t d HL t d LH
Table 17. Power outputs switching times
Parameter Test condition Min.
Output delay time high-side driver on (OUT
1,2,3,4,5,6
)
Output delay time high-side driver on (OUT
7,8
)
Output delay time high-side driver off (OUT
1,4,5,6
)
Output delay time high-side driver off (OUT
2,3, 7,8
)
V
S
= 13.5 V; V
1
= 5 V; corresponding low-side driver is not active
(1)(2)(3)
(from CSN 50% to OUT
V = 13.5 V; V
1
= 5 V
(from CSN 50% to
OUT 50%) see
15
20
50
20
Output delay time high-side driver on (OUT9 …OUT15, OUT_HS)
Output switch off delay time highside driver on (OUT9 …OUT15,
OUT_HS)
Output delay time low-side driver
(OUT
1-6
, ECV) on
Output delay time low-side driver
(OUT
1-6
) off
Output delay time low-side driver
(ECV) off
Cross current protection time
(OUT
1-6
) dV
OUT
/dt Slew rate of OUT
1
-OUT
8
, ECV
V
S
V
1
/V
SREG
= 13.5 V;
= 5 V; (from CSN 80% to
OUT 80%)
V
S
V
1
/V
SREG
= 13.5 V;
= 5 V; (from CSN 80% to
OUT 20%)
V
S
= 13.5 V; V
1
= 5 V; corresponding high-side
(from CSN 50% to OUT
V = 13.5 V; V
1
= 5 V
(from CSN 50% to
OUT 50%) see
V = 13.5 V; V
1
= 5 V
(from CSN 50% to
OUT 50%) see
t cc ONLS_OFFHS
– t d OFF H
(4) t cc ONHS_OFFLS
– t d OFF L
V = 13.5 V; V
1
= 5 V
15
40
15
50
0.1
dVmax/dt dV
OUT f
PWMx
/dt
Maximum external applied slew rate on OUT1-OUT6 without switching on the LS and HS (only in
Active mode)
Guaranteed by design
Slew rate of OUT9-OUT15,
OUT_HS
(00) PWM switching frequency
V
S
V
1
/V
= 13.5 V;
V
S
V
1
/V
SREG
= 5 V
= 13.5 V;
20
Typ.
40
40
150
70
30
150
45
200
0.2
2
100
Max.
Unit
80
90
300
130
30
35
70
300
110
400
0.6
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
V/µs
V/µs
V/µs
Hz
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 17. Power outputs switching times (continued)
Parameter Test condition Min.
f f f
PWMx
PWMx
PWMx
(01) PWM switching frequency
(10) PWM switching frequency
(11) PWM switching frequency
V
S
V
1
/V
SREG
= 5 V
= 13.5 V;
V
S
V
1
/V
SREG
= 5 V
= 13.5 V;
V
S
V
1
/V
SREG
= 5 V
= 13.5 V;
1. R
LOAD
= 16 Ω at OUT
1,6
and OUT
7,8
in low on-resistance mode
2. R
LOAD
= 4 Ω at OUT
4,5
3. R
LOAD
= 128 Ω at OUT
2,3,4,9,10,11,12,13,15,15,HS
, ECV and OUT
7,8
in high on-resistance mode
4. t
CC
is the switch-on delay time if complement in half bridge has to switch off
Typ.
200
330
500
Max.
Unit
Hz
Hz
Hz
Symbol
|I
OC1
|,
|I
OC6
|
|I
OC2
|,
|I
OC3
|
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.
≤ V
S
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Parameter
Table 18. Current monitoring
Test condition Min.
Typ.
Max.
Unit
V
S
= 13.5 V; V1 = 5 V; sink and source
3
0.5
5
1.0
A
A
|I
OC4
|
Overcurrent threshold HS & LS
V
S
= 13.5 V; V1 = 5 V; sink and source; T j
= -40 °C to
70 °C
V
S
= 13.5 V; V1 = 5 V; sink and source; T j
= 130 °C
7.5
6
10
10
A
A
|I
OC5_1
|
|I
OC5_2
|
|I
OC5_3
|
V
S
= 13.5 V; V1 = 5 V; sink and source
3
4.5
7.5
4
6
5
7.5
10
A
A
A
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol
Table 18. Current monitoring (continued)
Parameter Test condition
|I
|I
OC7
OC8
|
|
Overcurrent threshold HS in low onresistance mode
Overcurrent threshold HS in high on-resistance mode
Overcurrent threshold HS in low onresistance mode
Overcurrent threshold HS in high on-resistance mode
|I
|I
OC9
OC13
|,
|I
OC14
|,
|
Overcurrent threshold HS in high current mode
Overcurrent threshold to HS in low current mode
Overcurrent threshold HS in high current mode
|I
OC10
|
|I
|I
OC11
|,
|I
OC12
|I
OC15
|,
|,
OC_HS
|
Overcurrent threshold HS in low current mode
Overcurrent threshold HS in high current mode
Overcurrent threshold HS in low current mode
|I
OCECV
| output current threshold LS t
FOC
Filter time of overcurrent signal
V
S
V
1
/V
SREG
= 13.5 V;
= 5 V; source
V
S
= 13.5 V; V
1
= 5 V; sink
Duration of overcurrent condition to set the status bit f f rec0 rec1
Recovery frequency for OC;
OCR_FREQ (CR 7) = 0
Recovery frequency for OC;
OCR_FREQ (CR 7) = 1 t
AR
Auto recovery time limit
OUT1 to OUT6
OUT7, OUT8, OUT_HS
|I
OLD1
|I
OLD6
|,
|
|I
OLD2
|I
OLD3
|,
|
|I
OLD4
|I
OLD5
|,
|
Under-current threshold HS & LS
V
S
= 13.5 V; V and source
1
= 5 V; sink
Min.
1.5
0.35
0.7
0.35
0.35
0.15
0.5
0.25
0.25
0.15
0.5
10
1
2
6
6
40
Typ.
55
100
120
30
20
150
0.5
0.5
0.3
1.0
100
0.65
0.7
0.3
1
Max.
Unit
2.5
A
0.65
1.3
A
A
A
A
A
A
A
A
µs
A
A
4
6
80
30
300 kHz kHz ms ms mA mA mA
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 18. Current monitoring (continued)
Parameter Test condition
|I
|I
OLD7
OLD8
|
|
Under-current threshold HS in low on-resistance mode
Under-current threshold HS in high on-resistance mode
Under-current threshold HS in low on-resistance mode
Under-current threshold HS in high on-resistance mode
|I
I
OLD9
OLD13
|,
|I
OLD14
|,
|
Under-current threshold HS in high current mode
Under-current threshold HS in low current mode
V
V
S
1
/V
SREG
= 13.5 V;
= 5 V; source
Under -current threshold HS in high current mode
|I
OLD10
|
|I
|I
|I
OLD12
|I
OLD11
|,
OLD15
|,
|,
OLD_HS
|
Under -current threshold HS in low current mode
Under -current threshold HS in high current mode
Under -current threshold HS in low current mode
|I
OLDECV
| Under-current threshold LS t
OL_out
Filter time of open-load signal
V
S
= 13.5 V; V
1
= 5 V; sink
Duration of open-load condition to set the status bit
Min.
15
5
10
5
6
0.5
10
0.3
6
0.85
6
150
Typ.
40
10
30
10
20
200
4
12
4
30
250
4
30
15
12
Max.
Unit
60 mA
15
45 mA mA mA mA mA mA mA mA mA mA
µs
3.4.13 Heater
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S
≤ 28 V; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol
I
GHheater
R
GLheater
Parameter
Average charge-current
(charge stage)
On-resistance (dischargestage)
Table 19. Heater
Test condition
T j
= 25 °C
V
SLx
T j
= 0 V; I
= 25 °C
GHx
= 50 mA;
V
SLx
T j
= 0 V; I
= 130 °C
GHx
= 50 mA;
V
S
= SH= 6 V; I
CP
= 15 mA
V
GHheater
Gate-on voltage
V
S
= SH = 12 V; I
CP
= 15 mA
Min.
4
Typ.
0.3
8
11
Max.
Unit
10
14
V
SHheater
6
+
V
SHeahter
8
+ V
SHeater
+ 10
V
SHeater
+ 11.5
A
Ω
Ω
V
V
DS11546 Rev 5
196
Electrical specifications
T
T
Symbol
R
GSHeater
G(HL)xHL
G(HL)xLH t0
GHheaterr t0
GHheaterf
Parameter
Table 19. Heater (continued)
Test condition
Passive gate-clamp resistance
Propagation delay time high to low (switch mode)
Propagation delay time low to high (switch mode)
Rise time (switch mode)
Fall time (switch mode)
V
S
R
G
= 13.5 V; V
SHx
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
SLx
R
G
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
Sheater
R
G
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
Sheater
R
G
= 0 Ω ; C
G
= 0;
= 2.7 nF
Min.
L99DZ100G, L99DZ100GP
Typ.
15
1.5
1.5
45
85
Max.
Unit k Ω
µs
µs ns ns
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S otherwise specified.
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40°C to 150 °C, unless
Symbol
I
GHx(Ch)
R
GHx
V
GHHx
R
GSHx
I
GLx(Ch)
R
GLx
V
GHLx
R
GSLx
Parameter
Table 20. H-bridge driver
Test condition Min.
Drivers for external high-side PowerMOS
Typ.
Max.
Unit
Average charge current
(charge stage)
T j
= 25 °C 0.3
A
On-resistance (dischargestage)
Gate-on voltage
V
SHx
T j
= 0 V; I
= 25 °C
GHx
= 50 mA;
V
SHx
T j
= 0 V; I
= 130 °C
GHx
= 50 mA;
6 10
14
14
20
Ω
Ω
V
S
= SH = 6 V; I
CP
= 15 mA V
SHx
+ 6 V
V
S
= SH = 12 V; I
CP
= 15 mA V
SHx
+ 8 V
SHx
+ 10 V
SHx
+ 11.5
V
Passive gate-clamp resistance
V
GHx
= 0.5 V 15 k Ω
Average charge-current
(charge stage)
Drivers for external low-side Power-MOS
T j
= 25 °C
On-resistance (dischargestage)
Gate-on voltage
V
SLx
T j
= 0 V; I
= 25 °C
GHx
= 50 mA;
V
SLx
T j
= 0 V; I
= 130 °C
GHx
= 50 mA;
V
S
= 6 V; I
CP
= 15 mA
V
S
= 12 V; I
CP
= 15 mA
V
6
SLx
+ 6
0.3
10
14
14
20
A
Ω
Ω
V
V
SLx
+ 8 V
SLx
+ 10 V
SLx
+ 11.5
V
Passive gate-clamp resistance
15 k Ω
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
3.4.15 Gate drivers for the external Power-MOS switching times
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.
≤ V
S
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Symbol
Table 21. Gate drivers for the external Power-MOS switching times
Parameter
T
G(HL)xHL
T
G(HL)xLH
Propagation delay time high to low
(switch mode
(1)
Propagation delay time low to high
I
GHxrmax
I
GHxfmax dI
IGHxr dI
IGHxf
Maximum source current (current mode)
Maximum sink current (current mode)
Source current accuracy
Sink current accuracy
Test condition
V
S
R
G
= 13.5 V; V
SHx
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
SLx
R
G
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
SHx
V
GHx
= 1 V;
= 0;
SLEW<4:0> = 1 F
H
V
S
= 13.5 V, V
SHx
= 2 V;
= 0;
V
GHx
SLEW<4:0> = 1 F
H
V
S
V
= 13.5 V; V
SHx
GHx
= 1 V
= 0;
V
S
V
= 13.5 V; V
SHx
GHx
= 2 V
= 0;
Min.
Typ.
1.5
1.5
32
32
Max.
Unit
See
µs
µs mA mA
V
DSHxrSW
Switching voltage (V
S
-V
SH
) between current mode and switch mode (rising)
V
DSHxfSW
Switching voltage (V
S
-V
SH
) between switch mode and current mode (falling)
V
S
= 13.5 V
V
S
= 13.5 V
2.8
2.8
V
V t0
GHxr t0
GHxf t0
GLxr t0
GLxf
Rise time (switch mode)
Fall time (switch mode)
Rise time
Fall time
V
S
R
G
= 13.5 V; V
SHx
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
R
G
= 13.5 V; V
SHx
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
SLx
R
G
= 0 Ω ; C
G
= 0;
= 2.7 nF
V
S
= 13.5 V; V
SLx
R
G
= 0 Ω ; C
G
= 0;
= 2.7 nF
45
85
45
85 ns ns ns ns tccp
0001 tccp
0010 tccp
0011 tccp
0100 tccp
0101
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
500
750
1000
1250
1500 ns ns ns ns ns
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol
Table 21. Gate drivers for the external Power-MOS switching times (continued)
Parameter Test condition Min.
Typ.
Max.
Unit tccp
0110 tccp
0111 tccp
1000 tccp
1001 tccp
1010 tccp
1011 tccp
1100 tccp
1101 tccp
1110 tccp
1111
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
Programmable cross-current protection time
1750
2000
2250
2500
2750
3000
3250
3500
3750
4000 ns ns ns ns ns ns ns ns ns ns f
PWMH
V
S
R
G
= 13.5 V; V
SLx
= 0 Ω ; C
G
= 0;
= 2.7 nF;
PWMH-Duty-Cycle = 50%
50 kHz
1. Without cross-current protection time t
CCP
.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
9
&613:0+',5
9
&613:0+',5
Electrical specifications
Figure 11. H-driver delay times
7
*+/[/+
7
*+/[+/
W
W
9
*6+/[
W
*$3*&)7
Figure 12. IGHxr ranges
,*+[U DFFXUDF\
,*+[U0D[
,*+[U7\S
,*+[U0LQ
'DWDLQSXW
("1($'5
DS11546 Rev 5
196
Electrical specifications
Figure 13. IGHxf ranges
,*+[I DFFXUDF\
L99DZ100G, L99DZ100GP
,*+[I0D[
,*+[I7\S
,*+[I0LQ
'DWDLQSXW
("1($'5
3.4.16 Drain source monitoring external H-bridge
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S otherwise specified.
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40°C to 150 °C, unless
Symbol
V
SCd1_HB
V
SCd2_HB
V
SCd3_HB
V
SCd4_HB
V
SCd5_HB
V
SCd6_HB
V
SCd7_HB t
SCd_HB t scs_HB
Table 22. Drain source monitoring external H-bridge
Parameter Test condition Min.
Typ.
Max.
Unit
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source monitor filter time
Drain-source comparator settling time
V
S
= 13.5 V;
V
SH
= jump from GND to V
S
0.375
0.6
0,85
1,06
1,27
1,49
1,7
0,5 0.625
V
0,75 0.9
V
1 1,15 V
1,25
1,5
1,75
2
6
1,43
1,73
2,01
2,3 V
µs
V
V
V
5 µs
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
3.4.17 Drain source monitoring external heater MOSFET
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.
≤ V
S
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Symbol
V
SCd1_HE
V
SCd2_HE
V
SCd3_HE
V
SCd4_HE
V
SCd5_HE
V
SCd6_HE
V
SCd7_HE
V
SCd8_HE t
SCd_HE t scs_HE t scbl_HE
Table 23. Drain source monitoring external heater MOSFET
Parameter Test condition Min.
Typ.
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source threshold voltage
Drain-source monitor filter time
Drain-source comparator settling time
Drain-source monitoring blanking time
V
S
= 13.5 V; V from GND to V
SH
= jump
S
160
200
240
280
320
360
400
440
200
250
300
350
400
450
500
550
6
8
Max.
Unit
250
305
360
420
480
540
600
660 mV mV mV mV mV mV mV mV
µs
5 µs
µs
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.
≤ V
S
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Symbol
V
ODSL
V
ODSH
V
OLSHx
R pdOL t
OL_HB
Table 24. Open-load monitoring external H-bridge
Parameter Test condition Min.
Low-side drain-source monitor low off-threshold voltage
Low-side drain-source monitor high off-threshold voltage
Output voltage of selected SHx in open-load test mode
Pull-down resistance of the nonselected SHx pin in open-load mode
Open-load filter time
V
SLx
= 0 V; V
S
= 13.5 V
V
SLx
= 0 V; V
S
= 13.5 V
V
SLx
= 0 V; V
S
= 13.5 V
V
SLx
= 0 V; V
V
SHX
= 4.5 V
S
= 13.5 V;
Typ.
0.15 V
S
0.85 V
S
0.5 V
S
20
2
Max.
Unit
V
V
V k Ω ms
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.
≤ V
S
≤ 28 V; 6 V ≤ V
SREG
≤ 28 V; T j
= -40 °C to 150 °C, unless
Symbol
V
OLheater
I
OLheater t
OL_HE
Table 25. Open-load monitoring external heater MOSFET
Parameter Test condition Min.
Typ.
Open-load -threshold voltage
Pull-up current source open-load diagnosis activated
Open-load filter time
V
SLx
= 0 V; V
S
= 13.5 V
V
SLx
V
= 0 V; V
S
SHheater
= 13.5 V;
= 4.5 V
2
1
2
Max.
Unit
V mA ms
3.4.20 Electro-chrome mirror driver
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V ≤ V
S otherwise specified.
≤ 28V; 6V ≤ V
SREG
≤ 28V; T j
= -40 °C to 150 °C, unless
Table 26. Electro-chrome mirror driver
Symbol Parameter Min.
ECV_HV (Config Reg) = 1
(1)
1.4
V
CTRLmax
Maximum EC-control voltage
ECV_HV (Config Reg) = 0
1.12
Typ.
Max.
1.6
Unit
V
DNL
IdV dV dV
ECV
ECV
I
ECVnr
ECVhi t
FECVNR t
FECVHI
Differential Non Linearity
Voltage deviation between target and ECV
Difference voltage between target and ECV sets flag if
V
ECV
is below it
Difference voltage between target and ECV sets flag if
V
ECV
is above it
ECV
ECV
NR
HI
filter time
filter time
V
ECDRminHIGH
Output voltage range
V
ECDRmaxLOW
I
I dV
ECV
II
ECDR
= V target
(3)
I < 1 µA
- V
ECV
; dV
ECV
= V target
- V
ECV
; toggle bitx = 1; status reg. x dV
ECV
= V target
- V
ECV
; toggle bitx = 1; status reg. x
ECDR
ECDR
= -10 µA
= 10 µA
-2
-5% -
V1 -
0.3 V
0
120
-180
32
32
1.28
2
+5% +
1LSB
V
LSB
(2) mV
V1
0.7
mV mV
µs
µs
V
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Table 26. Electro-chrome mirror driver (continued)
Symbol Parameter Min.
I
ECDR
Current into ECDR
V
V
ECDR
> V
ECV
= 3.5 V
+ 500 mV;
V
< V
ECV
V
ECDR
V
ECV
= 0.5 V
- 500 mV;
= 1.0 V; V target
= 0 V;
-100
10
R ecdrdis
Pull-down resistance at
ECDR in fast discharge mode and while EC-mode is off
V
ECDR
= 0.7 V; ECON = ‘1’,
EC<5:0> = 0 or ECON = ‘0’
1. Bit ECV_HV (Config Reg) ='1' or ‘0’: ECV voltage, where II
ECDR
can change sign.
2. 1 LSB (Least Significant Bit) = 23.8 mV typ
3. V target
is set by bits EC<5:0> (CR 11) and bit ECV_HV (Config Reg); tested for each individual bit.
Typ.
Max.
-10
Unit
µA
100
10
µA k Ω
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
S
≤ 18 V; T j
= 40 °C to 150 °C, unless otherwise specified.
Symbol
V
OUT_max
R t
I t
DSON
OLimit
ONHL
OFFLH dV t
SCF max
/dt
Parameter
Table 27. Fail safe low-side switch
Test condition
Max output voltage in case of missing supply
I
OUT
= 1 mA; V
S
= V
SREG
= 0 V
DC output resistance
Overcurrent limitation
I
LOAD
= 250 mA; T j
= 25 °C
I
LOAD
= 250 mA; T j
= 130 °C
8 V < V
S
< 16 V
Turn on delay time to
10% V
OUT
Turn off delay time to
90% V
OUT
Short circuit filter time
Maximum external applied slew rate on
LS1_FSO and LS2_FSO without switching on LS
Guaranteed by design
Min.
500
60
Typ.
2
1.4
64
Max.
Unit
2.5
2.2
1500
100
100
V
Ω
Ω mA
µs
µs
µs
V/µs
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
3.4.22 Wake up input WU
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
SREG
≤ 28 V; T j
= 40 °C to 150 °C, unless otherwise specified.
Symbol
Table 28. Wake-up inputs
Test condition
V
WUthn
V
WUthp
V
HYST t
WU_stat
I
WU_stdby
R
WU_act t
WU_cyc
Parameter
Wake-up negative edge threshold voltage
Wake-up positive edge threshold voltage
Hysteresis
Static wake filter time
Input current in standby mode
Input resistor to GND in Active mode and in
Standby mode during
Wake-up input sensing
Cyclic wake filter time
V
WU
V
WU
< 1 V or
> (V
SREG
– 1.5 V)
Min.
0.4
V
SREG
0.5
V
SREG
0.05
V
SREG
5
80
Typ.
0.45
V
SREG
0.55
V
SREG
0.1
V
SREG
64
30
160
16
Max.
Unit
0.5
V
SREG
0.6
V
SREG
0.15
V
SREG
V
V
V
µs
60
300
μ A k Ω
µs
ISO 11898-2:2003 and ISO 11898-5:2007 compliant.
SAE J2284 compliant.
Selective wake functionality according to ISO 11898-6:2013.
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin.
5.5 V ≤ V
SREG
≤ 18 V; V specified. -12 V ≤ (V
CANH
CANSUP
= V1; T
+ V
CANL junction
=
) / 2 ≤ 12 V
-40 °C to 150 °C, unless otherwise
Symbol
V
SREG_COM
V
CANSUPlow
V
CANHL,CM
Table 29. CAN communication operating range
Parameter Test condition Min.
Supply voltage operating range for CAN communication
V
V1
= V
CANSUP
CAN supply low voltage flag V
V1
= V
CANSUP decreasing
Common mode Bus voltage
Measured with respect to the ground of each CAN node
5.5
4.5
-12
Typ.
4.65
Max.
Unit
18
4.8
12
V
V
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 30. CAN transmit data input: pin TxDC
Parameter Test condition
V
V
TXDCLOW
TXDCHIGH
Input voltage dominant level
Input voltage recessive level
V
TXDCHYS
R
TXDCPU t d,TXDC(dom-rec) t d,TXDC(rec-diff)
V
TXDCHIGH
-V
TXDCLOW
TXDC pull up resistor
TXDC - CAN
H,L time dominant - delay recessive
TXDC - CAN
H,L time recessive - delay dominant t dom(TXDC)
TXDC dominant time-out
1. Guaranteed by design.
R
L
= 60 Ω ; C
V
RXD
L
– 30% V
= 100 pF; 70 %
DIFF
; TXDC rise time = 10 ns (10% - 90%)
(1)
R
L
= 60 Ω ; C
V
RXD
L
– 70% V
= 100 pF; 30 %
DIFF
; TXDC fall time = 10 ns (90% - 10%)
Min.
1.0
1.2
0.2
16
0
0
0.8
Typ.
1.45
1.85
0.4
35
Max.
Unit
2.0
V
2.3
0.7
60
120
V
V k Ω ns
2
120
5 ns ms
Symbol
Table 31. CAN receive data output: Pin RxDC
Parameter Test condition t t
V
V
RXDCLOW
RXDCHIGH t t r,RXDC f,RXDC d,RXDC(dom-rec) d,RXDC(rec - dom)
Output voltage dominant level I
RXDC
= 2 mA
Output voltage recessive level
I
RXDC
= -2 mA
RXDC rise time
RXDC fall time
CAN dominant - recessive
CAN
H,L
H,L
– RXDC delay time
– RXDC delay time recessive - dominant
C
L
= 15 pF;
30% - 70% V
RXDC
(1)
C
L
= 15 pF;
70% - 30% V
C
L
= 15 pF;
30% V
DIFF
– 70% V
C
L
= 15 pF;
70% V
DIFF
– 30% V
1. Guaranteed by design.
Min.
0
Typ.
0.2
Max.
0.5
V1 - 0.5 V1 - 0.2
V1
0
0
0
0
25
25
120
120
Unit
V
V ns ns ns ns
Symbol
V
CANHdom
V
CANLdom
V
DIFF,dom
Table 32. CAN transmitter dominant output characteristics
Parameter Test condition Min.
Single ended CANH voltage level in dominant state
Single ended CANL voltage level in dominant state
Differential output voltage in dominant state: V
CANHdom
-
V
CANLdom
V
TXDC
65 Ω
= V
TXDCLOW
; R
L
= 50 Ω ;
V
TXDC
R
L
= V
TXDCLOW
= 50 Ω ; 65 Ω
;
V
R
TXDC
L
= V
TXDCLOW
= 50 Ω ; 65 Ω
;
2.75
0.5
1.5
Typ.
Max. Unit
3.5
1.5
2.0
4.5
2.25
V
3
V
V
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol
V
SYM
Table 32. CAN transmitter dominant output characteristics (continued)
Parameter Test condition Min.
Typ.
Max. Unit
I
OCANH,dom (0V)
I
OCANL,dom (5V)
Driver symmetry
V
SYM
= V
V
CANLdom
CANHdom
+
CANH output current in dominant state
CANL output current in dominant state
Measured over one 250 kHz period (4 µs) R f
TXDC
L
= 50 Ω ; 65 Ω ;
= 250 kHz (square wave,
50% duty cycle);
(1)
C
SPLIT
= 4.7 nF (+-5%)
V
TXDC
V
CANH
= V
TXDCLOW
= 0 V
;
V
TXDC
= V
TXDCLOW
; V
CANL
= 5 V
4.5
-100
45
5
-75
75
5.5
V
-45 mA
100 mA
I
OCANH,dom (40V)
CANH output current in dominant state
I
OCANL,dom (40V)
CANL output current in dominant state
V
TXDC
V
CANH
V
S
= V
= 40 V
TXDCLOW
= 40 V; R
L
;
= 65 Ω ;
V
TXDC
V
CANL
R
L
= V
TXDCLOW
;
= 40 V;
= 65 Ω ; V
S
= 40 V
0
0
5 mA
100 mA
1. Measurement equipment input load <20 pF, >1 M Ω .
Table 33. CAN transmitter recessive output characteristics, CAN normal mode
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
V
CANHrec
V
CANLrec
V
DIFF,recOUT
CANH voltage level in recessive state
CANL voltage level in recessive state
TRX ready state;
V
TXDC
= V
TXDCHIGH
; No load
TRX Ready state;
V
TXDC
= V
TXDCHiGH
; No load
Differential output voltage in recessive state
V
CANHrec
-V
CANLrec
TRX Ready state;
V
TXDC
= V
TXDCHIGH
; No load
2
2
-50
2.5
2.5
3
3
50
V
V mV
Note: CAN normal mode: tested in TRX ready state while the device is in active mode.
Table 34. CAN transmitter recessive output characteristics, CAN low-power mode, biasing active
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
V
V
CANHrecLPbias
CANLrecLPbias
V
DIFF,recOUTLPbias
CANH voltage level in recessive state
CANL voltage level in recessive state
TRX BIAS state;
V
TXDC
= V
TXDCHIGH
; No load
TRX BIAS state;
V
TXDC
= V
TXDCHiGH
; No load
Differential output voltage in recessive state
V
CANHrec
-V
CANLrec
TRX BIAS state;
V
TXDC
= V
TXDCHIGH
; No load
2
2
-50
2.5
2.5
3
3
50
V
V mV
Note: CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active mode, V1 Standby mode and Vbat_standby mode
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Table 35. CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
V
CANHrecLP
V
CANLrecLP
V
DIFF,recOUTLP
CANH voltage level in recessive state
CANL voltage level in recessive state
TRX Sleep state;
V
TXDC
= V
TXDCHIGH
; No load
TRX Sleep state;
V
TXDC
= V
TXDCHIGH
; No load
Differential output voltage in recessive state
V
CANHrec
-V
CANLrec
TRX Sleep state;
V
TXDC
= V
TXDCHIGH
; No load
-0.1
-0.1
-50
0
0
0.1
0.1
50
V
V mV
Note: CAN Low Power mode, biasing inactive: tested in TRX sleep state while the device is in active mode, V1 Standby mode and Vbat_standby mode.
Symbol
Table 36. CAN receiver input characteristics during CAN normal mode
Parameter Test condition
V
V
THdom
THrec
Differential receiver threshold voltage recessive to dominant state
Differential receiver threshold voltage dominant to recessive state
TRX ready state;
(V
CANH
+ V
2.5 V, 12 V
) / 2 = -12 V,
TRX Ready state;
(V
CANH
+ V
2.5 V, 12 V
) / 2 = -12 V,
1. Parameter evaluated with specific R
L
= 60 Ω ; guaranteed by characterization.
Min.
0.5
0.5
Typ.
—
—
Max.
Unit
0.9
0.9
V
V
Note: CAN normal mode: tested in TRX ready state while the device is in active mode.
Table 37. CAN receiver input characteristics during CAN low power mode, biasing active
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
V
V
THdomLPbias
THrecLPbias
Differential receiver threshold voltage recessive to dominant state
TRX BIAS state;
(V
CANH
+ V
2.5 V, 12 V
) / 2 = -12 V,
Differential receiver threshold voltage dominant to recessive state
TRX BIAS state;
(V
CANH
+ V
) / 2 = -12 V,
1. Parameter evaluated with specific R
L
= 60 Ω ; guaranteed by characterization.
0.5
0.5
—
—
0.9
0.9
V
V
Note: CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active mode, V1 Standby mode and Vbat_standby mode.
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Table 38. CAN Receiver input characteristics during CAN Low power mode, biasing inactive
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
V
V
THdomLP
THrecLP
Differential receiver threshold voltage recessive to dominant state
Differential receiver threshold voltage dominant to recessive state
TRX sleep state;
(V
CANH
+ V
CANL
) / 2 = -12 V; 0 V; 12 V
(1)
TRX Sleep state;
(V
CANH
+ V
CANL
) / 2 = -12 V; 0 V; 12 V
1. Parameter evaluated with specific R
L
= 60 Ω ; guaranteed by characterization.
0.5
0.5
—
—
0.9
0.9
V
V
Note: CAN Low Power mode, biasing inactive: Tested in TRX Sleep state while the device is in active mode, V1 Standby mode and Vbat_standby mode.
Symbol
R diff
R
CANH, CANL m
R
C in
C in,diff
Table 39. CAN receiver input resistance biasing active
Parameter Test condition Min.
Typ.
Max.
Unit
Differential internal resistance
Single ended Internal resistance
TRX Ready & TRX BIAS states;
V
TXDC
= V
TXDCHIGH
; no load
TRX Ready & TRX BIAS states;
V
TXDC
= V
TXDCHIGH
; no load
Internal Resistance matching R
CANH,CANL
TRX Ready & TRX BIAS states;
V
TXDC
= V
TXDCHIGH m
(R
R
= 2 x (R
CAN_H
CAN_H
+ R
CAN_L
)
; no load;
- R
CAN_L
) /
Internal capacitance Guaranteed by design
Differential internal capacitance
Guaranteed by design
40
20
-0.03
60
30
20
10
100
50
0.03
35
20 k Ω k Ω pF pF
Note: CAN Normal and Low Power mode, biasing active: Tested in TRX Ready and TRX BIAS state while the device is in active and V1 Standby mode.
Symbol t
TXpd,hl t
TXpd,lh
Parameter
Loop delay TXDC to
RXDC (High to Low)
Loop delay TXDC to
RXDC (Low to High)
Table 40. CAN transceiver delay
Test condition
R
L
= 60 Ω ; C
L
30% V
TXDC
= 100 pF;
– 30% V
RXDC
;
TXDC fall time = 10 ns (90% - 10%);
C
RXDC
= 15 pF; f
TXDC
= 250 kHz
R
L
= 60 Ω ; C
L
70% V
TXD
= 100pF;
– 70% V
RXD
;
TXDC rise time = 10 ns (10% - 90%);
C
RXDC
= 15 pF; f
TXDC
= 250 kHz
Min.
Typ.
Max.
Unit
255
255 ns ns
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Symbol Parameter
Table 40. CAN transceiver delay (continued)
Test condition Min.
T
Bitrec
Recessive Bit symmetry
R
L
= 60 Ω ; C
70% V
TXDC
(falling); C
L
= 100 pF;
(rising) - 30% V
RXDC
RXD
= 15 pF; 10 ns (10% -
90%, 90% - 10%); Rectangular pulse signal T
TXDC
= 6000 ns, high pulse
1000 ns, low pulse 5000 ns t t t
CAN
WUP-V1
(1)
WUF-V1
CAN permanent dominant time-out
Time between WUP
(2) on the CAN bus until
V1 goes active
Time between WUF
(3) on the CAN bus until
V1 goes active
Wake-Up according to ISO11898-
5:2007 (Bit SWEN = 0);
70% V
DIFF
– 90% V1(min)
Wake-Up according to ISO11898-
6:2013 (Bit SWEN = 1);
30% V
DIFF
– 90% V1(min)
1. Guaranteed by characterization.
2. Time starts with the end of last dominant phase of the WUP.
3. Time starts with the end of CRC delimiter of the WUF.
765
500
0
0
Electrical specifications
Typ.
Max.
Unit
1000 1255 ns
700 1000 μ s
200
200
µs
µs
Symbol
Table 41. Maximum leakage currents on CAN_H and CAN_L, unpowered
Parameter Test condition Min.
Typ.
Max.
Unit
I
I
Leakage, CANH
Leakage, CANL
Input leakage current
CANH
Input leakage current
CANL
Unpowered device; V
CANH
= 5 V;
V
CANL
= 5 V; V
SREG,
V
CANSUP via 0 Ω to GND; V
SREG
, V connected via 47 k Ω to GND
connected
T j
= -40 °C to 105 °C
(2)
T j
= 130 °C
(3)
Unpowered device; V
CANH
= 5 V;
V
CANL via 0 Ω
= 5 V; V
SREG,
V
CANSUP
connected
to GND; V via 47 k Ω to GND
V
CANSUP
connected
T j
T j
-10
-12
-10
-12
10
12
10
12
1. Guaranteed by design.
2. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range
3. Used for device test only.
μ A
μ A
Symbol t filter t wake
Parameter
CAN activity filter time
Wake-up time out
Table 42. Biasing control timings
Test condition Min.
0.5
0.5
Typ.
1
Max.
Unit
5
5
μ s ms
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol Parameter
Table 42. Biasing control timings (continued)
Test condition Min.
Typ.
Max.
Unit t
Silence
CAN timeout 600 700 1200 ms t
BIAS
Bias reaction time
R
L
= 50 Ω , 65 Ω ; C
L
= 100 pF; C
) = 100 pF;
;
GND
(= C
SPLIT
V
TXDC
50% V
DIFF
- V
CANH
V
CANL
= V
TXDCLOW
=
= V
CAN(H,L)rec(min)
(1)
;
Transition TRX Sleep to TRX BIAS in
Active, V1-Standby and Vbat_standby modes
0 200 µs
1. A wake-up-pattern is sent with a bit length of t the end of the 2 filter
. T
BIAS
is measured from the rising edge after having released the bus at
dominant bit until CANH and CANL reach the minimum recessive output voltage (V
CANHrec
, V
CANHrec
).
LIN 2.2 compliant for bit-rates up to 20 kBit/s SAE J2602 compatible.
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V specified.
≤ V
SREG
≤ 18 V; T junction
= -40 °C to 150°C unless otherwise
Symbol
V
TXDLOW
V
TXDHIGH
V
TXDHYS
R
TXDPU
Table 43. LIN transmit data input: pin TxD
Parameter Test condition Min.
Input voltage dominant level
Input voltage recessive level
V
TXDHIGH
-V
TXDLOW
TXD pull up resistor
Active mode
Active mode
Active mode
1.0
0.2
13
Typ.
Max.
Unit
29
2.3
46
V
V
V k Ω
Symbol
V
RXDLOW
V
RXDHIGH
Table 44. LIN receive data output: pin RxD
Parameter Test condition Min.
Output voltage dominant level Active mode
Output voltage recessive level Active mode V1-0.5
Typ.
0.2
V1-0.2
Max.
Unit
0.5
V
V
Symbol
V
THdom
V
Busdom
Table 45. LIN transmitter and receiver: pin LIN
Parameter Test condition Min.
Receiver threshold voltage recessive to dominant state
0.4
V
SREG
Receiver dominant state
V
THrec
V
Busrec
Receiver threshold voltage dominant to recessive state
Receiver recessive state
0.5
V
SREG
0.6
V
SREG
Typ.
0.45
V
SREG
0.55
V
SREG
Max.
Unit
0.5
V
SREG
0.4V
SRE
G
0.6
V
SREG
V
V
V
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 45. LIN transmitter and receiver: pin LIN (continued)
Parameter Test condition Min.
Typ.
Max.
Unit
V
V
V t
V
THhys
THcnt
THwkup
THwkdwn
LINBUS
Receiver threshold hysteresis: V
THrec
-V
THdom
Receiver tolerance center value: (V
THrec
+V
THdom
)/2
Activation threshold for wake-up comparator
Activation threshold for wake-up comparator
LIN Bus Wake-up Dominant
Filter time
Sleep mode; edge: rec-dom
V
0.475
V
V
0.07
SREG
SREG
1.0
SREG
3.5
-
V
V
V
0.1
SREG
0.5
SREG
1.5
SREG
2.5
64
V
0.175
V
SREG
0.525
V
SREG
2
SREG
1.5
-
V
V
V
V
μ s t dom_LIN
LIN Bus Wake-up Dominant
Filter time
Sleep mode; edge: rec-domrec
28 μ s
I
I
I
I
LINDomSC bus_PAS_dom bus_PAS_rec bus_NO_GND
V
I bus
LINdom
Transmitter input current limit in dominant state
Input leakage current at the receiver incl. pull-up resistor
Transmitter input current in recessive state
Input current if loss of GND at device
Input current if loss of V at device
BAT
V
TXD
= V
TXDLOW
V
LIN
= V
BATMAX
;
= 18 V
V
TXD
V
BAT
= V
TXDHIGH
; V
LIN
= 0 V;
= 12 V; Slave mode
In standby modes;
V
TXD
V
BAT
= V
TXDHIGH
; V
LIN
> 8 V;
< 18 V; V
LIN
≥ V
BAT
GND = V
V
BAT
SREG
;
0 V < V
LIN
< 18 V;
= 12 V
GND = V
S
; 0 V < V
Tj=-40 °C ....105 °C
LIN
(1)
< 18 V
LIN voltage level in dominant state
GND = V
S
; 0 V < V
Tj = 130°C
(2)
LIN
< 18 V
Active mode;
V
TXD
= V
TXDLOW
RBus=500 Ohm
40
-1
-1
100 180
20
1
30
35
1.2
mA mA
μ
μ
μ
A mA
A
A
V
V
LINrec
R
LINup
C
LIN
LIN voltage level in recessive state
Active mode;
I
V
TXD
LIN
= V
TXDHIGH
= 10 µA
;
LIN output pull up resistor V
LIN
LIN input capacitance
= 0 V
0.8*V
20
S
40 60
30
1. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range.
2. Used for device test only.
V k Ω pF
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V
S
< 28V; T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol t
RXpd t
RXpd_sym
D1
D2
D3
D4 t dom(TXDL) t
LIN t dom(bus)
Parameter
Table 46. LIN transceiver timing
Test condition
Receiver propagation delay time t t t
RXpd
RXpdf
= max(t
RXpdr
RXpdr
= t(0.5 V
= t(0.5 V
RXD
)-t(0.45 V
RXD
, t
RXpdf
);
)-t(0.55 V
LIN
);
);
=20 pF;
LIN
V
SREG
= 12 V; C
RXD
R
C
C bus bus bus
= 1 k Ω , C bus
= 6.8 nF; R
= 10 nF
= 1 nF; R bus bus
= 500 Ω ,
= 660 Ω ,
Symmetry of receiver propagation delay time
(rising vs. falling edge) t
RXpd_sym
R bus
= t
RXpdr
- t
RXpdf
; V
SRE
= 1 k Ω ; C bus
= 1 nF ; C
RXD
= 12 V;
= 20 pF
Duty Cycle 1
Duty Cycle 2
Duty Cycle 3
Duty Cycle 4
TH
Rec
TH
Dom
(max) = 0.744 * V
SREG
(max) = 0.581 * V
= 7 to 18 V, t bit
= 50 µs;
(min) / (2 x t bit
= 1 k Ω , C bus
);
;
SREG
;
V
SREG
D1 = t bus_rec
R bus
C bus
C bus
= 1 nF; R bus
= 6.8 nF; R bus
= 10 nF
= 500 Ω ,
= 660 Ω ,
TH
Rec
(min) = 0.422* V
SREG
;
TH
Dom
(min) = 0.284* V
SREG
V
SREG
= 7.6 to 18 V, t bit
D2 = t bus_rec
(max) / (2 x t bit
);
;
= 50 µs;
R bus
C bus
C bus
= 1 k Ω , C bus
= 1 nF; R bus
= 6.8 nF; R bus
= 10 nF
= 500 Ω ,
= 660 Ω ,
TH
Rec
(max) = 0.778* V
SREG
;
TH
Dom
(max) = 0.616* V
SREG
= 96 µs;
; V
SREG
= 7 to 18 V, t bit
D3 = t
R bus
C bus
C bus bus_rec
= 10 nF
(min) / (2 x t bit
= 1 k Ω , C bus
= 6.8 nF; R
);
= 1 nF; R bus
= 500 Ω bus
,
= 660 Ω ,
TH
Rec
(min) = 0.389* V
SREG
;
TH
Dom
(min) = 0.251* V
SREG
V
SREG
= 7.6 to 18 V, t bit
D4 = t bus_rec
(max) / (2 x t bit
);
;
= 96 µs;
R bus
C bus
C bus
= 1 k Ω , C bus
= 1 nF; R bus
= 6.8 nF; R bus
= 10 nF
= 500 Ω ,
= 660 Ω ,
TXDL dominant timeout
LIN permanent recessive time-out
LIN Bus permanent dominant time-out
Min.
-2
0.396
0.417
Typ.
Max.
Unit
12
40
12
6
2
0.581
0.590
μ s
μ s ms
μ s ms
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Figure 14. LIN transmit, receive timing
W
7;SGI
W
7;SGU
Electrical specifications
9
7['
WLPH
9
/,1UHF
9
/,1
9
7+UHF
9
7+GRP
9
/,1GRP
WLPH
9
5['
W
5;SGI
W
5;SGU
WLPH
*$3*&)7
3.4.25 SPI
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V
SREG unless otherwise specified.
< 18 V; V1 = 5 V; all outputs open; T j
= -40 °C to 150 °C,
Symbol
V
CSNLOW
V
CSNHIGH
V
CSNHYS
I
CSNPU
Parameter
Table 47. Input: CSN
Test condition
Input voltage low level Normal mode
Input voltage high level Normal mode
V
CSNHIGH
- V
CSNLOW
CSN Pull up resistor
Normal mode
Normal mode
Min.
Typ.
Max.
Unit
1.0
0.2
13 29
2.3
46
V
V
V k Ω
Symbol t t set set_CP
V in_L
V in_H
V in_Hyst
I pdin
Parameter
Table 48. Inputs: CLK, DI
Test condition
Delay time from standby to Active mode
Time until SPI, ADC and
OUT15/OUT_HS are operative
Delay time from standby to Active mode
Time until power stages that are supplied by the CP are operative
Input low level
Input high level
Input hysteresis
Pull down current at input
V in
= 1.5 V
Min.
Typ. Max.
Unit
10
560 750 960
1.0
2.3
0.2
5 30 60
µs
µs
V
V
V
µA
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
Symbol Parameter
Table 48. Inputs: CLK, DI (continued)
Test condition Min.
Typ. Max.
Unit
C f in
(1)
CLK
Input capacitance at input CSN, CLK, DI and
PWM
1,2
SPI input frequency at
CLK
Guaranteed by design
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
15
4 pF
MHz
Symbol t
CLK t
CLKH t
CLKL t set_CSN t set_CLK t set_DI t hold_DI t r_in t f_in
Table 49. DI, CLK and CSN timing
Parameter Test condition Min.
Clock period
Clock high time
Clock low time
CSN setup time, CSN low before rising edge of CLK
CLK setup time, CLK high before rising edge of CSN
DI setup time
DI hold time
Rise time of input signal DI,
CLK, CSN
Fall time of input signal DI,
CLK, CSN
250
100
100
150
150
25
25
Typ.
Max.
Unit ns ns ns ns
25
25 ns ns ns ns ns
Note: See
.
Symbol
V
DOL
V
DOH
I
DOLK
C
DO
Parameter
Table 50. Output: DO
Test condition
Output low level I
DO
= -4 mA
Output high level I
DO
= 4 mA
3-state leakage current
V
CSN
= V1, 0 V < V
DO
< V1
3-state input capacitance
Guaranteed by design
Min.
V1 - 0.5
-10
Typ.
Max.
Unit
0.5
V
V
10 μ A
10 15 pF
Symbol t r DO t f DO
Parameter
DO rise time
DO fall time
Table 51. DO timing
Test condition
C
L
= 50 pF; I
LOAD
= -1 mA
C
L
= 50 pF; I
LOAD
= -1 mA
Min.
Typ.
Max.
Unit
25
25 ns ns
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol t en DO tri L t dis DO L tri t en DO tri H t dis DO H tri t d DO
Parameter
Table 51. DO timing (continued)
Test condition Min.
DO enable time from
3-state to low level
DO disable time from low level to 3-state
DO enable time from
3-state to high level
DO disable time from high level to 3-state
DO delay time
C
L
= 50 pF; I
LOAD pull-up load to V1
= -1 mA;
C
L
= 50 pF; I
LOAD pull-up load to V1
= -1 mA;
C
L
= 50 pF; I
LOAD
= -1 mA; pull-down load to GND
C
L
= 50 pF; I
LOAD
= -1 mA; pull-down load to GND
V
DO
< 0.3 V1;
V
DO
> 0.7 V1; C
L
= 50 pF
Typ.
Max.
Unit
50 100 ns
100 ns 50
50 100 ns
50
30
100
60 ns ns
Note: See
Figure 17: SPI output timing .
Table 52. CSN timing
Test condition Symbol t
CSN_HI,min t
CSNfail
Parameter
Minimum CSN
High time, active mode
CSN low timeout
Transfer of SPI-command to
Input Register
Min.
6
20
Typ.
Max.
Unit
35 50
μ s ms
Note: See
Figure 18: SPI CSN - output timing .
3.4.26 Inputs TxD_C and TxD_L for Flash mode
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V ≤ V
SREG
≤ 18; V1 = 5 V; T j
= -40 °C to 150 °C.
Symbol
V flashL
V flashH
V flashHYS
Table 53. Inputs: TxD_C and TxD_L for Flash mode
Parameter Test condition Min.
Typ.
Max. Unit
Input low level (V
TXDC/L exit from Flash mode)
for
Input high level (V
TXDC/L
for transition into Flash mode)
Input voltage hysteresis
6.1
7.4
0.6
7.25
8.4
0.8
8.4
9.4
1.0
V
V
V
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
3.4.27 Inputs DIRH, PWMH
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
SREG
≤ 18 V; T j
= -40 °C to 150 °C.
Symbol
V
IL
V
IH
V
IHYS
I in
Parameter
Input voltage low level
Input voltage high level
Input hysteresis
Input pull-down current
Table 54. Inputs DIRH, PWMH
Test condition
V
SREG
= 13.5 V
V
SREG
= 13.5 V
V
SREG
= 13.5 V
V
SREG
= 13.5 V
Min.
Typ.
Max.
Unit
1
0.2
5 30
2.3
60
V
V
V
µA
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
SREG
≤ 18 V; T j
= -40 °C to 150 °C.
Symbol
V dIL
V dIH
V dIHYS
R din
Parameter
Table 55. Debug input
Test condition
Input voltage low level V
SREG
= 13.5 V
Input voltage high level V
SREG
= 13.5 V
Input hysteresis
Pull-down resistor
V
SREG
= 13.5 V
V
DEBUG
= 6 to 18 V
Min.
Typ.
Max.
Unit
1
0.2
2.5
5
2.3
7.5
V
V
V k Ω
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
SREG
≤ 18 V, T j
= -40 °C to 150 °C.
Symbol t con f
ADC
Acc
Parameter
Table 56. ADC characteristics
Test condition
Conversion time
Clock frequency (see f clk
2)
Accuracy
Voltage divider + reference
(1)
Overall accuracy for WU input: V
S
= 22 V
Overall accuracy for WU input: V
S
= 18 V
Overall accuracy for WU input: V
S
= 6 V
Overall accuracy for WU input: V
S
= 4.5 V
Min.
Typ.
Max.
Unit
2.5
µs
-2
-3
-3.5
-4
-4.6
8
2
3
3.5
4
4.6
MHz
%
DS11546 Rev 5
L99DZ100G, L99DZ100GP Electrical specifications
Symbol
Table 56. ADC characteristics (continued)
Parameter
V
IE
IE
I
D
I
I
AINVS
Integral linearity error
Differential linearity error
Conversion voltage range (V
S
WU)
, V
SREG
&
V
AINTemp
Conversion voltage range (T
CL
1 …T
CL
6)
1. Guaranteed by design.
Test condition Min.
Typ.
Max.
Unit
1
0
4
2
22
2
LSB
LSB
V
V
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
SREG
≤ 18 V, T j
= -40 °C to 150 °C
Symbol
Table 57. Temperature diode characteristics
Parameter
V
TROOM 1-6
V
TSENSE1-6
T
SENSE output voltage at 25 °C
T
SENSE output voltage 1 - 8
Test condition
V
S
= 12 V; T = 25 °C
T = 25 °C; T = 130 °C;
T = -40 °C
Min.
—
—
Typ.
Max.
Unit
1.4
-4
V mV/K
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V
SREG
≤ 18 V, T j
= -40 °C to 150°C
Symbol
V
INTL
V
INTH
I
INTLK t
Interrupt t
Int_react
Parameter
Table 58. Interrupt outputs
Test condition
Output low level I
INT
= -4 mA
Output high level I
INT
= 4 mA
3-state leakage current 0 V < V
INT
< V1
Interrupt pulse duration
(NINT, RxD_L/NINT,
RxD_C/NINT
Interrupt reaction time Tested by scan chain
Min.
V1 - 0.5
-10
6
Typ.
Max.
Unit
0.5
10
V
V
μ A
56
40
s
µs
DS11546 Rev 5
196
Electrical specifications L99DZ100G, L99DZ100GP
3.4.32 Timer1 and Timer2
6 V ≤ V
SREG
≤ 18 V; T j
= -40 °C to 150 °C
Table 59. Timer1 and Timer2
Test condition Min.
Symbol
T3
T4
T5
T6
T7
T8 ton 1 ton 2 ton 3 ton 4 ton 5
T1
T2
Parameter
Timer on time
Timer on time
Timer on time
Timer on time
Timer on time
Timer period
Timer period
Timer period
Timer period
Timer period
Timer period
Timer period
Timer period
Typ.
Max.
Unit
50
100
200
500
1000
2000
10
20
10
20
0.1
0.3
1 ms ms ms ms ms ms ms ms ms ms ms ms ms
Figure 15. SPI – transfer timing diagram
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CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
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Electrical specifications
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DS11546 Rev 5
196
Electrical specifications
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DS11546 Rev 5
L99DZ100G, L99DZ100GP
& 61
Electrical specifications
Figure 18. SPI CSN - output timing
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T j
= -40 °C to 150 °C, unless otherwise specified.
Symbol Parameter
Table 60. SGND loss comparator
Test condition Min.
V
SGNDloss t
SGNDloss
V
SGND loss threshold (V
SGND
– V
PGND )
V
SGND loss filter time
100
5
Typ.
Max.
Unit
270
7
500
9 mV
µs
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
, V
SREG
V
SREG
supplies voltage regulators V1 and V2, all internal regulated voltages for analog and digital functionality, LIN, CAN, the EC control block and both P-channel high-side switches
OUT15 and OUT_HS.
All other high-sides, Fail Safe block and the charge pump are supplied by V
S
.
In case the V
SREG switched off.
pin is disconnected, all power outputs connected to V
S
are automatically
The device contains two independent and fully protected low drop voltage regulators designed for very fast transient response and do not require electrolytic output capacitors for stability.
The output voltage is stable with ceramic load capacitors >220 nF.
The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load current to supply the system microcontroller and the integrated CAN transceiver. The V1 regulator is embedded in the power management and fail-safe functionality of the device and operates according to the selected operating mode. The V1 voltage regulator is supplied by pin V
SREG
.
In addition, the V1 regulator supplies the devices internal loads. The voltage regulator is protected against overload and overtemperature. An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors >220 nF.
In case the device temperature exceeds the TSD1 threshold (either cluster or grouped mode) the V1 regulator remains on. The micro controller has the possibility for interaction or error logging. If the chip temperature exceeds the TSD2 threshold (TSD2 > TSD1), V1 will be deactivated and all wakeup sources (CAN, LIN, WU and Timer) are disabled. After t
TSD the voltage regulator will restart automatically. If the restart fails 7 times within one minute
, the devices enter the Forced Vbat_standby mode. The status bit
FORCED_SLEEP_TSD2/V1SC (SR1) is set.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
4.2.3
4.2.4
The voltage regulator V2 is supplied by pin V
SREG
and can supply additional 5 V loads such as sensors or potentiometers. The maximum continuous load current is 50 mA. The regulator is protected against:
Overload
Overtemperature
Short-circuit (short to ground and battery supply voltage)
Reverse biasing
Voltage regulator failure
The V1, and V2 regulator output voltages are monitored.
In case of a drop below the failure thresholds (V1 < V1 fail t > t
V2fail
for t > t
), the failure bits V1FAIL, V2FAIL (SR 2) are latched.
V1fail
, V2 < V2 fail
for
Short to ground detection
At turn-on of the V1 and V2 regulators, a short-to-GND condition is detected by monitoring the regulator output voltage.
If V1 or V2 is below the V1 fail
(or V2 fail
) threshold for t > t
V1short
(t > t
V2short
) after turn-on, the devices will identify a short circuit condition at the related regulator will be switched off.
In case of V1 short-to-GND the device enters Forced Vbat_standby mode automatically. Bits
FORCED_SLEEP_TSD2/V1SC and (SR 1) V1FAIL (SR 2) are set.
In case of a V2 short-to-GND failure the V2SC (SR 2) and V2FAIL (SR 2) bits are set.
Once the output voltage of the corresponding regulator exceeded the V1 fail
(V2 fail
) threshold the short-to-ground detection is disabled. In case of a short-to-ground condition, the regulator is switched off due to thermal shutdown. V1 is switched off at TSD2, V2 is switched off at TSD1.
DS11546 Rev 5
196
Application information
4.2.5 Voltage regulator behavior
L99DZ100G, L99DZ100GP
Figure 20. Voltage regulator behaviour and diagnosis during supply voltage
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The devices can be operated in the following operating modes:
Active
LIN Flash
CAN Flash
V1_standby
VBAT_standby
Debug
All functions are available and the device is controlled by SPI.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Note:
To program the system microcontroller via LIN or HS CAN bus signals, the devices can be operated in LIN Flash mode or CAN Flash mode. The watchdog is disabled in these modes.
The Flash modes are entered by applying an external voltage at the respective pin:
V
TxDL
≥ V
FlashH
(CAN Flash mode)
V
TxDC
≥ V
FlashH
(LIN Flash mode)
In CAN Flash mode the CAN transceiver is set in TRX bias mode
(CAN_GO_TO_TRX_RDY = 1) and TRX Normal mode automatically
During CAN Flash mode, the watchdog can be deactivated by setting CR34: WDEN = 0.
Write access to this bit is only possible during CAN Flash mode in order to prevent accidental deactivation of the watchdog. After setting WDEN (CR 34) the CAN Flash mode can be left (V
TxDL
< V
FlashL
) and the Watchdog will remain deactivated (see Figure 21 )
Figure 21. Sequence to disable/enable the watchdog in CAN Flash mode
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In LIN Flash mode the maximum bitrate is increased to 100 kbit/s automatically
(LIN_HS_EN = 1).
A transition from Flash modes to V1_standby or Vbat_standby mode is not possible.
At exit from Flash modes (V
TxDL
< V
FlashL
, V
TxDC
< V
The watchdog starts with a Long Open Window (t
LW
).
FlashL
) no NReset pulse is generated.
Setting both TxDL and TxDC to high voltage levels (> V
FlashH
Communication at the respective TxD pin is not possible.
) is not allowed.
Note:
To allow software debugging, the watchdog can be deactivated by applying an external voltage to the DEBUG input pin (V debug
> V diH
).
In Debug mode, all device functionality and Operating modes are available. The watchdog is deactivated. At Exit from Debug mode (V debug
Open Window.
< V diL
) the watchdog starts with a Long
The device includes a test mode. This mode is activated by a dedicated sequence which includes a high voltage at the Debug Pin. The Debug Pin must be kept at nominal voltage levels in order to avoid accidental activation of the test mode.
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
The transition from Active mode to V1_standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the V1 voltage regulator remains active.
After the V1_standby command (CSN low to high transition), the device enters V1_standby mode immediately and the watchdog starts a Long Open Window (t
LW
). The watchdog is deactivated as soon as the V1 load current drops below the I
CMP
threshold (I
V1
< I cmp_fal
).
The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration the watchdog will be deactivated upon transition into V1_standby mode without monitoring the V1 load current.
Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting
ICMP_CONFIG_EN (Config Reg) = 1.
The ICMP_CONFIG_EN bit is reset to 0 automatically with the next SPI command.
Power outputs (except OUT_HS & OUT15) are switched off in V1_standby mode. OUT_HS
& OUT15 remain in the configuration programmed prior to the standby command in order to enable (cyclic) supply of external contacts. The timer signal (Timer1 or Timer2) can be mirrored to the NINT output pin during V1_standby mode.
CAN and LIN transmitters (TxDL, TxDC) are off.
Wake-up capability by CAN and LIN can be disabled by SPI. The CAN transceiver can be configured in Listen mode (TxDC disabled, RxDC enabled) in order to support pretended networking concepts (for details see
Section 4.10.6: Pretended networking )
4.3.5 Interrupt
Figure 22. NINT pins
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RxDL/NINT indicates:
a wake-up event from V1_standby mode (except wake-up by CAN) and the programmable timer interrupt
RxDL/NINT pin is pulled low for t = t interrupt
.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
RxDC/NINT indicates:
Mode transitions of the CAN transceiver according to Figure 31: CAN transceiver state diagram
CAN communication timeout (no CAN communication for t > t
Silence
). The CANTO flag is set. This interrupt can be masked by SPI (CR2: CANTO_IRQ_EN).
RxDC/NINT pin is pulled low for t = t interrupt
.
See also Section 4.3.6: CAN wake-up signalization
NINT indicates:
In Active mode:
V
SREG
dropped below the programmed early warning threshold in Control Register 3
(V
SREG
< VSREG_EW_TH); feature is deactivated if VSREG_EW_TH is set to 0 V.
In V1_standby mode
– Programmable timer interrupt; An NINT pulse is generated at the beginning of the timer on-time (Timer 1 or Timer2)
– CAN communication timeout (no CAN communication for t > t
Silence
). The CANTO flag is set. This interrupt can be masked by SPI (CR2: CANTO_IRQ_EN).
– Wake-up from V1_standby mode by any wake-up source
NINT is pulled low for t = t interrupt
In case of increasing V1 load current during V1_standby mode (I
V1
> I cmp_ris
), the device remains in standby mode and the watchdog starts with a Long Open Window. No Interrupt signal is generated.
Table 61. CAN wake-up signalization
Operating mode
Event Mode transition Status flag Interrupt pin
Active
V1_standby
WUP or
WUP/WUF (1)
CAN Timeout
WUP
WUP or
CAN Timeout
WUP
(3)
Transition to TRX_Ready
Transition to TRX_Sleep
Transition into TRX_Bias
Transition into Active mode; TRX_Ready
Transition to TRX_Sleep
Transition into TRX_Bias
WAKE_CAN
WUP/WUF
CANTO
WUP
WAKE_CAN
WUP/WUF
CANTO
WUP
RxDC
RxDC
RxDC
RxDC
and
and
(2)
NINT
NINT
RxDC and NINT
RXDC and NINT
V bat
_standby
WUP or
CAN Timeout
Transition into Active mode; TRX_Ready
Transition to TRX_Sleep
WAKE_CAN
WUP/WUF
CANTO none
1. SW_EN = 0, PNW_EN = 0:
— wake-up according ISO 11898-5:2007 (on WUP)
— Flags: Wake_CAN, WUP
SW_EN = 1:
— wake-up according ISO 11898-6:2013 (on WUP/WUF combination)
— After the reception of a wake-up pattern (WUP) the CAN Enhanced Voltage Biasing is turned on until a CAN timeout is detected
— Flags: Wake_CAN, WUP, WUF
DS11546 Rev 5
196
Application information
2. Interrupt can be disabled by SPI (CANTO_IRQ_EN).
3. SW_EN = 0, PWN_EN = 1 (Pretended Networking mode)
— no wake-up
— after reception of a wake-up patter (WUP) the transceiver enters TRX Bias mode
— Flags: WUP
Note:
See also Figure 31: CAN transceiver state diagram
.
L99DZ100G, L99DZ100GP
4.4
The transition from Active mode to Vbat_standby mode is initiated by an SPI command. In
Vbat_standby mode, the voltage regulators V1 and V2 (depending on configuration in
CR 1), the power outputs (except OUT15 and OUT_HS) as well as LIN and CAN transmitters are switched off.
An NReset pulse is generated upon wake-up from Vbat_standby mode. At transition into
Vbat_standby mode with selective wake-up enabled (SWEN = 1), the CAN transceiver is automatically set to TRX_standby configuration (RXEN = 0).
Wake-up from Standby modes
A wake-up from standby mode will switch the device to Active mode. This can be initiated by one or more of the following events:
Wake up source
Table 62. Wake-up events description
Description
LIN bus activity
CAN bus activity
Can be disabled by SPI
Can be disabled by SPI
Selective Wake-up can be enabled and configured by SPI
Can be configured or disabled by SPI Level change of WU
I
V1
>I cmp_ris
Timer Interrupt / Wake up of µC by TIMER
Device remains in V1_standby mode but watchdog is enabled (If
I
CMP
= 0). No interrupt is generated.
Programmable by SPI:
– V
1
_standby mode : configurable timer interrupt. NINT and RxDL/NINT interrupt signals are generated
– V bat
_standby mode : device wakes up after programmable timer expiration, V1 regulator is turned on and NReset signal is generated
SPI Access
Always active (except in V
BAT_STANDBY
mode )
Wake up event: CSN is low and first rising edge on CLK
To prevent the system from a deadlock condition (no wake up from standby possible) a configuration where the wake up by LIN and HS CAN are both disabled is not allowed. All wake-up sources are configured to default values in case of such invalid setting. The SPI
Error Bit SPIE (Global Status Byte) is set.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
The WU input can be configured as wake-up source. The wake-up input is sensitive to any level transition (positive and negative edge) and can be configured for static or cyclic monitoring of the input voltage level.
For static contact monitoring, a filter time of t
WU_STAT
is implemented. The filter is started when the input voltage passes the specified threshold V
WU_THP
or V
WU_THN
.
Cyclic contact monitoring allows periodical activation of the wake-up input to read the status of the external contact. The periodical activation can be configured to Timer 1 or Timer 2.
The input signal is filtered with a filter time of t
WU_CYC
after a delay (80% of the configured
Timer on-time. A Wake-up will be processed if the status has changed versus the previous cycle. The buffered output OUT_HS can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up input.
In standby modes, the input WU is configurable with an internal pull-up or pull-down current source according to the setup of the external contact. In Active mode the inputs have an internal pull down resistor (R
WU_act
) and the input status can be read by SPI. Static sense should be configured before the read operation is started in order to reflect the actual input level.
Voltage regulator V1
Voltage regulator V2
Reset generator
Wake up
Table 63. Status of different functions/features vs operating modes
Operating modes
Function Comments
Active mode
V
1
-standby static mode (cyclic sense)
V bat
-standby static mode (cyclic sense)
Window watchdog
V
OUT
= 5 V
V
OUT
= 5 V
V
1
monitor
On
On/ Off
(2)
On
On
Off
On
(1)
/ Off
On
Off (on if I
V1 and I
CMP
> I
CMP
= 0)
Active
(3)
Off
On
Off
Off
HS-cyclic supply
Oscillator time base
LIN 2.2a
On / Off
/ Off On
LIN
HS_CAN
Oscillator OSC1
Oscillator OSC2
V
SREG-Monitor
V
S-Monitor
2 MHz
32 MHz
On
On / Off
(5)
On
ON
On
On
Off
(4)
On/Off (6)
ON/Off
(7)
(8)
Off
Off
Off
On/Off
ON/Off
Off
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
Table 63. Status of different functions/features vs operating modes (continued)
Operating modes
Function Comments
Active mode
V
1
-standby static mode (cyclic sense)
V bat
-standby static mode (cyclic sense)
H Bridge Gate Driver, EC control, bridge drivers, heater driver, all high-side drivers
(except OUT_HS & OUT15) supplied by V
S
Fail-safe low-side switches
Short circuit protection for fail-safe low-side switches (in case LS is switched on)
OUT_HS & OUT15 (Pchannel HS) supplied by
V
SREG
Charge pump
ADC (SPI read out and
V
SREG
early warning interrupt)
Thermal shutdown TSD2
Thermal shutdown TSD1x for
OUT_HS and OUT15 (Pchannel HS)
On/ Off
On
On
On
On
On
(9)
Off
On
On
Off
Off
On
Off
On
On
On/ Off
Off
Off
Off
On/ Off
1. Supply the processor in low current mode.
2. According to SPI setting and DIR.
3. Unless disabled by SPI.
4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding of internal filter time (if wake-up by LIN or CAN is not disabled by SPI). Selective Wake functionality if enabled by SPI
5. After power-on, the HS CAN transceiver is in CAN_TRX_SLEEP mode. It is activated by SPI command
(CAN_GO_TRX_RDY= 1)
6. ON, if cyclic sense is enabled or during wake-up request.
7. ON if SWEN=1 (CAN partial networking enabled) and ongoing CAN communication on the bus.
8. Cyclic activation = pulsed ON during cyclic sense.
9. ON in Fail-Safe mode; if standby mode is entered with active Fail-safe mode the output remains ON in standby mode.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Figure 23. Main operating modes
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4.6 Configurable window watchdog
During normal operation, the watchdog monitors the micro controller within a programmable trigger cycle.
After power-on or standby mode, the watchdog is started with a timeout (Long Open
Window t
LW
). The timeout allows the micro controller to run its own setup and then to start the window watchdog by setting TRIG (CR1,ConfigReg) =1
Subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit TRIG (CR1,Config Reg) within the safe trigger area T
SWX
.
The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately start the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off for t
V1OFF
. After 7 additional watchdog failures the V1 regulator is turned off permanently and the device goes into Forced Vbat_standby mode. The status bit FORCED_SLEEP_WD
(SR 1) is set. A wake-up is possible by any activated wake-up source.
After wake-up from Forced Vbat_standby mode and the watchdog trigger still fails, the device enters Forced Vbat_standby mode again after one Long Open Window.
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
This actually produces an additional watchdog failure but the watchdog fail counter will remain at maximum value of 15 failures.
This sequence is repeated until a valid watchdog trigger event is performed by writing
TRIG = 1.
In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit
WDFAIL (SR 1) is set to 1. A reset pulse is generated at NReset output and the device enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe
low-side switches are turned on. Please refer to chapter Section 4.7: Fail-safe mode for
more details.
The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are split into 3 parts. First diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which can
affect the watchdog behavior. Figure 26: Watchdog in Flash mode
shows the transition in
and out of Flash modes. Figure 24 ,
Figure 25 and Figure 26 can be overlapped to get all the
possible state transitions under all circumstances. For a better readability, they were split in normal operating, operating with errors and Flash mode.
Figure 24. Watchdog in normal operating mode (no errors)
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DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Figure 25. Watchdog with error conditions
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Whenever the device is operated without servicing the mandatory watchdog trigger events, a sequence of 15 consecutive reset events is performed and the device enters the
Forced_Vbat_Stby mode with bit FORCED_SLEEP_WD in SR1 set.
If the device is woken up after such a forced VBAT_Standby condition and the watchdog is still not serviced, the device, after one long open watchdog window will re-enter the same
Forced_Vbat_Stby mode until the next wake up event. In this case, an additional watchdog failure is generated, but the fail counter is not cleared, keeping the maximum number of 15 failures. This sequence is repeated until a valid watchdog trigger event is performed by writing TRIG = 1.
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config
Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command.
The devices enter Fail-safe mode in case of:
Watchdog failure
V1 turn on failure
– V1 short (V1 < V1 fail
for t > t
V1short
)
V1 failure (V1 < V
RTxfalling
for t > t
V1FS
)
Thermal Shutdown TSD2
The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode the Fail Safe mode is entered in the following cases:
V1 failure (V1 < V
RTxfalling
for t > t
V1FS
)
Watchdog failure (if watchdog still running due to I
V1
> I cmp_fal
)
Thermal Shutdown TSD2
In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated to the system in the Global Status Byte. The conditions during Fail Safe mode are:
All outputs beside LS1_FSO and LS2_FSO are turned off
All Control Registers are set to fail safe default values except:
– SWEN (CR1<bit 7>): selective Wake-up enable
– Partial Networking Configuration: CR23-CR29
Write operations to Control Registers are blocked until the Fail Safe condition is cleared. The following bits are not WRITE protected:
– TRIG (CR1<bit 0>, Config Register <bit 0>): watchdog trigger bit
– V2_x (CR1<bit 4:5>): Voltage Regulator V2 control
– CAN_GO_TRX_RDY (CR1<bit 8>): activation of CAN transceiver
– CR2 (bit <8:23>): Timer1 and Timer2 settings
– OUT_HS_x (CR5 <bit 0:3>): OUT_HS configuration
– OUT15_x (CR6<bit 0:3>): OUT15 configuration
– PWMx_freq_y (CR12): PWM frequency configuration
– PWMx_DC_y (CR13 – CR17): PWM duty cycle configuration
LIN and HS CAN transmitter and SPI remain on (transmitters are deactivated in case of thermal shutdown TSD1 (TSD1 cluster 5 or 6 in cluster mode)
Corresponding Failure Bits in Status Registers are set
FS Bit (Global Status Byte) is set
LS1_FSO and LS2_FSO will be turned on
Charge pump is switched off
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the actions to exit Fail safe mode are as shown in the following table.
Failure source
Table 64. Temporary failures description
Failure condition Diagnosis Exit from Fail-safe mode
Microcontroller
(oscillator)
V1
Temperature
Watchdog early write failure or expired window
Short at turn-on
Undervoltage
T j
> T
SD2
FS (Global Status Byte) =1;
WDFAIL (SR 1) =1;
WDFAIL_CNT_x (SR 1) = n+1
FS (Global Status Byte) =1;
FORCED_SLEEP_TSD2/V1SC
(SR 1) =1
FS (Global Status Byte) = 1; V1UV
(SR 1) = 1; V1fail (SR 2) = 1
(1)
FS (Global Status Byte) = 1; TW
(SR 2) = 1;
TSD1 (SR 1) =1;
TSD2 (SR 1) =1
1. If V1 < V1 fail
(for t > t
V1fail
). The Fail-safe Bit is located in the Global Status Register.
TRIG (CR 1) = 1 during long open window Read&Clear
SR1
Wake-up;
Read&Clear SR1
V1 >V
RTrising
;
Read&Clear SR1
T j
< T
SD2
;
Read&Clear SR1
If the Fail-safe condition persists and all attempts to return to normal system operation fail, the devices enter the Forced Vbat_standby mode in order to prevent damage to the system.
The Forced Vbat_standby mode can be terminated by any wake-up source. The root cause of the Forced Vbat_standby mode is indicated in the SPI Status Registers. In forced
Vbatstby mode and with Fail Safe conditions still present at wake-up, the Fails safe low side outputs LSx_FSO are switched OFF for 25us after the wake up event.
In Forced Vbat_standby mode, all Control Registers are set to power-on default values except:
SWEN (CR1<bit 7>)
All bits from CR23 to CR29
CP_DITH_DIS (Config. Reg <bit 5>)
The Forced Vbat_standby mode is entered in case of:
Multiple watchdog failures: FORCED_SLEEP_WD (SR 1) = 1 (15 x watchdog failure)
Multiple thermal shutdown 2: FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 (7 x TSD2)
V1 short at turn-on (V1 < V1 fail
for t > t
V1short
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
):
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
Failure source Failure condition
Microcontroller
(Oscillator)
15 consecutive
Watchdog Failures
V1 Short at turn-on
Temperature 7 times TSD2
Table 65. Non-recoverable failure
Diagnosis Exit from Fail-safe mode
FS (Global Status Byte) = 1; WDFAIL (SR
1) = 1; FORCED_SLEEP_WD (SR 1) = 1
FS (Global Status Byte) = 1;
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Wake-up;
TRIG (CR 1) = 1 during long open window; Read&Clear
SR1
Wake-up;
Read&Clear SR1
FS (Global Status Byte) =1; TW (SR 2) = 1;
TSD1 (SR 1) = 1; TSD2 (SR 1) = 1;
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Wake-up;
Read&Clear SR1
4.8 Reset output (NReset)
Figure 27. NReset pin
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If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is pulled up to V1 by an internal pull-up resistor after a reset delay time (t
V1R
). This is necessary for a defined start of the micro controller when the application is switched on.
Since the NReset output is realized as an open drain output it is also possible to connect an external NReset open drain NReset source to the output. As soon as the NReset is released by the devices the watchdog starts with a long open window.
A reset pulse is generated in case of:
V1 drops below V
RTxfalling
(configurable by SPI) for t > t
UV1
Watchdog failure
Turn-on of the V1 regulator (V
SREG
Power-on or wake-up from Vbat_standby mode)
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.9 LIN Bus Interface
Figure 28. RxDL pin
9 (6'SURW
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4.9.1 Features
LIN 2.2a compliant (SAEJ2602 compatible) transceiver
LIN Cell has been designed according to “Hardware requirements for transceivers
(version 1.3)”
Bitrate up to 20 kbit/s
Dedicated LIN Flash mode with bitrate up to 100 kbit/s
GND disconnection fail safe at module level
Off mode: does not disturb network
GND shift operation at system level
Micro controller Interface with CMOS-compatible I/O pins
Internal pull-up resistor
Receive-only mode
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
Matched output slopes and propagation delay
Wake-up behaviour according to LIN2.2a and Hardware Requirements for LIN, CAN and Flexray Interfaces (version 1.3)
At V
SREG
> V
POR
(i.e. V
SREG
power-on reset threshold), the LIN transceiver is enabled. The
LIN transmitter is disabled in case of the following errors:
Dominant TxDL time out
LIN permanent recessive
Thermal shutdown 1
V
SREG
overvoltage/ undervoltage
The LIN receiver is not disabled in case of any failure condition.
The default bitrate of the transceiver allows communication up to 20 kbit/s. To enable fast flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit
LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode.
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
4.9.3
The devices LIN transceiver provides the following 3 error handling features.
Dominant TxDL time out
If TXD_L is in dominant state (low) for t > t dom(TXDL) status bit LIN_TXD_DOM (SR 2) will be set.
the transmitter will be disabled, the
The transmitter remains disabled until the status bit is cleared.
The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0).
Permanent recessive
If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < t
LIN the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set.
The transmitter remains disabled until the status bit is cleared.
Permanent dominant
If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure will be detected. The status bit LIN_PERM_DOM (SR 2) will be set.
The transmitter will not be disabled.
Wake up from Standby modes
In low power modes (V1_standby mode and Vbat_standby mode) the devices can receive two types of wake up signals from the LIN bus (configurable by SPI bit LIN_WU_CONFIG
(Config Reg)):
Recessive-Dominant-recessive pattern with t > t dom_LIN
(default, according LIN 2.2a)
State Change recessive-to-dominant or dominant-to-recessive (according LIN 2.1)
Pattern Wake-up (default)
Figure 29. Wake-up behavior according to LIN 2.2a
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DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Status change wake-up - Recessive-to-dominant
Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high) state. A dominant level at LIN for t > t to Active mode.
LINBUS
, will switch the devices
Status change wake-up - Dominant-to-recessive
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for t > t
LINBUS
, will switch the devices to Active mode.
The LIN transmitter can be disabled in Active mode by setting the bit LIN_REC_ONLY
(CR2). In this mode it is possible to listen to the bus but not sending to it.
Figure 30. RxDC pin
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DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
4.10.1 Features:
ISO 11898-2:2003 and ISO 11898-5:2007 compliant
ISO 11898-6: 2013 compliant (Selective wake-up functionality up to 500kbps); only
L99DZ100GP
HS-CAN cell has been designed according to “Requirements for partial networking
(version 2.2)” and “Hardware requirements for transceivers (version 1.3)”
Supports pretended networking
Listen mode (transmitter disabled)
Enhanced Voltage Biasing according to ISO 11898-6:2013
SAE J2284 compliant
Bitrate up to 1Mbit/s.
Function range from -27V to +40V DC at CAN pins.
GND disconnection fail safe at module level.
GND shift operation at system level.
Micro controller Interface with CMOS compatible I/O pins.
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
Matched output slopes and propagation delay
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
4.10.2 CAN transceiver operating modes
Figure 31. CAN transceiver state diagram
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TRX Ready State
In this state the bus-biasing is on. The Frame Decoder is enabled, if selective wake-up is activated (SWEN=1).
The transmitter and receiver can be configured by SPI (RXEN, TXEN) as follows:
TRX Standby (default): transmitter and receiver disabled
TRX Listen: transmitter disabled, receiver enabled
TRX Normal: transmitter enabled, receiver enabled
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
TRX BIAS State
In this transceiver state the bus biasing is on and the Automatic Voltage Biasing is active
(i.e. transceiver enters TRX_Sleep at t > t
Silence
and turns off the biasing). The Frame
Decoder is enabled if selective wake-up is configured (SWEN = 1).
The CAN transmitter is disabled. The receiver can be configured by SPI (RXEN) as follows:
TRX Standby(default): receiver disabled
TRX Listen: receiver enabled
The CAN receiver is capable to detect a wake-up pattern (WUP) or a wake-up frame (WUF; if selective wake-up is enabled by SWEN = 1). In V1_standby mode and Active mode, a wake-up is indicated to the micro-controller by an interrupt signal and the transceiver enters
TRX_Ready State (receiver and transmitter according to setting of TXEN and RXEN). After serving the interrupt, the micro controller can enable the receiver and transmitter by setting
TXEN = 1 and RXEN = 1.
In case of a Frame-Detect-Error (FDERR = 1), an automatic wake up is performed and the selective wakeup feature is disabled (SWEN = 0).
TRX SLEEP State
After Power-on the CAN transceiver enters TRX_Sleep state. In this state, the CAN transceiver is disabled and the biasing is turned off. Transmitter and receiver are disabled
(TRX_Standby state). The CAN selective wakeup reference oscillator and the Frame
Decoder are off. After the detection of CAN communication (WUP), an interrupt signal is generated and the transceiver enters TRX_Ready state (if SWEN = 0) or TRX_BIAS state (if
SWEN = 1). Receiver and transmitter are configured according to setting of TXEN and
RXEN.
TRX_Sleep state is entered automatically after a CAN communication timeout (see
Section 4.10.3: Automatic voltage biasing )
The Automatic Voltage Biasing is described in ISO 11898-6:2013. This feature is active in all transceiver low-power modes independent of the SBC operating modes and independent if selective wake-up is enabled or not (SWEN (CR 1) = 0 or SWEN = 1).
t
If there has been no activity on the bus for longer than t
Silence towards 0V via the receiver input resistors R in
V
CANLrec
Bias
.
, the bus lines are biased
. If wake-up activity on the bus lines is detected (Wake-up pattern, WUP), the bus lines are biased to V
CANHrec
via the internal receiver input resistors R in
respectively
. The biasing is activated not later than
4.10.4 Wake-up by CAN
The devices support 2 wake-up modes. The selective wake-up according to ISO 11898-
6:2013 or the wake-up by any bus activity according to ISO 11898-2:2003/-5:2007 (default configuration). The wake-up behavior can be configured by SPI.
Wake-up by CAN pattern (WUP)
The default setting for the wake up behavior after Power-on reset is the wake-up by regular communication on the CAN bus according to ISO 11898-5:2007 (SWEN=0). When the CAN
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information transceiver is in a low power mode (TRX_BIAS or TRX_Sleep) the device can be woken up by sending 2 consecutive dominant bits separated by a recessive bit.
A wake-up can be detected if the CAN transceiver was set in standby mode while the CAN bus was in recessive (high) state or dominant (low) state (see
Figure 32: CAN wake up capabilities ).
Figure 32. CAN wake up capabilities
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For details, see Figure 31: CAN transceiver state diagram
Wakeup by Wake-up Frame (WUF)
In this configuration, the wake-up behavior is according to ISO 11898-6:2013. This option is activated by setting SWEN = 1. Upon reception of a valid wake up frame, an interrupt will be generated, the WUF flag will be set and the device enters Active mode.
The included frame-error-counter according ISO 11898-6:2013 is reset whenever selective wake-up is set to enable and whenever t
Silence has expired in TRX BIAS state (i.e. either on a transition SWEN = 0 -> 1 or on a transition TRX BIAS -> TRX Sleep).
To detect a failure of the internal 32 MHz oscillator, the following mechanism is implemented. While selective wake-up is enabled a timer is started with each recessive to dominant edge. After 64 µs and with periodic 64 µs timer, a check is performed on CAN PN oscillator activity, and if an oscillator fail is detected, the osc_mon bit is set to ‘1’.
Subsequently the device enters wake-up mode according to ISO11898-5 (wake-up pattern wake-up).
For details, see Figure 31: CAN transceiver state diagram .
Sequence for enabling selective wakeup
After Power-On-Reset, the selective wakeup feature is disabled. The PN Configuration
Registers have to be read and verified by the microcontroller in order to ensure a valid configuration. A read operation to Registers CR23 to CR29 is required to allow enabling the selective wake-up feature (set SWEN=1). SWRD_CRxx (SR 12) bits will indicate a valid read operation. The SWRD_CRxx bits are reset to 0 with every WRITE operation.
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Application information L99DZ100G, L99DZ100GP
When all SWRD_CRxx bits are set, SWEN can be set to enable the Selective Wakeup function. In case SYSERR (SR 12) is set while Selective Wakeup is enabled, the Selective
Wakeup will be disabled automatically. In case SYSERR is set, enabling the Selective
Wakeup function is blocked. While selective wake-up is enabled (SWEN = 1), writing to
CR23 – CR29 is blocked but SWEN is reset to ‘0’. To re-configure the selective wakeup feature, it is recommended to set SWEN = 0 before writing to CR23 - CR29.
Wake up from TRX SLEEP
If the CAN Transceiver is in TRX_Sleep state the CAN frame detection logic is disabled. The wake up can be done in two steps. To enable the CAN frame detection logic a wake up pattern must be sent on the bus. With the detection of the wake up pattern an automatic state transition to TRX_BIAS State is done. WUP flag is set. In TRX_BIAS State the CAN frame detection logic is enabled. If there is no bus communication for longer than t
Silence
an automatic state transition to TRX_Sleep state will be done and the CAN frame detection logic will be disabled. At frame error counter (FECNT_x) overflow, a wake up will be
performed and the selective wakeup feature will be disabled. For details, see Figure 31:
CAN transceiver state diagram .
If CAN_LOOP_EN (CR 2) is set the TxD_C input is mapped directly to the RxD_C pin. This mode can be used in combination with the CAN Receive-only mode, to run diagnosis for the
CAN protocol handler of the micro controller.
To support pretended networking concepts, the devices can be configured as follows:
V1_standby mode or Active mode (if watchdog is required)
Pretended Networking enabled (PNW_EN (CR 2) = 1)
In this configuration, the microcontroller is supplied by V1 in low current mode. The CAN
Automatic Voltage Biasing is active. Upon incoming CAN messages, the biasing is turned on (TRX_BIAS State) and an interrupt is generated. If the device is in V1_standby mode it remains in this mode.
The incoming CAN frames are passed to the microcontroller via the RxD_C signal line for decoding.
4.10.7 CAN error handling
The devices provide the following four error handling features. After Power-on Reset (V
S
) the CAN transceiver is disabled. The transceiver is enabled by setting
>
V
POR
CAN_GO_TRX_RDY(CR 1) = 1. The CAN transmitter will be disabled automatically in case of the following errors:
Dominant TxD_C time out
CAN permanent recessive
RxD_C permanent recessive
Thermal Shutdown 1
The CAN receiver is not disabled in case of any failure condition.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Dominant TxDC time out
If TXD_C is in dominant state (low) for t > t dom(TxDC)
the transmitter will be disabled,
CAN_TXD_DOM (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.
CAN Permanent Recessive
If TXD_C changes to dominant (low) state but CAN bus does not follow for 4 times, the transmitter will be disabled, CAN_PERM_REC (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.
CAN Permanent Dominant
If the bus state is dominant (low) for t > t
CAN
a permanent dominant status will be detected.
CAN_PERM_DOM (SR 2) will be latched and can be read and optionally cleared by SPI.
The transmitter will not be disabled.
RXDC Permanent Recessive
If RXD_C pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RXD_C does not follow TXD_C for 4 times the transmitter will be disabled. CAN_RXD_REC (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.
A 32-bit SPI is used for bi-directional communication with the microcontroller.
The SPI is driven by a microcontroller with its SPI peripheral running in following mode:
CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output pins and one input pin is needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag
(fault condition) of the device.
Chip Select Not (CSN)
The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started.
The state during CSN = 0 is called a communication frame.
If CSN = low for t > t
CSNfail
the DO output is switched to high impedance in order to not block the signal line for other SPI nodes.
Serial Data In (DI)
The input Pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register is transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN
DS11546 Rev 5
196
Application information
Note:
L99DZ100G, L99DZ100GP low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the
CSN Pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 4 MHz.
4.12.1 V
S
supply failure
V
S
overvoltage
If the supply voltages V
S
reaches the overvoltage threshold V
SOV
:
LIN remains enabled
CAN remains enabled
OUT1 to OUT_14 are turned off (default).
The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR 3) = 0)
Charge pump is disabled (and is switched on automatically in case the supply voltage recovers to normal operating voltage)
H-bridge gate driver and heater MOSFET gate driver are switched into sink condition
ECV is switched in high impedance state and ECDR is discharged by R
ECDRDIS
(to ensure the gate of the external MOSFET is discharged => EC mode considered as off)
Recovery of outputs after overvoltage condition is configurable by SPI:
– VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2).
– VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after V
S condition has recovered.
overvoltage
The overvoltage bit VS_OV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
V
S
undervoltage
If the supply voltage V
S
drops below the under voltage threshold voltage (V
SUV
):
LIN remains enabled
CAN remains enabled
OUT1 to OUT14 are turned off (default).
The shutdown of outputs may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0)
Heater MOSFET gate driver switched into sink condition
ECV is switched in high impedance state and ECDR is discharged by R
ECDRDIS
(to ensure the gate of the external MOSFET is discharged => EC mode considered as off)
Recovery of outputs after undervoltage condition is configurable by SPI:
– VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_UV (SR 2).
– VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after V
S condition has recovered.
undervoltage
The undervoltage bit VS_UV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The undervoltage bit is removed automatically if VS_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.
4.12.2 V
SREG
supply failure
V
SREG
overvoltage
If the supply voltages V
SREG
reaches the overvoltage threshold V
SREG_OV
:
LIN is switched to high impedance
CAN remains enabled
OUT15 and OUT_HS are turned off (default).
The shutdown of outputs may be disabled by SPI (V
SREG_OV_SD_EN
(CR 3) = 0)
Recovery of outputs after overvoltage condition is configurable by SPI:
– VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_OV
(SR 2).
– VSREG_LOCK_EN (CR 3) = 0: outputs turned on automatically after V
SREG overvoltage condition has recovered.
The overvoltage bit VSREG_OV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage bit is reset automatically if VSREG_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered.
DS11546 Rev 5
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Application information L99DZ100G, L99DZ100GP
V
SREG
undervoltage
If the supply voltage V
SREG
drops below the under voltage threshold voltage (V
SREG_UV
):
LIN is switched to high impedance
CAN remains enabled
OUT15 and OUT_HS are turned off (default).
The shutdown of outputs may be disabled by SPI (VSREG_UV_SD_EN (CR 3) = 0)
Recovery of outputs after undervoltage condition is configurable by SPI:
– VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_UV
(SR 2).
– VSREG_LOCK_EN (CR 3) = 0: Outputs turned on automatically after V
SREG undervoltage condition has recovered.
The undervoltage bit VSREG_UV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The undervoltage bit is removed automatically if
VSREG_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Figure 33. Thermal shutdown protection and diagnosis
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The Thermal State machine will recover the same state were it was before entering Standby mode. In case of a TSD2 it will enter TSD1 state.
DS11546 Rev 5
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Application information L99DZ100G, L99DZ100GP
Note:
The component provides a total of 6 half bridges outputs OUT1..6 to drive motors and 10 stand alone high-side outputs OUT7..15 and OUT_HS to drive e.g. LED’s, bulbs or to supply contacts. All high-side outputs beside OUT_HS and OUT15 are supplied by the pin VS and
OUT_HS and OUT15 are supplied by the buffered supply V
SREG
. OUT_HS is intended to be used as contact supply. Beside OUT15 and OUT_HS the high-side switches can be activated only in case of running charge pump. OUT15 and OUT_HS can be activated also in standby modes.
All high-side and low-side outputs switch off in case of:
V
S
(V
SREG
) overvoltage and undervoltage (depending on configuration, see
Section 4.12.2: VSREG supply failure
)
Overcurrent (depending on configuration, auto recovery mode (see below)
Overtemperature (TSD1x/ cluster or single mode)
Fail safe event
Loss of GND at SGND pin
In case of overcurrent or overtemperature (TSD1_CLx (SR 6)) condition, the drivers will switch off. The according status bit will be latched and can be read and optionally cleared by
SPI. The drivers remain off until the status is cleared. In case overvoltage/ undervoltage condition, the drivers will be switched off. The according status bit will be latched and can be read and optionally cleared by SPI. If VSREG_LOCK_EN (CR 3) respectively
VS_LOCK_EN (CR 3) are set, the drivers remain off until the status is cleared. If the
VS_LOCK_EN or VSREG_LOCK_EN) bit is set to 0, the drivers will switch on automatically if the error condition disappears. Undervoltage and overvoltage shutdown can be disabled by SPI. In case of open-load condition, the according status register will be latched. The status can be read and optionally cleared by SPI. The high and low-side outputs are not switched off in case of open-load condition.
For OUT1..OUT8 and OUT_HS the auto recovery feature (OUTx_OCR (CR 7)) can be enabled. If these bits are set to 1 the driver will automatically restart from an overload condition. This overload recovery feature is intended for loads which have an initial current higher than the overcurrent limit of the output (e.g. Inrush current of cold light bulbs). The
SPI bits OUTx_OCR_ALERT (SR4) indicate that the output reached auto-recovery condition.
The maximum voltage and current applied to the High-side Outputs is specified in the
‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to respect these limits under application conditions. In case of outputs switch off due to loss of ground at SGND pin, the device has to be re-started through a power off on both V
S
V
SREG
.
and
Each of the stand alone high-side driver outputs OUT7 … OUT15 and OUT_HS can be driven with an internally generated PWM signal, an internal Timer or with DIR1 respectively
DIR2. See table below.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Table 66. Power output settings
OUTx_3 OUTx_2 OUTx_1 OUTx_0 Description
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
1
OFF
ON
Timer1 output is controlled by timer1; starting with ON phase after timer restart
Timer2 output is controlled by timer2; starting with ON phase after timer restart
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
DIR1
DIR2
4.15 Auto-recovery alert and thermal expiration
The thermal expiration feature provides a robust protection against possible microcontroller malfunction, switching off a given channel if continuously driven in auto-recovery. If the temperature of the related cluster increases by more than 30 °C after reaching the autorecovery time t
AR
, the channel is switched off. The thermal expiration status bit
OUTx_TH_EX (SR 3) is set.
During auto-recovery condition, OUTx_OCR_ALERT (SR 4) is set. The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.
The thermal expiration feature is controlled by SPI (OUTx_OCR_THX_EN (CR 8).
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
Figure 34. Example of long auto-recovery on OUT7. Temperature acquisition starts after t
AR thermal expiration occurs after a ∆ T = 30°
,
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Figure 35. Block diagram of physical realization of AR alert and thermal expiration
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The charge pump uses two external capacitors, which are switched with f
CP
. The output of the charge pump has a current limitation. In standby mode and after a thermal shutdown has been triggered the charge pump is disabled. If the charge pump output voltage remains too low for longer than T
CP
, the power-MOS outputs and the EC-control are switched off.
The H-bridge MOSFET gate drivers and the Heater MOSFET gate driver are switched to resistive low and CP_LOW (SR 2) is set. This bit has to be cleared to reactivate the drivers.
If the bit CP_LOW_CONFIG (Configuration Register 0x3F) is set to ‘1’, CP_LOW (SR2) behaves as a ‘live’ bit and the outputs are re-activated automatically upon recovery of the charge pump output voltage.
In case of reaching the overvoltage shutdown threshold V
SOV and automatically restarted after V
S
the charge pump is disabled
recovered to normal operating voltage.
Figure 36. Charge pump low filtering and start up implementation
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DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
Each of the half bridges is built by internally connected high-side and low-side power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external freewheeling diodes. The high-side drivers OUT7 to OUT15 and OUT_HS are intended to drive resistive loads only. Therefore only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 100 μ H) an external freewheeling diode connected between GND and the corresponding output is required. The low-side driver at
ECV does not have a freewheel diode built into the device.
The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for t > t
OL_OUT load bit OUTx_OL (SR 5) is set in the status register.
the corresponding open-
An overcurrent condition is detected after a filter time of t
FOC
and is indicated by the status bit OUTx_OC (SR 3). In case of overcurrent, the corresponding driver switches off to reduce the power dissipation and to protect the integrated circuit. If the outputs are not configured in recovery mode, the microcontroller has to clear the according status bits to reactivate the corresponding drivers.
The current monitor sources a current image of the power stage output current at the current monitor pin CM, which has a fixed ratio (I
CMr
) of the instantaneous current of the selected high-side driver. The signal at output CM is blanked for t cmb
after switching on the driver until correct settlement of the circuitry. The bits CM_SELx (CR 7) define which of the outputs is multiplexed to the current monitor output CM. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an openload or overload condition. For example, it can be used to detect the motor state (starting, free running, stalled). The current monitor output is enabled after the current-monitor blanking time, when the selected output is switched on. If this output is off, the current monitor output is in high impedance mode. The current monitor can be deactivated by
CM_EN (CR 7).
4.21 PWM mode of the power outputs
Description see Section 7.3: Status register overview
.
The six half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned off, the activation of the other driver of the same half bridge will be automatically delayed by the crosscurrent protection time. After the crosscurrent
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior, it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct.
4.23 Programmable soft-start function to drive loads with higher inrush current
Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors) can be driven by using the programmable soft-start function (i.e. overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit
OUTx_OCR (CR 7). If this bit is set, the device automatically switches the outputs on again after a programmable recovery time. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency is defined by CR7<8:12> setting.
The device itself cannot distinguish between a real overload (e.g. short-circuit condition) and a load characterized by operation currents exceeding the short-circuit threshold.
Examples are non-linear loads like a light bulb used on the HS outputs or a motor used on the half bridge output with inrush and stall currents that shall be limited by the auto recovery feature.
For the bulb, a real overload condition can only be qualified by time. For overload detection the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first e.g. 50 ms. After clearing the recovery bit, the output will be switched off automatically if the overload condition remains.
For the half bridges the high current can be present during all motor activation and another
SW strategy must be applied to identify a SC to GND or Supply. Before running the motor e.g. with a first SPI command all bridge LS are switched on (without auto recovery functionality / cleared overcurrent recovery bit), all HS are switched off and a SC to Battery can be diagnosed. With a next SPI command, all HS are switched on (without auto recovery functionality/ cleared overcurrent recovery bit) and all LS are switched off. In this sequence, a short to GND can be diagnosed. If in both sequences no overload condition is identified, the motor can be run by switching on the according HS and LS each configured in auto recovery mode (see
Figure 37: Software strategy for half bridges before applying autorecovery mode
). Such sequence can be applied before any motor activation to identify SC just before operating the motor (in case the delay due to the 2 additional SPI commands is not limiting the application) or in case of power up of the system resp. applied on a certain time base.
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
Figure 37. Software strategy for half bridges before applying auto-recovery mode
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As soon as an output reaches auto-recovery condition, OUTx_OCR_ALERT (SR 4)) is set.
The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
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Application information
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The PWMH and DIRH inputs control the drivers of the external H-bridge transistors. In single Motor mode the motor direction can be chosen with the direction input (DIRH), the duty cycle and frequency with the PWMH input (single mode). With the SPI bits SD (CR 10) and SDS (CR 10) four different slow-decay modes (via drivers and via diode) can be selected using the high-side or the low-side transistors. Unconnected inputs are defined by internal pull-down current.
Alternatively, the bridge can be driven in half bridge mode (dual mode). By setting the dual mode bit DM (Config Reg) = 1, both half-bridges can be controlled independently.
DS11546 Rev 5
196
Application information
Control pins
Control bits
Table 67. H-bridge control truth table
Failure bits Output pins
L99DZ100G, L99DZ100GP
Motor config
Comment
Nb
1
6
7
8
9
10
11 x
0 x
0
1
1 x x
1
0
0
0
1
0
0
1
1
1
1
1
1 x x
0
0
0 x
1 x x
0
1
1 x
0 x
0
0
0
0
0
0 x
0
0
0
0
0
0 x
0
0
0
0
0
0 x
0
0
0
0
0
0 x
0
0
0
0
0
0 x
0
0
0
0
0
0
RL RL RL RL
2 x x 1 x x 0 1 0 0 0 0 RL RL RL RL
3 x x 1 x x 0 0 x x x 1 RL RL RL RL
4 x x 1 x x 0 0 1 0 0 0 L L L L
5 x x 1 x x 0 0 0 0 1 0 L
(1)
L
L
L
L
H
H
L
H
H
H
L
L
L
H
L
L
L
L
H
L
H
L
H
H
L
Single
H-bridge disabled
Charge pump voltage too low
Thermal shutdown
Overvoltage
Short-circuit
Bridge H2/L1 on
Slow-decay mode LS1 and
LS2 on
Slow-decay mode LS1 on
Slow-decay mode LS2 on
Bridge H1/L2 on
Slow-decay mode HS1 and
HS2 on
Slow-decay mode HS1 on
Slow-decay mode HS2 on
12 0 0 1 1 1 0 0 0 0 0 0 L L H L
13 1 0 1 1 1 0 0 0 0 0 0 H L L L
14 0 0 1 1 0 1 0 0 0 0 0 L L L L
15 0 1 1 1 0 1 0 0 0 0 0 L L L H
16 1 0 1 1 0 1 0 0 0 0 0 L H L L
17 1 1 1 1 0 1 0 0 0 0 0 L H L H
18 0 0 1 0 1 1 0 0 0 0 0 L L L L
19 0 1 1 0 1 1 0 0 0 0 0 L L H L
20 1 0 1 0 1 1 0 0 0 0 0 H L L L
21 1 1 1 0 1 1 0 0 0 0 0 H L H L
22 0 0 1 1 1 1 0 0 0 0 0 H L H L
23 0 1 1 1 1 1 0 0 0 0 0 H L L H
24 1 0 1 1 1 1 0 0 0 0 0 L H H L
25 1 1 1 1 1 1 0 0 0 0 0 L H L H
Dual Half bridge mode
1. Only the H-bridge (low-side and high-side), in which one MOSFET is in short-circuit condition is switched off. Both
MOSFETs of the other H-bridge remain active and driven by DIRH and PWMH.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
During watchdog long-open window, the H-bridge drivers are forced off until the first valid watchdog trigger in window mode (setting TRIG = 0 during safe window). The Control
Registers remain accessible during long open window.
The rising and falling slope of the drivers for the external high-side Power-MOS can be slew rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this Power-MOS is below the switch threshold. The current is programmed using the bits SLEW_x<4:0> (CR 10), which represent a binary number. This number is multiplied by the minimum current step. This minimum current step is the maximum source-/sink-current (I
GHxrmax
/ I
GHxfmax
) divided by 31. Programming
SLEW_x <4:0> to 0 disables the slew rate control and the output is driven by the lowimpedance output driver switch.
Figure 39. H-bridge GSHx slope
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The resistive output mode protects the devices and the H-bridge in the standby mode and in some failure modes (thermal shutdown TSD1 (SR 1), charge pump low CP_LOW (SR 2) and DI pin stuck at ‘1’ SPI_INV_CMD (SR 2)). When a gate driver changes into the resistive output mode due to a failure a sequence is started. In this sequence the concerning driver is
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP switched into sink condition for 32 μ s to 64 μ s to ensure a fast switch-off of the H-bridge transistor. If slew rate control is enabled, the sink condition is slew-rate controlled.
Afterwards the driver is switched into the resistive output mode (resistive path to source).
4.27 Short circuit detection / drain source monitoring
The Drain - Source voltage of each activated external MOSFET of the H-bridge is monitored by comparators to detect shorts to ground or battery. If the voltage-drop over the external
MOSFET exceeds the configurable threshold voltage V
SCd_HB t > t
SCd_HB
(DIAG_x (CR 10) for longer
the corresponding gate driver switches off the external MOSFET and the corresponding drain source monitoring flag DS_MON_x (SR 2) is set. The DSMON_x bits have to be cleared through the SPI to reactivate the gate drivers. This monitoring is only active while the corresponding gate driver is activated. If a drain-source monitor event is detected, the corresponding gate-driver remains activated for at maximum the filter time.
When the gate driver switches on, the drain-source comparator requires the specified settling time until the drain-source monitoring is valid. During this time, this drain-source monitor event may start the filter time. The threshold voltage V
SCd_HB using the SPI bits DIAG_x (CR 10).
can be programmed
Figure 40. H-bridge diagnosis
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The drain source voltages of the H-bridge driver external transistors can be monitored, while the transistors are switched off. If either bit OL_H1L2 (CR 10) or OL_H2L1 (CR 10) is set to
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
1, while bit HEN (CR 1) = 1, the H-drivers enter resistive low mode and the drain-source voltages can be monitored. Since the pull-up resistance is equal to the pull-down resistance on both sides of the bridge a voltage of 2/3 V
S
on the pull-up highside and 1/3 V
S
on the lowside is expected, if they drive a low-resistive inductive load (e.g. motor). If the drain source voltage on each of these Power-MOS is less than 1/6 V
S associated driver is set.
, the drain-source monitor bit of the
The open-load filter time is t
OL_HB
.
Figure 41. H-bridge open-load-detection (no open-load detected)
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DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
Figure 43. H-bridge open-load-detection (short to ground detected)
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S
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Table 68. H-bridge monitoring in off-mode
Control bits Failure bits
Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2
1
5
6
7
2
3
4
0
1
0
0
1
1
1
0
0
1
1
0
0
0
0
1 x
0 x
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
Comments
Drain-Source monitor disabled
No open-load detected
Open-load SH2
Short to GND
Short to VS
No open-load detected
Open-load SH1
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Table 68. H-bridge monitoring in off-mode (continued)
Control bits Failure bits
Comments
Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2
8
9
0
0
1
1
0
1
1
1
1
1
Short to GND
Short to VS
The external PowerMOSFETs transistors in H-bridge (two half-bridges) configuration are switched on with an additional delay time t cross current protection time t
CCP
CCP
to prevent cross current in the halfbridge. The
can be programmed with the SPI bits COPT_x<3:0>
(CR 10). The timer is started when the gate driver is switched on in the device.
The PWMH module has 2 timers to configure locking time for high-side and freewheeling low-side. The programmable time t in PWM mode is the following:
CCP-TIM1
/ t
CCP-TIM2
is the same. Sequence for switching
HS switch off after locking t
CCP-TIM1
LS switch on after 2nd locking t
CCP-TIM1
HS switch on after locking t
CCP-TIM2
which starts with rising edge on PWM input
Figure 45. PWMH cross current protection time implementation
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The two LS Switches LS1_FSO and LS2_FSO are intended to be used to switch off the gates of the external high-side MOSFETs in the power window h-bridge if a fatal error happens. This block must work also in case the MOSFET driver and the according control blocks on the chip are destroyed. Therefore it is necessary to have a complete separated safety block on the device, which has it’s own supply and GND connection, separated from the other supplies and GNDs. In the block is implemented an own voltage regulator and oscillator.
The safety block is surrounded by a GND isolation ring realized by deep trench isolation.
The LS driver must work down to a lower voltage than the other circuits. The block has its
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP own internal supply and an own oscillator for monitoring the failure signals (WWD, V1 fail,
SPI fail & Tj) which are Manchester encoded and decoupled by high ohmic resistances. In case of fail-safe event, both LS switches LS1_FSO and LS2_FSO are switched on.
In case of entering V1_standby mode or Vbat_standby mode both fail safe low-side switches are switched on to minimize the current drawn by the fail safe block (e.g. oscillator is switched off and Manchester Encoding is deactivated). Short circuit protection to V
S active in both standby modes limiting the current to I
OLimit
for a filter of t
SCF
.
is
After this filter time the fail-safe switches are switched off and LSxFSO_OC (SR 3) is set. To reactivate the low-side functionality this bit has to be set back by a read and clear command.
In case of V
S
loss the fail safe switches are biased by their own output voltage to turn on the low-side switches down to VOUT_max.
To allow verification of the Fail-Safe path, the low-side switches LS1_FSO and LS2_FSO can be turned on by SPI (Configuration Register 0x3F bit 4: FS_FORCED)
Figure 46. LSx_FSO: low-side driver “passively” turned on, taking supply from output pin (if main supply fails), can guarantee V
LSx_FSO
< V
OUT_max
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DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
The Heater MOSFET Driver stage is controlled by control bit GH (CR 5). The driver contains two diagnosis features to indicate short-circuit in active mode (external MOSFET switched on) and open-load in off state (External MOSFET switched off).
Short circuit detection in on state is realized by monitoring the drain source voltage of the activated external MOSFET by a comparator to detect a short-circuit of SH heater to ground. If the voltage-drop over the external MOSFET exceeds the programmed threshold voltage
V
SCd_HE
for longer than the drain-source monitor filter time t
SCd_HE
the gate driver switches off the external MOSFET and the corresponding drain source monitoring flag
DSMON_HEAT (SR 4) is set. The drain source-monitoring bit has to be cleared by SPI to reactivate the gate driver. The drain source monitoring is only active while the gate driver is activated. If a drain source monitoring event is detected, the gate-driver remains activated for the maximum filter time. The threshold voltage can be programmed by SPI bits GH_THx
(CR 10).
Open-load detection in off state is realized by monitoring the voltage difference between
SH heater
and GND and supplying SH heater
by a pull up current source that can be controlled by SPI bit GH_OL_EN (CR 10). When no load is connected to the external MOSFET source, the voltage will be pulled to V
S set. and in case of exceeding the threshold V a time longer than the open-load filter time t
OL_He
OLheater
for
the open-load bit GH_OL (SR 5) will be
Figure 48. Heater MOSFET open-load and short-circuit to GND detection
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DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
5
6
7
3
4
1
2
Nb
Control bit
GH
ON/OFF x
1
0 x
1 x x
CP_LOW VS_OV VS_UV DS
1
0
0
0
0
0
0
Table 69. Heater MOSFET control truth table x x
1
0
0
0
0
Failure bits x x x x
1
0
0
0
0
0 x
1 x x
TSD1
0
0
0
0
0 x
1
Output pin
GH heater
L
H
L
RL
RL
L
L
Comment
Charge puump voltage too low
Thermal shutdown
Overload
Short-circuit condition
Undervoltage
Heater MOFET driver enabled
Heater MOFET driver enabled
Note: RL = resistive low, L = active low, H = active high.
4.32 Controller of electro-chromic glass
The voltage of an electro-chromic element connected at pin ECV can be controlled to a target value, which is set by the bits EC_x <5:0> (CR 11). Setting bit ECON (CR 11) enables this function. An on-chip differential amplifier and an external MOS source follower, with its gate connected to pin ECDR, and which drives the electro-chrome mirror voltage at pin
ECV, form the control loop. The drain of the external MOS transistor is supplied by OUT10.
A diode from pin ECV (anode) to pin ECDR (cathode) has been placed on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to be added to pin
ECDR for loop-stability.
The target voltage is binary coded with a full-scale range of 1.5 V. If bit ECV_HV (Config
Reg) is set to 0, the maximum controller output voltage is clamped to 1.2 V without changing the resolution of bits EC_x<5:0> (CR 11). When programming the ECV low-side driver
ECV_LS (CR 11) to on-state, the voltage at pin ECV is pulled to ground by a 1.6 Ω low-side switch until the voltage at pin ECV is less than d
VECVhi
higher than the target voltage (fast discharge). The status of the voltage control loop is reported via SPI. Bit ECV_VHI (SR 6) is set, if the voltage at pin ECV is higher, whereas Bit ECV_VNR (SR 6) is set, if the voltage at pin ECV is lower than the target value. Both status bits are valid, if they are stable for at least the filter time t
FEC_VNR
and t
FEC_VHI
. Since OUT10 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched off). In electro-chrome mode, OUT10 cannot be controlled by PWM mode. For EMS reasons, the loop capacitor at pin ECDR as well as the capacitor between ECV and GND has to be placed to the respective pins as
close as possible (see Figure 49: Electro-chrome control block
for details).
Pin ECDR is pulled resistively (R
ECDRDIS
) to ground while not in electro-chrome mode.
EC glass control behavior in case of failure on OUT10:
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
ECON (CR11) = 1 (EC glass control enabled)
OUT10 is turned ON
OUT10 settings in CR5 are ignored (PWM, DIRx, TIMERx)
OUT10 settings in CR5 are recovered when ECON is set to 0.
In case of a failure on OUT10 while ECON = 1 (overcurrent, V
S
TSD1)
overvoltage /undervoltage,
OUT10 is turned OFF (regardless of VS_OV_SD_EN and VS_UV_SD_EN in CR3)
DAC is reset: EC_x (CR11) set to ‘000000’
ECDR pin is pulled to GND
ECON (CR11) remains ‘1’
ECV_LS (CR11) remains as programmed
Re-start of EC control after OUT10 failure
Read&Clear or automatic restart (if CR3 Vs_LOCK_EN = 0)
Write EC_x (CR11)
Figure 49. Electro-chrome control block
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If any of the cluster (see Section 4.34: Thermal clusters ) junction temperatures rises above
the temperature warning threshold TW, the temperature warning flag TW (SR 2) is set after the temperature warning filter time t jtft
and can be read via SPI. If the junction temperature increases above the temperature shutdown threshold (TSD1), the thermal shutdown bit
TSD1 (SR 1) is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter time. The gates of the H-bridge and the heater
MOSFET are discharged by the ‘Resistive Low’ mode. After these bits have been cleared, the output stages are reactivated. If the temperature is still above the thermal warning threshold, the thermal warning bit is set after t jtft
. Once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after t jtft
and
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP the outputs are switched off. Therefore the minimum time after which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermal shutdown threshold is twice the thermal warning/ thermal shutdown filter time t jtft
.
Note:
In order to provide an advanced on-chip temperature control, the power outputs are grouped in six clusters with dedicated thermal sensors. The sensors are suitably located on the device (see
Figure 50: Thermal clusters identification ). In case the temperature of an
output cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster are shut down (all other outputs remain active). Each output cluster has a dedicated temperature warning and shutdown flag (SR 6) and the cluster temperature can be read out by SPI.
Hence, the thermal cluster concept allows to identify a group of outputs in which one or more channels are in overload condition.
If thermal shutdown has occurred within an output cluster, or if temperature is rising within a cluster, it may be desired to identify which of the output (s) is (are) determining the temperature increase. An additional evaluation, based on current monitoring and cluster temperature read-out, supports identification of the outputs mainly contributing to the temperature increase. The cluster temperatures are available in SR 7, SR 8 and SR 9 and can be calculated from the binary coded register value using the following formula:
Decimal code = (350 – Temp) / 0.488
Example:
T = -40 °C => decimal code is 799 (0x31F)
T = 25 °C => decimal code is 666 (0x29A)
Thermal clusters can be configured using bit TSD_CONFIG (Config Reg):
Standard mode (default): as soon as any cluster reaches thermal threshold the device is switched off. V1 regulator remains on and is switched off reaching TSD2.
Cluster mode: only the cluster which reached shutdown temperature is switched off.
If Cluster Th_CL6 (global) or Cluster Th_CL5 (Voltage Regulators) reachTSD1, the whole device is OFF (beside V1).
Clusters related to power outputs (clusters 1 to 4, see
Figure 50: Thermal clusters identification
) will be managed digitally only, by mean of the ADC conversion of related thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators) since ADC can be off, e.g. in V1_standby mode. Temperature reading provided by ADC may differ from real junction temperature of a specific output due to spatial placement of thermal sensor. Such an effect is more visible during fast thermal increases of junction temperature.
For some of the Power outputs, located between two different sensors, it may happen that temperature raising also affects the adjacent Cluster.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Figure 50. Thermal clusters identification
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Table 70. Thermal cluster definition
Th_CL3 Th_CL4
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TW & TSD1 Both digitally managed
TW & TSD1 Both digitally managed
TW & TSD1 Both digitally managed
TW & TSD1 Both digitally managed
Th_CL5
VREG 1
VREG 2
TW digitally managed
TSD1 & TSD2
Both analog managed
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TSD1 Analog managed
4.35 V
S
compensation (duty cycle adjustment) module
All stand-alone HS outputs can be programmed to calculate some internal duty cycle adjustment to adapt the duty cycle to a changing supply voltage at V
S
. This feature is aimed to avoid LED brightness flickering in case of alternating supply voltage. The correction of the duty cycle is based on the following formula:
Equation 1: Duty cycle correction
DutyCycle =
V
V
Bat
–
–
V
V
LED
DC nom
V th
= Duty cycle reference voltage: defined as 10 V
DS11546 Rev 5
196
Application information L99DZ100G, L99DZ100GP
V
Bat
= Reference voltage: defined as voltage at pin VS
V
LED
= Voltage drop on the external LED
DC nom
= Nominal Duty Cycle programmed by SPI< PWMx DCx>
To be compatible to different LED load characteristics the value for V
LED
can be programmed for each output by a dedicated control register OUT7_VLED …
OUT_HS_VLED (CR 18 to CR 22). Auto compensation features can be activated for all HS outputs each by setting OUTx_AUTOCOMP_EN (CR 18 to CR 22).
The programmed LED voltage (OUTx_V_LED (CR18 to CR22)) must be lower than V th
(10 V).
Figure 51. Block diagram V
S
compensation (duty cycle adjustment) module
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4.36 Analog digital converter
Voltage signals V
S
, V
SREG
, V
WU
and TH_CL1..6 are read out sequentially. The voltage signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, that is sampled with the main clock f clk2
/ f
ADC
.
Each channel will be converted with a conversion time tcon, therefore an update of the ADC value is available every t con
* 9. In case of WU is directly connected to Clamp 30, the input must be protected by a series resistance of typical 1k Ω to sustain reverse battery condition.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Application information
Figure 52. Sequential ADC Read Out for V
SREG
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DS11546 Rev 5
196
Serial Peripheral Interface (SPI)
5 Serial Peripheral Interface (SPI)
Note:
L99DZ100G, L99DZ100GP
A 32-bit SPI is used for bi-directional communication with the microcontroller.
The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output Pins and one input
Pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin will reflect the global error flag (fault condition) of the device.
Chip Select Not (CSN)
The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame. If CSN = low for t > t
CSNfail
the DO output will be switched to high impedance in order to not block the signal line for other SPI nodes.
Serial Data In (DI)
The input Pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the
CSN Pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 4 MHz.
The ST-SPI is a standard used in ST Automotive ASSP devices.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI)
This chapter describes the SPI protocol standardization. It defines a common structure of the communication frames and defines specific addresses for product and status information.
The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular product. In addition, failsafe mechanisms are implemented to protect the communication from external influences and wrong or unwanted usage.
The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0.
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Chip Select Not (CSN)
The communication interface is de-selected, when this input signal is logically high. A falling edge on CSN enables and starts the communication while a rising edge finishes the communication and the sent command is executed when a valid frame was sent.
During communication start and stop the Serial Clock (SCK) has to be logically low.
The Serial Data Out (SDO) is in high impedance when CSN is high or a communication timeout was detected.
Serial Clock (SCK)
This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are shifted out to Serial Data Out
(SDO).
Serial Data Input (SDI)
This input is used to transfer data serially into the device. Data is latched on the rising edge of Serial Clock (SCK).
Serial Data Output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK).
DS11546 Rev 5
196
Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP
Figure 54. SDO pin
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The ST-SPI can be driven by a microcontroller with its SPI peripheral running in following mode:
CPOL = 0
CPHA = 0
Figure 55. SPI signal description
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The communication frame starts with the falling edge of the CSN (Communication Start).
SCK has to be low.
The SDI data is then latched at all following rising SCK edges into the internal shift registers.
After Communication Start the SDO will leave 3-state mode and present the MSB of the data shifted out to SDO. At all following falling SCK edges data is shifted out through the internal shift registers to SDO.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI)
The communication frame is finished with the rising edge of CSN. If a valid communication took place (e.g. correct number of SCK cycles, access to a valid address), the requested operation according to the Operating Code will be performed (Write or Clear operation).
SDI Frame
The devices Data-In Frame consist of 32-bit (OpCode (2 bits) + Address (6 bits) + Data Byte
3 + Data Byte 2 + Data Byte 1). The first two transmitted bits (MSB, MSB-1) contain the
Operation Code which represents the instruction which will be performed. The following 6 bits (MSB-2 to MSB-7) represent the address on which the operation will be performed. The subsequent bytes contain the payload.
Figure 56. SDI Frame
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Operating code
The operating code is used to distinguish between different access modes to the registers of the slave device.
OC1
1
1
0
0
OC0
0
1
0
1
Table 71. Operation codes
Description
Write Operation
Read Operation
Read & Clear Operation
Read Device Information
A Write Operation will lead to a modification of the addressed data by the payload if a write access is allowed (e.g. Control Register, valid data). Beside this a shift out of the content
(data present at Communication Start) of the registers is performed.
A Read Operation shifts out the data present in the addressed register at Communication
Start. The payload data will be ignored and internal data will not be modified. In addition a
Burst Read can be performed.
DS11546 Rev 5
196
Serial Peripheral Interface (SPI)
Note:
Note:
L99DZ100G, L99DZ100GP
A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by address, second by payload bits set to ‘1’. Beside this a shift out of the content (data present at Communication Start) of the registers is performed.
Status registers which change status during communication could be cleared by the actual
Read & Clear Operation and are neither reported in actual communication nor in the following communications. To avoid a loss of any reported status it is recommended just clear status registers which are already reported in the previous communication (Selective
Bitwise Clear).
Advanced operation codes
To provide beside the separate write of all control registers and the bitwise clear of all status registers, two Advanced Operation Codes can be used to set all control registers to the default value and to clear all status registers. A ‘set all control registers to default’ command is performed when an OpCode ‘11’ at address b’111111 is performed.
Please consider that potential device specific write protected registers cannot be cleared with this command as therefore a device Power-on-Reset is needed.
A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.
Data-in payload
The Payload (Data Byte 1 to Data Byte 3) is the data transferred to the devices with every
SPI communication. The Payload always follows the OpCode and the Address bits. For
Write access the Payload represents the new data written to the addressed register. For
Read & Clear operations the Payload defines which bits of the adressed Status Register will be cleared. In case of a ‘1’ at the corresponding bit position the bit will be cleared.
For a Read Operation the Payload is not used. For functional safety reasons it is recommended to set unused Payload to ‘0’.
SDO frame
The data-out frame consists of 32-bit (GSB + Data Byte 1 to 3).
The first eight transmitted bits contain device related status information and are latched into the shift register at the time of the Communication Start. These 8-bit are transmitted at every
SPI transaction. The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK edge. This could lead to an inconsistency of data between the GSB and Payload due to different shift register load times. Anyhow, no unwanted Status Register clear should appear, as status information should just be cleared with a dedicated bit clear after.
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI)
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Global Status Byte (GSB)
The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the Status
Registers. Therefore no direct Read & Clear can be performed on these bits inside the GSB.
Bit 31
GSBN
Bit 30
RSTB
Table 72. Global Status Byte
Bit 29 Bit 28 Bit 27 Bit 26
SPIE PLE FE DE
Bit 25
GW
Bit 24
FS
Global Status Bit Not (GSBN)
The GSBN is a logically NOR combination of Bit 24 to Bit 30. This bit can also be used as
Global Status Flag without starting a complete communication frame as it is present directly after pulling CSN low.
Reset Bit (RSTB)
The RSTB indicates a device reset. In case this bit is set, specific internal Control Registers are set to default and kept in that state until the bit is cleared. The RSTB bit is cleared after a Read & Clear of all the specific bits in the Status Registers which caused the reset event.
SPI Error (SPIE)
The SPIE is a logical OR combination of errors related to a wrong SPI communication.
Physical Layer Error (PLE)
The PLE is a logical OR combination of errors related to the LIN and HS CAN transceivers.
Functional Error (FE)
The FE is a logical OR combination of errors coming from functional blocks (e.g. High-side overcurrent).
Device Error (DE)
The DE is a logical OR combination of errors related to device specific blocks (e.g. VS overvoltage, overtemperature
DS11546 Rev 5
196
Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP
Global Warning (GW)
The GW is a logical OR combination of warning flags (e.g. thermal warning).
Fail Safe (FS)
The FS bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal errors (e.g. Watchdog failure, Voltage regulator failure).
Data-Out Payload
The Payload (Data Bytes 1 to 3) is the data transferred from the slave device with every SPI communication to the master device. The Payload always follows the OpCode and the address bits of the actual shifted in data (In-frame-Response).
OC1
0
0
1
Table 73. Device application access
Operating Code
OC0
0
1
0
RAM Address
32H
31H
…
22H
3FH
3CH
…
1DH
…
02H
OC1
1
Table 74. Device information read access
Operating Code
OC0
1
Table 75. RAM address range
Description
Configuration Register
Status Register 12
…
Status Register 2
Status Register 1
…
Control Register 34
Control Register 29
…
Control Register 2
Access
R/C
R/C
R/W
R/W
R/C
R/W
R/W
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI)
RAM Address
Table 75. RAM address range (continued)
Description
01H
00H
Control Register 1 reserved
Access
R/W
ROM Address
0AH
…
06H
05H
12H
11H
10H
…
04H
03H
02H
01H
00H
16H
15H
14H
13H
3FH
3EH
…
20H
Table 76. ROM address range
Description
<Advanced Op.>
<GSB Options>
<SPI CPHA test>
<WD bit pos. 4>
<WD bit pos. 3>
<WD bit pos. 2>
<WD bit pos. 1>
<WD Type 2>
<WD Type 1>
<SPI mode>
<Silicon Ver.>
<Device No.5>
<Device No.4>
<Device No.3>
<Device No.2>
<Device No.1>
<Device Family>
<Company Code>
R
R
R
R
R
R
R
Access
R
R
R
R
W
R
R
R
R
R
R
Information registers
The Device Information Registers can be read by using OpCode ‘11’. After shifting out the
GSB the 8-bit wide payload will be transmitted. By reading Device Information Registers a communication width which is minimum 16-bit plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the
SDO.
DS11546 Rev 5
196
Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP
06H
05H
04H
03H
02H
01H
00H
ROM
Adress
13H
12H
11H
10H
…
0AH
…
3FH
3EH
…
20H
16H
15H
14H
Description
<Advanced Op.>
<GSB Options>
<SPI CPHA test>
<WD bit pos. 4>
<WD bit pos. 3>
<WD bit pos. 2>
<WD bit pos. 1>
<WD Type 2>
<WD Type 1>
<SPI mode>
<Silicon Ver.>
<Device No.5>
<Device No.4>
<Device No.3>
<Device No.2>
<Device No.1>
<Device Family>
<Company Code>
Table 77. Information Registers Map
Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
R
R
R
R
R
R
R
→
→
→
→
→
→
→
→
→
→
→
→
R
R
R
R
R
R
R
R
R
→
→
→
→
→
→
0
0
0
1
0
0
0
1
0
0
0
1
0
0
C0H
7FH
C0H
41H
91H
28H
B0H major revision minor revision
L99DZ100G: 01H
L99DZ100GP: 00H
09H
46H
42H
55H
01H
00H
0
1
Device Identification Registers
These registers represent a unique signature to identify the device and silicon version.
<Company Code>: 00H (STMicroelectronics)
<Device Family>: 01H (BCD Power Management)
<Device No. 1>: 55H
<Device No. 2>: 42H
<Device No. 3>: 46H
<Device No. 4>: 09H
<Device No. 5>: for L99DZ100G: 01H for L99DZ100GP: 00H
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI)
SPI modes
By reading out the <SPI mode> register general information of SPI usage of the Device
Application Registers can be read.
Bit 7
BR
1
Bit 6
DL2
0
Bit 5
Table 78. SPI Mode Register
Bit 4 Bit 3 Bit 2
DL1
1
DL0
1
0
0
0
0
Bit 1
S1
0
Bit 0
S0
0
<SPI mode>: B0H (Burst mode read available, 32-bit, no data consistency check)
SPI Burst Read
Bit 7
0
1
Table 79. Burst Read Bit
Description
BR not available
BR available
The SPI Burst Read bit indicates if a burst read operation is implemented. The intention of a
Burst Read is e.g. used to perform a device internal memory dump to the SPI Master.
The start of the Burst Read is like a normal Read Operation. The difference is, that after the
SPI Data Length the CSN is not pulled high and the SCK will be continuously clocked. When the normal SCK max count is reached (SPI Data Length) the consecutive addressed data will be latched into the shift register. This procedure is performed every time when the SCK payload length is reached.
In case the automatic incremented address is not used by the device, undefined data is shifted out. An automatic address overflow is implemented when address 3FH is reached.
The SPI Burst Read is limited by the CSN low timeout.
SPI Data Length
The SPI Data Length value indicates the length of the SCK count monitor which is running for all accesses to the Device Application Registers. In case a communication frame with an
SCK count not equal to the reported one will lead to a SPI Error and the data will be rejected.
DS11546 Rev 5
196
Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP
Bit 6
DL2
0
0
0
0
1
Table 80. SPI Data Length
Bit 5
DL1
0
0
1
1
1
Bit 4
DL0
0
1
0
1
1
Description
N/A
Data Consistency Check (Parity/CRC)
Bit 1
1
1
S1
0
0
Table 81. Data Consistency Check
Bit 0
S0
0
1
0
1
Description not used
Parity used
CRC used
Invalid invalid
16-bit SPI
24-bit SPI
32-bit SPI
…
64-bit SPI
Watchdog Definition
In case a watchdog is implemented the default settings can be read out via the Device
Information Registers .
<WD Type 1/2>
Bit 7
WD1
0
Table 82. WD Type/Timing
Bit 6 Bit 5 Bit 4 Bit 3
WD0
0
Bit 2
Register is not used
Bit 1 Bit 0
<WD Type 1> 0 1
1
<WD Type 2> 1
1
0
0
WT5
1
WT4
0
WT3
1
WT2
0
WT1
0
WT0
0
Watchdog Timeout / Long Open Window WT[5:0] * 5ms
OW2
0
OW1
1
OW0
0
Open Window OW[2:0] *
5ms
CW2
0
CW1
0
CW0
1
Closed Window CW[2:0] *
5ms
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI)
Bit 7
Table 82. WD Type/Timing (continued)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
<WD Type 1/2> 1 1 Invalid
<WD Type 1>: 28H (Long Open Window: 200ms)
<WD Type 2>: 91H (Open Window. 10ms, Closed Window: 5ms)
<WD Type 1> indicates the Long Open Window (timeout) which is opened at the start of the watchdog. The binary value of WT[5:0] times 5ms indicates the typical value of the Timeout
Time.
<WD Type 2> describes the default timing of the window watchdog.
The binary value of CW[2:0] times 5ms defines the typical Closed Window time and OW[2:0] times 5ms defines the typical Open Window time.
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The watchdog trigger bit location is defined by the <WD bit pos. X> registers.
<WD bit pos. X>
Bit 7
WB1
0
Table 83. WD bit position
Bit 6 Bit 5 Bit 4 Bit 3
WB0
0
Bit 2
Register is not used
Bit 1 Bit 0
<WD bit pos. X>
<WD bit pos. 1>
<WD bit pos. 3>
<WD bit pos. X>
0
0
0
1
1
1
1
0
WBA5 WBA4 WBA3 WBA2 WBA1 WBA0
0
1
0
1
0
1
0
1
0
1
1
1
Defines the register addresses of the WD trigger bits
WBA5 WBA4 WBA3 WBA2 WBA1 WBA0
DS11546 Rev 5
196
Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP
Bit 7
Table 83. WD bit position (continued)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Defines the stop address of the address range (previous
<WD bit pos. X> is a WB = ‘01’). The consecutive <WD bit pos. X> has to be a WB = ‘11’
<WD bit pos. X>
<WD bit pos. 2>
<WD bit pos. 4>
1
1
1
1
1
1
0
0
0
WBP 4 WBP3 WBP2 WBP1 WBP0
0 0 0 0 0
0 0 0 0 0
Defines the binary bit position of the WD trigger bit within the register
< WD bit pos 1>: 41H;watchdog trigger bit located at address 01H ( CR1 )
<WD bit pos 2>: C0H; watchdog trigger bit location is bit0
<WD bit pos 3>: 7FH;watchdog trigger bit located at address 3FH (Config Register)
<WD bit pos 4>: C0H; watchdog trigger bit location is bit0
Device Application Registers (RAM)
The Device Application Registers are all registers accessible using OpCode ‘00’, ‘01’ and
‘10’. The functions of these registers are defined in the device specification.
To realize a protocol which covers certain failsafe requirements a basic set of failure detection mechanisms are implemented.
Clock monitor
During communication (CSN low to high phase) a clock monitor counts the valid SCK clock edges. If the SCK edges do not correlate with the SPI Data Length an SPIE is reported with the next command and the actual communication is rejected.
By accessing the Device Information Registers (OpCode = ‘11’) the Clock Monitor is set to a minimum of 16 SCK edges plus a multiple by 8 (e.g. 16, 25, 32, …). Providing no SCK edge during a CSN low to high phase is not recognized as an SPIE. For a SPI Burst Read also the SPI Data Length plus multiple numbers of Payloads SCK edges are assumed as a valid communication.
SCK Polarity (CPOL) check
To detect the wrong polarity access via SCK the internal Clock monitor is used. Providing first a negative edge on SCK during communication (CSN low to high phase) or a positive edge at last will lead to an SPI Error reported in the next communication and the actual data is rejected.
SCK Phase (CPHA) check
To verify, that the SCK Phase of the SPI master is set correctly a special Device Information
Register is implemented. By reading this register the data must be 55H. In case AAH is read
DS11546 Rev 5
L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) the CPHA setting of the SPI master is wrong and a proper communication cannot be guaranteed.
CSN timeout
By pulling CSN low the SDO is set active and leaves its 3-state condition. To ensure communication between other SPI devices within the same bus even in case of CSN stuck at low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After timer end is reached the actual communication is rejected and the SDO is set to 3-state condition.
SDI stuck at GND
As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be distinguished between a valid command and a SDI stuck at GND this communication is not allowed. Nevertheless, in case a stuck at GND is detected the communication will be rejected and the SPIE will be set with the next communication.
SDI stuck at HIGH
As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be distinguished between a valid command and a SDI stuck at HIGH this communication is not allowed. In case a stuck at HIGH is detected the communication will be rejected and the
SPIE will be set with the next communication.
SDO stuck @
The SDO stuck at GND and stuck at HIGH has to be detected by the SPI master. As the definition of the GSB guarantees at least one toggle, a GSB with all-‘0’ or all –‘1’ reports a stuck at error.
DS11546 Rev 5
196
Application
6 Application
L99DZ100G, L99DZ100GP
Figure 59. Typical application diagram
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DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
7.1 Global Status Byte GSB
Bit name
Reset
Access
31
Table 84. Global Status Byte (GSB)
30 29 28 27
GSBN
1
RSTB
0
SPIE
0
PLE
0
R
FE
0
26
DE
0
25
GW
0
24
FS
0
Bit
31
30
29
Name
GSBN
RSTB
SPIE
(2)
Table 85. GSB signals description
Description
Global Status Bit Inverted
The GSBN is a logically NOR combination of GSB Bits 24 to Bit 30
(1)
.
This bit can also be used as Global Status Flag without starting a complete communication frame as it is present at SDO directly after pulling CSN low.
0: error detected (1 or several GSB bits from 24 to 30 are set)
1: no error detected (default after Power-on)
Specific failures may be masked in the Configuration Register 0x3F. A masked failure will still be reported in the GSB by the related failure flag, however it is not reflected in the GSBN (bit 31).
Reset
The RSTB indicates a device reset and it is set in case of the following events:
– VPOR (SR1 - 0x31)
– WDFAIL (SR1 - 0x31)
– V1UV (SR1 - 0x31)
– FORCED_SLEEP_TSD2/V1SC (SR1 - 0x31)
0: no reset signal has been generated (default)
1: Reset signal has been generated
RSTB is cleared by a Read & Clear command to all bits in Status Register 1 causing the Reset event.
SPI Error Bit
The SPIE indicates errors related to a wrong SPI communication.
– SPI_INV_CMD (SR2 - 0x32)
– SPI_SCK_CNT (SR2 - 0x32)
The bit is also set in case of an SPI CSN Time-out detection
0: no error (default)
1: error detected
SPIE is cleared by a valid SPI command.
DS11546 Rev 5
196
SPI Registers
Bit
28
27
L99DZ100G, L99DZ100GP
Name
FE
Table 85. GSB signals description (continued)
Description
Physical Layer Error
The PLE is a logical OR combination of errors related to the LIN and CAN transceivers.
– LIN_PERM_DOM (SR2 - 0x32)
– LIN_TXD_DOM (SR2 - 0x32)
– LIN_PERM_REC (SR2 - 0x32)
– CAN_RXD_REC (SR2 - 0x32)
– CAN_PERM_REC (SR2 - 0x32)
– CAN_PERM_DOM (SR2 - 0x32)
– CAN_TXD_DOM (SR2 - 0x32)
– SYSERR (SR12 - 0x3C)
– OSC_FAIL (SR12 - 0x3C)
– FDERR (SR12 - 0x3C)
0: no error (default)
1: error detected
PLE is cleared by a Read & Clear command to all related bits in Status
Registers 2 and 12 .
Functional Error Bit
The FE is a logical OR combination of errors coming from functional blocks.
– V2SC (SR2 - 0x32)
– DSMON_HSx (SR2 - 0x32)
– DSMON_LSx (SR2 - 0x32)
– OUTxHS_OC TH EX (SR3 - 0x33)
– OUTxLS_OC TH EX (SR3 - 0x33)
– OUTHS_OC TH EX (SR3 - 0x33)
– OUTx_OC (SR3 - 0x33)
– LSxFS_OC (SR3 - 0x33)
– ECV_OC (SR4 - 0x34)
– DSMON_HEAT (SR4 - 0x34)
– OUTxHS_OL (SR5 - 0x35) (3)
– OUTxLS_OL (SR5 - 0x35)
– OUTx_OL (SR5 - 0x35)
– OUTHS_OL (SR5 - 0x35)
– GH_OL (SR5 - 0x35)
– ECV_OL (SR5 - 0x35)
0: no error (default)
1: error detected
FE is cleared by a Read & Clear command to all related bits in Status
Registers 2, 3, 4, 5
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
26
25
SPI Registers
Name
DE
Table 85. GSB signals description (continued)
Description
Device Error Bit
DE is a logical OR combination of global errors related to the device.
– VS_OV (SR2 - 0x32)
– VS_UV (SR2 - 0x32)
– VSREG_OV (SR2 - 0x32)
– VSREG_UV (SR2 - 0x32)
– CP_LOW (SR2 - 0x32)
– TSD1_CLx (SR6 - 0x36)
0: no error (default)
1: error detected
DE is cleared by a Read & Clear command to all related bits in Status
Registers 2 and 6
Global Warning Bit
GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions.
– VSREG_EW (SR2 - 0x32)
– V1_FAIL (SR2 - 0x32)
– V2_FAIL (SR2 - 0x32)
– CAN_SUP_LOW (SR2 - 0x32)
– TW
– SPI_INV_CMD (SR2 - 0x32)
– SPI_SCK_CNT (SR2 - 0x32)
0: no error (default)
1: error detected
GW is cleared by a Read & Clear command to all related bits in Status
Register 2.
DS11546 Rev 5
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SPI Registers L99DZ100G, L99DZ100GP
Bit Name
Table 85. GSB signals description (continued)
Description
24 FS
Fail Safe
The FS bit indicates the device was forced into a safe state due to the following failure conditions:
– WDFAIL (SR1 - 0x31)
– V1UV (SR1 - 0x31)
– TSD2 (SR1 - 0x31)
– FORCED_SLEEP_TSD/V1SC (SR1 - 0x31)
All Control Registers are set to default except the following bits:
– SWEN (CR1 - 0x01)
– CR23 (0x17) to CR29 (0x1D); Configuration of CAN Selective Wake-up functionality
Control Registers are blocked for WRITE access except the following bits:
– TRIG (CR1 - 0x01)
– V2_0 (CR1 - 0x01)
– V2_1 (CR1 - 0x01)
– GoTRXRDY (CR1 - 0x01)
– Timer settings (bits 8…23) (CR2 - 0x02)
– OUTHS_x (bits 0…3) (CR5 - 0x05)
– OUT15_x (bits 0…3) (CR6 - 0x06)
– CR12 (0x0C) to CR17 (0x11); PWM frequency and duty cycles
0: Fail Safe inactive (default)
1: Fail Safe active
FS is cleared upon exit from Fail-Safe mode (refer to chapter ‘Fail-Safe mode’)
1. Individual failure flags may be masked in the Configuration Register (0x3F).
2. Bit may be masked in the Configuration Register (0x3F), i.e. the bit will not be included in the Global Status
Bit (GSBN).
3. Open-load status flags may be masked in the Configuration register (0x3F), i.e. the open-load flag will be included in the FE flag, but will not set the GSBN. TW failure status flags may be masked in the
Configuration register (0x3F), i.e. the TW flag will be included in the GW flag, but will not set the GSBN.
DS11546 Rev 5
0x02 CR2
0x03 CR3
0x04 CR4
0x05 CR5
0x06 CR6
0x07 CR7
L99DZ100G, L99DZ100GP
7.2 Control register overview
Table 86. Control register overview
Bit
SPI Registers
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 reserved
0x01 CR1
Reserved
DS11546 Rev 5
196
SPI Registers
Table 86. Control register overview (continued)
Bit
L99DZ100G, L99DZ100GP
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x08 CR8 Reserved
0x09 CR9
0x0A CR10
0x0B CR11
0x0C CR12
0x0D CR13
0x0E CR14
0x0F CR15
Reserved
Reserved Reserved
DS11546 Rev 5
Reserved
L99DZ100G, L99DZ100GP
Table 86. Control register overview (continued)
Bit
SPI Registers
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x10 CR16
0x11 CR17
0x12 CR18
0x13 CR19
0x14 CR20
DS11546 Rev 5
196
SPI Registers
Table 86. Control register overview (continued)
Bit
L99DZ100G, L99DZ100GP
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x15 CR21
0x16 CR22
0x17 CR23 Reserved
0x18 CR24
0x19 CR25 Reserved
0x1A CR26
0x1B CR27
Reserved
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Table 86. Control register overview (continued)
Bit
SPI Registers
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x1C CR28
0x1D CR29
0x22 CR34
0x3F
Conf
Reg
Reserved
Reserved
Note: All reserved bits (RES) are read-only (R) and will be read as ‘0’. Writing ‘1’ to a reserved bit is ignored and does not cause an SPI error.
DS11546 Rev 5
196
0x32 SR2
0x33 SR3
0x34 SR4
0x35 SR5
SPI Registers L99DZ100G, L99DZ100GP
7.3 Status register overview
Table 87. Status register overview
Bit
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x31 SR1 OR R
Reserved R
R
R
SO_OC R
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
Table 87. Status register overview
Bit
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x36 SR6 Reserved
_CL1 R
0x37 SR7
0x38 SR8
0x39 SR9
0x3A SR10
0x3B SR11
0x3C SR12
Reserved
R
R
R
R
R
R
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
7.4.1 Control Register CR1 (0x01)
Table 88. Control Register CR1
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 1 0 0
R R/W R R/W
0
R
0 0 0 0 0 1 1 1 0 0 0
R/W
0 0 0 0 0 0 0
1. Either LIN or CAN must be enabled as wake-up source. Setting both bits 12 and 13 to '0' is an invalid setting. In this case, both bits will be set to '1' (wake-up enabled; default) and the SPI Error Bit (SPIE) in the Global Status Byte will be set.
0
19
18
17
16
Bit
23
22
21
20
15
Name
Reserved
WU_EN
Reserved
WU_PU
Table 89. CR1 signals description
Description
—
Wake-up Input 1 (WU) enable
(1)
0: WU disabled
1: WU enabled (default)
—
Wake-up Input1 Pull-up/down configuration: configuration of internal current source
0: pull-down (default)
1: pull-up
Reserved —
WU_FILT_1
WU_FILT_0
TIMER_NINT_WAKE_SEL
Wake-up Input1 Filter configuration Bits: configuration of input filter
See Table 90: Wake-up input1 filter configuration
Select Timer for NINT / Wake: select timer for periodic interrupt in standby modes
0: Timer 2 (default)
1: Timer 1
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
14
13
12
11
10
9
8
7
6
5
4
SPI Registers
Name
LIN_WU_EN
(2)
CAN_ RXEN
CAN_TXEN
SWEN
HEN
V2_1
V2_0
Table 89. CR1 signals description (continued)
Description
TIMER_NINT_EN
CANTO_ IRQ_EN
CAN_Go_TRX_RDY
Timer NINT enable: enable timer interrupt in standby modes
0: timer interrupt disabled (default)
1: timer interrupt enabled
V1_standby mode: periodic NINT pulse generated by timer (NINT pulse at start of timer on-phase)
Vbat_standby mode: device wakes up after timer expiration and generates NReset
LIN Wake-up enable: enable wake-up by LIN
(3)
0: disabled
1: enabled (default)
CAN Wake-up enable: enable wake-up by CAN
(4)
0: disabled
1: enabled (default)
CANTO Interrupt enable: enables interrupt signal in case of CAN timeout
0: CAN TO interrupt disabled
1: CAN TO interrupt enabled (default)
CAN transceiver configuration
See Table 91: CAN transceiver mode
CAN Transceiver transition into TRX READY mode.
0: CAN transceiver in TRX BIAS mode (default)
1: CAN transceiver is sent into TRX READY mode
At Exit from TRX READY mode, this bit is set to '0' automatically.
CAN Flash mode: CAN Go TRX RDY is set to '1' automatically
After power-on, this bit should be set to ’0’ and a clear command should be sent to status registers.
CAN Selective Wake-up enable: enable selective wake-up for CAN
(5)
0: No Selective Wakeup (default)
1: Selective Wakeup enabled
Enable H-bridge
0: H-bridge disabled (default)
1: H-bridge enabled
Refer to chapter H-bridge Control for details
Voltage Regulator V2 Configuration
See Table 92: Voltage regulator V2 configuration
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
Bit Name
Table 89. CR1 signals description (continued)
Description
3
2
1
PARITY
STBY_SEL
GO_STBY
PARITY: Standby Command Parity Bit
STBY SEL: Select Standby mode
GO_STBY: Execute transition into Standby mode
The STBY_SEL and GO_STBY bits are protected by a parity check.
The bits STBY_SEL, GO_STBY and PARITY must represent an even number of '1', otherwise the command is ignored and the SPI_INV_CMD bit is set.
Table 93: Standby transition configuration
shows the valid settings.
All other settings are invalid; command will be ignored and SPI_INV_CMD will be set. The GO_STBY bit is not cleared automatically after wake-up.
Watchdog Trigger Bit 0 TRIG
1. Setting is only valid if input is configured as wake-up input in Configuration Register (0x3F).
2. Either LIN or CAN must be enabled as wake-up source. Setting both bits 12 and 13 to '0' is an invalid setting. All wake-up sources will be configured according to default setting; SPI Error Bit (SPIE) in Global Status Byte will be set.
3. The wake-up behavior is configurable in the Configuration Register (0x3F).
4. Wake-up occurs at a wake –up event according to ISO 11898-5:2007 (default) Wake-up according ISO 11898-6:2013
(selective wake-up) is configurable (refer to chapter High Speed CAN Bus Transceiver).
5. A dedicated procedure must be followed to set SWEN (CR 1) = 1 (refer to chapter High Speed CAN Bus Transceiver).
Table 90. Wake-up input1 filter configuration
WU _ FILT_1 WU _ FILT_0
0
0
1
1
0
1
0
1
Wake-up inputs monitored in static mode (filter time twu_stat) (default)
Wake- up inputs monitored in cyclic mode with Timer2 (filter time: t
WU_cyc
; blanking time 80% of timer ON time)
Wake- up inputs monitored in cyclic mode with Timer1 (filter time: t
WU_cyc
; blanking time 80% of timer ON time)
Invalid setting; command will be ignored and SPI INV CMD will be set
Table 91. CAN transceiver mode
CAN _ RXEN CAN _ TXEN
0
0 x x
TRX Standby: Receiver disabled, Transmitter disabled
1
1
0
1
TRX Listen: Receiver enabled, Transmitter disabled
TRX Normal
(1)
: Receiver enabled, Transmitter enabled
1. CAN Flash mode: TRX Normal Mode functionality is configured automatically but SPI registers are not updated.
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
V2_1
Table 92. Voltage regulator V2 configuration
V2_0
0
0
1
1
0
1
0
1
V2 OFF in all modes (default)
V2 ON in Active mode; OFF in Standby modes
V2 ON in Active and V1_standby mode; OFF in Vbat_standby mode
V2 ON in all modes (1)
1. This configuration will not be taken into account if CAN_SUP_5V2_EN = 1.
Table 93. Standby transition configuration
PARITY STBY_SEL GO_STBY
0
1
0
1
1
0
0
1
1
1
0
0
Go to V1 standby
Go to Vbat_standby
No transition to standby
7.4.2 Control Register CR2 (0x02)
Table 94. Control Register CR2
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
R/W
Bit
23
22
21
20
19
Name
T1_RESTART
T1_DIR1
T1_ON_2
T1_ON_1
T1_ON_0
Table 95. CR2 signals description
Description
Timer 1 Restart: Restart of Timer 1
0: timer is running with period and on-time according to configuration (default)
1: restart of timer at CSN low to high transition; starting with ON phase (1)
Bit is automatically reset with next SPI frame.
T1_DIR1: Timer 1 Direct Drive by DIR1
T1_ON_x: Timer 1 On-Time Bits
Configuration of Timer 1 on-time, for details see Table 96
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
11
10
9
14
13
12
Bit
18
17
16
15
8
7
6
5
Name
Table 95. CR2 signals description (continued)
Description
T1_PER_2
T1_PER_1
T1_PER_0
T2_RESTART
Configuration of Timer 1 Period
000: T1 (default)
001: T2
010: T3
011: T4
100: T5
101: T6
110: T7
111: T8
Timer 2 Restart: restart of timer 2
0: timer is running with period and on-time according to configuration (default)
1: restart of timer at CSN low to high transition; starting with ON phase
Bit is automatically reset with next SPI frame.
T2_DIR1
T2_ON_2
T2_ON_1
T2_DIR1: Timer 2 Direct Drive by DIR1
T2_ON_x: Timer 2 On-Time Bits
Configuration of Timer 2 on-time, for details see Table 96
T2_ON_0
T2_PER_2
T2_PER_1
T2_PER_0
Configuration of Timer 2 Period
000: T1 (default)
001: T2
010: T3
011: T4
100: T5
101: T6
110: T7
111: T8
LIN_REC_ONLY
CAN_LOOP_EN
LIN Transceiver Receive Only mode
0: LIN receive only mode disabled (default)
1: LIN receive only mode enabled
LIN_TXD_TOUT_EN
LIN TxD Timeout Enable
0: LIN TxD timeout detection disabled
1: LIN TxD timeout detection enabled (default)
CAN Loop Enable: CAN Looping of TxDC to RxDC
0: CAN looping disabled (default)
1: CAN looping enabled
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
Bit Name
Table 95. CR2 signals description (continued)
Description
4
3
2
PNW_EN
V1_RESET_1
V1_RESET_0
CAN Pretented Networking mode
A WUP leads to transition into TRX Bias mode and an interrupt is generated.
0: pretended networking disabled (default)
1: pretended networking enabled
This bit can only be set to '1' if:
SWEN = 0 (selective wake-up disabled)
CAN RXEN = 1
The bit is automatically reset to '0' if selective wake-up is enabled (SWEN = 1) device enters Vbat_standby mode
Voltage Regulator V1 Reset Threshold
00: Vrt4 (default)
01: Vrt3
10: Vrt2
11: Vrt1 thresholds are monitored in Active mode and V1_standby mode
1
0
WD_TIME_1
WD_TIME_0
Watchdog Trigger Time
00: TSW1 (default)
01: TSW2
10: TSW3
11: TSW4
Writing to WD_TIME_x is blocked unless WD CONFIG EN = 1.
The modified WD Trigger Time is valid immediately after the Write command (CSN transition low-high).
The watchdog timer is reset when the trigger time is modified (restart at CSN transition low-high).
1. Timer restart behavior:
Write to CR2 when Tx_ON_x and Tx_PERx remain unchanged:
Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time
Tx_RESTART = 0: write operation to CR2 has no effect on timers
Write to CR2 when Tx_ON_x and Tx_PERx are modified
Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time and according to new setting (ON time and period)
Tx_RESTART = 0: behavior is not defined; if a predictable behavior is needed, it is recommended to set Tx_RESTART = 1
Table 96. Configuration of Timer x on-time
Tx_DIR1 Tx_ON_2 Tx_ON_1 Tx_ON_0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0 ton1 (default) ton2 ton3 ton4 ton5
Invalid setting; command will be ignored and SPI
INV CMD will be set
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
Table 96. Configuration of Timer x on-time (continued)
Tx_DIR1 Tx_ON_2 Tx_ON_1 Tx_ON_0
1
(1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1 ton1 controlled by DIR1 input signal (logical AND) ton2 controlled by DIR1 input signal (logical AND) ton3 controlled by DIR1 input signal (logical AND) ton4 controlled by DIR1 input signal (logical AND) ton5 controlled by DIR1 input signal (logical AND)
Invalid setting; command will be ignored and SPI
INV CMD will be set
1. Tx_DIR1 = 1 is only valid for OUT7-OUT15 and OUT_HS control; the DIR1 signal has no influence for WU monitoring if WU is monitored by timer.
Figure 60. Timer_x controlled by DIR1
7[',5
7[
WRQ[
7LPHU;
',5
287[
("1($'5
7.4.3 Control Register CR3 (0x03)
Table 97. Control Register CR3
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
Bit
23
22
21
20
19
18
17:10
Name
Table 98. CR3 signals description
Description
VSREG_LOCK_EN
VS_LOCK_EN
VSREG_OV_SD_EN
VSREG_UV_SD_EN
VS_OV_SD_EN
VS_UV_SD_EN
Reserved
V
SREG
lockout enable: Lockout of V
SREG
related outputs after V
SREG
overvoltage/ undervoltage shutdown
0: V
SREG
related Outputs are turned on automatically and status bits
(VSREG_UV, VSREG_OV) are cleared
1: V
SREG
related Outputs remain turned off until status bits (VSREG_UV,
VSREG_OV) are cleared (default)
Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions
V
S
lockout enable: Lockout of V
S
related outputs after V
S
over/undervoltage shutdown
0: V
S
related Outputs are turned on automatically and status bits (VS_UV,
VS_OV) are cleared
1: V
S
related Outputs remain turned off until status bits (VS_UV, VS_OV) are cleared (default)
Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions
V
SREG of V
overvoltage shutdown enable: shutdown of V
SREG
SREG
overvoltage
related outputs in case
0: no shutdown of V
SREG
related outputs in case of V
SREG
overvoltage
1: shutdown of V
SREG
related outputs in case of V
SREG
overvoltage (default)
V
SREG
undervoltage shutdown enable: shutdown of V
SREG
related outputs in case of V
SREG
undervoltage
0: no shutdown of V
SREG
related outputs in case of V
SREG
undervoltage
1: shutdown of V
SREG
related outputs in case of V
SREG
undervoltage (default)
In case of V1 undervoltage due to VSREG_UV, the device enters Fail-Safe mode and the outputs are turned off
V
S
overvoltage shutdown enable: shutdown of V
S
related outputs in case of V
S overvoltage
0: no shutdown of V
S
related outputs in case of V
S
overvoltage if charge pump output voltage is still sufficient (until CPLOW threshold is reached)
1: shutdown of V
S
related outputs in case of V
S
overvoltage (default)
V
S
undervoltage shutdown enable: shutdown of V undervoltage
S
related outputs in case of V
S
0: no shutdown V
S
related of outputs in case of V
S
undervoltage
1: shutdown of V
S
related outputs in case of V
S
undervoltage (default)
In case of V1 undervoltage due to VS_UV, the device enters Fail-Safe mode and the outputs are turned off
Reserved
DS11546 Rev 5
196
Bit
3
2
5
4
1
0
7
6
9
8
SPI Registers L99DZ100G, L99DZ100GP
Name
VSREG_EW_TH_9
VSREG_EW_TH_8
VSREG_EW_TH_7
VSREG_EW_TH_6
VSREG_EW_TH_5
VSREG_EW_TH_4
VSREG_EW_TH_3
VSREG_EW_TH_2
VSREG_EW_TH_1
VSREG_EW_TH_0
Table 98. CR3 signals description (continued)
Description
V
SREG
early warning threshold.
At V
SREG
< VSREG_EW_TH, an interrupt is generated at NINT and status bit
VSREG_EW in SR2 is set (in Active mode)
0000000000: 0 V (default) feature deactivated
...
1111111111: V
AINVS
7.4.4 Control Register CR4 (0x04)
Table 99. Control Register CR4
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23:22
Name
Reserved
21
20
19:18
OUT1_HS
OUT1_LS
Reserved
Table 100. CR4 signals description
Description
Reserved
OUT1 High-Side Driver control
0: OUT1_HS is turned off (default)
1: OUT1_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously.
OUT1 Low-Side Driver control
0: OUT1_LS is turned off (default)
1: OUT1_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously.
Reserved
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
17
16
15:14
13
12
11:10
9
8
7:6
5
4
SPI Registers
Name
OUT2_HS
OUT2_LS
Reserved
OUT3_HS
OUT3_LS
Resrved
OUT4_HS
OUT4_LS
Reserved
OUT5_HS
OUT5_LS
Table 100. CR4 signals description (continued)
Description
OUT2 High-Side Driver control
0: OUT2_HS is turned off (default)
1: OUT2_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT2 are switched on simultaneously.
OUT2 Low-Side Driver control
0: OUT2_LS is turned off (default)
1: OUT2_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT2 are switched on simultaneously.
Reserved
OUT3 High-Side Driver control
0: OUT3_HS is turned off (default)
1: OUT3_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT3 are switched on simultaneously.
OUT3 Low-Side Driver control
0: OUT3_LS is turned off (default)
1: OUT3_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT3 are switched on simultaneously.
Reserved
OUT4 High-Side Driver control
0: OUT4_HS is turned off (default)
1: OUT4_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT4 are switched on simultaneously.
OUT4 Low-Side Driver control
0: OUT4_LS is turned off (default)
1: OUT4_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT4 are switched on simultaneously.
Reserved
OUT5 High-Side Driver control
0: OUT5_HS is turned off (default)
1: OUT5_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT5 are switched on simultaneously.
OUT5 Low-side Driver control
0: OUT5_LS is turned off (default)
1: OUT5_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT5 are switched on simultaneously.
DS11546 Rev 5
196
SPI Registers
Bit
3:2
1
0
L99DZ100G, L99DZ100GP
Name
Reserved
OUT6_HS
OUT6_LS
Table 100. CR4 signals description (continued)
Description
Reserved
OUT6 High-side Driver control
0: OUT6_HS is turned off (default)
1: OUT6_HS is turned on
An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously.
OUT6 Low-side Driver control
0: OUT6_LS is turned off (default)
1: OUT6_LS is turned on
An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously.
7.4.5 Control Register CR5 (0x05)
Table 101. Control Register CR5
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
18
17
16
15:12
11
10
9
8
23
22
21
20
19
Name
Table 102. CR5 signals description
Description
OUT7_3
OUT7_2
OUT7_1
OUT7_0
OUT8_3
OUT7 Configuration Bits: High-Side Driver OUT7 Configuration
For OUT7 bits configuration see Table 103: OUTx Configuration bits
OUT8_2
OUT8_1
OUT8_0
OUT8 Configuration Bits: High-Side Driver OUT8 Configuration
For OUT8 bits configuration see Table 103: OUTx Configuration bits
Reserved —
OUT10_3
OUT10_2
OUT10 Configuration Bits: High-Side Driver OUT10 Configuration
For OUT10 bits configuration see
Table 103: OUTx Configuration bits
OUT10_1
OUT10_0
DS11546 Rev 5
Bit
7:5
4
1
0
3
2
L99DZ100G, L99DZ100GP SPI Registers
Name
Table 102. CR5 signals description (continued)
Description
Reserved —
GH
Gate Heater Control: Control of gate driver for external heater MOSFET
0: GH_heater is turned off (default)
1: GH_heater is turned on
OUTHS_3
OUTHS_2
OUTHS_1
OUTHS_0
OUTHS Configuration Bits: High-side Driver OUTHS Configuration
For OUTHS bits configuration see Table 103: OUTx Configuration bits
OUTx_2
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
OUTx_3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Table 103. OUTx Configuration bits
OUTx_1 OUTx_0 Description
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1
1
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
DIR1
DIR2
Off (default)
On
Timer1
Timer2
PWM1
PWM2
PWM3
PWM4
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
7.4.6 Control Register CR6 (0x06)
Table 104. Control Register CR6
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
8
7
6
5
4
3
2
1
0
14
13
12
11
10
9
20
19
18
17
16
15
23
22
21
Name
OUT13_0
OUT14_3
OUT14_2
OUT14_1
OUT14_0
OUT15_3
OUT15_2
OUT15_1
OUT15_0
OUT9_3
OUT9_2
OUT9_1
OUT9_0
OUT11_3
OUT11_2
OUT11_1
OUT11_0
OUT12_3
OUT12_2
OUT12_1
OUT12_0
OUT13_3
OUT13_2
OUT13_1
Table 105. CR6 signals description
Description
OUT9 Configuration Bits: High-Side Driver OUT9 Configuration
For OUT9 bits configuration see Table 103: OUTx Configuration bits
OUT11 Configuration Bits: High-Side Driver OUT11 Configuration
For OUT11 bits configuration see
Table 103: OUTx Configuration bits
OUT12 Configuration Bits: High-Side Driver OUT12 Configuration
For OUT12 bits configuration see
Table 103: OUTx Configuration bits
OUT13 Configuration Bits: High-Side Driver OUT13 Configuration
For OUT13 bits configuration see
Table 103: OUTx Configuration bits
OUT14 Configuration Bits: High-Side Driver OUT14 Configuration
For OUT14 bits configuration see
Table 103: OUTx Configuration bits
OUT15 Configuration Bits: High-side Driver OUT15 Configuration
For OUT15 bits configuration see
Table 103: OUTx Configuration bits
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
7.4.7 Control Register CR7 (0x07)
Table 106. Control Register CR7
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
R/W
Bit
20
19
18
23
22
21
17
16
15
14:13
12
11
10
9
8
7
6
Name
OUT1_OCR
OUT2_OCR
OUT3_OCR
OUT4_OCR
OUT5_OCR
OUT6_OCR
OUT7_OCR
OUT8_OCR
Table 107. CR7 signals description
Overcurrent recovery for OUTx
Description
0: overcurrent recovery is turned off (default)
1: overcurrent recovery is turned on
OUTHS_OCR
Reserved
HB_TON_1
HB_TON_0
HS_TON_1
HS_TON_0
OCR_FREQ
OUT5_OC1
OUT5_OC0
Overcurrent recovery for OUTHS
0: overcurrent recovery is turned off (default)
1: overcurrent recovery is turned on
—
Half-bridge minimum ON time and related overcurrent recovery frequency
For details see
Table 108: Half-bridge minimum ON time and related overcurrent recovery frequency
High-side minimum ON time and related overcurrent recovery frequency
For details see
Table 109: High-side minimum ON time and related overcurrent recovery frequency
Overcurrent recovery frequency
See
Table 108: Half-bridge minimum ON time and related overcurrent recovery frequency
and
Table 109: High-side minimum ON time and related overcurrent recovery frequency
Overcurrent Threshold for OUT5
00: IOC5_3 overcurrent threshold 3 (default)
01: IOC5_1 overcurrent threshold 1
10: IOC5_2 overcurrent threshold 2
11: IOC5_3 overcurrent threshold 3
DS11546 Rev 5
196
SPI Registers
Bit
5
4
3
2
1
0
L99DZ100G, L99DZ100GP
Name
CM_EN
Reserved
CM_SEL_3
CM_SEL_2
CM_SEL_1
CM_SEL_0
Table 107. CR7 signals description (continued)
Description
Current monitor:
0: off (3-state)
1: on (default)
—
Current Monitor Select Bits.
A current image of the selected binary coded output is multiplexed to the CM output. If a corresponding output does not exist, the current monitor is deactivated.
0000: OUT1
0001: OUT2
0010: OUT3
0011: OUT4
0100: OUT5
0101: OUT6
0110: OUT7
0111: OUT8
1000: OUT9
1001: OUT10
1010: OUT11
1011: OUT12
1100: OUT13
1101: OUT14
1110: OUT15
1111: OUT_HS
Table 108. Half-bridge minimum ON time and related overcurrent recovery frequency
HB_TON_1 HB_TON_ OCR_FREQ T
ON_min
(recovery frequency)
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
104 µs (1.7 kHz)
104 µs (3 kHz)
88 µs (2.2 kHz)
88 µs (3.8 kHz)
80 µs (2.6 kHz)
80 µs (4.4 kHz)
72 µs (3 kHz)
72 µs (5 kHz)
Table 109. High-side minimum ON time and related overcurrent recovery frequency
HS_TON_1
0
HS_TON_
0
OCR_FREQ
0
T
ON_min
(recovery frequency)
104 µs (1.7 kHz)
0 0 1 104 µs (3 kHz)
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
Table 109. High-side minimum ON time and related overcurrent recovery frequency
HS_TON_1 HS_TON_ OCR_FREQ T
ON_min
(recovery frequency)
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
88 µs (2.2 kHz)
88 µs (3.8 kHz)
80 µs (2.6 kHz)
80 µs (4.4 kHz)
72 µs (3 kHz)
72 µs (5 kHz)
7.4.8 Control Register CR8 (0x08)
Table 110. Control Register CR8
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Resrved
Reset
Access
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
21
20
19
Bit
23
22
18
17
16
Table 111. CR8 signals description
Name
OUT1_OCR_THX_EN
Description
OUT2_OCR_THX_EN
OUT3_OCR_THX_EN
OUT4_OCR_THX_EN
OUT5_OCR_THX_EN
OUT6_OCR_THX_EN
OUT7_OCR_THX_EN
OUT8_OCR_THX_EN
Enable Overcurrent Recovery with Thermal Expiration for OUTx.
0: Overcurrent Recovery with Thermal Expiration is off
1: Overcurrent Recovery with Thermal Expiration is on (default)
The output is turned off after Thermal Expiration.
DS11546 Rev 5
196
SPI Registers
Bit
15
14:0
L99DZ100G, L99DZ100GP
Table 111. CR8 signals description (continued)
Name Description
OUTHS_OCR_THX_EN
Reserved
Enable Overcurrent Recovery with Thermal Expiration for OUTHS.
0: Overcurrent Recovery with Thermal Expiration is off
1: Overcurrent Recovery with Thermal Expiration is on (default)
The output is turned off after Thermal Expiration.
—
7.4.9 Control Register CR9 (0x09)
Table 112. Control Register CR9
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23
22
21:16
15
14
13
12
11
10
9
8
Name
OUT7_RDSON
OUT8_RDSON
Table 113. CR9 signals description
Description
Select Rdson for OUT7
0: r on_low
(default)
1: r on_high
Select Rdson for OUT8
0: r on_low
(default)
1: r on_high
— Reserved
OUTHS_OL
OUT15_OL
OUT14_OL
OUT13_OL
OUT12_OL
OUT11_OL
OUT10_OL
OUT9_OL
Open-load Threshold for OUTx
0: I
OLD1
; high-current mode (default)
1: I
OLD1
; low-current mode
DS11546 Rev 5
Bit
1
0
3
2
5
4
7
6
L99DZ100G, L99DZ100GP
Table 113. CR9 signals description (continued)
Name Description
OUTHS_OC
OUT15_OC
OUT14_OC
OUT13_OC
OUT12_OC
OUT11_OC
OUT10_OC
OUT9_OC
Overcurrent Threshold for OUTx
0: I
OC
; high-current mode (default)
1: I
OC
; low-current mode
SPI Registers
Table 114. Control Register CR10
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
R/W
20
19
Bit
23
22
21
Name
DIAG_2
DIAG_1
DIAG_0
GH_OL_EN
Reserved
Table 115. CR10 signals description
Description
Drain-source monitoring threshold for external H-bridge
000: V
SCd1_HB
001: V
SCd2_HB
010: V
SCd3_HB
011: V
SCd4_HB
100: V
SCd5_HB
101: V
SCd6_HB
110: V
SCd7_HB
111: V
SCd7_HB
(default)
Control open-load diagnosis for Gate Heater output
0: open-load diagnosis off (default)
1: open-load diagnosis on
—
DS11546 Rev 5
196
SPI Registers
3
2
1
0
7
6
5
4
Bit
18
17
16
15:14
13
12
11
10
9
8
L99DZ100G, L99DZ100GP
Name
Table 115. CR10 signals description (continued)
Description
GH_TH_2
GH_TH_1
GH_TH_0
Reserved
SD
SDS
Drain source monitoring threshold voltage for external heater MOSFET
000: V
SCd1_HE
001: V
SCd2_HE
010: V
SCd3_HE
011: V
SCd4_HE
100: V
SCd5_HE
101: V
SCd6_HE
110: V
SCd7_HE
111: V
SCd8_HE
(default)
—
Slow decay
Slow decay single
COPT_3
COPT_2
COPT_1
COPT_0
Cross current protection time
0000: not allowed
0001: tccp
0001
0010: tccp
0010
0011: tccp
0011
0100: tccp
0100
0101: tccp
0101
0110: tccp
0110
0111: tccp
0111
1000: tccp
1000
1001: tccp
1001
1010: tccp
1010
1011: tccp
1011
1100: tccp
1100
1101: tccp
1101
1110: tccp
1110
1111: tccp
1111
(default)
H_OLTH_HIGH H-bridge OL high threshold (5/6 * V
S
) select
OL_H1L2 Test open-load condition between H1 and L2
OL_H2L1 Test open-load condition between H2 and L1
SLEW_4
SLEW_3
SLEW_2
SLEW_1
SLEW_0
Binary coded slew rate of H-bridge (bit0 = LSB; bit4 = MSB)
00000: Control disabled (default)
11111: I
GHxmax
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
7.4.11 Control Register CR11 (0x0B)
Table 116. Control Register CR11
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
23:14
13
12
11:9
7:6
5
4
3
2
1
0
Bit name Reserved Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
R/W
8
Name
Reserved
ECV_LS
ECV_OCR
Reserved
ECON
Reserved
EC_5
EC_4
EC_3
EC_2
EC_1
EC_0
Table 117. CR11 signals description
Description
—
Control of ECV low-side switch
0: ECV low-side switch off (default)
1: ECV low-side switch on
Overcurrent recovery for output ECV
0: overcurrent recovery is turned off (default)
1: overcurrent recovery is turned on
—
Electro-chrome Control
The electro-chrome control enables the driver at pin ECDR and switches
OUT10 directly on ignoring the control bits OUT10_x in CR5
0: Electro-chrome control off (default)
1: Electro-chrome control on
—
EC Reference Voltage Bits
The reference voltage for the electro-chrome voltage controller at pin ECV is binary coded.
(bit0 = LSB; bit5 = MSB)
00 0000: V
ECV
= 0 V xx xxxx: V
ECV
= V
CTRLma x/63 x register value
11 1111: V
ECV
= V
CTRLmax
For ECV_HV (Configuration Register) = 0, the maximum EC control voltage is clamped at lower value (see
Section 3.4.20: Electro-chrome mirror driver
)
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
Table 118. Control Register CR12
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
20
19
16
15
Bit
23
22
21
18
17
14
Name
Table 119. CR12 signals description
Description
PMW1_FREQ_1 Frequency of PWM channel PWM1
00: f
PWMx
(00) (default)
PMW1_FREQ_0
01: f
PWMx
(01)
10: f
PWMx
(10)
11: f
PWMx
(11)
PMW2_FREQ_1 Frequency of PWM channel PWM2
00: f
PWMx
(00) (default)
01: f
PWMx
(01)
PMW2_FREQ_0 10: f
PWMx
(10)
11: f
PWMx
(11)
PMW3_FREQ_1 Frequency of PWM channel PWM3
00: f
PWMx
(00) (default)
PMW3_FREQ_0
01: f
PWMx
(01)
10: f
PWMx
(10)
11: f
PWMx
(11)
PMW4_FREQ_1 Frequency of PWM channel PWM4
00: f
PWMx
(00) (default)
01: f
PWMx
(01)
PMW4_FREQ_0 10: f
PWMx
(10)
11: f
PWMx
(11)
PMW5_FREQ_1 Frequency of PWM channel PWM5
00: f
PWMx
(00) (default)
PMW5_FREQ_0
01: f
PWMx
(01)
10: f
PWMx
(10)
11: f
PWMx
(11)
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
13
12
11
10
9
8
7
6
5
4
3:0
Name
Table 119. CR12 signals description (continued)
Description
PMW6_FREQ_1 Frequency of PWM channel PWM6
00: f
PWMx
(00) (default)
PMW6_FREQ_0
01: f
PWMx
(01)
10: f
PWMx
(10)
11: f
PWMx
(11)
PMW7_FREQ_1 Frequency of PWM channel PWM7
00: f
PWMx
(00) (default)
01: f
PWMx
(01)
PMW7_FREQ_0 10: f
PWMx
(10)
11: f
PWMx
(11)
PMW8_FREQ_1 Frequency of PWM channel PWM8
00: f
PWMx
(00) (default)
PMW8_FREQ_0
01: f
PWMx
(01)
10: f
PWMx
(10)
11: f
PWMx
(11)
PMW9_FREQ_1 Frequency of PWM channel PWM9
00: f
PWMx
(00) (default)
01: f
PWMx
(01)
PMW9_FREQ_0 10: f
PWMx
(10)
11: f
PWMx
(11)
PMW10_FREQ_1 Frequency of PWM channel PWM10
00: f
PWMx
(00) (default)
PMW10_FREQ_0
01: f
PWMx
(01)
10: f
PWMx
(10)
11: f
PWMx
(11)
Reserved —
SPI Registers
Table 120. Control Register CR13 to CR17
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Where: x = 1 + (z * 2), z = 0 to 4
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
Bit
6
5
4
3
2
1
0
9
8
7
18
17
16
15
14
23:22
21
20
19
13
12
11:10 y = 2 + (z * 2), z = 0 to 4
Name
Reserved
PWMx_DC_9
PWMx_DC_8
PWMx_DC_7
PWMx_DC_6
PWMx_DC_5
PWMx_DC_4
PWMx_DC_3
PWMx_DC_2
PWMx_DC_1
PWMx_DC_0
Reserved
PWMy_DC_9
PWMy_DC_8
PWMy_DC_7
PWMy_DC_6
PWMy_DC_5
PWMy_DC_4
PWMy_DC_3
PWMy_DC_2
PWMy_DC_1
PWMy_DC_0
—
Table 121. CR13 to CR17 signals description
Description
Binary coded on-dutycycle of PWM channel PWMx (bit12 = LSB; bit21 = MSB)
00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1023 x register value
11 1111 1111. duty cycle 100%
—
Binary coded on-dutycycle of PWM channel PWMy (bit0 = LSB; bit9 = MSB)
00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1023 x register value
11 1111 1111. Duty cycle 100%
Binary coded on-dutycycle of PWM channel PWMy
Table 122. Control Register CR18
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
DS11546 Rev 5
Bit
15
14
13
12
11
10
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
9
8
7
L99DZ100G, L99DZ100GP SPI Registers
Reset
Access
Table 122. Control Register CR18 (continued)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Where: x = 7 + (z * 2), z = 0 to 4 y = 8 + (z * 2), z = 0 to 4
Name
Table 123. CR18 to CR22 signals description
Description
Reserved —
OUTx_AUTOCOMP_EN Setting this bit to ‘1’ enables the automatic V
S
compensation for OUTx
OUTx_VLED_9
OUTx_VLED_8
OUTx_VLED_7
OUTx_VLED_6
OUTx_VLED_5
OUTx_VLED_4
Binary coded nominal LED voltage of OUTx (bit12 = LSB; bit21 = MSB)
00 0000 0000: V
LED
= 0 V (default) xx xxxx xxxx: V
LED
= V
AINVS
/1023 x register value
01 1101 0000: V
LED
= V
AINVS
V
LED
is clamped at 10 V (0x1D0h) OUTx_VLED_3
OUTx_VLED_2
OUTx_VLED_1
OUTx_VLED_0
Reserved —
OUTy_AUTOCOMP_EN Setting this bit to ‘1’ enables the automatic V
S
compensation for OUTy
OUTy_VLED_9
OUTy_VLED_8
OUTy_VLED_7
OUTy_VLED_6
OUTy_VLED_5
OUTy_VLED_4
OUTy_VLED_3
OUTy_VLED_2
Binary coded nominal LED voltage of OUTy (bit0 = LSB; bit9 = MSB)
00 0000 0000: V
LED
= 0 V (default) xx xxxx xxxx: V
LED
= V
AINVS
/1023 x register value
01 1101 0000: V
LED
= V
AINVS
V
LED
is clamped at 10 V (0x1D0h)
OUTy_VLED_1
OUTy_VLED_0
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
Table 124. Control Register CR23
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23:18
17:0
Name
Table 125. CR23 signals description
Description
Reserved —
EXT_ID_x
Extended CAN Identifier
Definition of Extended CAN Identifier which will cause a wake-up (WUF)
To enable wake-up frame detection on Extended CAN Identifier also CAN_IDE (Control
Register 24, bit 22) must be set
ID Bits are maskable in CR25
Table 126. Control Register CR24
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23
22
Name
Table 127. CR24 signals description
Description
Reserved —
CAN_IDE
Enable CAN wake-up frame detection on Extended Identifier
0: CAN Identifier matching based on CAN Standard Message Format (default)
1: CAN Identifier Matching based on CAN Extended Message Format
DS11546 Rev 5
Bit
21
11
10
9
8
7
6
15
14
13
12
5
4
3
2
1
0
L99DZ100G, L99DZ100GP
20
19
18
17
16
SPI Registers
Name
Table 127. CR24 signals description (continued)
Description
BR_1
BR_0
Bit Rate for CAN wake-up frame detection
00: 500 kbit/s (default)
01: 250 kbit/s
10: 500 kbit/s
11: 125 kbit/s
SAMPLE_3 Sample Point for CAN wake-up frame detection
SAMPLE_2
0000: 65.625 %
0001: 67.1875 %
SAMPLE_1
0010: 67.75 %
...
SAMPLE_0
1010: 81.25 % (default)
...
1110: 87.5 %
1111: 89.065 %
DLC_3
DLC_2
DLC_1
DLC_0
CAN Data Length Code
Defines the amount of Data Bytes used for the CAN wake-up frame detection.
Possible values up to 8 Byte according to CAN message format
Reserved —
ID_10
ID_9
ID_8
ID_7
ID_6
ID_5
ID_4
ID_3
CAN Identifier
Definition of CAN Identifier which will cause a wake-up (WUF)
ID Bits are maskable in CR26
ID_2
ID_1
ID_0
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
Table 128. Control Register CR25
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23:18
17:0
Name
Reserved
EXT_ID_MASK_x
Table 129. CR25 signals description
Description
—
Masking Bits for Extended CAN Identifier
0: Extended CAN Identifier Bit will be matched (default)
1: Extended CAN Identifier Bit will be ignored for matching
Table 130. Control Register CR26
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23:11
10:0
Name
Reserved
ID_MASK_x
Table 131. CR26 signals description
Description
—
Masking Bits Standard CAN Identifier
0: CAN Identifier Bit will be matched (default)
1: CAN Identifier Bit will be ignored for matching
The extended ID and extended ID mask are composed as follows (mask is composed by equivalent bits in CR25 and CR26:
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Figure 61. Extended ID and extended ID mask
67',' E E E E E E E E E E E
,'B
&5ELW
,'B
SPI Registers
(;7,' E E E E E E E E E E E 655 ,'( E E E E E E E E E E E E E E E E E E
,'B
&5ELW
,'B (;,'B
&5ELW«
(;,'B
("1($'5
Table 132. Control Register CR27
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23:16
15:8
7:0
Table 133. CR27 signals description
Name
DATA_BYTE3
DATA_BYTE2
DATA_BYTE1
Description
Data field for data matching
Table 134. Control Register CR28
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
DS11546 Rev 5
196
SPI Registers
Bit
23:16
15:8
7:0
L99DZ100G, L99DZ100GP
Table 135. CR28 signals description
Name Description
DATA_BYTE6
DATA_BYTE5
DATA_BYTE4
Data field for data matching
Table 136. Control Register CR29
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Reset
Access
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Bit
23:16
15:8
7:0
Table 137. CR29 signals description
Name
Reserved
DATA_BYTE8
DATA_BYTE7
—
Description
Data field for data matching
Table 138. Control Register CR34
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R/W
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
Bit
23:3
2
1
0
Name
Reserved
CP_OFF
ICMP
WD_EN
Table 139. CR34 signals description
Description
—
Charge pump control
0: Enabled; charge pump on in active mode (default)
1: Disabled; charge pump off in active mode setting CP_OFF = 1 is only possible when CP_OFF_EN = 1
V1 load current supervision
0: Enabled; Watchdog is disabled in V1 Standby when I v1
< I
CMP
(default)
1: Disabled; watchdog is disabled upon transition into V1_standby mode setting ICMP = 1 is only possible when ICMP_config_en = 1
Watchdog Enable
0: Watchdog disabled
1: Watchdog enabled (default)
Writing to this bit is only possible during CAN Flash mode (V
TxDL
> V flash
)
7.4.23 Configuration Register (0x3F)
Table 140. Configuration Register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Reset
Access
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R/W
Bit
23
22
Name
WU_CONFIG
LIN_WU_CONFIG
Table 141. CR signals description
Description
Configuration of input pin WU
Input configured as wake-up input
0: WU configured as wake-up input
1: WU configured for input voltage measurement (default)
Configuration of LIN wake-up behaviour
0: wake up at recessive - dominant - recessive with t dom
> t dom_LIN
(default)
(according to LIN 2.2a and Hardware Requirements for Transceivers version
1.3)
1: wake up at recessive - dominant transition
DS11546 Rev 5
196
SPI Registers
Bit
21
20
19
18
17
16
15
14
13
12
L99DZ100G, L99DZ100GP
Name
LIN_HS_EN
TSD_CONFIG
ECV_HV
DM
MASK_OL_HS1
MASK_OL_LS1
MASK_TW
MASK_EC_OL
Table 141. CR signals description (continued)
Description
ICMP_CONFIG_EN
WD_CONFIG_EN
Configuration of LIN transceiver bit rate
0: LIN transceiver in normal communication mode (20kbit/s) (default)
1: LIN transceiver in high speed mode for fast Flashing (115kbit/s)
Configuration of thermal shutdown behaviour
0: in case of TSD1 all power stages are switched off (default)
1: selective shut down of power stage cluster
Configuration of maximum voltage of electrochrome controller (see electrical parameter V
CTRLmax
)
0: maximum electrochrome controller voltage clamped to 1.2V (typ); (default)
1: maximum electrochrome controller voltage set to 1.5V (typ)
H-bridge configuration
0: single motor mode (default)
1: dual motor mode
ICMP configuration Enable
0: writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default)
1: writing ICMP = 1 is possible with next SPI command bit is automatically reset to 0 after next SPI command
Watchdog configuration Enable
0: writing to WD Configuration (CR2 [0:1] is blocked (default)
1: writing to WD Configuration Bits is possible with next SPI command bit is automatically reset to 0 after next SPI command
Mask Open-load HS1
0: Open-load condition at HS1 is not masked (default)
1: Open-load condition at HS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
Mask Open-load LS1
0: Open-load condition at LS1 is not masked (default)
1: Open-load condition at LS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
Mask Thermal Warning
0: Thermal warning is not masked (default)
1: Thermal warning is masked i.e. it is reported as a Global Warning (GSB bit 1) but not as a Global Error
(GSB bit 7)
Mask Electro-chrome Open-load
0: Open-load condition at ECV and OUT10 is not masked (default)
1: Open-load condition at ECV and OUT10 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
11
10
9
8
7
6
5
4
3
2:1
0
SPI Registers
Name
MASK_OL
MASK_SPIE
MASK_PLE
MASK_GW
CP_OFF_EN
CP_LOW_CONFIG
CP_DITH_DIS
FS_FORCED
Reserved
TRIG
Table 141. CR signals description (continued)
Description
CAN_SUP_5V2_EN
Mask open-load
0: Open-load condition at all outputs are not masked (default)
1: Open-load condition at all outputs are masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
Mask SPI error
0: SPI errors are not masked (default)
1: SPI errors are masked i.e. reported as am SPI Error (GSB bit 5) but not as a Global Error (GSB bit 7)
Mask physical layer error
0: Physical Layer Errors are not masked (default)
1: Physical Layer Errors are masked i.e. reported as a Physical Layer Error (GSB bit 4) but not as a Global Error
(GSB bit 7)
Mask global warning
0: Global Warning conditions are not masked (default)
1: Global Warning conditions are masked i.e. reported as a Global Warning (GSB bit 1) but not as a Global Error (GSB bit 7)
Charge pump control enable
0: writing CP_OFF = 1 is blocked (writing CP OFF = 0 is possible); (default)
1: writing CP_OFF = 1 is possible with next SPI command
Bit is automatically reset to 0 after next SPI command
Charge pump low configuration
0: CP_low (SR 2, bit 9) is latched and outputs are off until R&C; (default)
1: CP_low (SR 2, bit 9) is a ‘live’ bit; outputs are re-activated automatically upon recovery of the charge pump output voltage
Charge pump clock dithering
0: CP clock dithering is enabled; (default)
1: CP clock dithering is disabled
Force LSx_FSO ON
LSx_FSO low-side outputs are forced ON (to allow diagnosis of the fail-safe path)
0: LSx_FSO outputs are controlled by the Fail-safe logic (default)
1: LSx_FSO outputs are forced ON and the device enters Fail-Safe mode; no
NReset is generated
CAN supplied by V2 enable (to allow CAN Partial Networking in V1stdby)
0: CAN supplied by V1; (default)
1: CAN supplied by V2; in this case the configuration CR1<5:4> = 11 is ignored
—
Watchdog Trigger bit
DS11546 Rev 5
196
SPI Registers L99DZ100G, L99DZ100GP
7.5.1 Status Register SR1 (0x31)
Table 142. Status Register SR1 (0x31)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C R
Bit
23
22
21
20
19
18
17
R/C R R/C
Name
Reserved
WU_STATE
Reserved
WU_WAKE
WAKE_CAN
WAKE_LIN
WAKE_TIMER
Table 143. SR1 signals description
Description
—
State of WU input
0: input level is low
1: input level is high
The bit shows the momentary status of WU and cannot be cleared (“Live bit”)
Note: The status is only valid if WU is configured as wake-up input in
Configuration Register (0x3F). Otherwise this bit is read at its previous logic state
—
Wake-up by WU: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
Wake-up by CAN: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
Wake-up by LIN: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
Wake-up by Timer: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI Registers
Name
Table 143. SR1 signals description (continued)
Description
DEBUG_ACTIVE
V1UV
Debug Mode Active: indicates Device is in Debug mode
1: Debug mode
The bit shows the momentary status and cannot be cleared (“Live bit”)
Indicates undervoltage condition at voltage regulator V1 (V1 < V
RTx
)
1: undervoltage
Bit is latched until a “Read and clear” command
V1_RESTART_2
V1_RESTART_1
Indicates the number of TSD2 events which caused a restart of voltage regulator V1
Bits cannot be cleared; counter will be cleared automatically if no additional
TSD2 event occurs within 1 minute.
V1_RESTART_0
WDFAIL_CNT_3
WDFAIL_CNT_2
WDFAIL_CNT_1
Indicates number of subsequent watchdog failures.
Bits cannot be cleared; will be cleared with a valid watchdog trigger
WDFAIL CNT_0
DEVICE_STATE_1 State from which the device woke up
DEVICE_STATE_0
00: Active mode, after Read&Clear command or after Flash mode state
01: Active mode after wake-up from V1_standby mode (before Read&Clear command)
10: in Active mode after Power-on or after wake-up from Vbat_standby mode
(before Read&Clear command)
11: Flash mode (LIN Flash or CAN Flash mode)
TSD2
TSD1
FORCED_SLEEP_
TSD2/V1SC
Bit is latched until a “Read and clear” command
After a “read and clear access”, the device state will be updated
Thermal Shutdown 2 was reached
Bit is latched until a "Read and clear" command
Thermal Shutdown 1 was reached (Logical Or combination of all TSD1_CLx; see status register SR6).
This bit cannot be cleared directly. It is reset if the corresponding TSD1_CLx bits in SR6 are cleared.
Device entered Forced Vbat_standby mode due to:
– Thermal shutdown or
– Short circuit on V1 during startup
Bit is latched until a "Read and clear" command
FORCED_SLEEP_WD
Device entered Forced Vbat_standby mode due to multiple watchdog failures
Bit is latched until a "Read and clear" command
WDFAIL
VPOR
Watchdog failure
Bit is latched until a "Read and clear" command
V
S
Power-on Reset threshold (VPOR) reached
Bit is latched until a "Read and clear" command
DS11546 Rev 5
196
SPI Registers
7.5.2 Status Register SR2 (0x32)
L99DZ100G, L99DZ100GP
Table 144. Status Register SR2 (0x32)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C R R/C
15
14
13
12
Bit
23
22
21
20
19
18
17
16
Name
LIN_PERM_DOM
LIN_TXD_DOM
LIN_PERM_REC
CAN_RXD_REC
CAN_PERM_REC
CAN_PERM_DOM
CAN_TXD_DOM
CAN_SUP_LOW
Table 145. SR2 signals description
Description
LIN bus signal is dominant for t > t dom(bus)
Bit is latched until a “Read and clear” command
TxDL pin is dominant for t > t dom(TXDL)
The LIN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
LIN bus signal does not follow TxDL within t
LIN
The LIN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
RxDC has not followed TxDC for 4 times
The CAN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
CAN bus signal did not follow TxDC for 4 times
The CAN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
CAN bus signal is dominant for t > t
CAN
Bit is latched until a “Read and clear” command
TxDC pin is dominant for t > t dom(TXDC)
The CAN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
Voltage at CAN supply pin reached the CAN supply low warning threshold
V
CANSUP
< V
CANSUPlow
Bit is latched until a “Read and clear” command
DSMON_HS2
DSMON_HS1
DSMON_LS2
DSMON_LS1
Drain-Source Monitoring
‘1’ indicates a short-circuit or open-load condition was detected
Bit is latched until a “Read and clear” command
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
11
10
9
8
7
6
5
4
3
SPI Registers
Name
SPI_INV_CMD
SPI_SCK_CNT
CP_LOW
TW
V2SC
V2FAIL
V1FAIL
VSREG_EW
VSREG_OV
Table 145. SR2 signals description (continued)
Description
Invalid SPI command
‘1’ indicates one of the following conditions was detected:
– access to undefined address
– Write operation to Status Register
– DI stuck at '0' or '1'
– CSN timeout
– Parity failure
– invalid or undefined setting
The SPI frame is ignored
Bit is latched until a “Read and clear” command
SPI clock counter
‘1’ indicates an SPI frame with wrong number of CLK cycles was detected
Bit is latched until a valid SPI frame
Charge pump voltage low
‘1’ indicates that the charge pump voltage is too low
Bit is latched until a “Read and clear” command
Thermal warning
‘1’ indicates the temperature has reached the thermal warning threshold (logical
OR combination of bits TW_CLx in SR6)
Bit is latched until a “Read and clear” command
V2 short circuit detection
‘1’ indicates a short circuit to GND condition of V2 at turn-on of the regulator
(V2 < V2_fail for t > t v2_short
)
Bit is latched until a “Read and clear” command
V2 failure detection
‘1’ indicates a V2 fail event occurred since last readout
(V2 < V2_fail for t > t v2_fail
)
Bit is latched until a “Read and clear” command
V1 failure detection
‘1’ indicates a V1 fail event occurred since last readout
(V1 < V1_fail for t > t v1_fail
)
Bit is latched until a “Read and clear” command
V
SREG
early warning
‘1’ indicates the voltage at V
SREG
(configured in CR3)
has reached the early warning threshold
In Active mode, an interrupt pulse is generated at NINT
Bit is latched until a “Read and clear” command.
Bit needs a "Read and clear" command after wake-up from standby modes
V
SREG
overvoltage
‘1’ indicates the voltage at V
SREG
has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
DS11546 Rev 5
196
SPI Registers
Bit
2
1
0
L99DZ100G, L99DZ100GP
Name
VSREG_UV
VS_OV
VS_UV
Table 145. SR2 signals description (continued)
Description
V
SREG
undervoltage
‘1’ indicates the voltage at V
SREG
has reached the undervoltage threshold
Bit is latched until a “Read and clear” command
V
S
overvoltage
‘1’ indicates the voltage at V
S
has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
V
S
undervoltage
‘1’ indicates the voltage at V
S
has reached the undervoltage threshold
Bit is latched until a “Read and clear” command
7.5.3 Status Register SR3 (0x33)
Table 146. Status Register SR3 (0x33)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
15
14
13
12
11
10
19
18
17
16
23
22
21
20
6
5
4
3
9
8
7
2
1
0
SPI Registers
Name
Table 147. SR3 signals description
Description
OUT1_HS_OC_TH_EX
OUT1_LS_OC_TH_EX
OUT2_HS_OC_TH_EX
OUT2_LS_OC_TH_EX
OUT3_HS_OC_TH_EX
OUT3_LS_OC_TH_EX
OUT4_HS_OC_TH_EX
OUT4_LS_OC_TH_EX
OUT5_HS_OC_TH_EX
OUT5_LS_OC_TH_EX
OUT6_HS_OC_TH_EX
OUT6_LS_OC_TH_EX
OUT7_OC_TH_EX
OUT8_OC_TH_EX
OUT9_OC
OUT10_OC
OUT11_OC
OUT12_OC
OUT13_OC
OUT14_OC
OUT15_OC
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):
Bit is set upon overcurrent condition and output is turned off.
If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):
In case of overcurrent condition this bit is not set. The output goes into
Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'
In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):
Bit is set after thermal expiration and output is turned off
Bit is latched until a “Read and clear” command
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
Bit is latched until a “Read and clear” command
OUTHS_OC_TH_EX
LS2FSO_OC
LS1FSO_OC
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):
Bit is set upon overcurrent condition and output is turned off.
If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):
In case of overcurrent condition this bit is not set. The output goes into
Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'
In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):
Bit is set after thermal expiration and output is turned off
Bit is latched until a “Read and clear” command
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
Bit is latched until a “Read and clear” command
DS11546 Rev 5
196
SPI Registers
7.5.4 Status Register SR4 (0x34)
L99DZ100G, L99DZ100GP
Table 148. Status Register SR4 (0x34)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Access
Bit
17
16
15
14
13
12
11
10
9:3
23
22
21
20
19
18
2
R R/C R R/C
Name
OUT1_HS_OCR_ALERT
OUT1_LS_OCR_ALERT
OUT2_HS_OCR_ALERT
OUT2_LS_OCR_ALERT
OUT3_HS_OCR_ALERT
OUT3_LS_OCR_ALERT
OUT4_HS_OCR_ALERT
OUT4_LS_OCR_ALERT
OUT5_HS_OCR_ALERT
OUT5_LS_OCR_ALERT
OUT6_HS_OCR_ALERT
OUT6_LS_OCR_ALERT
OUT7_OCR_ALERT
OUT8_OCR_ALERT
Reserved
Table 149. SR4 signals description
Description
Autorecovery Alert
‘1’ indicates that the output reached the overcurrent threshold and is in autorecovery mode
Bit is not latched and cannot be cleared.
OUTHS_OCR_ALERT
—
Autorecovery Alert
‘1’ indicates that the output reached the overcurrent threshold and is in autorecovery mode
Bit is not latched and cannot be cleared.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Bit
1
0
SPI Registers
Name
ECV_OC
Table 149. SR4 signals description (continued)
Description
DSMON_HEAT
Drain-Source Monitoring Heater output
‘1’ indicates a short-circuit condition was detected
Bit is latched until a “Read and clear” command
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
Bit is latched until a “Read and clear” command
7.5.5 Status Register SR5 (0x35)
Table 150. Status Register SR5 (0x35)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C
DS11546 Rev 5
196
SPI Registers
Name
OUT1_HS_OL
OUT1_LS_OL
OUT2_HS_OL
OUT2_LS_OL
OUT3_HS_OL
OUT3_LS_OL
OUT4_HS_OL
OUT4_LS_OL
OUT5_HS_OL
OUT5_LS_OL
OUT6_HS_OL
OUT6_LS_OL
OUT7_OL
OUT8_OL
OUT9_OL
OUT10_OL
OUT11_OL
OUT12_OL
OUT13_OL
OUT14_OL
OUT15_OL
OUTHS_OL
GH_OL
ECV_OL
Bit
15
14
13
12
11
10
19
18
17
16
23
22
21
20
6
5
4
3
2
1
0
9
8
7
Table 151. SR5 signals description
Description
L99DZ100G, L99DZ100GP
Open-load
‘1’ indicates an open-load condition was detected at the output
Bit is latched until a “Read and clear” command
DS11546 Rev 5
L99DZ100G, L99DZ100GP
7.5.6 Status Register SR6 (0x36)
SPI Registers
Table 152. Status Register SR6 (0x36)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name Reserved
Access R R/C R R/C
Bit
23
22
21:18
17
16
15:14
13
12
11
10
9
8
7:6
Name
Table 153. SR6 signals description
Description
WD_TIMER_STATE_1 Watchdog timer status
WD_TIMER_STATE_0
00: 0 - 33%
01: 33 - 66%
11: 66 - 100%
Reserved —
ECV_VNR
ECV_VHI
Electrochrome voltage not reached: electrochrome voltage status
'1' indicates the electrochrome voltage is not reached
Bit is not latched
Electrochrome voltage high: electrochrome voltage status
'1' indicates the electrochrome voltage is not reached
Bit is not latched
— Resrved
TW_CL6
TW_CL5
TW_CL4
TW_CL3
TW_CL2
TW_CL1
Reserved
Thermal warning for Cluster x
‘1’ indicates Cluster x has reached the thermal warning threshold
Bit is latched until a “Read and clear” command
—
DS11546 Rev 5
196
Bit
3
2
5
4
1
0
SPI Registers L99DZ100G, L99DZ100GP
Name
TSD1_CL6
TSD1_CL5
TSD1_CL4
TSD1_CL3
TSD1_CL2
TSD1_CL1
Table 153. SR6 signals description (continued)
Description
Thermal shutdown of Cluster x
‘1’ indicates Cluster x has reached the thermal shutdown threshold (TSD1) and the output cluster was shut down
Bit is latched until a “Read and clear” command
Table 154. Status Register SR7 (0x37) to SR9 (0x39)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access
Bit
17
16
15
14
13
12
11:10
23:22
21
20
19
18
R/C R R/C R
Where: x = 2 + (z * 2), z = 0 to 2 y = 1 + (z * 2), z = 0 to 2
Table 155. SR7 to SR9 signals description
Description
—
Name
Reserved
TEMP_CLx_9
TEMP_CLx_8
TEMP_CLx_7
TEMP_CLx_6
TEMP_CLx_5
TEMP_CLx_4
TEMP_CLx_3
TEMP_CLx_2
TEMP_CLx_1
TEMP_CLx_0
Reserved
Temperature Cluster x: Binary coded voltage of temperature diode for cluster x
(bit12 = LSB; bit21 = MSB) (see
Section 4.34: Thermal clusters )
Bits cannot be cleared.
—
DS11546 Rev 5
Bit
3
2
5
4
1
0
7
6
9
8
L99DZ100G, L99DZ100GP SPI Registers
Name
Table 155. SR7 to SR9 signals description (continued)
Description
TEMP_CLy_9
TEMP_CLy_8
TEMP_CLy_7
TEMP_CLy_6
TEMP_CLy_5
TEMP_CLy_4
TEMP_CLy_3
TEMP_CLy_2
TEMP_CLy_1
TEMP_CLy_0
Temperature Cluster y: binary coded voltage of temperature diode for cluster y
(bit0 = LSB; bit9 = MSB) (see
Section 4.34: Thermal clusters )
Bits cannot be cleared.
7.5.8 Status Register SR10 (0x3A)
Table 156. Status Register SR10 (0x3A)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C
Reserved
R/C R
Bit
15
14
13
12
11:0
23:22
21
20
19
18
17
16
Name
Table 157. SR10 signals description
Description
Reserved —
VSREG_9
VSREG_8
VSREG_7
VSREG_6
VSREG_5
VSREG_4
VSREG_3
VSREG_2
Binary coded voltage at V
SREG
pin (bit12 = LSB; bit21 = MSB)
00 0000 0000: 0V xx xxxx xxxx: V
AINVS
/1023 x register value
11 1111 1111: V
AINVS
Bits cannot be cleared.
VSREG_1
VSREG_0
Reserved —
DS11546 Rev 5
196
SPI Registers
7.5.9 Status Register SR11 (0x3B)
L99DZ100G, L99DZ100GP
Table 158. Status Register SR11 (0x3B)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C R R/C R
Bit
12
11:10
9
8
7
6
18
17
16
15
14
13
23
21
20
19
5
4
3
2
1
0
Name
Table 159. SR11 signals description
Description
Reserved —
VS_9
VS_8
VS_7
VS_6
VS_5
VS_4
Binary coded voltage at V
S
pin (bit12 = LSB; bit21 = MSB)
00 0000 0000: 0V xx xxxx xxxx: V
AINVS
/1023 x register value
11 1111 1111: V
AINVS
Bits cannot be cleared.
VS_3
VS_2
VS_1
VS_0
Reserved —
VWU_9
VWU_8
VWU_7
VWU_6
VWU_5
VWU_4
VWU_3
Binary coded voltage at WU pin (bit0 = LSB; bit9 = MSB)
00 0000 0000: 0V xx xxxx xxxx: V
AINVS
/1023 x register value
11 1111 1111: V
AINVS
Bits cannot be cleared.
VWU_2
VWU_1
VWU_0
DS11546 Rev 5
L99DZ100G, L99DZ100GP SPI Registers
7.5.10 Status Register SR12 (0x3C)
Table 160. Status Register SR12 (0x3B)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name
Access R/C R R/C R
Bit
23:21
20
19
18
17
16
12
11
10
9
8
15
14
13
7
6
Name
Reserved
FECNT_4
FECNT_3
FECNT_2
FECNT_1
FECNT_0
Table 161. SR12 signals description
Description
—
CAN Frame Detect Error Counter
This counter is increased by 1 in case a frame was not received/decoded correctly
(CRC error, stuff-bit error, form error).
The counter is decreased by 1 with every frame which is decoded correctly
If FECNT = 31, the next erroneous frame will wake-up the device, set FDERR = 1 and reset FECNTx = 0
‘Live’ Bit Updated after each sent CAN Frame
— Reserved
SWRD_CR29
SWRD_CR28
SWRD_CR27
SWRD_CR26
SWRD_CR25
SWRD_CR24
SWRD_CR23
Status flag for Read operation to Selective Wakeup relevant Registers
0: Read not done
1: Read done
All bits must be ‘1’ in order to allow activation of selective wake-up (set SWEN = 1)
Bits are automatically cleared if the configuration of the respective Control Register is modified
SYSERR
OSC_FAIL
CAN System Error
Bit is a logical OR combination of:
NOT(SWRD_x) OR OSC_Fail OR FD_ERR
If SWRD_x are all 1, OSC_Fail is 0 and FD_ERR is 0, this bit is 0, otherwise this bit is 1.
The selective wake feature cannot be enabled
(SW_EN = 1) if SYS_ERR = 1
In case of a SYS_ERR the selective wake-up feature is disabled (SW_EN = 0)
Live bit; will be updated upon change of SWRD_x, OSC_Fail and FD_ERR
CAN selective wake oscillator failure
OSC Failure Flag (used device internally)
Bit is latched until a read and clear access
DS11546 Rev 5
196
SPI Registers
Bit
5
4
3
2
1
0
L99DZ100G, L99DZ100GP
Name
CAN_SILENT
TX_SYNC
CANTO
WUP
WUF
FDERR
Table 161. SR12 signals description (continued)
Description
Online monitoring bit to see if there is silence on the bus for longer than t
Silence
This flag shows the actual status of the CAN bus (activity/silence). A microcontroller in Stop mode may check this flag priodically
Status flag for synchronous reference oscillator of the CAN transceiver. Indicates that the last received frame was decoded correctly
0: Not synchronous
1: Synchronous
‘Live’ Bit Updated after each sent CAN Frame
CAN communication timeout
Bit is set if there is no communication on the bus for t > t
Silence
CANTO indicates that there was a transition from TRX BIAS to TRX Sleep
Bit is latched until a read and clear access
Wake up flag for Wake up Pattern
Bit is latched until a read and clear access
Wake up flag for Wake up Frame
Bit is latched until a read and clear access
Frame Detect Error
This bit is set at overflow of the Frame Error Counter (FECNT) in SR12
In case of a Frame Detect Error, the device will wake up from TRX BIAS mode
Bit is latched until a read and clear access
DS11546 Rev 5
L99DZ100G, L99DZ100GP Package information
8.1
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
LQFP-64 package information
Figure 62. LQFP-64 package dimension
Symbol
Θ
Θ 1
Θ 2
Θ 3
("1($'5
Table 162. LQFP-64 mechanical data
Millimeters
Min.
0º
0º
11º
11º
Typ. Max.
3.5°
9°
12°
12°
6°
12°
13°
13°
DS11546 Rev 5
196
Package information L99DZ100G, L99DZ100GP
Table 162. LQFP-64 mechanical data (continued)
Millimeters
Symbol
Min.
Typ. Max.
A 1.60
A2 1.35 1.40 1.45 b b1 0.17
0.20
0.27
0.23
c1 0.09
0.127
0.16
6.85
N
R1
R2
S
E3
L
L1
D2
D3 e
E
E1
E2 aaa bbb ccc ddd
5.7
0.50 BSC
12.00 BSC
10.00 BSC
3.3
0.45
0.60
1.00
64
0.08
0.08
0.20
Tolerance of form and position
0.20
0.20
0.08
0.08
4.79
0.75
0.20
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Figure 63. LQFP-64 footprint
Package information
("1($'5
8.2 LQFP-64 marking information
Figure 64. LQFP-64 marking information
.BSLJOHBSFB
.BSLJOHBSFB
PS
4QFDJBMGVODUJPOEJHJUT
&4&OHJOFFSJOHTBNQMF
CMBOL$PNNFSDJBMTBNQMF
-2'15017*&8
OPUJOTDBMF
("%(."(
Parts marked as ES are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.
DS11546 Rev 5
196
Revision history L99DZ100G, L99DZ100GP
Date
16-Mar-2016
01-Sep-2016
12-Sep-2016
29-Sep-2016
11-Mar-2019
Table 163. Document revision history
Revision Changes
1
2
3
4
5
Initial release.
Updated Table 3: Absolute maximum ratings
;
Updated Table 12: Reset output
;
Updated Table 15: Charge pump electrical characteristics ;
Updated Table 17: Power outputs switching times
;
Updated Table 18: Current monitoring ;
Updated Table 20: H-bridge driver
;
Updated Section 4.7.2: Non-recoverable failures – forced Vbat_standby mode ;
Updated Table 115: CR10 signals description ;
Updated Table 143: SR1 signals description
;
Added Section 8.2: LQFP-64 marking information
Updated Table 4: ESD protection
.
Added AEC Q100 compliant qualified
Updated Section 8.2: LQFP-64 marking information
Moved “Device summary” table in cover page.
Added the "Sustainable Technology" logo to the datasheet in cover page.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS11546 Rev 5
197
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Key features
LIN 2.2a compliant (SAEJ2602 compatible) transceiver
Advanced high speed CAN transceiver (ISO 11898-2:2003 /-5:2007 and SAE J2284 compliant) with local failure and bus failure diagnosis and selective wake-up functionality according to ISO 11898-6:2013
1 half bridge for 7.5 A load (RON = 100 mΩ)
1 configurable high-side driver for up to 1.5 A load (RON = 500 mΩ) or 0.35 A (RON = 1600 mΩ)
Fully protected driver for external high-side MOSFET
Control block for electro-chromic element
Two 5 V voltage regulators for microcontroller and peripheral supply
Programmable reset generator for power-on and undervoltage
Configurable window watchdog
Frequently asked questions
The device can handle a maximum load current of 7.5 A for one half bridge.
The device has two 5 V voltage regulators for microcontroller and peripheral supply.
Yes, the device supports selective wake-up functionality according to ISO 11898-6:2013.