STMicroelectronics L99DZ200G Datasheet

L99DZ200G

Automotive front door device with LIN and CAN providing dual

H-bridge driving

Datasheet

-

production data

Features

 AEC-Q100 qualified

 2 configurable half bridges for 7.5 A load

(R

ON

= 150 mΩ) or 3 A load (R

ON

= 300 mΩ)

 2 half bridges for 0.5 A load (R

ON

= 2000 mΩ)

 1 configurable high-side driver for up to 1.5 A

(R

ON load

= 500 mΩ) or 0.35 A (R

ON

= 1600 mΩ)

 1 configurable high-side driver for 0.7 A

(R

ON load

= 800 mΩ) or 0.35 A (R

ON

= 1600 mΩ)

 3 configurable high-side drivers for

0.15 A/0.35 A (R

ON

=2 Ω)

 1 configurable high-side driver for 0.25 A/0.5 A

(R

ON

= 2 Ω) to supply EC Glass MOSFET

 1 configurable P-channel high-side drivers for

0.15 A/0.25 A (R

ON

= 5 Ω)

 Internal 10-bit PWM timer for each stand-alone high-side driver

 Buffered supply for voltage regulators and 1 high-side driver (OUT15 P-channel) to supply e.g. external contacts

 Programmable soft-start function to drive loads with higher inrush currents as current limitation value for OUT1-6 (i.e. motors) and OUT7,

OUT8 (i.e. bulbs) with thermal expiration feature

 Flexible HS drivers (OUT7, OUT8 and OUT9) suitable to drive external LED modules with high input capacitance

 All the embedded outputs come with protection and supervision features:

– Current Monitor (high-side only)

– Open-load and Overcurrent

– Thermal warning and Thermal shutdown

 2 fully protected drivers for external MOSFETs in

H-bridge configuration, dual Half bridge configuration and combined configuration to drive 3 motors

 Fully protected driver for external high-side

MOSFET

 Control block for electro-chromic element

 One 5 V voltage regulators for microcontroller supply

 One 5 V voltage tracker for peripheral supply

 Programmable reset generator for power-on and under voltage

 Configurable window watchdog

 LIN 2.2a compliant (SAEJ2602 compatible and

SAE J2962-1 compliant) transceiver

 Advanced high speed CAN transceiver (ISO

11898-2:2003 /-5:2007 and SAE J2284 & SAE

J2962-2 compliant) with local failure and bus failure; HS-CAN Transceiver Conformance

Test according to «Interoperability test specification for high-speed CAN transceiver or equivalent devices IOPT.CAN v02d00»

 Separated (Isolated) fail-safe block with 2 LS

(R

ON

= 1 Ω) to pull down the gates of the external HS MOSFETs

 Thermal clusters

 A/D conversion of supply voltages and internal temperature sensors

 Embedded and programmable VS duty cycle adjustment for LED driver outputs

 Generator Mode for Power Trunk/Tailgate applications

April 2021 DS13220 Rev 5 1/198 www.st.com

1

2

3

Contents

Contents

L99DZ200G

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.1

LQFP64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

3.4.8

Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4.9

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.10

Outputs OUT1 - OUT15, ECV, ECDR . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.4.11

Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4.12

Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.4.13

Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.14

H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.15

Gate drivers for the external Power-MOS switching times . . . . . . . . . . 41

3.4.16

Drain source monitoring external H-bridges . . . . . . . . . . . . . . . . . . . . . 45

3.4.17

Drain source monitoring external heater MOSFET . . . . . . . . . . . . . . . . 45

3.4.18

Open-load monitoring external H-bridges . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.19

Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . 46

3.4.20

Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.21

Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.4.22

Wake up input WU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.4.23

High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.4.24

LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2/198 DS13220 Rev 5

L99DZ200G

4

Contents

3.4.25

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4.26

Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.27

PWMH(1/2)A, PWMH(1/2)B and DIR inputs . . . . . . . . . . . . . . . . . . . . . 64

3.4.28

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.4.29

Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.4.30

Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.4.31

Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.4.32

SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.1

Supply Vs, Vsreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.2

Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Voltage Regulator Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.3

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Flash Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SW-Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

V1_Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

VBAT_Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4

Wake up from Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4.1

Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.5

Functional Overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.6

Configurable Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.6.1

Change Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.7

Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.7.1

4.7.2

Temporary Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Non-recoverable failures – forced VBAT_Standby mode . . . . . . . . . . . 82

4.8

Reset output (NReset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.9

LIN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.9.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

DS13220 Rev 5 3/198

6

Contents L99DZ200G

4.9.2

4.9.3

4.9.4

Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Wake up from Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.10

High-speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.10.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.10.2

CAN Transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.10.3

Automatic Voltage Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.10.4

Wake up by CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.10.5

CAN looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.10.6

Pretended Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.10.7

CAN Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.11

Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 92

4.12

Power Supply Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.12.1

Vs supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.12.2

Vsreg supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.13

Temperature warning and thermal shut-down . . . . . . . . . . . . . . . . . . . . . 96

4.14

Power Outputs OUT1…15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.15

Auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 98

4.16

Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.17

Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.18

Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.19

Overcurrent Management: Recovery or Latch . . . . . . . . . . . . . . . . . . . . 100

4.20

Overcurrent Recovery and Short-Circuit detection . . . . . . . . . . . . . . . . . 101

4.21

Constant current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.22

Current monitor and direct drive input . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.23

PWM-Mode of the Power-Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.24

Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.25

Programmable soft-start function to drive loads with higher inrush current 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.26

H-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.27

H-Bridge Driver Slew-Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.28

Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.29

Short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . 109

4.30

H-Bridge-Monitoring in Off-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

4.31

Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . .113

4/198 DS13220 Rev 5

6

7

L99DZ200G

5

Contents

4.32

Power window H-bridge safety switch off block . . . . . . . . . . . . . . . . . . .114

4.33

Generator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

4.33.1

Generator Mode in Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.33.2

Generator Mode in Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.34

Heater MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

4.35

Controller of electro-chromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

4.36

Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.37

Thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.38

VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . 122

4.39

Analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.1

ST SPI 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.1.1

Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.2

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.2.1

5.2.2

5.2.3

5.2.4

Clock and data characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Address Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Protocol Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

7.1

Global Status Byte GSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

7.2

Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.3

Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

7.4

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.8

7.4.9

Control Register CR1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Control Register CR2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Control Register CR3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Control Register CR4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Control Register CR5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Control Register CR6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Control Register CR7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Control Register CR8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Control Register CR9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

DS13220 Rev 5 5/198

6

9

10

Contents

8

L99DZ200G

7.4.10

Control Register CR10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

7.4.11

Control Register CR11 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

7.4.12

Control Register CR12 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

7.4.13

Control Register CR13 (0x0D) to CR16 (0x10) . . . . . . . . . . . . . . . . . . 172

7.4.14

Control Register CR17 (0x11) to CR20 (0x14) . . . . . . . . . . . . . . . . . . 173

7.4.15

Control Register CR21 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

7.4.16

Control Register CR22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.4.17

Configuration Register (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.5

Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

7.5.7

7.5.8

Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . 189

Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

7.5.9

Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.5.10

Status Register SR12 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8.1

LQFP-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8.2

LQFP-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6/198 DS13220 Rev 5

L99DZ200G

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pin definition and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Temperature Warning and Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Electrical parameters numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9.

Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10.

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11.

Voltage Regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 12.

Voltage Tracker V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13.

Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 14.

Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 15.

Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16.

Charge pump electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17.

Outputs OUT1 - OUT15, ECV and ECDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 18.

Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 19.

Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20.

Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 21.

H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 22.

Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 23.

Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24.

Drain source monitoring external heater MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25.

Open-load monitoring external H-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26.

Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27.

Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28.

Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29.

Wake-up inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30.

CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 31.

CAN transmit data input: pin TxD_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 32.

CAN receive data output: Pin RxD_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 33.

CAN transmitter dominant output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 34.

CAN transmitter recessive output characteristics, CAN normal mode . . . . . . . . . . . . . . . . 51

Table 35.

CAN transmitter recessive output characteristics, CAN low-power mode,  biasing active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 36.

CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive 51

Table 37.

CAN receiver input characteristics during CAN normal mode . . . . . . . . . . . . . . . . . . . . . . 52

Table 38.

CAN receiver input characteristics during CAN low power mode, biasing active . . . . . . . . 52

Table 39.

CAN Receiver input characteristics during CAN Low power mode, biasing inactive . . . . . 52

Table 40.

CAN receiver input resistance biasing active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 41.

CAN transceiver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 42.

Maximum leakage currents on CAN_H and CAN_L, unpowered . . . . . . . . . . . . . . . . . . . . 54

Table 43.

Biasing control timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 44.

LIN transmit data input: pin TxD_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 45.

LIN receive data output: pin RxD_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 46.

LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 47.

LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

DS13220 Rev 5 7/198

9

List of tables L99DZ200G

Table 48.

Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 49.

Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 50.

DI, CLK and CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 51.

Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 52.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 53.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 54.

Inputs: TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 55.

Inputs PWMH1A, PWMH2A, PWMH1B, PWMH2B, DIR . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 56.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 57.

Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 58.

Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 59.

Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 60.

SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 61.

CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 62.

Wake-up events description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 63.

Status of different functions/features vs operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 64.

Temporary failures description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 65.

Non-recoverable failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 66.

Power output settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 67.

Current Monitor/Direct configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 68.

H-bridge y (y = A, B) control truth table in Single mode (DMy = 0). . . . . . . . . . . . . . . . . . 107

Table 69.

H-bridge y (y = A, B) control truth table in Dual Mode (DMy = 1) for the leg x (x= 1, 2) . . 108

Table 70.

H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 71.

Wake UP for Generator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 72.

Wake UP for Generator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 73.

Heater MOSFET control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 74.

Thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 75.

Operating Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 76.

Global Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 77.

Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 78.

Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 79.

RAM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 80.

ROM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 81.

Information Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 82.

SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 83.

Burst Read Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 84.

SPI Data Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 85.

Data Consistency Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 86.

WD Type/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 87.

WD bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 88.

Global Status Byte (GSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 89.

Global Status Byte (GSB) description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 90.

Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 91.

Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 92.

CR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 93.

Wake-up input1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 94.

CAN transceiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 95.

Voltage regulator V2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 96.

Standby transition configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 97.

CR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 98.

Configuration of Timer x on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 99.

CR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

8/198 DS13220 Rev 5

L99DZ200G List of tables

Table 100. CR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 101. CR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 102. OUTx Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 103. CR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 104. CR7 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 105. CR8 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 106. CR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 107. CR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 108. CR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 109. CR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 110. CR13 to CR16 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 111. CR17 to CR20 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 112. CR21 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 113. CR22 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 114. Configuration Register signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 115. SR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 116. SR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 117. SR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 118. SR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 119. SR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 120. SR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 121. SR7 to SR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 122. SR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 123. SR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 124. SR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 125. LQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 126. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

DS13220 Rev 5 9/198

9

List of figures

List of figures

L99DZ200G

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2.

Pin Connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3.

Activation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4.

Activation profile (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 5.

LQFP64 package and PCB thermal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.

Voltage regulator V1 characteristics (quiescent current and accuracy) . . . . . . . . . . . . . . . 28

Figure 7.

Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 8.

Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9.

H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 10.

IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 11.

IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 12.

LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 13.

SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 14.

SPI input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 15.

SPI output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 16.

SPI CSN - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 17.

SPI – CSN high to low transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 63

Figure 18.

Voltage regulator behavior and diagnosis during supply voltage . . . . . . . . . . . . . . . . . . . . 70

Figure 19.

Sequence to disable/enable the watchdog in CAN Flash mode . . . . . . . . . . . . . . . . . . . . . 71

Figure 20.

Sequence to enter in SW-Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 21.

NINT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 22.

Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 23.

Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 24.

Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 25.

Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 26.

NReset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 27.

RxD_L pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 28.

Wake-up behavior according to LIN 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 29.

RxD_C pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 30.

CAN transceiver state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 31.

CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 32.

Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 33.

Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR, . . . . . . .

thermal expiration occurs after ∆=30°. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 34.

Block diagram of physical realization of AR alert and thermal expiration . . . . . . . . . . . . . . 99

Figure 35.

Charge pump low filtering and start up implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 36.

Example of programmable soft start function for inductive loads and incandescent bulbs101

Figure 37.

Typical working current for a motor connected to OUT1 and OUT6 in low on resistance and

related over-current and short circuit thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 38.

Triggering cases of over-current and short circuit thresholds . . . . . . . . . . . . . . . . . . . . . . 103

Figure 39.

Constant current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 40.

Software strategy for half bridges before applying auto-recovery mode. . . . . . . . . . . . . . 106

Figure 41.

H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 42.

H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 43.

H-bridge open-load-detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 44.

H-bridge open-load-detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 45.

H-bridge open-load-detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 46.

H-bridge open-load-detection (short to Vs detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10/198 DS13220 Rev 5

L99DZ200G List of figures

Figure 47.

PWMH cross current protection time implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 48.

LSx_FSO: low-side driver “passively” turned on, taking supply from output pin . . . . . . . . . .

(if main supply fails), can guarantee VLSx_FSO < VOUT_max . . . . . . . . . . . . . . . . . . . . 115

Figure 49.

Safety concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 50.

Heater MOSFET open-load and short-circuit to GND detection . . . . . . . . . . . . . . . . . . . . 118

Figure 51.

Electro-chrome control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 52.

Thermal clusters identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 53.

Block diagram Vs compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 123

Figure 54.

Sequential ADC Read Out for VSREG, VS, WU and THCL1... THCL6 . . . . . . . . . . . . . . 124

Figure 55.

SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 56.

SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 57.

SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 58.

SDI Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 59.

SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 60.

Window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 61.

Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 62.

Control Register CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 63.

Control Register CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 64.

Timer_x controlled by DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 65.

Control Register CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 66.

Control Register CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 67.

Control Register CR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 68.

Control Register CR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 69.

Control Register CR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 70.

Control Register CR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 71.

Control Register CR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 72.

Control Register CR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 73.

Control Register CR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 74.

Control Register CR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 75.

Control Register CR13 to CR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 76.

Control Registers CR17-CR20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 77.

Control Register CR21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 78.

Control Register CR22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 79.

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 80.

Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 81.

Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 82.

Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 83.

Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 84.

Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 85.

Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 86.

Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 87.

Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 88.

Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 89.

Status Register SR12 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 90.

LQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 91.

LQFP-64 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 92.

LQFP-64 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

DS13220 Rev 5 11/198

11

Description

1

Description

L99DZ200G

The L99DZ200G is a door zone systems IC providing electronic control modules with enhanced power management power supply functionality, including various standby modes, as well as LIN and HS CAN physical communication layers.

The two low-drop voltage regulators of the device supply the system microcontroller and external peripheral loads such as sensors and provide enhanced system standby functionality with programmable local and remote wake-up capability. In addition 5 high-side drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration level.

Three High Side drivers can be configured to support the so-called Constant Current mode conceived to supply external LED modules with huge decoupling capacitors.

Up to 3 DC motors and 8 external MOS transistors (4 for each of the 2 H-bridges) in Hbridge configuration can be driven. An additional gate drive can control an external

MOSFET in high-side configuration to supply a resistive load connected to GND (e.g. mirror heater). An electro-chromic mirror glass can be controlled using the integrated SPI-driven module in conjunction with an external MOS transistor. All outputs are SC protected and implement an open-load diagnosis.

The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables generic software development.

12/198 DS13220 Rev 5

L99DZ200G

2

Block diagram and pin descriptions

Block diagram and pin descriptions

Figure 1. Block diagram

Pin

1

2

3

4

Symbol

WU

GL1B

SH1B

GH1B

CP2M

CP1P

CP1M

VSREG

5V_1

NRESET

5V_2

CAN SUP

RxD_C/NINT

TxD_C

CAN_H

CAN_L

RxD_L/NINT

TxD_L

LIN

GH(1/2)A

SH(1/2)A

GL(1/2)A

PWMH1A

PWMH2A

LSA_FSO

LSB_FSO

PWMH1B

PWMH2B

GH(1/2)B

SH(1/2)B

GL(1/2)B

Charge

Pump

H-Bridge A

Generator

Mode

2 x

Fail Safe

H-Bridge B

Generator

Mode

HS

HS

HS

HS

HS

HS

HS

P-Channel

287Pȍ$UHVSPȍ$

287Pȍ$

287Pȍ$

287Pȍ$UHVSPȍ$

287Pȍ$UHVSȍ$:DWW%XOE

287Pȍ$UHVSȍ$:DWW%XOE

287ȍ$$

287ȍ$$

287ȍ$$

287ȍ$$

287ȍ$$

GH heater

SH heater

2 x

VREG1

VTRK2

HS-CAN

LIN

VSREG

VS

NINT

WU

4 x Tj

Cl 1..4

2 x Tj

Cl 5..6

10 Bit

ADC/SAR

EC Glass

Control Block

6BIT SPI controlled

Direct Drive

ECDR

ECV

CM/DIR

CSN

CLK

DI

DO

GND

(SGND)

PGND

GAPG0508151130CFT

Table 1. Pin definition and functions

Function

Wake-up Input: Input pin for static or cyclic monitoring of external contacts or Vbat measurement (configurable via SPI)

Gate driver for PowerMOS low-side switch in half-bridge 1 (H-bridge B)

Source of high-side switch in half-bridge 1 (H-bridge B)

Gate driver for PowerMOS high-side switch in half-bridge 1 (H-bridge B)

DS13220 Rev 5 13/198

197

Block diagram and pin descriptions L99DZ200G

18

19

20

13

14

15

16

Pin

9

10

11

12

7

8

5

6

17

21

22

23

24

25

26

27

Symbol

Table 1. Pin definition and functions (continued)

Function

GH2B

SH2B

GL2B

CP2M

CP2P

CP

CP1P

CP1M

GHheater

Gate driver for PowerMOS high-side switch in half-bridge 2 (H-bridge B)

Source of high-side switch in half-bridge 2 (H-bridge B)

Gate driver for PowerMOS low-side switch in half-bridge 2 (H-bridge B)

Charge pump pin for capacitor 2, negative side

Charge pump pin for capacitor 2, positive side

Charge pump output

Charge pump pin for capacitor 1, positive side

Charge pump pin for capacitor 1, negative side

Gate driver for external power N-Channel MOSFET in high-side configuration to control the heater

SHheater Source of high-side MOSFET to control the heater

LSA_FSO Fail Safe low-side switch (Active low)

LSB_FSO Fail Safe low-side switch (Active low)

VS

Power supply voltage for power stage outputs (external reverse battery protection required). For this input a ceramic capacitor as close as possible to GND is recommended.

Important: for the capability of driving the full current at the outputs, all pins of VS must be externally connected!

VS; 2nd pin Current capability (pin description see above)

OUT13

OUT10

High-side-driver output to drive LEDs

High-side-driver-output; Important: Beside the bits OUT10_x (CR 5) this output can be switched on setting the ECON bit for electro-chrome control mode with higher priority.

OUT9

OUT7

OUT6

High-side-driver output to drive LEDs; it can be configured to work in Constant Current

Mode.

High-side-driver output to drive LEDs or a 10 Watt bulb (programmable Rdson); it can be configured to work in Constant Current Mode.

Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)

OUT6; 2 nd pin

Current capability (pin description see above)

OUT1

Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)

OUT1; 2 nd pin

Current capability (pin description see above)

OUT8

High-side-driver output to drive LEDs or a 5 Watt bulb (programmable R dson

); it can be configured to work in Constant Current Mode.

14/198 DS13220 Rev 5

L99DZ200G Block diagram and pin descriptions

Pin Symbol

Table 1. Pin definition and functions (continued)

Function

30

31

32

28

29

33

34

35

36

OUT2

Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)

OUT3

Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to V

S

, low-side driver from GND to output)

VS; 3rd pin Current capability (for the pin description see above)

OUT14

PGND

High-side-driver output to drive LEDs

Power Ground

ECV

ECDR

OUT15

V

SREG

SGND

ECV: using the device in EC control mode this pin is used as voltage monitor input. For fast discharge an additional low-side-switch is implemented

ECDR: using the device in EC control mode this pin is used to control the gate of an external

N-Channel MOSFET

P-Channel High-side-driver output to drive LEDs or to supply contacts even in standby mode; supplied by V SREG

Power supply voltage to supply the internal voltage regulator, the internal voltage tracker and

OUT15 (external reverse battery protection required / Diode) for this input a ceramic capacitor as close as possible to GND and an electrolytic back up capacitor is recommended.

Signal Ground 37

38

39

40

41

42

43

44

CM / DIR

CLK

DO

DI

CSN

TxD_L

RxD_L/NINT

Current monitor output / DIR input: depending on the selected multiplexer bits CM_SEL_x

( CR 7 ) of the Control Register, this output sources an image of the instant current; through the corresponding high-side driver with a fixed ratio. This pin is bidirectional. The

Microcontroller can overdrive the current monitor signal to provide the Direct Drive Input.

SPI: serial clock input

SPI: serial data output (push pull output stage)

SPI: serial data input

SPI: chip select not input

LIN Transmit data input

RxD_L -> LIN receive data output; NINT -> indicates local/remote wake-up events (push pull output stage)

CAN transmit data input 45 TxD_C

46 RxD_C/NINT

47

48

NINT

PWMH1B

CAN receive data output; NINT -> indicates local/remote wake-up events (push pull output stage)

Interrupt output (low active; push-pull output stage) to indicate V

SREG early warning (Active mode); indicates wake-up events from V1_Standby mode

PWMH1 input for H-bridge B: this input signal can be used to control the H-bridge B Gate

Drivers.

DS13220 Rev 5 15/198

197

Block diagram and pin descriptions L99DZ200G

Pin

49

50

51

52

57

58

59

53

54

55

56

60

61

62

63

64

TAB

Symbol

Table 1. Pin definition and functions (continued)

Function

PWMH2B

PWMH1A

PWMH2A

NRESET

PWMH2 input for H-bridge B: this input signal can be used to control the H-bridge B Gate

Drivers.

PWMH1 input for H-bridge A: this input signal can be used to control the H-bridge A Gate

Drivers.

PWMH2 input for H-bridge A: this input signal can be used to control the H-bridge A Gate

Drivers.

NReset output to microcontroller; (reset state = LOW) (Low-side switch with drain connected to the output pin and internal pull up resistance to 5V_1)

5V_1 Voltage regulator 1 output: 5 V supply e.g. microcontroller, CAN transceiver

CAN_SUP CAN supply input; to allow external CAN supply from V1 regulator

CAN_L

CAN_H

CAN low level voltage I /

CAN high level voltage I

O

/ O

LIN

GL1A

SH1A

LIN bus line

Gate driver for PowerMOS low-side switch in half-bridge 1 (H-bridge A)

Source of high-side switch in half-bridge 1 (H-bridge A)

GH1A

GH2A

SH2A

GL2A

Gate driver for PowerMOS high-side switch in half-bridge 1 (H-bridge A)

Gate driver for PowerMOS high-side switch in half-bridge 2 (H-bridge A)

Source of high-side switch in half-bridge 2 (H-bridge A)

Gate driver for PowerMOS low-side switch in half-bridge 2 (H-bridge A)

5V_2

Voltage Regulator or Tracker 2 output: 5 V supply for external loads (potentiometer, sensors). 5V_2 pin is protected against short to ground or to battery

Connect to ground

16/198 DS13220 Rev 5

L99DZ200G Block diagram and pin descriptions

Figure 2. Pin Connection (top view)

CP2M

CP2P

CP

CP1P

CP1M

GHheater

SHheater

LSA_FSO

WU

CL1B

SH1B

GH1B

GH2B

SH2B

GL2B

LSB_FSO

10

11

12

13

8

9

6

7

3

4

1

2

5

14

15

16

Tab

L99DZ200G

LQFP-64 40

39

38

44

43

42

41

48

47

46

45

37

36

35

34

33

PWMH1B

NINT

RxD_C/NINT

TxD_C

RxD_L/NINT

TxD_L

CSN

DI

DO

CLK

CM/DIR

SGND

VSREG

OUT15

ECDR

ECV

GAPG0508151137CFT

DS13220 Rev 5 17/198

197

Electrical specifications

3 Electrical specifications

L99DZ200G

3.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 2 may cause permanent damage to the

device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Symbol

Table 2. Absolute maximum ratings

Parameter / Test condition

DC supply voltage / “jump start”

V

S,

V

SREG

5V_1

5V_2

(1)

Load dump

Stabilized supply voltage, logic supply

Stabilized supply voltage

V

DI

, V

CLK

,V

CSN,

V

DO,

V

RXDL/NINT,

V

RXDC,

V

NRESET,

V

CM,

V

DIR

,

V

PWMH

, V

INT

V

TXDC,

V

TXDL

Logic input / output voltage range

Multi-Level Inputs

V

LSA_FSO,

V

LSB_FSO

Output voltage range of Fail-Safe Low-side Switches

DC Wake up input voltage / “jump start”

V

WU

Load dump

V

LIN LIN bus I/O voltage range

Current injection into V

S related input pins I

Input(3)

I

OUT_INJ

(3)

V

CANSUP

(4)

V

CANH

, V

CANL

Current injection into V

CAN supply

S related outputs

CAN bus I/O voltage range

V

CANH

- V

CANL

Differential CAN-Bus Voltage

V

OUTn,

V

ECDR,

V

ECV Output voltage (n = 1,2,3,6,7,8,9,10,13,14,15)

V

GH1

, V

GH2

(V

GHx

) High Voltage Signal Pins

Value [DC Voltage]

-0.3 to +28

-0.3 to +40

-0.3 to 6.5 V1 < V

SREG

-0.3 to +28

(2)

-0.3 to V1+0.3

-0.3 to 40

-0.3 to 35

-0.3 to +28

-0.3 to +40

-20 to +40

20

20

-0.3 to +5.25

-27 to +40

-5 to +10

-0.3 to V S +0.3

V

SHx

-0.3 to V

SHx

+13;

V

CP

+0.3

-0.3 to 13;

-1 to V

S

+0.3

V

GL1,

V

GL2

(V

GLx

) High Voltage Signal Pins

High Voltage Signal Pins

V

SH1

, V

SH2

(V

SHx

)

High Voltage Signal Pins; single pulse with t

200 ns max

=

V

CP1P

V

CP2P

High Voltage Signal Pins

High Voltage Signal Pins

V

CP1M

, V

CP2M

V

CP

High Voltage Signal Pins

High Voltage Signal Pin V

S

≤ 26 V

-5 to 40

V

S

-0.3 to V

S

+14

V

S

-0.6 to V

S

+14

-0.3 to V

S

+0.3

V

S

-0.3 to V

S

+14

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V mA mA

V

V

V

V

V

V

V

V

V

18/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Symbol

Table 2. Absolute maximum ratings (continued)

Parameter / Test condition Value [DC Voltage] Unit

V

GH_heater

High Voltage Signal Pin V

S

> 26 V V

S

-0.3 to +40

V

Sheater

-0.3 to

V

Sheater

+13; V

CP

+0.3

-0.3 to Vs+0.3

V

V

V

SH_heater

IOUT2, IOUT3,

IOUT8, IOUT9,

IOUT10, IOUT13,

IOUT14

IOUT7

IECV, IOUT15

IOUT1,6

I

VScum

I

VScum

Output current

(2)

±2.5

V

A

I

I

I

I

I

I

I

I

I

VScum

VScum

VScum

VScum

VSREG

PGNDcum

PGNDcum

PGNDcum

PGNDcum

Maximum cumulated current at V

S drawn by OUT1

(2)

Maximum cumulated current at V

S drawn by OUT6

(2)

Maximum cumulated current at V

S drawn by OUT3 &

OUT14

(2)

Maximum cumulated current at V S drawn by OUT2 &

OUT8 (2)

Maximum cumulated current at V

S drawn by OUT7

(2)

Maximum cumulated current at V

S drawn by OUT9,

OUT10, OUT13 and CP

Maximum current at V

SREG pin

(2)

(5V_1. 5V_2) &

OUT15

Maximum cumulated current at PGND drawn by

OUT1 (2)

Maximum cumulated current at PGND drawn by

OUT6 (2)

Maximum cumulated current at PGND drawn by

OUT2 (2)

Maximum cumulated current at PGND drawn by OUT3

& ECV

(2)

Maximum current at SGND (2)

PGND versus SGND

±5

±1.25

±10

10

10

2.5

2.5

5

2.5

±1.25

10

10

2.5

2.5

A

A

A

A

A

A

A

A

A

I

SGND

GND pins

±1.25

-0.3 to 0.3

1. 5V_2 is robust against SC to 28 V only in case V

SREG is supplied.

2. Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power dissipation or other limits.

3. Guaranteed by design.

4. When CAN_SUP pin is directly connected to the 5V_1 pin, the relevant absolute maximum rating becomes [-0.3V, 5.25V] for both the connected pins.

A

V

A

A

A

A

A

Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit!

DS13220 Rev 5 19/198

197

Electrical specifications

Note:

L99DZ200G

Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current.

3.2 ESD protection

Table 3. ESD protection

Parameter

All pins

(1)

All power output pins

(2)

: OUT1-15, ECV

Value

+/-2

Unit kV

+/-4 kV

LIN

CAN_H, CAN_L

+/-25

(3)

+/-15

(4)

+/-8

(2)

+/-8

(5)

+/-6

(6)

+/-15

(7)

+/-8

(2)

+/-6

(6)

+/-500 kV kV kV

All pins

(8)

Corner pins

(8)

V

+/-750 V

1. HBM (human body model, 100pF, 1.5 k ) according to AEC-Q100-002.

2. HBM with all none zapped pins grounded.

3. Air discharge for LIN (according to SAE J2962-1, July 2019) C = 150pF, R = 2kΩ and ST ESDLIN1524BJ.

4. Air discharge for LIN (according to SAE J2962-1, July 2019) C = 330pF, R = 2kΩ and ST ESDLIN1524BJ.

5. Indirect ESD Test according to IEC 61000-4-2 (150pF, 330Ω) and 'Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications' (version 1.3, May 2012).

6. Direct ESD Test according to IEC 61000-4-2 (150pF, 330Ω) and 'Hardware Requirements for LIN, CAN and

Flexray Interfaces in Automotive Applications' (version 1.3, May 2012).

7. Air discharge for CAN (according to SAE J2962-2, July 2019) C = 330pF, R = 2kΩ and ST ESDCAN04-

2BWY.

8. Charged Device Model according to AEC-Q100-011.

3.3 Thermal data

Symbol

T j

Table 4. Operating junction temperature

Parameter

Operating junction temperature

Value

-40 to 175

Unit

°C

20/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Note:

Note:

All parameters are guaranteed in the junction temperature range -40 to 150°C (unless otherwise specified); the device is still operative and functional at higher temperatures (up to

175°C).

Parameters limits at higher junction temperatures than 150°C may change with respect to what is specified as per the standard temperature range.

Device functionality at high junction temperature is guaranteed by characterization .

Item (1) Symbol

Table 5. Temperature Warning and Thermal Shutdown

Parameter Min.

F.025

F.026

T

W

Thermal warning threshold T j

(2)

T j

(2)

Cluster 1-4

T

SD1

Thermal shutdown junction temperature 1

F.027

T j

(2)

Cluster 5-6

T j

(2)

F.028

T

SD2

Thermal shutdown junction temperature 2

F.029

T

SD12hys Hysteresis

F.030

T jtft (3)

Thermal warning / shutdown filter time

1. The Item numbering is described in

Section 3.4: Electrical characteristics

.

2. Non-overlapping.

3. Tested by scan.

140

165

165

175

Typ.

150

175

175

185

5

32

Max.

160

185

193

198

Unit

°C

°C

°C

°C

µs

3.3.1 LQFP64 thermal data

L99DZ200G embeds a multitude of junctions (i.e. Outputs based on a Power MOSFET stage) housed in a relatively small piece of silicon. The devices contain, among all the described features, 4 Half-bridges (8 N-Channel PowerMOS), 7 high-sides, two voltage regulators (one of which can work as voltage tracker); all the other derivatives, even if smaller than the family super set device, still contain a significant number of junctions.

For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or major power dissipation contributor) does not allow to predict thermal behavior of the whole device and therefore it is not possible to assess if a device is thermally suitable for a given activation profile and loads characteristics.

Thermal information is provided as temperature reading by different clusters placed close to the most dissipative junctions.

Some representative and realistic worst-case thermal profiles are described in the below paragraph.

The following measurement methods can be easily implemented, by the final user, for a specific activation profile.

L99DZ200G thermal profiles

Activation Profile

DS13220 Rev 5 21/198

197

Electrical specifications L99DZ200G

Battery Voltage: 16 V, ambient temperature start: 85°C

DC activation

 V1 charged with 70 mA (DC activation)

 V2 charged with 30 mA (DC activation)

 OUT7: 1 x10W bulb (DC activation)

 OUT8: 1 x 5W bulb (DC activation)

 OUT13: 300 Ω resistor (DC activation

 OUT14: 300 Ω resistor (DC activation)

Cyclic activation

 OUT1 – OUT6: 5.6 Ω resistor placed across those outputs

– 2 activations of Fold/Unfold. (3s ON; 1s OFF; 2x)

– OUT1 and OUT6 configured with the lowest Rdson

Test execution:

Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation” sequence is applied.

Figure 3. Activation profile

22/198 DS13220 Rev 5

L99DZ200G

Figure 4. Activation profile (first cycle)

Electrical specifications

Figure 5. LQFP64 package and PCB thermal configuration

Note: Layout condition for Thermal Characterization (board finishing thickness 1.5 mm +/- 10%, board four layers, board dimension 77 mm x 114 mm, board material FR4, Cu thickness

0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm).

DS13220 Rev 5 23/198

197

Electrical specifications

3.4 Electrical characteristics

L99DZ200G

For an efficient and easy tracking, numbering has been added to each electrical parameter.

Device features are split into categories, see Table 6 , and each of them is represented by a

letter (A, B, C, etc.); all parameters will be completely identified by a letter and a three digit number (e.g. B.125, C.096…) for their whole lifetime.

New inserted parameters will continue with the numbering of the related category, no matter where they are placed.

To facilitate insertion, the last number inserted for each category is also reported in

Table 6

.

Category

Table 6. Electrical parameters numbering

Parameters numbering

Analog I/O

Digital I/O

Voltage Regulators

Outputs

Transceivers

Others

A.xxx

B.xxx

C.xxx

D.xxx

E.xxx

F.xxx

Last Inserted

A.188

B.034

C.056

D.093

E.092

F.030

3.4.1

Item

A.001

A.002

A.003

A.004

A.005

Due to these rules and taking into account that deleted parameter numbers will be no more reassigned, numbering inside each category may be not sequential.

Supply and supply monitoring

All SPI communication, logic and oscillator parameters are working down to V SREG = 3.5 V and parameters are as specified in the following chapters (guaranteed by design).

 SPI thresholds

 Oscillator frequency (delay times correctly elapsed)

 Internal register status correctly kept (reset at default values for V SREG < V POR )

 Reset threshold correctly detected

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Symbol

V

SUV

V hyst_UV

V

SOV

V hyst_OV

Table 7. Supply and supply monitoring

Parameter Test condition

V

S undervoltage threshold

V

S undervoltage hysteresis

V

S increasing / decreasing

V

S overvoltage threshold

V

S increasing

V

S decreasing

V

S overvoltage hysteresis

Min. Typ. Max. Unit

4.7

0.04

19.5

18.5

0.5

0.1

1

5.4

0.2

22.5

22.5

1.5

V

V

V

V

24/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item Symbol

Table 7. Supply and supply monitoring (continued)

Parameter Test condition Min. Typ. Max. Unit

A.185

A.186

V

SOV_DET

V

S

OverVoltage Detection threshold

V

S

increasing

V

S

decreasing

22.5

21

24

23

25.5

25

V

A.187

V

A.006

A.007

A.008

A.009

A.010

A.011

A.188

A.012

A.013

A.014

A.015

A.016

A.017

A.019

hyst_OV_DET

V

SREG_UV

V

I hyst_UV qCAN

V

S

OverVoltage Detection hysteresis

V

SREG undervoltage threshold

V

SREG undervoltage hysteresis

Quiescent current adder for

CAN wake up activated

V

SREG increasing / decreasing

V

I t

SREG_OV

V

I hyst_OV ovuv_filt

I t

FOV

V(act)

V(BAT)

V(BAT)CS

V

SREG overvoltage threshold

Current consumption in

VBAT_Standby mode with cyclic sense enabled

(1)

V

SREG increasing

V

SREG decreasing

V

SREG overvoltage hysteresis

V

S

/V

SREG over/undervoltage filter time

V

S

OV Detection Filter Time GENERATOR_MODE_EN = 1

Current consumption in

Active mode

V

S

= V

SREG

= 12 V;

TxD CAN = high;

TxD LIN = high;

V1 = ON;

V2 = ON;

HS/LS Driver OFF; CP = ON

Current consumption in

VBAT_Standby mode

(1)

V

S

= 12 V;

Both voltage regulators deactivated;

HS/LS Driver OFF;

No CAN communication;

CAN automatic voltage biasing enabled

V

S

= 12 V;

Both voltage regulators deactivated;

T = 50 ms, t

ON

= 100 µs

I

I

V(BAT)CW

V(V1stby)

Current consumption in

VBAT_Standby mode with

cyclic wake enabled

(1)

Current consumption in

V1_Standby mode

(1)

Current consumption in

V1_Standby mode

(1)(2)

V

S

= 12 V; Both voltage regulators deactivated during standby phase

V

S

= 12 V; Voltage regulator V1 active; (I

V1

= 0); HS/LS Driver

OFF

V

S

= 12 V; Voltage regulator V1 active; (I

V1

= I

CMP

); HS/LS

Driver OFF

Guaranteed by design

0.5

4.2

0.04

19.5

18.5

0.5

8

40

40

16

1

0.1

1

64

64

11

21

100

100

56

0

1.5

4.9

0.2

22.5

22.5

1.5

15

38

143

143

86

146

V

V

V

V

V

µs

µs mA

µA

µA

µA

µA

µA

µA

DS13220 Rev 5 25/198

197

Electrical specifications L99DZ200G

Item Symbol

Table 7. Supply and supply monitoring (continued)

Parameter Test condition Min. Typ. Max. Unit

A.020

A.021

A.022

I

I qLIN

OUT15_DIR

I timer

Quiescent current adder for

LIN wake up activated

Quiescent current adder if

OUT15 i s configured for

Direct Drive; value during output off

Guaranteed by design

Guaranteed by design

Quiescent current adder if timer1 and/or timer 2 are active to provide interrupt on

NINT upon timer expiration

Guaranteed by design

0

0

65

1. Conditions for specified current consumption: 

V

LIN

> (V

S

-1.5 V) 

(V

CAN_H

– V

CAN_L

) < 0.4 V or (V

CAN_H

– V

CAN_L

) > 1.2 V 

V

WU

< 1 V or V

WU

> (V

SREG

– 1.5 V)

2. Iq = Iq0 + 0.1% * I

LOAD

; see also Figure 6: Voltage regulator V1 characteristics (quiescent current and accuracy)

.

5

110

µA

µA

µA

3.4.2 Oscillator

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Table 8. Oscillator

Item

A.023

A.024

Symbol f

CLK1 f

CLK2

(1)

(2)

Parameter

Oscillation frequency OSC1

Oscillation frequency OSC2

1. OSC1: charge pump, SPI, output drivers, watchdog.

2. OSC2: ADC, CAN.

Test condition Min.

1.66

26.8

Typ.

2.0

32.0

Max.

2.34

37.2

Unit

MHz

MHz

3.4.3 Power-on reset (V

SREG

)

All outputs open; T j = -40 °C to 150 °C, unless otherwise specified.

Item

A.025

A.026

A.184

Symbol

V

V

POR_R

POR_F

Table 9. Power-on reset (VSREG)

Parameter Test condition

V

POR threshold rising V

SREG rising

V

POR threshold falling

Min.

Typ.

Max.

Unit

3.45

V

V

SREG falling

(1)

T j

= 25 ºC to 150 ºC 2.45

V

SREG

falling

(1)

T j

= -40 ºC 2.1

1. This threshold is valid if V SREG had already reached V POR_R (max) previously.

4.5

3.5

3.5

V

26/198 DS13220 Rev 5

L99DZ200G Electrical specifications

3.4.4 Voltage regulator V1

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ V S ≤ 28 V; 4.5 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item Symbol

Table 10. Voltage regulator V1

Parameter Test condition Min.

Typ.

Max.

Unit

C.001

C.002

C.004

C.005

C.006

C.007

C.008

C.009

C.010

C.011

C.012

C.013

C.014

C.015

C.019

C.020

C.021

C.022

C.023

V

I

I

I

I

SREG_abs

V1

V1 min

_250mA

V

I

V1

_hi_acc

DP1

CC1

CCmax1

C t load1

TSD

CMP_ris

CMP_fal

CMP_hys

Output voltage

V

SREG absolute minimum value for controlling NRESET output

Output voltage tolerance

High accuracy mode

I

LOAD

= 0 to 100 mA;

V

SREG

= 13.5 V

Output voltage tolerance

(100 to 250 mA)

I

LOAD

= 250 mA; 

V SREG = 13.5 V

Drop-out Voltage

I

LOAD

= 50 mA; V

SREG

= 5 V

I

LOAD

= 100 mA; V

SREG

= 5 V

I

LOAD

= 150 mA; V

SREG

= 5 V

Output current in Active mode

Short circuit output current

Load capacitor1

V1 deactivation time after thermal shut-down

Max. continuous load current

Current limitation

Ceramic (+/- 20%)

Tested by scan

Current comp. rising thresh

Current comp. falling threshold

Current comp.

Hysteresis

V

V

SREG

SREG

= 13.5V

rising/falling

Rising current

Falling current t

V1 fail

V1fail

V1 fail threshold

V1 fail filter time t

V1short

V1 short filter time t

V1FS

V1 forced

Tested by scan

Tested by scan

V1 Fail-Safe Filter Time Tested by scan t

V1off

V1 deactivation time after 8 consecutive WD failures

Tested by scan

-2

-3

340

0.22

2

1.5

150

(1)

5.0

0.2

0.3

0.45

600

1

4.9

4

0.9

2

2

4

2

200

2

2

3

0.4

0.5

0.6

250

900

10

7

6

250

1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.

V

V

%

%

V

V

V mA mA

µF sec mA mA mA ms

V

µs ms ms

DS13220 Rev 5 27/198

197

Electrical specifications L99DZ200G

I q

Figure 6. Voltage regulator V1 characteristics (quiescent current and accuracy)

I q0

High accuracy

(V1 = 5V ± 2%)

V1stdby / WD off

Active mode / WD on

High accuracy

(V1 = 5V ± 2%)

V1stdby / WD on

Active mode / WD on

LOAD

3.4.5

I

CMP

1. The 0.1% reported in the slope is Typical value.

I

LOAD

Voltage regulator V2

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ V S ≤ 28 V; 4.5 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

In case the V2 regulator works as a classical voltage regulator (default case), the electrical

specifications are reported in Table 11

; in case V2 is configured to work as voltage tracker of

V1, the electrical specifications are reported in Table 12

.

Item Symbol

Table 11. Voltage Regulator V2

Parameter Test condition

C.024

C.025

C.026

C.027

C.029

C.030

C.031

C.032

C.033

I

V

V

V

I

2_1mA

2_25mA

2_50mA

C.028

V

2_100mA

V

V2

DP2

CC2

CCmax2

Output voltage

Output voltage tolerance (0 to 1 mA)

Output voltage tolerance (1 to 25 mA)

Output voltage tolerance (25 to 50 mA)

Output voltage tolerance (50 to

100 mA)

I

I

I

I

V

SREG

LOAD

LOAD

LOAD

LOAD

= 13.5 V

= 1 mA; V

SREG

= 25 mA; V

= 50 mA; V

SREG

SREG

= 100 mA; V

= 13.5 V

= 13.5 V

= 13.5 V

SREG

= 13.5 V

Drop-out voltage

I

LOAD

= 25 mA; V

SREG

= 5.25 V

I

LOAD

= 50 mA; V

SREG

= 5.25 V

I

LOAD

= 100 mA; V

SREG

= 13.5 V

Output current in Active mode

Max. continuous load current

Short circuit output current

Current limitation

Min.

-6.5

-3

-4

-4

100

Typ.

Max.

Unit

5.0

V

6.5

%

0.3

0.4

1

150

3

4

4

%

%

%

0.4

0.8

1.6

100 mA

V

V

V

250 mA

28/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item

C.034

C.035

C.036

C.037

Symbol

Table 11. Voltage Regulator V2 (continued)

Parameter Test condition Min.

C load

V2 fail

Load capacitor

V2 fail threshold t

V2fail

V2 fail filter time t

V2short

V2 short filter time

Ceramic (+/- 20%)

V2 forced

Tested by scan

Tested by scan

0.22

(1)

Typ.

Max.

Unit

2

2

4

10

1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.

μF

V

µs ms

Item Symbol Parameter

Table 12. Voltage Tracker V2

Test condition

C.038

C.056

C.039

ΔVo

V

DP2

Output voltage tracking accuracy

I cc2_trk

= 100 μA to 50 mA, I cc1

=30mA,

V sreg

= 6.5 V to 21 V

I cc2_trk

= 100 μA to 50 mA, I cc1

=30mA,

V sreg

= 21 V to 28 V

Tracker Drop-out voltage

I cc2_trk

= 25 mA; VSREG = 5.25 V

C.040

I

CC2_trk

C.041 I

CCmax2_trk

Tracker Output current in Active mode

Tracker Output Current

Limitation

Max. continuous load current

Min.

-15

-20

Typ. Max. Unit

0.3

15

20

0.4

100 mV mV

V mA

100 150 250 mA

C.042

C load_trk

Tracker Load capacitor Ceramic (+/- 20%)

0.22

(1)

10 μF

C.043

C.044

t

V2 fail_trk

V2short_trk

V2 Tracker Short Circuit voltage to switch V2 off and set SPI bit (V2FAIL)

V2 tracker short filter time

Tested by scan

2

4

3

1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.

V ms

3.4.6

Item

C.045

C.046

C.047

C.048

C.049

Reset output

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol

Table 13. Reset output

Parameter

V

RT1falling

Reset threshold voltage1

V

RT2falling Reset threshold voltage2

V

RT3falling

Reset threshold voltage3

V

RT4falling Reset threshold voltage4

V

RTrising

Reset threshold voltage4

Test condition

V

V1 decreasing

V

V1 decreasing

V

V1 decreasing

V

V1 decreasing

V

V1 increasing

Min.

3.25

3.55

3.75

4.1

4.67

Typ.

Max.

Unit

3.5

3.8

4.0

4.3

4.8

3.7

4

4.2

4.5

4.87

V

V

V

V

V

DS13220 Rev 5 29/198

197

Electrical specifications

Item

C.050

C.051

C.052

C.053

C.054

C.055

Symbol

Table 13. Reset output (continued)

Parameter Test condition

V

RESET

Reset Pin low output voltage V1 > 1 V; I

RESET

= 5 mA

R

RESET

Reset pull up int. resistor t

RR

Reset reaction time

I

LOAD

= 1 mA, Tested by scan t

UV1 t t

V1R

WDR

V1 undervoltage filter time Tested by scan

Reset pulse duration (V1 undervoltage and V1 power on reset)

Tested by scan

Reset pulse duration

(watchdog failure)

Tested by scan

Min.

10

6

1.5

3

Typ.

Max.

Unit

0.2

20

0.4

30

V kΩ

16

40 µs

µs

2.0

2.5

ms

4

L99DZ200G

5 ms

3.4.7

Item

A.034

A.035

A.036

A.037

A.038

A.039

A.027

A.028

A.029

A.030

A.031

A.032

A.033

Watchdog timing

4.5 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Symbol

Table 14. Watchdog timing

Parameter t

LW Long open window

T

EFW1

Early Failure Window 1

T

LFW1

Late Failure Window 1

T

SW1

Safe Window 1

T

EFW2

Early Failure Window 2

T

LFW2

Late Failure Window 2

T

SW2 Safe Window 2

T

EFW3

Early Failure Window 3

T

LFW3

Late Failure Window 3

T

SW3

Safe Window 3

T

EFW4

Early Failure Window 4

T

LFW4

Late Failure Window 4

T

SW4 Safe Window 4

Test condition

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Min.

160

20

7.5

100

37.5

200

75

400

150

Typ.

Max.

Unit

200 240

4.5

12 ms

22.3

ms ms

60

45

120

90

240 ms ms ms ms ms ms ms ms ms ms

30/198 DS13220 Rev 5

L99DZ200G

Figure 7. Watchdog timing

Electrical specifications

DS13220 Rev 5 31/198

197

Electrical specifications

Figure 8. Watchdog early, late and safe windows

TSWn = Safe window #1..4

TEFWn = Early Failure window #1..4

TLFWn = Late failure window #1..4

TLFWn_ min

TSWn_min

TEFWn_max

TSWn_max

L99DZ200G

Early

Watchdog failure undefined safe trigger area undefined

Late watchdog failure time

3.4.8

Item

A.040

A.041

A.042

A.043

A.044

A.045

Current monitor output (CM)

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Symbol

V

CM

I

CMr

Table 15. Current monitor output (CM)

Parameter Test condition Min.

Functional voltage range

Current monitor output ratio: ICM/IOUT1,6 and

7(low R

ON

)

Current monitor output ratio: ICM/IOUT1,6 (high

R

ON

)

Current monitor output ratio: ICM/IOUT8 (low

R

ON

)

Current monitor output ratio: ICM/IOUT 2,3 and

ICM/IOUT7,8 (high R

ON

)

Current monitor output ratio:

ICM/IOUT9,10,13,14,15

0 V ≤ V

CM

≤ (V

1

- 1 V)

0

Typ.

1/10000

1/5000

1/6500

1/2000

1/1000

Max.

Unit

V

1

-1V V

32/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item Symbol

Table 15. Current monitor output (CM) (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

A.046

A.047

A.048

A.049

A.050

A.051

I

CM acc_2ol

Current monitor accuracy accI

CMOUT1,6 and 7 

(low R

ON

)

0 V ≤ V

CM

≤ (V

1

- 1 V);

I

OUTmin(1)

= 2 * I

OLD1,6,7

;

I

OUT1,6max

= 7.4 A;

I

OUT7max

= 1.4 A

Current monitor accuracy accI

CMOUT 8 

(low on-resistance)

0 V ≤ V

CM

≤ (V

1

- 1 V);

I

OUTmin(1)

= 2 * I

OLD8

;

I

OUT8max

= 0.6 A

Current monitor accuracy accI

CMOUT 1,6 

(high R

ON

)

0 V ≤ V

CM

≤ (V

1

- 1 V);

I

OUTmin(1)

= 2 * I

OLD1,6

;

I

OUT1,6max

= 2.9 A;

Current monitor accuracy accI

CMOUT2, 3, 9, 13,14,15 and

OUT7,8

(high R

ON

)

0 V ≤ V

CM

≤ (V

1

- 1 V);

I

OUT.min(1)

= 2*I

OLD2,3,9,13,

14,15

;

I

OUT2,3max

= 0.4 A;

I

OUT9,13,14max

= 0.3 A;

I

OUT15

= 0.2 A;

I

OUT7,8 max

= 0.3 A

Current monitor accuracy accI

CMOUT10

0 V ≤ V

CM

≤ (V

1

- 1 V);

I

OUT.min(1)

= 2 * I

OLD10

;

I

OUT10max

= 0.4 A t cmb

Current monitor blanking time

Tested by scan

-8% - 2%

FS

(2)

32

8% +

2%

FS

(2)

1. IOUTmin = 2 * IOLDmax for OUT9, 10, 13, 14 and 15 in low current mode. IOUTmin = 2 * IOLDtyp for the other cases.

2. FS (full scale) = IOUTmax * ICMr.

µs

3.4.9

Item

A.052

A.053

A.054

A.055

A.056

Charge pump

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28V; T j = -40 °C to 150 °C, unless otherwise specified.

Symbol

V

CP

I

CP

I

CPlim

V

CP_low

Table 16. Charge pump electrical characteristics

Parameter Test condition

Charge pump output voltage

Charge pump output current

(1)

Charge pump output current limitation

(2)

Charge pump low threshold voltage

V

S

= 6 V, I

CP

= -15 mA

V

S

≥ 10 V, I

CP

= -15 mA

V

CP

= V

S

+ 10 V; 

V

S

= 13.5 V;

C

1

= C

2

= C

CP

= 100 nF

V

CP

= V

S

; V

S

= 13.5 V;

C

1

= C

2

= C

CP

= 100 nF

Min.

Typ.

Max.

Unit

V

S

+6 V

S

+7 V

V

S

+11 V

S

+12 V

S

+13.5

V

22.5

70

V

S

+4.5

V

S

+5 V

S

+5.5

mA mA

V

DS13220 Rev 5 33/198

197

Electrical specifications L99DZ200G

Item Symbol

Table 16. Charge pump electrical characteristics (continued)

Parameter Test condition Min.

Typ.

A.057

A.058

T f

CP

CP

Charge pump low filter time Tested by scan

Charge Pump frequency Tested by scan

64

400

1. I

CP is the minimum current the device can provide to an external circuit without V

CP going below V

S

+ 10 V.

2. I

CPlim is the maximum current, which flows out of the device in case of a short to V

S

.

Max.

Unit

µs kHz

3.4.10 Outputs OUT1 - OUT15, ECV, ECDR

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V, all outputs open; 

T j = -40 °C to 150 °C, unless otherwise specified.

Item

D.001

D.002

D.003

D.004

D.005

D.006

D.007

D.008

D.009

D.010

D.011

D.012

D.013

D.014

Symbol

Table 17. Outputs OUT1 - OUT15, ECV and ECDR

Parameter Test condition r

ON OUT1,6

(low rdson)

On-resistance to supply or

GND

V

S

= 13.5 V; T j

= 25°C;

I

OUT1,6

= ±3 A

V

S

= 13.5 V; T j

= 130°C

I

OUT1,6

= ±1.5 A and ±3 A

(1)

V

S

= 13.5 V; T j

= 25°C;

I

OUT1,6

= ±1.5 A r r

ON OUT1,6

(high rdson) r r

ON OUT2,3

ON OUT7

ON OUT8

On-resistance to supply or

GND

On-resistance to supply or

GND

V S = 13.5 V; T j = 130°C

I

OUT1,6

= ±1.5 A

V

S

= 13.5 V; T j

= 25 °C;

I

OUT2,3

= ±0.25 A

V

S

= 13.5 V; T j

= 130 °C;

I

OUT2,3

= ±0.25 A

On-resistance to supply in low resistance mode

V S = 13.5 V; T j = 25 °C;

I

OUT7

= -0.8 A

V

S

= 13.5 V; T

I

OUT7

= -0.8 A j

= 130 °C;

On-resistance to supply in high resistance mode

V

S

= 13.5 V; T j

= 25°C; 

I

OUT7

= -0.2 A

V S = 13.5 V; T j = 130 °C;

I

OUT7

= -0.2 A

On-resistance to supply in low resistance mode

I

V

S

= 13.5 V; T j

= 25 °C;

OUT8

= -0.4 A

V

S

= 13.5 V; T j

= 130 °C;

I

OUT8

= -0.4 A

On-resistance to supply in high resistance mode

V S = 13.5 V; T j = 25 °C;

I

OUT8

= -0.2 A

V

S

= 13.5 V; T

I

OUT8

= -0.2 A j

= 130 °C;

Min.

Typ.

Max. Unit

150

300

2000

500

1600

800

1600 mΩ

300 mΩ mΩ

600 mΩ mΩ

4000 mΩ mΩ

1000 mΩ mΩ

3200 mΩ mΩ

1600 mΩ mΩ

3200 mΩ

34/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item Symbol

Table 17. Outputs OUT1 - OUT15, ECV and ECDR (continued)

Parameter Test condition Min.

Typ.

Max. Unit

D.015

D.016

D.017

D.018

D.019

D.020

D.021

D.022

D.023

D.024

D.025

D.026

D.027

D.028

r r

I

ON

OUT9,10,1

3,14

ON OUT15

QLL

On-resistance to supply

On-resistance to supply

V

S

= 13.5 V; T j

= 25 °C;

I

OUT9,10,13,14

= -75 mA

V

S

= 13.5 V; T j

= 130 °C;

I

OUT9,10,13,14

= -75 mA

V

S

= 13.5 V; T j

= 25 °C;

I

OUT15

= -75 mA

V

S

= 13.5 V; T j

= 130 °C;

I

OUT15

= -75 mA r

ON ECV

I

I

QLH

QLH

On-resistance to GND

V

S

= 13.5 V; T j

= 25 °C;

I

OUTECV,ECFD

= +0.4 A

V

S

= 13.5 V; T j

= 130 °C;

I

OUTECV,ECFD

= +0.4 A

Switched-off output current high-side drivers of OUT7- 8-9-

10-13-14-15

V

OUT

= 0 V; standby mode

V

OUT

= 0 V; active mode

Switched-off output current high-side drivers of OUT1-2-3-

6

V OUT = 0 V; standby mode

V

OUT

= 0 V; active mode

Switched-off output current low-side drivers of OUT1-2-3-6

V

OUT

= V

S

; standby mode

V

OUT mode

= V

S

- 0.5 V; active

Switched-off output current low-side driver of ECV

V OUT = V S - 2.5 V with

ECDR = V

S

; standby mode

V

OUT

= V

S

- 2.5 V with

ECDR = V

S

; active mode

1. Guaranteed by design.

-5

-10

-5

-100

-100

-15

-10

2000

5

4000 mΩ

10 mΩ

Ω

Ω

1600 2200 mΩ

2500 3400 mΩ

µA

µA

µA

µA

165 µA

15

µA

µA

µA

3.4.11 Power outputs switching times

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item

D.029

D.030

Symbol t d ON H

Table 18. Power outputs switching times

Parameter Test condition

Output delay time high-side driver on (OUT

1,2,3,6

)

Output delay time high-side driver on (OUT

7,8

)

V

S

= 13.5 V; V

1

= 5 V; corresponding low-side driver is not active

(1)(2)(3)

(from CSN

50% to OUT 50% see

Figure 16: SPI CSN - output timing

)

Min.

Typ.

Max.

Unit

15

20

40

40

80

90

µs

µs

DS13220 Rev 5 35/198

197

Electrical specifications L99DZ200G

Item Symbol

Table 18. Power outputs switching times (continued)

Parameter Test condition

D.031

D.032

D.033

t t d OFF H d ON H

Output delay time high-side driver off (OUT

1,6

)

Output delay time high-side driver off (OUT

2,3, 7,8

)

Output delay time high-side driver on (OUT9, OUT10,

OUT13, OUT14, OUT15)

V

S

= 13.5 V; V

1

= 5 V

(1)(3)

(from CSN 50% to

OUT 50%) see Figure 16: SPI

CSN - output timing

V

S

/V

SREG

= 13.5 V;

V

1

= 5 V; (from CSN 80% to

OUT 80%)

D.034

t d OFF H

Output switch off delay time high- side driver on (OUT9,

OUT10, OUT13, OUT14,

OUT15)

V

S

/V

SREG

= 13.5 V;

V

1

= 5 V; (from CSN 80% to

OUT 20%)

D.035

D.036

t d ON L

Output delay time low-side driver (OUT

1-2-3-6

, ECV) on

Output delay time low-side driver (OUT

1-2-3-6

) off

V

S

= 13.5 V; V

1

= 5 V; corresponding high-side driver is not active

(1)(3)

(from CSN 50% to OUT 50%)

see

Figure 16: SPI CSN - output timing

V

S

= 13.5 V; V

1

= 5 V

(1)(3)

(from CSN 50% to

OUT 50%) see

Figure 16: SPI

CSN - output timing

D.037

D.038

D.039

D.040

D.041

D.042

D.043

D.044

D.045

D.046

f f f t t d HL d LH dVmax/dt f t d OFF L dV dV

OUT

OUT

PWMx

PWMx

PWMx

PWMx

/dt

/dt

Output delay time low-side driver (ECV) off

Cross current protection time

(OUT

1-2-3-6

)

V S = 13.5 V; V 1 = 5 V

(1)(2)(3)

(from CSN 50% to

OUT 50%) see

Figure 16: SPI

CSN - output timing

t cc ONLS_OFFHS

– t d OFF L

(4) t cc ONHS_OFFLS

– t

d OFF L (4)

Slew rate of OUT

1

-OUT

8

,

ECV

Maximum external applied slew rate on OUT1-2-3-6 without switching on the LS and HS (only in Active mode)

Slew rate of OUT9, OUT10,

OUT13, OUT14-OUT15

V

Guaranteed by design

V

S

S

= 13.5 V; V

/V

(1)(3)

SREG

1

= 5 V

= 13.5 V; V

(1)(2)(3)

1

= 5 V

(00) PWM switching frequency

(01) PWM switching frequency

(10) PWM switching frequency

(11) PWM switching frequency

V

S

/V

SREG

= 13.5 V; V

1

= 5 V

Tested by scan

V

S

/V

SREG

= 13.5 V; V

1

= 5 V

Tested by scan

V

S

/V

SREG

= 13.5 V; V

1

= 5 V

Tested by scan

V

S

/V

SREG

= 13.5 V; V

1

= 5 V

Tested by scan

1. R

LOAD

= 16 Ω at OUT

1,6 in high on-resistance mode and OUT

7,8 in low on-resistance mode.

Min.

Typ.

Max.

Unit

20

10

15

40

15

50

0.1

20

1

150 300

70

30

130

30

35

70

150 300

45 110

200 480

0.2

2

100

200

330

500

µs

µs

µs

µs

µs

µs

µs

µs

0.6

V/µs

3

V/µs

V/µs

Hz

Hz

Hz

Hz

36/198 DS13220 Rev 5

L99DZ200G Electrical specifications

2. R

LOAD

= 4 Ω at OUT

4,5 1,6 in low on-resistance mode

.

3. R

LOAD

= 128 Ω at OUT

2,3,4,9,10,13,14, 15

, ECV and OUT

7,8 in high on-resistance mode.

4. t

CC is the switch-on delay time if complement in half bridge has to switch off.

3.4.12 Current Monitoring

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item

D.047

D.048

D.049

D.050

D.051

D.052

Symbol

Table 19. Current monitoring

Parameter Test condition Min.

Typ.

|I

SC_OUT2

|,

|I

SC_OUT3

|

|I

SC_OUT1

|,

|I

SC_OUT6

|

|I

|I

|I

|I

OC2

OC3

OC1

OC6

|,

|,

|

|

Short-circuit threshold HS &

LS

V

S

= 13.5 V, V1 = 5 V, sink

Full V

S design

ranges guaranteed by

Short-circuit threshold HS &

LS in low on resistance mode V

S

= 13.5 V, V1 = 5 V, sink

Short-circuit threshold HS &

LS in high on resistance

Full V

S design

ranges guaranteed by mode

Over-current threshold HS &

LS

Over- current threshold HS &

LS in low on resistance mode

V

S

= 13.5 V, V1 = 5 V, sink

Full V

S design

ranges guaranteed by

V

S

= 13.5 V, V1 = 5 V,  sink and source; Tj = -40 °C to

130 °C

Over - current threshold HS &

LS in high on resistance mode

V

S

= 13.5 V, V1 = 5 V, sink

Full V

S design

ranges guaranteed by

1.05

11

5.5

0.5

7.5

3

Max.

Unit

1.8

17

9

1

11

5

A

A

A

A

A

A

DS13220 Rev 5 37/198

197

Electrical specifications L99DZ200G

Item Symbol

Table 19. Current monitoring (continued)

Parameter Test condition Min.

Typ.

D.053

D.054

D.055

D.056

D.057

D.058

D.059

D.060

|I

OC9

|,

|I

OC13

|,

|I

OC14

|

|I

|I

|I

OC7

OC8

OC10

|

|

|

Overcurrent threshold HS in low on- resistance mode

Overcurrent threshold HS in high on-resistance mode

Overcurrent threshold HS in low on- resistance mode

Overcurrent threshold HS in high on-resistance mode

Overcurrent threshold HS in high current mode

Overcurrent threshold to HS in low current mode

Overcurrent threshold HS in high current mode

Overcurrent threshold HS in low current mode

V

V

S

1

/V

SREG

= 13.5 V;

= 5 V; source

D.061

D.062

D.063

|I

OCECV

| output current threshold LS

D.064

D.093

D.068

D.069

D.070

D.071

D.072

|I

|I

CCM8

|

|I

CCM9

|

|I

OC15

CCM7

|

|

Overcurrent threshold HS in high current mode

Overcurrent threshold HS in low current mode

Constant Current value for

OUT8 and OUT9

Constant Current value for

OUT7

V

S

= 13.5 V; V

1

= 5 V; sink

V

S

= 13.5 V; V

OUTx

> 3.0 V ;

OUTx_CCM_EN = 1 (x= 8, 9)

V

S

= 13.5 V; V

OUT7

> 3.0V ;

OUT7_CCM_EN = 1

(1)

OUTx_CCM_EN = 1 (x= 7, 8,

9)

(2) (3)

D.065

t

CCMtimeout

D.066

t

FSC

Constant Current Mode expiration time

Filter time of short-circuit signal in all drivers

D.067

D.073

D.074

D.075

t t f f t

BLK

OCR00

OCR01 t

OCR10 t

OCR11 f f rec00 rec01 rec10 rec11

(2)

Blanking time of over-current signal in Half Bridges and in

High Sides

Guaranteed by design

Over Current Filter Time for

Half Bridges and High Side

Drivers 7, 8 and 15

OUTxx_OCR_TON = 00 (2)(3)

OUTxx_OCR_TON = 01

(2)(3)

OUTxx_OCR_TON = 10

(2)(3)

OUTxx_OCR_TON = 11

(2)(3)

OUTxx_OCR_FREQ = 00 (2)(3)

Recovery frequency for OC configurable in CR8

OUTxx_OCR_FREQ = 01

(2)(3)

OUTxx_OCR_FREQ = 10

(2)(3)

OUTxx_OCR_FREQ = 11

(2)(3)

1.5

0.35

0.7

0.35

0.35

0.15

0.5

0.25

0.25

0.15

0.5

100

80

1

175

175

10

2

40

2.2

3

4.4

88

80

72

64

1.7

Max.

Unit

2.5

A

0.65

1.3

0.65

0.7

0.3

1

0.5

0.5

A

A

A

A

A

A

A

A

0.3

1.0

250

A

A mA

250 mA

3 ms

µs

µs

µs

µs

µs

µs kHz kHz kHz kHz

38/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item Symbol

Table 19. Current monitoring (continued)

Parameter Test condition

D.076

D.077

t t

AR_HB

AR_HS

Auto recovery time limit for

Half Bridges (OUT1, OUT2,

OUT3, OUT6)

Auto recovery time limit for

High Sides (OUT7, OUT8,

OUT15)

Tested by scan

Tested by scan

D.078

|I

|I

OLD2

|,

OLD3

|

Under-current threshold HS

& LS

V

S

= 13.5 V, V1 = 5 V, sink and source



D.079

D.080

D.081

D.082

D.083

D.084

|I

|I

|I

|I

OLD1

OLD6

OLD7

OLD8

|,

|

|

|

Under-current threshold HS &

LS in low on-resistance mode

Under-current threshold HS &

LS in high on-resistance mode

V

S

= 13.5 V, V1 = 5 V,  sink and source

Under-current threshold HS in low on-resistance mode

Under-current threshold HS in high on-resistance mode

Under-current threshold HS in low on-resistance mode

Under-current threshold HS in high on-resistance mode

D.085

D.086

|I

OLD9

|,

|I

OLD13

|,

|I

OLD14

|

Under-current threshold HS in high current mode

Under-current threshold HS in low current mode

V

S

/V

SREG

= 13.5 V;

V

1

= 5 V; source

D.087

Under -current threshold HS in high current mode

D.088

D.089

|I

OLD10

|

Under -current threshold HS in low current mode

Under -current threshold HS in high current mode

D.090

|I

OLD15

|

Under -current threshold HS in low current mode

D.091

|I

OLDECV

| Under-current threshold LS

D.092

t

OL_out

Filter time of open-load signal

V

S

= 13.5 V; V

1

= 5 V; sink

Duration of open-load condition to set the status bit

(2)

Min.

Typ.

6

40

6

15

5

10

5

6

0.25

10

0.8

6

0.5

6

100

120

20

150

30

40

10

30

10

20

150 200

1. OUT7 in high on-resistance mode.

2. Tested by scan.

3. Where xx = HB, 7, 8, 15.

Max.

Unit

30

300 mA

90

60

15

45

15

12

4

30

4

12

4

30

250 ms mA mA mA mA mA mA mA mA

µs

DS13220 Rev 5 39/198

197

Electrical specifications L99DZ200G

3.4.13 Heater

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item Symbol Parameter

Table 20. Heater

Test condition

A.059

A.060

A.061

A.062

A.063

A.064

A.065

A.066

T

T

I

R

V

R

A.067 t0

GHheaterr

A.068 t0

GHheater

GLheater

GHheater

GSHeater

G(HL)xHL

G(HL)xLH

GHheaterf

Average charge-current

(charge stage)

T j

= 25 °C

On-resistance (discharge- stage)

Gate-on voltage

V

SLx

= 0 V; I

GHx

= 50 mA; T j

= 25 °C

V

SLx

= 0 V; I

GHx

= 50 mA; T j

= 130 °C

V

S

= SH= 6 V;

I

CP

= 15 mA

V

S

= SH = 12 V;

I

CP

= 15 mA

Passive gate-clamp resistance

Propagation delay time high to low (switch mode)

Propagation delay time low to high (switch mode)

Rise time (switch mode)

Fall time (switch mode)

V

R

S

G

V

S

= 13.5 V; V

SHx

= 0 Ω; C

G

= 13.5 V; V

SLx

R

G

= 0 Ω; C

G

= 0;

= 2.7 nF

= 0;

= 2.7 nF

V

S

= 13.5 V;

V

Sheater

= 0; R

G

= 0 Ω;

C

G

= 2.7 nF

V

S

= 13.5 V;

V

Sheater

C

G

= 0; R

= 2.7 nF

G

= 0 Ω;

Min.

4

Typ.

0.3

8

11

V

SHheater

+

6

V

SHheater

+

8

V

SHeater

+ 10

V

SHeater

+ 11.5

15

1.5

1.5

45

85

Max.

Unit

10

14

A

Ω

Ω

V

V kΩ

µs

µs ns ns

3.4.14 H-bridge driver

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40°C to 150 °C, unless otherwise specified.

Item Symbol Parameter

Table 21. H-bridge driver

Test condition

Drivers for external high-side PowerMOS

Min.

A.069

I

GHx(Ch)

Average charge current (charge stage)

T j

= 25 °C

Typ.

0.3

Max.

Unit

A

40/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item Symbol Parameter

Table 21. H-bridge driver (continued)

Test condition Min.

Typ.

Max.

Unit

A.070

A.071

A.072

R

GHx

On-resistance

(discharge- stage)

V

SHx

= 0 V; I

GHx

= 50 mA; 

T j

= 25 °C

V

SHx

= 0 V; I

GHx

= 50 mA; 

T j

= 130 °C

V

S

= SH = 6 V; I

CP

= 15 mA

4

V

SHx

+ 6

10

14

14

20

Ω

Ω

V

A.073

A.074

A.075

A.076

A.077

A.078

A.079

I

R

GSHx

GLx(Ch)

R

GLx

Passive gate-clamp resistance

V

GHx

= 0.5 V

Drivers for external low-side Power-MOS

Average chargecurrent (charge stage)

T j

= 25 °C

On-resistance

(discharge- stage)

V

GHLx

Gate-on voltage

V

SLx

= 0 V; I

GHx

= 50 mA; 

T j

= 25 °C

V SLx = 0 V; I GHx = 50 mA; 

T j

= 130 °C

V

S

= 6 V; I

CP

= 15 mA

V

S

= 12 V; I

CP

= 15 mA

4

15

0.3

10

14

14

20 kΩ

A

Ω

Ω

V

SLx

+ 6 V

V

SLx

+ 8 V

SLx

+ 10 V

SLx

+ 11.5

V

A.080

V

R

GHHx

GSLx

Gate-on voltage

Passive gate-clamp resistance

V

S

= SH = 12 V; I

CP

= 15 mA V

SHx

+ 8 V

SHx

+ 10

15

V

SHx

+

11.5

V kΩ

3.4.15 Gate drivers for the external Power-MOS switching times

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item Symbol

Table 22. Gate drivers for the external Power-MOS switching times

Parameter Test condition Min.

Typ.

Max.

Unit

A.081 T

G(HL)xHL

Propagation delay time high to low (switch mode)

(1)

V

S

= 13.5 V; V

SHx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF

A.082 T

G(HL)xLH

Propagation delay time low to

high (switch mode)

(1)

V

S

= 13.5 V; V

SLx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF

A.083

A.084

I

I

GHxrmax

GHxfmax

Maximum source current

(current mode)

Maximum sink current

(current mode)

V

S

= 13.5 V; V

SHx

= 0;

V

GHx

= 1 V;

SLEW<4:0> = 1 F

H

V

S

= 13.5 V, V

SHx

= 0;

V

GHx

= 2 V;

SLEW<4:0> = 1 F

H

1.5

1.5

32

32

µs

µs mA mA

DS13220 Rev 5 41/198

197

Electrical specifications L99DZ200G

Table 22. Gate drivers for the external Power-MOS switching times (continued)

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

A.085

A.086

dI dI

IGHxr

IGHxf

Source current accuracy

Sink current accuracy

V

S

= 13.5 V; V

SHx

= 0;

V

GHx

= 1 V

V

S

= 13.5 V; V

SHx

= 0;

V

GHx

= 2 V

A.087 V

DSHxrSW

Switching voltage (V

S

-V

SH

) between current mode and switch mode (rising)

A.088 V

DSHxfSW

Switching voltage (V

S

-V

SH

) between switch mode and current mode (falling)

V

V

S

S

= 13.5 V

= 13.5 V

A.089

A.090

A.091

A.092

A.093

A.094

A.095

A.096

A.097

A.098

A.099

A.100

A.101

A.102

A.103

A.104

t0 t0 t0 t0

GHxr

GHxf

GLxr

GLxf tccp tccp tccp tccp tccp tccp tccp tccp tccp tccp tccp tccp

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

Rise time (switch mode)

Fall time (switch mode)

Rise time

Fall time

V

S

= 13.5 V; V

SHx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF

V

S

= 13.5 V; V

SHx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF

V

S

= 13.5 V; V

SLx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF

V

S

= 13.5 V; V

SLx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

See

Figure 10: IGHxr ranges

See

Figure 11: IGHxf ranges

2.8

2.8

45

85

45

85

250

500

750

1000

1250

1500

1750

2000

2250

2500

2750

3000

V

V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

42/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Table 22. Gate drivers for the external Power-MOS switching times (continued)

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

A.105

A.106

A.107

A.108

tccp tccp tccp tccp

1100

1101

1110

1111

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Programmable cross-current protection time

Tested by scan

Tested by scan

Tested by scan

Tested by scan

A.109

f

PWMH PWMH switching frequency (1)

V

S

= 13.5 V; V

SLx

= 0;

R

G

= 0 Ω; C

G

= 2.7 nF;

PWMH-Duty-Cycle = 50%,

Tested by scan

1. Without cross-current protection time t

CCP

.

3250

3500

3750

4000

50 ns ns ns ns kHz

Figure 9. H-driver delay times

T

G(HL)xLH

T

G(HL)xHL

50%

V

CSN,PWMH, DIR t

50%

V

CSN,PWMH, DIR t

80%

V

GS(HL)x

20% t

DS13220 Rev 5 43/198

197

Electrical specifications

Figure 10. IGHxr ranges

L99DZ200G

Figure 11. IGHxf ranges

44/198 DS13220 Rev 5

L99DZ200G Electrical specifications

3.4.16 Drain source monitoring external H-bridges

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40°C to 150 °C, unless otherwise specified.

Item Symbol

Table 23. Drain source monitoring external H-bridge

Parameter

A.110

V

SCd1_HB

Drain-source threshold voltage

A.111

V

SCd2_HB

Drain-source threshold voltage

A.112

V

SCd3_HB

Drain-source threshold voltage

A.113

V

SCd4_HB

Drain-source threshold voltage

A.114

V

SCd5_HB

Drain-source threshold voltage

A.115

V

SCd6_HB

Drain-source threshold voltage

A.116

V

SCd7_HB

Drain-source threshold voltage

A.117

t

SCd_HB

Drain-source monitor filter time

Test condition Min.

A.118

t scs_HB

Drain-source comparator settling time

Tested by scan

V

S

= 13.5 V;

V

SH

= jump from

GND to V

S

0.375

0.6

0,85

1,06

1,27

1,49

1,7

Typ.

0,5

0,75

1

1,25

1,5

1,75

2

6

Max.

Unit

0.625

0.9

1,15

1,43

1,73

2,01

2,3

V

V

V

V

µs

V

V

V

5 µs

3.4.17 Drain source monitoring external heater MOSFET

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item Symbol

Table 24. Drain source monitoring external heater MOSFET

Parameter Test condition

A.119

V

SCd1_HE

Drain-source threshold voltage

A.120

V

SCd2_HE

Drain-source threshold voltage

A.121

V

SCd3_HE

Drain-source threshold voltage

A.122

V

SCd4_HE

Drain-source threshold voltage

A.123

V

SCd5_HE Drain-source threshold voltage

A.124

V

SCd6_HE

Drain-source threshold voltage

A.125

V

SCd7_HE

Drain-source threshold voltage

A.126

V

SCd8_HE

Drain-source threshold voltage

A.127

t

SCd_HE

Drain-source monitor filter time

Tested by scan

A.128

t scs_HE

Drain-source comparator settling time

V S = 13.5 V; V SH = jump from GND to V

S

A.129

t scbl_HE

Drain-source monitoring blanking time

Tested by scan

Min.

320

360

400

440

160

200

240

280

Typ.

6

8

400

450

500

550

200

250

300

350

Max.

480

540

600

660

250

305

360

420

5

µs

µs

µs

Unit mV mV mV mV mV mV mV mV

DS13220 Rev 5 45/198

197

Electrical specifications L99DZ200G

3.4.18 Open-load monitoring external H-bridges

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item Symbol

A.130

A.131

V

ODSL

V

ODSH

A.132

V

OLSHx

A.133

A.134

R pdOL t

OL_HB

Table 25. Open-load monitoring external H-bridge

Parameter Test condition Min.

Low-side drain-source monitor low off-threshold voltage

Low-side drain-source monitor high off-threshold voltage

Output voltage of selected

SHx in open-load test mode

Pull-down resistance of the non- selected SHx pin in open-load mode

Open-load filter time

V

SLx

= 0 V; V

S

= 13.5 V

V

SLx

= 0 V; V

S

= 13.5 V

V

SLx

= 0 V; V

S

= 13.5 V

V

SLx

= 0 V;

V

S

= 13.5 V;

V

SHX

= 4.5 V

Tested by scan

Typ.

0.15 V

S

0.85 V

S

0.5 V

S

20

2

Max.

Unit

V

V

V kΩ ms

3.4.19 Open-load monitoring external heater MOSFET

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40 °C to 150 °C, unless otherwise specified.

Item

A.135

A.136

A.137

Symbol

V

OLheater

I

OLheater t

OL_HE

Table 26. Open-load monitoring external heater MOSFET

Parameter Test condition Min.

Typ.

Max.

Unit

2 V Open-load -threshold voltage V

SLx

= 0 V; V

S

= 13.5 V

Pull-up current source openload diagnosis activated

V

SLx

= 0 V; V

S

= 13.5

V;

V

SHheater

= 4.5 V

Open-load filter time Tested by scan

1

2 mA ms

3.4.20 Electro-chrome mirror driver

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 28 V; 6 V ≤ V SREG ≤ 28 V; T j = -40°C to 150°C, unless otherwise specified.

46/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item

A.138

A.139

A.140

A.141

A.142

A.143

A.144

A.145

Symbol

V

CTRLmax

DNL

ECV

IdV

ECV

I dV

ECVnr dV

ECVhi t

FECVNR t

FECVHI

Table 27. Electro-chrome mirror driver

Parameter Test condition

Maximum EC-control voltage

ECV_HV (Config Reg) = 1

(1)

ECV_HV (Config Reg) = 0

(1)

Differential Non Linearity

Voltage deviation between target and ECV dV

ECV

=V target

(3) -V

ECV

;

II

ECDR

I < 1 µA

Difference voltage between target and ECV sets flag if V

ECV is below it dV

ECV

= V

target(3)

- V

ECV

; toggle bitx = 1; status reg. x

Difference voltage between target and ECV sets flag if V

ECV is above it dV

ECV

= V

target(3)

- V

ECV

; toggle bitx = 1; status reg. x

ECV

NR filter time Tested by scan

ECV

HI filter time Tested by scan

Min.

Typ.

Max.

1.4

1.12

-2

-5% -

1LSB

(2)

120

-135

32

32

1.6

1.28

2

+5% +

1LSB

(2)

A.146

V

ECDRminHIGH

Output voltage range

A.147

V

ECDRmaxLOW

A.148

A.149

I

ECDR

Current into ECDR

I

ECDR

= -10 µA

I ECDR = 10 µA

V

target(3)

> V

ECV

+ 500 mV;

V ECDR = 3.5 V

V

target(3)

< V

ECV

- 500 mV;

V

ECDR

= 1.0 V;

V target

= 0 V; V

ECV

= 0.5 V

V1 -0.3

V

0

-100

10

V1

0.7

-10

100

A.150

R ecdrdis

Pull-down resistance at

ECDR in fast discharge mode and while ECmode is off

V

ECDR

= 0.7 V; ECON = ‘1’,

EC<5:0> = 0 or ECON = ‘0’

10

1. Bit ECV_HV (Config Reg) ='1' or ‘0’: ECV voltage, where II

ECDR can change sign.

2. 1 LSB (Least Significant Bit) = 23.8 mV typ.

3. V target is set by bits EC<5:0> (CR 11) and bit ECV_HV (Config Reg); tested for each individual bit.

Unit

V

V

LSB

(2) mV mV mV

µs

µs

V

V

µA

µA kΩ

3.4.21 Fail safe low-side switch

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 18 V; T j = 40 °C to 150 °C, unless otherwise specified.

Item

A.151

Symbol

V

OUT_max

Table 28. Fail safe low-side switch

Parameter Test condition

Max output voltage in case of missing supply

I OUT = 1 mA;

V

S

= V

SREG

= 0 V

Min.

Typ.

2

Max.

Unit

2.5

V

DS13220 Rev 5 47/198

197

Item

A.152

A.153

A.154

A.155

A.156

A.157

Electrical specifications

A.158

Symbol

R

DSON

I

OLimit t

ONHL t

OFFLH t

SCF dV max

/dt

Table 28. Fail safe low-side switch (continued)

Parameter Test condition Min.

DC output resistance

I

LOAD

= 250 mA; T j

= 25 °C

I

LOAD

= 250 mA; T j

= 130°C

Overcurrent limitation

Turn on delay time to

10% V

OUT

8 V < V

S

< 16 V

Turn off delay time to

90% V

OUT

Short circuit filter time Tested by scan

Maximum external applied slew rate on

LSA_FSO and

LSB_FSO without switching on LS

Guaranteed by design

500

60

L99DZ200G

Typ.

1.4

Max.

Unit

2.2

Ω

Ω

1500 mA

100 µs

64

100 µs

µs

V/µs

3.4.22 Wake up input WU

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V SREG ≤ 28 V; T j = 40 °C to 150 °C, unless otherwise specified.

Item

A.159

A.160

A.161

A.162

Symbol

V

WUthn

V

WUthp

Parameter

Table 29. Wake-up inputs

Test condition

Wake-up negative edge threshold voltage

Wake-up positive edge threshold voltage

V

HYST Hysteresis

Min.

0.4

V

SREG

0.5

V

SREG

0.05

V

SREG

Typ.

0.45

V

SREG

0.55

V

SREG

0.1

V

SREG

64

Max.

Unit

0.5

V

SREG

0.6

V

SREG

0.15

V

SREG

V

V

V

µs

A.163

A.164

A.165

I t

WU_stat

Static wake filter time

WU_stdby

Input current in standby mode

R

WU_act

Input resistor to GND in

Active mode and in

Standby mode during

Wake-up input sensing t

WU_cyc

Cyclic wake filter time

Tested by scan

V

WU

< 1 V or

V

WU

> (V

SREG

– 1.5 V)

Tested by scan

5

80

30

160

16

60

300

μA kΩ

µs

3.4.23 High speed CAN transceiver

ISO 11898-2:2003 and ISO 11898-5:2007 compliant.

SAE J2284 compliant.

48/198 DS13220 Rev 5

L99DZ200G Electrical specifications

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin.

5.5 V ≤ V SREG ≤ 18 V; V CANSUP = V1; T junction = -40 °C to 150 °C, unless otherwise specified.

-12 V ≤ (V CANH + V CANL ) / 2 ≤ 12 V

Item Symbol

Table 30. CAN communication operating range

Parameter Test condition

E.001

V

SREG_COM

Supply voltage operating range for CAN communication

V

V1

= V

CANSUP

E.002

V

CANSUPlow

CAN supply low voltage flag V

V1

= V

CANSUP decreasing

E.003

V

CANHL,CM

Common mode Bus voltage

Measured with respect to the ground of each CAN node

Min.

5.5

4.1

-12

Typ.

Max.

Unit

4.3

18

4.5

12

V

V

V

Item Symbol

Table 31. CAN transmit data input: pin TxD_C

Parameter

E.004

V

TXDCLOW

Input voltage dominant level

E.005

V

TXDCHIGH

Input voltage recessive level

E.006

V

TXDCHYS

V

TXDCHIGH

-V

TXDCLOW

E.007

R

TXDCPU

TXD_C pull up resistor

Test condition Min.

1.0

1.2

0.2

16

E.008

E.009

t d,TXDC(domrec)

TXDC - CAN

H,L delay time dominant - recessive t d,TXDC(recdiff)

TXDC - CAN

H,L delay time recessive - dominant

E.010

t dom(TXDC) TXDC dominant time-out

1. Guaranteed by design.

R

L

= 60 Ω; C

L

= 100 pF;

70% V

RXD

– 30% V

DIFF

;

TXDC rise time = 10 ns

(10% - 90%)

(1)

R

L

= 60 Ω; C

L

= 100 pF;

30% V

RXD

– 70% V

DIFF

;

TXDC fall time = 10 ns

(90% - 10%)

(1)

Tested by scan

0

0

0.8

Typ.

Max.

Unit

1.45

2.0

V

1.85

0.4

35

2.3

0.7

60

V

V kΩ

2

120 ns

120 ns

5 ms

Item

E.011

E.012

E.013

E.014

Symbol

V

RXDCLOW

V

RXDCHIGH t r,RXDC t f,RXDC

Table 32. CAN receive data output: Pin RxD_C

Parameter Test condition Min.

Output voltage dominant level

Output voltage recessive level

I

RXDC

= 2 mA

I

RXDC

= -2 mA

0

V1 - 0.5

RxD_C rise time

RxD_C fall time

C

L

= 15 pF;

30% - 70% V

RXDC

(1)

C

L

= 15 pF;

30% - 70% V

RXDC

(1)

0

0

Typ.

Max.

Unit

0.2

V1 -

0.2

0.5

V1

25

25

V

V ns ns

DS13220 Rev 5 49/198

197

Electrical specifications L99DZ200G

Item Symbol

Table 32. CAN receive data output: Pin RxD_C (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

E.015 t d,RXDC(dom-rec)

CAN

H,L

– RXDC delay time dominant - recessive

E.016

t d,RXDC(rec - dom)

1. Guaranteed by design.

CAN

H,L

– RXDC delay time recessive - dominant

C

L

= 15 pF;

30% - 70% V

RXDC

(1)

C

L

= 15 pF;

30% - 70% V

RXDC

(1)

0

0

120

120 ns ns

Item Symbol

Table 33. CAN transmitter dominant output characteristics

Parameter Test condition Min.

E.017

E.018

E.019

E.020

E.021

E.022

E.023 I

E.024

I

I

I

V

V

V

CANHdom

CANLdom

DIFF,dom

V

SYM

OCANH,dom (0V)

OCANL,dom (5V)

OCANH,dom (40V)

OCANL,dom (40V)

Single ended CANH voltage level in dominant state

Differential output voltage in dominant state:

V

CANHdom

- V

CANLdom

V

R

Single ended CANL voltage level in dominant state

V

TXDC

= V

TXDCLOW

;

R

L

= 50 Ω; 65 Ω

V

R

TXDC

L

= 50 Ω; 65 Ω

TXDC

L

= V

= V

TXDCLOW

TXDCLOW

= 50 Ω; 65 Ω

;

;

Driver symmetry V

V

V

CANHdom

CANLdom

+

SYM

=

Measured over one 250 kHz period (4 µs)

R

L

= 50 Ω; 65 Ω; f

TXDC

= 250 kHz (square wave, 50% duty cycle);

(1)

C

SPLIT

= 4.7 nF (+-5%)

CANH output current in dominant state

CANL output current in dominant state

CANH output current in dominant state

CANL output current in dominant state

V

V

V

V

TXDC

CANH

TXDC

CANL

= V

= V

TXDCLOW

= 0 V

TXDCLOW

= 5 V

;

;

V

TXDC

= V

TXDCLOW

;

V

CANH

= 40 V; R

L

= 65 Ω;

V

S

= 40 V

V

TXDC

= V

TXDCLOW

;

V

CANL

= 40 V;

R

L

= 65 Ω; V

S

= 40 V

1. Measurement equipment input load <20 pF, >1 MΩ.

2.75

0.5

1.5

4.5

-100

45

0

0

Typ.

Max.

Unit

3.5

1.5

2.0

5

-75

75

4.5

2.25

3

5.5

-45

100

5

100

V

V

V

V mA mA mA mA

50/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item

E.025

E.026

E.027

Table 34. CAN transmitter recessive output characteristics, CAN normal mode

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

V

CANHrec

V

CANLrec

V

DIFF,recOUT

CANH voltage level in recessive state

TRX ready state;

V

TXDC

= V

TXDCHIGH

; No load

CANL voltage level in recessive state

TRX Ready state;

V

TXDC

= V

TXDCHiGH

; No load

Differential output voltage in recessive state V

CANHrec

-

V

CANLrec

TRX Ready state;

V

TXDC

= V

TXDCHIGH

; No load

2

2

-50

2.5

2.5

3

3

50

V

V mV

Note: CAN normal mode: tested in TRX ready state while the device is in active mode.

Item

Table 35. CAN transmitter recessive output characteristics, CAN low-power mode, biasing active

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

E.028

V

CANHrecLPbias

E.029

V

CANLrecLPbias

CANH voltage level in recessive state

CANL voltage level in recessive state

E.030

V

DIFF,recOUTLPbias

Differential output voltage in recessive state

V

CANHrec

-V

CANLrec

TRX BIAS state;

V

TXDC

= V

TXDCHIGH

;

No load

TRX BIAS state;

V

TXDC

= V

TXDCHiGH

; No load

TRX BIAS state;

V

TXDC

= V

TXDCHIGH

; No load

2

2

-50

2.5

2.5

3

3

50

V

V mV

Note: CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active mode, V1_Standby mode and VBAT_Standby mode.

Table 36. CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

E.031

E.032

V

V

CANHrecLP

CANLrecLP

E.033

V

DIFF,recOUTLP

CANH voltage level in recessive state

CANL voltage level in recessive state

TRX Sleep state;

V

TXDC

= V

TXDCHIGH

;

No load

TRX Sleep state;

V

TXDC

= V

TXDCHIGH

;

No load

Differential output voltage in recessive state V

CANHrec

-

V

CANLrec

TRX Sleep state;

V

TXDC

= V

TXDCHIGH

;

No load

-0.1

-0.1

-50

0

0

0.1

0.1

50

V

V mV

DS13220 Rev 5 51/198

197

Electrical specifications L99DZ200G

Note: CAN Low Power mode, biasing inactive: tested in TRX sleep state while the device is in active mode, V1_Standby mode and VBAT_Standby mode.

Item

Table 37. CAN receiver input characteristics during CAN normal mode

Symbol Parameter Test condition

E.034

E.035

V

V

THdom

THrec

Differential receiver threshold voltage recessive to dominant state

Differential receiver threshold voltage dominant to recessive state

TRX ready state;

(V

CANH

+ V

CANL

) / 2 = -12

V, 2.5 V, 12 V

(1)

TRX Ready state;

(V

CANH

+ V

CANL

) / 2 = -12

V, 2.5 V, 12 V

(1)

1. Parameter evaluated with specific R L = 60 Ω; guaranteed by characterization.

Min.

Typ.

Max.

Unit

0.5

0.5

—

—

0.9

0.9

V

V

Note: CAN normal mode: tested in TRX ready state while the device is in active mode.

Table 38. CAN receiver input characteristics during CAN low power mode, biasing active

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

E.036 V

THdomLPbias

E.037 V

THrecLPbias

Differential receiver threshold voltage recessive to dominant state

Differential receiver threshold voltage dominant to recessive state

TRX BIAS state;

(V

CANH

+ V

CANL

) / 2 = -12

V, 2.5 V, 12 V

(1)

TRX BIAS state;

(V

CANH

+ V

CANL

) / 2 = -12

V, 2.5 V, 12 V

(1)

1. Parameter evaluated with specific R

L

= 60 Ω; guaranteed by characterization.

0.5

0.5

—

—

0.9

0.9

V

V

Note: CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active mode, V1_Standby mode and VBAT_Standby mode.

Table 39. CAN Receiver input characteristics during CAN Low power mode, biasing inactive

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

E.038

E.039

V

V

THdomLP

THrecLP

Differential receiver threshold voltage recessive to dominant state

TRX sleep state;

(V

CANH

+ V

CANL

) / 2 = -12

V; 0 V; 12 V

(1)

Differential receiver threshold voltage dominant to recessive state

TRX Sleep state;

(V

CANH

+ V

CANL

) / 2 = -12

V; 0 V; 12 V (1)

1. Parameter evaluated with specific R

L

= 60 Ω; guaranteed by characterization.

0.5

0.5

—

—

0.9

0.9

V

V

Note: CAN Low Power mode, biasing inactive: Tested in TRX Sleep state while the device is in active mode, V1_Standby mode and VBAT_Standby mode.

52/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item

E.040

E.041

E.042

E.043

E.044

Symbol

R diff

R

CANH,

CANL m

R

C in

C in,diff

Table 40. CAN receiver input resistance biasing active

Parameter Test condition Min.

Typ.

Max.

Unit

Differential internal resistance

TRX Ready & TRX BIAS states;

V

TXDC

= V

TXDCHIGH

; no load

Single ended

Internal resistance

TRX Ready & TRX BIAS states;

V

TXDC

= V

TXDCHIGH

; no load

Internal Resistance matching

R

CANH,CANL

TRX Ready & TRX BIAS states;

V

TXDC

= V

TXDCHIGH

; no load; m

R

= 2 x (R

CAN_H

- R

CAN_L

) / (R

CAN_H

+

R

CAN_L

)

Internal capacitance

Guaranteed by design

Differential internal capacitance

Guaranteed by design

40

20

-0.03

60

30

50

10

100

50

0.03

20 kΩ kΩ pF pF

Note: CAN Normal and Low Power mode, biasing active: Tested in TRX Ready and TRX BIAS state while the device is in active and V1 Standby mode.

Item Symbol Parameter

Table 41. CAN transceiver delay

Test condition

E.045

E.046

E.047

E.048

E.049

t t t

TXpd,hl

TXpd,lh

T t

Bitrec

CAN

WUP-V1(1)

Loop delay TxD_C to RxD_C (High to

Low)

R

L

= 60 Ω; C

L

= 100 pF; 30% V

TXDC

–

30% V

RXDC

;

TXDC fall time = 10 ns (90% - 10%);

C

RXDC

= 15 pF; f

TXDC

= 250 kHz

Loop delay TxD_C to RxD_C (Low to

High)

R

L

= 60Ω; C

L

= 100pF; 70% V

TXD

–

70% V

RXD

;

TXDC rise time = 10 ns (10% - 90%);

C

RXDC

= 15 pF; f

TXDC

= 250 kHz

Recessive Bit symmetry

R

L

= 60 Ω; C

L

= 100 pF;

70% V

TXDC

(rising) - 30% V

RXDC

(falling); C

RXD

= 15 pF; 10 ns (10% -

90%, 90% - 10%); Rectangular pulse signal T

TXDC

= 6000 ns, high pulse

1000 ns, low pulse 5000 ns

CAN permanent dominant time-out

Time between

WUP (2) on the

CAN bus until V1 goes active

Tested by scan

Wake-Up according to

ISO11898- 5:2007;

70% V

DIFF

– 90% V1(min)

1. Guaranteed by characterization.

2. Time starts with the end of last dominant phase of the WUP.

Min.

765

500

0

Typ.

Max.

Unit

1000 1255

700

255

255

1000

200 ns ns ns

μs

µs

DS13220 Rev 5 53/198

197

Electrical specifications L99DZ200G

Item

Table 42. Maximum leakage currents on CAN_H and CAN_L, unpowered

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

E.050

E.051

E.052

I

I

Leakage,

CANH

Leakage,

CANL

Input leakage current

CANH

Unpowered device; V

CANH

= 5 V;

V

CANL

= 5 V; V

SREG,

V

CANSUP connected via 0 Ω to GND; V

SREG

,

V

CANSUP connected via 47 kΩ to

GND

(1)

T j

= -40 °C to 105 °C (2)

T j

= 130 °C

(3)

Input leakage current CANL

Unpowered device; V

CANH

= 5 V;

V

CANL

= 5 V; V

SREG,

V

CANSUP connected via 0 Ω to GND; V

SREG,

V

CANSUP connected via 47 kΩ to GND

(1)

T j

= -40 °C to 105 °C

(2)

T j

= 130 °C (3)

-10

-12

-10

10

12

10

E.053

-12 12

1. Guaranteed by design.

2. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range.

3. Used for device test only.

μA

μA

Item Symbol Parameter

Table 43. Biasing control timings

Test condition Min.

Typ.

Max.

Unit

E.054

E.055

E.056

E.057

t t t t filter wake

Silence

BIAS

CAN activity filter time

Tested by scan

Wake-up time out

Tested by scan

CAN timeout Tested by scan

Bias reaction time

R

L

= 50 Ω, 65 Ω; C

L

= 100 pF;

C

GND

(= C

SPLIT

) = 100 pF; V

TXDC

=

V

TXDCLOW

;

50% V

DIFF

- V

CANH

=V

CANL

=

V

CAN(H,L)rec(min)

(1)

;

Transition TRX Sleep to TRX BIAS in

Active, V1_Standby and VBAT_Standby modes

0.5

0.5

600

0

1

700

5

5

1200

200

μs ms ms

µs

1. A wake-up-pattern is sent with a bit length of t filter

. T

BIAS is measured from the rising edge after having released the bus at the end of the 2 nd dominant bit until CANH and CANL reach the minimum recessive output voltage (V

CANHrec

, V

CANHrec

).

3.4.24 LIN transceiver

LIN 2.2 compliant for bit-rates up to 20 kbit/s SAE J2602 compatible.

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V SREG ≤ 18 V; T junction = -40 °C to 150°C unless otherwise specified.

54/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item

E.058

E.059

E.060

E.061

Symbol

Table 44. LIN transmit data input: pin TxD_L

Parameter Test condition

V

TXDLOW

Input voltage dominant level Active mode

V

TXDHIGH

Input voltage recessive level Active mode

V

TXDHYS

V

TXDHIGH

-V

TXDLOW

R

TXDPU TXD pull up resistor

Active mode

Active mode

Min.

1.0

0.2

13

Typ.

Max.

Unit

29

2.3

46

V

V

V kΩ

Item

E.062

E.063

Symbol

V

RXDLOW

V

RXDHIGH

Table 45. LIN receive data output: pin RxD_L

Parameter Test condition Min.

Output voltage dominant level

Output voltage recessive level

Active mode

Active mode

Typ.

Max.

Unit

0.2

V1-0.5 V1-0.2

0.5

V

V

E.070

E.071

E.072

E.073

E.074

Item

E.064

E.065

E.066

E.067

E.068

E.069

Symbol

Table 46. LIN transmitter and receiver: pin LIN

Parameter Test condition Min.

Typ.

Max.

Unit

V

THdom

Receiver threshold voltage recessive to dominant state

V

0.4

SREG

V

0.45

SREG

V

0.5

SREG

I

V

V

V

V

V t t

Busdom

V

V

THrec

Busrec

THhys

THcnt

THwkup

THwkdwn

LINBUS dom_LIN

LINDomSC

Receiver dominant state

0.4

V

SREG

Receiver threshold voltage dominant to recessive state

V

0.5

SREG

V

0.55

SREG

V

0.6

SREG

Receiver recessive state

0.6

V

SREG

Receiver threshold hysteresis: V

THrec

-

V

THdom

Receiver tolerance center value: (V

THrec

+V

THdom

)/2

Activation threshold for wake-up comparator

Activation threshold for wake-up comparator

LIN Bus Wake-up

Dominant Filter time

LIN Bus Wake-up

Dominant Filter time

Transmitter input current limit in dominant state

Sleep mode; edge: rec-dom;

Tested by scan

Sleep mode; edge: rec-dom- rec; Tested by scan

V

TXD

= V

TXDLOW

;

V

LIN

= V

BATMAX

= 18 V

0.07

V

SREG

0.475

V

SREG

1.0

V

V

0.1

SREG

0.5

SREG

0.175

V

SREG

0.525

V

SREG

V

SREG

- 3.5

V

SREG

- 2.5

V

SREG

- 1.5

28

40

1.5

64

100

2

180

V

V

V

V

V

V

V

V

μs

μs mA

DS13220 Rev 5 55/198

197

Electrical specifications L99DZ200G

Item Symbol

Table 46. LIN transmitter and receiver: pin LIN (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

E.075

E.076

I

I bus_PAS_dom bus_PAS_rec

E.077

I bus_NO_GND

Input leakage current at the receiver incl. pull-up resistor

Transmitter input current in recessive state

Input current if loss of

GND at device

V

TXD

= V

TXDHIGH

;

V

LIN

= 0 V;

V

BAT

= 12 V; Slave mode

In standby modes;

V

TXD

= V

TXDHIGH

;

V

LIN

> 8 V; V

BAT

< 18 V; V

LIN

≥ V

BAT

GND = V

SREG

;

0 V < V

LIN

< 18 V; V

BAT

= 12

V

E.078

E.079

E.080

E.081

V

V

I bus

LINdom

LINrec

Input current if loss of

V

BAT at device

LIN voltage level in dominant state

LIN voltage level in recessive state

GND = V

S

; 0 V < V

LIN

< 18 V

Tj = -40 °C...105 °C

(1)

GND = V

S

; 0 V < V

LIN

< 18 V

Tj = 130°C

(2)

Active mode;

V

TXD

= V

TXDLOW

RBus=500 Ohm

Active mode;

V

TXD

= V

TXDHIGH

;

I

LIN

= 10 µA

E.082

E.083

R

LINup

C

LIN

LIN output pull up resistor

LIN input capacitance

V

LIN

= 0 V

-1

-1

0.8*V

S

20 40

20

1

30

35

1.2

60

30

1. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range.

2. Used for device test only.

mA

μA mA

μA

μA

V

V kΩ pF

Item

E.084

E.085

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V S < 28V; T j = -40 °C to 150 °C, unless otherwise specified.

Symbol t

RXpd t

RXpd_sym

Table 47. LIN transceiver timing

Parameter Test condition

Receiver propagation delay time

Symmetry of receiver propagation delay time

(rising vs. falling edge) t

RXpd

= max (t

RXpdr

, t

RXpdf

); t

RXpdf

= t(0.5 V

RXD

)-t(0.45 V

LIN

); t

RXpdr

= t(0.5 V

RXD

)-t(0.55 V

LIN

);

V

SREG

= 12 V; C

RXD

=20 pF;

R bus

= 1 kΩ, C bus

= 1 nF;

R bus

= 660 Ω, C bus

= 6.8 nF;

R bus

= 500 Ω, C bus

= 10 nF t

RXpd_sym

= t

RXpdr

- t

RXpdf

;

V

SRE

= 12 V; R bus

= 1 kΩ;

C bus

= 1 nF; C

RXD

= 20 pF

Min.

Typ.

Max.

Unit

-2

6

2

μs

μs

56/198 DS13220 Rev 5

L99DZ200G

Item

E.086

E.087

E.088

E.089

E.090

E.091

E.092

Electrical specifications

Symbol

D1

D2

D3

D4 t dom(TXDL) t

LIN t dom(bus)

Table 47. LIN transceiver timing (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

Duty Cycle 1

Duty Cycle 2

Duty Cycle 3

Duty Cycle 4

TH

Rec

(max) = 0.744 * V

SREG

;

TH

Dom

(max) = 0.581 * V

SREG

;

V

SREG

= 7 to 18 V, t bit

= 50 µs;

D1 = t bus_rec

(min) / (2 x t bit

); R bus

= 1 kΩ, C bus

= 1 nF;

R bus

= 660 Ω, C bus

= 6.8 nF;

R bus

= 500 Ω, C bus

= 10 nF

TH

Rec

(min) = 0.422*V

SREG

;

TH

Dom

(min) = 0.284*V

SREG

;

V

SREG

= 7.6 to 18 V, t bit

= 50 µs;

D2 = t bus_rec

(max) / (2 x t bit

);

R bus

= 1 kΩ, C bus

= 1 nF;

R bus

= 660 Ω, C bus

= 6.8 nF;

R bus

= 500 Ω, C bus

= 10 nF

TH

Rec

(max) = 0.778* V

SREG

;

TH

Dom

(max) = 0.616* V

SREG

;

V

SREG

= 7 to 18 V, t bit

= 96 µs;

D3 = t bus_rec

(min) / (2 x t bit

);

R bus = 1 kΩ, C bus = 1 nF;

R bus

= 660 Ω, C bus

= 6.8 nF;

R bus = 500 Ω, C bus = 10 nF

TH

Rec

(min) = 0.389*V

SREG

;

TH

Dom

(min)= 0.251*V

SREG

;

V

SREG

= 7.6 to 18 V, t bit

= 96 µs;

D4 = t bus_rec

(max) / (2 x t bit

);

R bus

= 1 kΩ, C bus

= 1 nF;

R bus

= 660 Ω, C bus = 6.8 nF;

R bus

= 500 Ω,

C bus

= 10 nF

0.39

6

0.41

7

TXD_L dominant time- out

LIN permanent recessive time-out

LIN Bus permanent dominant time-out

Tested by scan

Tested by scan

Tested by scan

12

40

12

0.581

0.590

ms

μs ms

DS13220 Rev 5 57/198

197

Electrical specifications L99DZ200G

Figure 12. LIN transmit, receive timing t

TXpdf t

TXpdr

V

TxD time

V

LINrec 80%

V

LIN

V

THrec

V

THdom

V

LINdom

20% time

V

RxD time t

RXpdf t

RXpdr

GAPG0608151126CFT

3.4.25 SPI

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V SREG < 18 V; V1 = 5 V; all outputs open; T j = -40 °C to 150 °C, unless otherwise specified.

Item

B.001

B.002

B.003

B.004

Symbol

Table 48. Input: CSN

Parameter Test condition

V

CSNLOW Input voltage low level Normal mode

V

CSNHIGH

Input voltage high level Normal mode

V

CSNHYS

V

CSNHIGH

- V

CSNLOW

Normal mode

I

CSNPU

CSN Pull up resistor Normal mode

Min.

Typ.

Max.

Unit

1.0

0.2

13 29

2.3

46

V

V

V kΩ

Item

B.005

B.006

B.007

B.008

B.009

B.010

Symbol t set t set_CP

V in_L

V in_H

V in_Hyst

I pdin

Table 49. Inputs: CLK, DI

Parameter Test condition

Delay time from standby to Active mode

Time until SPI, ADC and

OUT15 are operative

Delay time from standby to Active mode

Time until power stages that are supplied by the CP are operative

Input low level

Input high level

Input hysteresis

Pull down current at input

V in

= 1.5 V

Min.

Typ. Max.

Unit

10 µs

560 750 960 µs

1.0

0.2

5 30

2.3

60

V

V

V

µA

58/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item Symbol

Table 49. Inputs: CLK, DI (continued)

Parameter Test condition

B.011

B.012

C f in

(1)

CLK

Input capacitance at input CSN, CLK, DI

SPI input frequency at

CLK

Guaranteed by design

Tested by scan

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Min.

Typ. Max.

Unit

15

4 pF

MHz

Item

B.013

B.014

B.015

B.016

B.017

B.018

B.019

B.020

B.021

Symbol t

CLK t

CLKH t

CLKL t set_CSN t set_CLK t set_DI t hold_DI t r_in t f_in

Table 50. DI, CLK and CSN timing

Parameter Test condition

Clock period

Clock high time

Clock low time

CSN setup time, CSN low before rising edge of CLK

CLK setup time, CLK high before rising edge of CSN

DI setup time

DI hold time

Rise time of input signal DI,

CLK, CSN

Fall time of input signal DI,

CLK, CSN

Tested by scan

Min.

250

100

100

150

150

25

25

Typ.

Max.

Unit ns ns ns ns

25

25 ns ns ns ns ns

Note:

Item

B.022

B.023

B.024

B.025

See

Figure 14: SPI input timing

.

Symbol

V

DOL

V

DOH

I

DOLK

C

DO

Parameter

Table 51. Output: DO

Test condition

Output low level I

DO

= + 4 mA

Output high level I

DO

= - 4 mA

3-state leakage current

V

CSN

= V1, 0 V < V

DO

< V1

3-state input capacitance

Guaranteed by design

Min.

V1 - 0.5

-10

Typ.

Max.

Unit

0.5

V

V

10 μA

10 15 pF

Item

B.026

B.027

Symbol t r DO t f DO

Parameter

Table 52. DO timing

Test condition

DO rise time

DO fall time

C

L

= 50 pF; I

LOAD

= -1 mA

C

L

= 50 pF; I

LOAD

= +1 mA

Min.

-

-

Typ.

Max.

Unit

25

(1)

25 (1)

ns ns

DS13220 Rev 5 59/198

197

Electrical specifications L99DZ200G

Item

B.028

B.029

B.030

B.031

B.032

Symbol t en DO tri L t dis DO L tri t en DO tri H t dis DO H tri t d DO

Table 52. DO timing (continued)

Parameter Test condition

DO enable time from

CSN falling edge: 3state to low level on

DO

C

L

= 50 pF; I

LOAD pull-up load to V1

= +1 mA;

DO disable time from

CSN rising edge: low level to 3-state on DO

C

L

= 50 pF; I

LOAD pull-up load to V1

= +1 mA;

DO enable time from

CSN falling edge:

3-state to high level on

DO

C

L

= 50 pF; I

LOAD

= +1 mA; pull-up load to V1

From CSN rising with

DO at high level to 3states measured at 0.3

V1

C

L

= 50 pF; I

LOAD

= -1 mA; pull-down load to GND

DO delay time

V

DO

< 0.3 V1;

V

DO

> 0.7 V1; C

L

= 50 pF

1. Guaranteed by design.

Min.

-

-

-

-

-

Typ.

Max.

Unit

50

50

50

50

30

100 ns

100 ns

100 ns

100 ns

60 ns

Note:

Item

B.033

B.034

See

Figure 15: SPI output timing .

Symbol t

CSN_HI,min t

CSNfail

Parameter

Table 53. CSN timing

Test condition

Minimum CSN

High time, active mode

Transfer of SPI-command to

Input Register

CSN low timeout Tested by scan

Min.

6

20

Typ.

Max.

Unit

35 50

μs ms

Note: See

Figure 15: SPI output timing .

60/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Figure 13. SPI – transfer timing diagram

CSN

CLK

DI

CSN

CLK

DI

DO

Input

Data

Register

CSN high to low: DO enabled time

31 30 29 28 27 26 25 24

X X

5 4 3 2 1 0

DI: data will be accepted on the rising edge of CLK signal

31 30 29 28 27 26 25 24 X X 5 4 3 2 1 0

Command Byte Data

DO: data will change on the falling edge of CLK signal

31 30 29 28 27 26 25 24

Global Status Byte

Global Error

X X 5 4 3 2 1 0

CSN low to high: actual data is transfered to output power switches old data

31

31 30

31 30 time time

30 time new data time

GAPG0909151612CFT

The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

Figure 14. SPI input timing

0.8 VCC

0.2 VCC t set CSN t

CLKH t set CLK

0.8 VCC

0.2 VCC t set DI t hold DI t

CLKL

Valid Valid

0.8 VCC

0.2 VCC

DS13220 Rev 5 61/198

197

Electrical specifications

CLK

DO

(low to high)

DO

(high to low)

CSN

L99DZ200G

Tf

CLK

Figure 15. SPI output timing

Tr

CLK

Tf

CSN

Tr

DO

Td

DO

Tf

DO

Ten

DO_tri_L

Ten

DO_tri_H

Tr

CSN

0.8 Vcc

0.5 Vcc

0.2 Vcc

50 %

Tdis

DO_L_tri

Tdis

DO_H_tri

50 %

GAPG0608151112CFT

0.8 Vcc

0.5 Vcc

0.2 Vcc

0.8 Vcc

0.2 Vcc

0.8 Vcc

0.2 Vcc

62/198 DS13220 Rev 5

L99DZ200G

CSN

Output voltage of a driver

Output voltage of a driver

Electrical specifications

Figure 16. SPI CSN - output timing

CSN low to high: data from shift register is transferred to output powers switches t r i n t

CSN_HI,min t f in

80%

50%

20% t d O F F

ON state OFF state

80%

50%

20% t d O N t

O F F t

O N

OFF state ON state

80%

50%

20%

GAPG0608151117CFT

Figure 17. SPI – CSN high to low transition and global status bit access transferred

3.4.26 Inputs TxD_C and TxD_L for Flash mode

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V ≤ V SREG ≤ 18; V1 = 5 V; T j = -40 °C to 150 °C.

DS13220 Rev 5 63/198

197

Electrical specifications L99DZ200G

Item

A.166

A.167

A.168

Symbol

Table 54. Inputs: TxD_C and TxD_L for Flash mode

Parameter

V

V flashL flashH

Input low level (V

TXDC/L for exit from Flash mode)

Input high level (V

TXDC/L for transition into Flash mode)

V flashHYS

Input voltage hysteresis

Test condition

-

-

-

Min.

6.1

7.4

0.6

Typ.

Max. Unit

7.25

8.4

V

V

8.4

0.8

9.4

1.0

V

3.4.27 PWMH(1/2)A, PWMH(1/2)B and DIR inputs

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V SREG ≤ 18 V; T j = -40 °C to 150 °C.

DIR Input refers to the CM_DIR pin when working as a Direct Drive Input (see Section 4.22:

Current monitor and direct drive input

).

Item Symbol

Table 55. Inputs PWMH1A, PWMH2A, PWMH1B, PWMH2B, DIR

Parameter Test condition Min.

Typ.

Max.

Unit

A.169

A.170

A.171

A.172

A.173

V

IL

V

IH

Input voltage low level

Input voltage high level

V

IHYS

Input hysteresis

I in

Input pull-down current

C in

(1)

Input capacitance at input

PWMH1A, PWMH2A,

PWMH1B and PWMH2B

V

SREG

= 13.5 V

V SREG = 13.5 V

V

SREG

= 13.5 V

V

SREG

= 13.5 V

Guaranteed by design

1

0.2

5

1. Value of input capacitance is not measured in production test. Parameter guaranteed by design.

30

2.3

60

15 pF

V

V

V

µA

3.4.28 ADC characteristics

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V SREG ≤ 18 V, T j = -40 °C to 150 °C.

Item

F.001

F.002

Symbol t con f

ADC

Table 56. ADC characteristics

Parameter Test condition

Conversion time Tested by scan

Clock frequency (see f clk2

) Tested by scan

Min.

Typ.

Max.

Unit

3

8

µs

MHz

64/198 DS13220 Rev 5

L99DZ200G Electrical specifications

Item

F.003

F.004

F.005

F.006

F.007

F.008

F.009

F.010

Symbol

Acc

IE

I

I

IE

D

I

V

AINVS

F.011

V

AINTemp

1. Guaranteed by design .

Table 56. ADC characteristics (continued)

Parameter Test condition

Accuracy

Voltage divider + reference

(1)

Overall accuracy for WU input:

V

WU

= 22 V

Overall accuracy for WU input:

V

WU

= 18 V

Overall accuracy for WU input:

V

WU

= 6 V

Overall accuracy for WU input:

V

WU

= 4.5 V

Integral linearity error

Differential linearity error

Conversion voltage range

(V

S

, V

SREG

& WU)

Conversion voltage range

(T

CL

1 …T

CL

6)

Min.

Typ.

Max.

Unit

-2

-3

-3.5

-4

-4.6

1

0

4

2

2

3

3.5

4

4.6

6

4

22

2

%

LSB

LSB

V

V

3.4.29 Temperature diode characteristics

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V SREG ≤ 18 V, T j = -40 °C to 150 °C

Item

A.174

A.175

Symbol

Table 57. Temperature diode characteristics

Parameter

V

TROOM 1-6

V

TSENSE1-6

T

SENSE output voltage at 25 °C

T

SENSE output voltage

Test condition

V

S

= 12 V; T = 25 °C

T = 25 °C; T = 130 °C;

T = -40 °C

Min.

—

—

Typ.

Max.

Unit

1.4

-4

V mV/

K

3.4.30 Interrupt outputs

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V SREG ≤ 18 V, T j = -40 °C to 150°C

Item

A.176

A.177

A.178

Symbol

Table 58. Interrupt outputs

Parameter

V

INTL

Output low level

V

INTH

Output high level

I

INTLK

3-state leakage current

Test condition

I

INT

= +4 mA

I

INT

= -4 mA

0 V < V

INT

< V1

Min.

V1 - 0.5

-10

Typ.

Max.

Unit

0.5

10

V

V

μA

DS13220 Rev 5 65/198

197

Electrical specifications

Item

A.179

A.180

Symbol

Table 58. Interrupt outputs (continued)

Parameter t

Interrupt

Interrupt pulse duration

(NINT, RxD_L/NINT,

RxD_C/NINT t

Int_react

Interrupt reaction time

Test condition

Tested by scan

Tested by scan

Min.

6

L99DZ200G

Typ.

Max.

Unit

56

40

μs

µs

66/198 DS13220 Rev 5

L99DZ200G

3.4.31 Timer1 and Timer2

6 V ≤ V SREG ≤ 18 V; T j = -40 °C to 150 °C

Item

F.019

F.020

F.021

F.022

F.023

F.024

F.012

F.013

F.014

F.015

F.016

F.017

F.018

Symbol

T3

T4

T5

T6

T7

T8 ton 1 ton 2 ton 3 ton 4 ton 5

T1

T2

Table 59. Timer1 and Timer2

Parameter Test condition

Timer on time

Timer on time

Timer on time

Timer on time

Timer on time

Timer period

Timer period

Timer period

Timer period

Timer period

Timer period

Timer period

Timer period

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

Tested by scan

3.4.32 SGND loss comparator

T j = -40 °C to 150 °C, unless otherwise specified

Item

A.181

A.183

A.182

Symbol

Table 60. SGND loss comparator

Parameter Test condition

V

SGNDloss

V

SGND loss threshold (V

SGND

– V

PGND

)

V

SGNDloss_hys t

SGNDloss

V

SGND loss filter time Tested by scan

Electrical specifications

Min.

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ.

Max.

Unit

50

100

200

500

1000

2000

10

20

10

20

0.1

0.3

1

-

-

-

-

-

-

-

-

-

-

-

-

ms ms ms ms ms ms ms ms ms ms ms ms ms

Min.

200

40

-

Typ.

Max.

Unit

420

70

7

650 mV

150 mV

µs

DS13220 Rev 5 67/198

197

Application information

4 Application information

4.1

L99DZ200G

Supply V s

, V sreg

V SREG supplies voltage regulator V1, voltage tracker V2, all internal regulated voltages for analog and digital functionality, LIN, CAN, the EC control block and the P-channel high-side switch OUT15. All other high-sides, Fail Safe block and the charge pump are supplied by V S .

In case the V SREG pin is disconnected, all power outputs connected to V S are automatically switched off.

4.2

4.2.1

4.2.2

Voltage Regulators

The device contains two independent and fully protected low drop voltage regulators designed for very fast transient response and do not require electrolytic output capacitors for stability.

Voltage regulator: V1

The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load current to supply the system microcontroller and the integrated CAN transceiver. The V1 regulator is embedded in the power management and fail-safe functionality of the device and operates according to the selected operating mode. The V1 voltage regulator is supplied by pin V SREG .

In addition, the V1 regulator supplies the devices internal loads. The voltage regulator is protected against overload and overtemperature. An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors >220 nF.

In case the device temperature exceeds the TSD1 threshold (either cluster or grouped mode) the V1 regulator remains on. The microcontroller has the possibility for interaction or error logging. If the chip temperature exceeds the TSD2 threshold (TSD2 > TSD1), V1 will be deactivated and all wake-up sources (CAN, LIN, WU and Timer) are disabled. After t

TSD

, the voltage regulator will restart automatically. If the restart fails 7 times within one minute the devices enter the Forced VBAT_Standby mode. The status bit

FORCED_SLEEP_TSD2/V1SC (SR1) is set.

Voltage regulator: V2

The voltage regulator V2 can be configured by means of the V2_CONFIG bit in the Config

Reg as a classical LDO (V2_CONFIG=0, default) or as a tracker of the V1 voltage regulator; when V2 is configured as Voltage Tracker of V1, it provides a 5V output that tracks the V1 regulator output voltage with +-20 mV accuracy with load currents up to 50 mA.

When V2 voltage regulator is configured in Tracking mode, the V1 Reset Threshold shall be configured to be the VRT1 (V1_RESET_1 = 1, V1_RESET_0 = 1 in CR2).

68/198 DS13220 Rev 5

L99DZ200G

4.2.3

4.2.4

Application information

In both cases the V2 regulator is protected against:

 Overload

 Overtemperature

 Short-circuit (short to ground and battery supply voltage)

 Reverse biasing

Voltage Regulator Failure

The V1, and V2 regulator output voltages are monitored.

In case of a drop below the failure thresholds (V1 < V1 fail for t > t V1fail , V2 < V2 fail (a) for t > t V2fail ), the failure bits V1FAIL, V2FAIL (SR 2) are latched.

Short to ground detection

At turn-on of the V1 and V2 regulators, a short-to-GND condition is detected by monitoring the regulator output voltage.

If V1 or V2 is below the V1 fail (or V2 fail

(a) ) threshold for t > t

V1short (t > t V2short (b) ) after turn-on, the devices will identify a short circuit condition and the related regulator will be switched off.

In case of V1 short-to-GND the device enters Forced VBAT_Standby mode automatically. Bits

FORCED_SLEEP_TSD2/V1SC (SR 1) and V1FAIL (SR 2) are set.

In case of a V2 short-to-GND failure the V2SC (SR 2) and V2FAIL (SR 2) bits are set.

Once the output voltage of the corresponding regulator exceeded the V1 fail (V2

fail(a)

) threshold the short-to-ground detection is disabled. In case of a short-to-ground condition, the regulator is switched off due to thermal shutdown. V1 is switched off at TSD2, V2 is switched off at TSD1 a. V2 fail_trk

in case of tracker.

b. t > t

V2short_trk

.

DS13220 Rev 5 69/198

197

Application information

4.2.5 Voltage regulator behavior

L99DZ200G

Figure 18. Voltage regulator behavior and diagnosis during supply voltage

Vsreg [ V ]

4.3

VSregUV

VPOR

VsregABS min

V1 [ V ]

V1

VRTH

V1fail

RSTB bit is set and registers are set to default at VPOR_R

100 μs t < t

UV1 t > t

UV1 t > t

V1fail

VsregUV bit is set

(filter time tOVUV_filt)

Control

Registers set to default at VPOR_F t > t

UV1

No Reset generated V1fail bit is set

Nreset output

High

Low

If t > tv1short

V1 short detected

Vbatt standby tv1r trr tv1r trr tV1FS specific Control Registers are set to default values

High Z Grounded VsregABSmin:

VSregUV:

VPOR_R/F:

VRTH:

V1FAIL: minimum Vsreg to control NReset

Vsreg under-voltage

Vsreg power-on reset voltage

(rising/falling)

V1 reset threshold voltage

V1 fail threshold voltage tUV1: tV1fail: trr: tv1r: tV1short: tV1FS: tOVUV_filt:

V1 under-voltage filter time

V1 fail filter time reset pulse reaction time reset pulse duration

V1 short filter time

V1 fail safe filter time

Vsreg over-/undervoltage filter time

GAPG0408151424CF

Operating Modes

The devices can be operated in the following operating modes:

 Active

 LIN Flash

 CAN Flash

 V1_Standby

 VBAT_Standby

 SW-Debug

70/198 DS13220 Rev 5

L99DZ200G

4.3.1

4.3.2

Application information

Active Mode

All functions are available and the device is controlled by SPI.

Flash Modes

To program the system microcontroller via LIN or HS CAN bus signals, the devices can be operated in LIN Flash mode or CAN Flash mode. The watchdog is disabled in these modes.

The Flash modes are entered by applying an external voltage at the respective pin:

 V TxDL ≥ V FlashH (CAN Flash mode)

 V TxDC ≥ V FlashH (LIN Flash mode)

In CAN Flash mode the CAN transceiver is set in TRX READY mode (CAN_GO_TRX_RDY

= 1) and TRX Normal mode automatically. During CAN Flash mode, the watchdog can be deactivated by setting CR22: WD_EN = 0. Write access to this bit is only possible during

CAN Flash mode in order to prevent accidental deactivation of the watchdog. After setting

WD_EN (CR 22) the CAN Flash mode can be left (V TxDL < V FlashL ) and the Watchdog will remain deactivated (see

Figure 19

).

Figure 19. Sequence to disable/enable the watchdog in CAN Flash mode

Note:

4.3.3

In LIN Flash mode the maximum bitrate is increased to 100 kbit/s automatically (LIN_HS_EN

= 1).

A transition from Flash modes to V1_Standby or VBAT_Standby mode is not possible.

At exit from Flash modes (V TxDL < V FlashL , V TxDC < V FlashL ) no NReset pulse is generated.

The watchdog starts with a Long Open Window (t LW ).

Setting both TxD_L and TxD_C to high voltage levels (> V FlashH ) is not allowed.

Communication at the respective TxD pin is not possible.

SW-Debug Mode

The SW-Debug mode is conceived to be used during the microcontroller debugging; in this mode, all the L99DZ200G functionalities and operating modes are available and the watchdog is deactivated easing the debug of the microcontroller firmware.

The DEBUG_ACTIVE bit (SR1) indicates if the L99DZ200G is in SW-Debug mode; it is recommended that the system microcontroller reads this bit after every cold start and wake-

DS13220 Rev 5 71/198

197

Application information L99DZ200G up events in order to ensure which is the device mode (DEBUG_ACTIVE = 1 for SW-Debug mode, DEBUG_ACTIVE = 0 for Normal mode).

Enter procedure

To enter in SW-Debug mode, the watchdog can be deactivated by applying at the power rising a high-level voltage (5V) on the PWMH1B input pin; this procedure shall be done before the rising edge of the NRESET pin, in order to avoid any possible constraint for the application development. The high voltage on PWMH1B pin can be achieved by tying together both the V1 and the PWMH1B signals; after a time interval t

V1R

(typ. 2 ms), once the PWMH1B signal is put low, the NRESET output rises at its highest value and the

L99DZ200G is from now on in SW-Debug mode (see Figure 20: Sequence to enter in SW-

Debug mode ).

Exit procedure

When in SW-Debug mode, the microcontroller has the possibility to let the L99DZ200G exit from this mode by setting the DEBUG_EXIT bit in CR22.

When the L99DZ200G is in SW-Debug mode, if the DEBUG_EXIT bit is set to 1, it exits from

SW-Debug mode and the watchdog starts a Long Open Window; in this case the

DEBUG_EXIT bit remains fixed to 1 (even if the device is already in Normal mode) and the system microcontroller can clear it.

When the L99DZ200G is in Normal mode, setting DEBUG_EXIT bit does not produce any effect on the device.

72/198 DS13220 Rev 5

L99DZ200G Application information

Figure 20. Sequence to enter in SW-Debug mode

V

SREG

[V]

STEP1: push the jumper & start

PWMH1B

VPOR

V1 [V]

V1

V

RTH

V1fail ȝV

9Bȝ& 5V_1

MCU L99DZ200G

To start up in SW-Debug mode, it is strongly recommended that 5V_1 and PWMH1B pins are tied together by means of a jumper, avoiding configurations in which the 5V for the PWMH1B pin are externally provided.

NRESET output

High (5V) t

V1R

STEP2: pull the jumper

PWMH1B

SW-Debug mode

Low (0V)

PWMH1B input

High (5V)

9Bȝ& 5V_1

GAPG0408151424CFT

MCU L99DZ200G

NRESET goes high when PWMH1B is put Iow; from now on PWMH1B can assume whatever value and

L99DZ200G remains in SW-Debug mode until a POR or the DEBUG_Exit bit in CR22 is set 1.

Low (0V)

4.3.4 t

V1R

= minimum time interval (typ. 2 ms) in which the PWMH1B shall at least be > V

IH

V1_Standby mode

The transition from Active mode to V1_Standby mode is controlled by SPI.

To supply the microcontroller in a low power mode, the V1 voltage regulator remains active.

After the V1_Standby command (CSN low to high transition), the device enters V1_Standby mode immediately and the watchdog starts a Long Open Window (t LW ). The watchdog is deactivated as soon as the V1 load current drops below the I CMP threshold (I V1 < I cmp_fal ).

The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration the watchdog will be deactivated upon transition into V1_Standby mode without monitoring the V1 load current.

Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting

ICMP_CONFIG_EN (Config Reg) = 1.

The ICMP_CONFIG_EN bit is reset to 0 automatically with the next SPI command.

Power outputs (except OUT15 (c) ) are switched off in V1_Standby mode. OUT15 remains in the configuration programmed prior to the standby command in order to enable cyclic supply c.

This exception applies only if OUT15 is not driven with an internally generated PWM signal

DS13220 Rev 5 73/198

197

Application information

4.3.5

L99DZ200G of external contacts. The timer signal (Timer1 or Timer2) can be mirrored to the NINT output pin during V1_Standby mode.

CAN and LIN transmitters (TxD_L, TxD_C) are off.

Wake-up capability by CAN and LIN can be disabled by SPI. The CAN transceiver can be configured in Listen mode (TxD_C disabled, RxD_C enabled) in order to support pretended networking concepts (for details see

Section 4.10.6: Pretended Networking ).

Interrupt

Figure 21. NINT pins

V1 ESD prot

Data In

Enable

Digital logic

Data Out

74/198

GND GND

GAPG2608151615CFT

RxD_L/NINT indicates:

 a wake-up event from V1_Standby mode (except wake-up by CAN) 

RxD_L/NINT pin is pulled low for t = t interrupt .

RxD_C/NINT indicates:



Mode transitions of the CAN transceiver according to Figure 30: CAN transceiver state diagram

 CAN communication timeout (no CAN communication for t > t Silence ). The CANTO flag is set. This interrupt can be masked by SPI (CR1: CANTO_IRQ_EN).



RxD_C/NINT pin is pulled low for t = t interrupt . See also

Section 4.3.6: CAN wake-up signalization

NINT indicates:

 In Active mode: 

V

SREG

dropped below the programmed early warning threshold in Control Register 3

(V SREG < VSREG_EW_TH); feature is deactivated if VSREG_EW_TH is set to 0 V.

In V1_Standby mode

– Programmable timer interrupt; an NINT pulse is generated at the beginning of the timer on-time (Timer 1 or Timer2)

– CAN communication timeout (no CAN communication for t > t

Silence

). The CANTO flag is set. This interrupt can be masked by SPI (CR1: CANTO_IRQ_EN).

– Wake-up from V1_Standby mode by any wake-up source

DS13220 Rev 5

L99DZ200G Application information

NINT is pulled low for t = t interrupt

In case of increasing V1 load current during V1_Standby mode (I V1 > I cmp_ris ), the device remains in standby mode and the watchdog starts with a Long Open Window. No Interrupt signal is generated.

4.3.6 CAN wake-up signalization

Table 61. CAN wake-up signalization

Operating mode Event Mode transition Status flag Interrupt pin

WUP

(1)

Transition to TRX_Ready WUP

(1)

Active CAN Timeout

WUP

(3)

Transition to TRX_Sleep

Transition into TRX_Bias

CANTO

WUP

V1_Standby

WUP

WUP

WUP

(1)

CAN Timeout

(3)

(1)

Transition into Active mode; TRX_Ready

Transition to TRX_Sleep

Transition into TRX_Bias

Transition into Active mode; TRX_Ready

WAKE_CAN WUP

CANTO

WUP

WAKE_CAN WUP

VBAT_Standby

CAN Timeout Transition to TRX_Sleep CANTO

1. PNW_EN = 0: 

- wake-up according ISO 11898-5:2007 (on WUP) 

- Flags: WUP (device in all modes), WAKE_CAN (device wake up by CAN from Standby modes)

2. Interrupt can be disabled by SPI (CANTO_IRQ_EN).

3. PWN_EN = 1 (Pretended Networking mode) 

- no wake-up 

- after reception of a wake-up patter (WUP) the transceiver enters TRX Bias mode 

- Flags: WUP

(1)

(1)

RxD_C

RxD_C

RxD_C

RxD_C none

(2) and and

NINT

NINT

RxD_C and

NINT

(2)

RxD_C and NINT

Note:

4.3.7

See also Figure 30: CAN transceiver state diagram

.

VBAT_Standby mode

The transition from Active mode to VBAT_Standby mode is initiated by an SPI command. In

VBAT_Standby mode, the voltage regulators V1 and V2 (depending on configuration in CR 1), the power outputs (except OUT15

(d)

) as well as LIN and CAN transmitters are switched off.

An NReset pulse is generated upon wake-up from VBAT_Standby mode.

4.4 Wake up from Standby Modes

A wake-up from standby mode will switch the device to active mode. This can be initiated by one or more of the following events: d. This exception applies only if OUT15 is not driven with an internally generated PWM signal

DS13220 Rev 5 75/198

197

Application information

4.4.1

L99DZ200G

Wake up source

LIN bus activity

Table 62. Wake-up events description

Can be disabled by SPI

Description

CAN bus activity Can be disabled by SPI

Level change of WU

I

V1

>I cmp_ris

Can be configured or disabled by SPI

Device remains in V1_Standby mode, but watchdog is enabled (If I

CMP

=

0). No interrupt is generated.

Timer Interrupt / Wake up of µC by TIMER

Programmable by SPI:

V1_Standby mode: configurable timer interrupt. NINT interrupt signal is generated

VBAT_Standby mode: device wakes up after programmable timer expiration, V1 regulator is turned on and NReset signal is generated

SPI Access

Always active (except in VBAT_Standby mode

)

Wake up event: CSN is low and first rising edge on CLK

V

S

Over Voltage

Only when Generator Mode is enabled (GENERATOR_MODE_EN=1 in

CR22 0x16)

To prevent the system from a deadlock condition (no wake up from standby possible) a configuration where the wake up by LIN and HS CAN are both disabled is not allowed; in this case the SPI Error Bit SPIE (Global Status Byte)

is set (see Note 1 in Figure 62 ).

Wake up inputs

The WU input can be configured as wake-up source. The wake-up input is sensitive to any level transition (positive and negative edge) and can be configured for static or cyclic monitoring of the input voltage level.

For static contact monitoring, a filter time of t

WU_stat is implemented. The filter is started when the input voltage passes the specified threshold V WU_THP or V WU_THN .

Cyclic contact monitoring allows periodical activation of the wake-up input to read the status of the external contact. The periodical activation can be configured to Timer 1 or Timer 2. The input signal is filtered with a filter time of t

WU_CYC after a delay (80% of the configured Timer on-time). A Wake-up will be processed if the status has changed versus the previous cycle.

The buffered output OUT15 can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up input.

In standby modes, the input WU is configurable with an internal pull-up or pull-down current source according to the setup of the external contact. In Active mode the inputs have an internal pull down resistor (R WU_act ) and the input status can be read by SPI. Static sense should be configured before the read operation is started in order to reflect the actual input level.

76/198 DS13220 Rev 5

L99DZ200G Application information

4.5 Functional Overview (truth table)

Table 63. Status of different functions/features vs operating modes

Operating modes

Function Comments

Active mode

V1_Standby static mode (cyclic sense)

VBAT_Standby static mode (cyclic sense)

Voltage regulator V1

Voltage tracker V2

Reset generator

V

V

OUT

OUT

= 5 V

= 5 V

On

On/ Off

(2)

On

On

(1)

On (2)

/ Off

On

Off

On (2)

/ Off

Off

Window watchdog V

1 monitor On

Off (on if I

V1

> I

CMP and I

CMP

= 0)

Active

(3)

Off

Wake up Off Active

(3)

OUT15 HS cyclic supply

LIN

HS_CAN

Oscillator OSC1

Oscillator OSC2

V

SREG-Monitor

V

S-Monitor

H Bridge Gate Driver, EC control, bridge drivers, heater driver, all high-side drivers (except OUT15) supplied by V

S

Fail-safe low-side switches

Oscillator time base

LIN 2.2a

2 MHz

32 MHz

On / Off

On

On / Off

On

ON

On

On

On/ Off

(5)

(2)

On/ Off

(9)

On (2)

Off

(7)

Off

Off

On

/ Off

Off

(4)

Off

(4)

On/Off

(8)

(6)

On (2)

/ Off

Off

(4)

Off

(4)

On/Off

Off

(7)

Off

Off

On

(6)

Short circuit protection for fail-safe low-side switches (in case LS is switched on)

On On On

OUT15 (P-channel HS) supplied by V

SREG

Charge pump

ADC (SPI read out and V

SREG early warning interrupt)

On/ Off

On

On

(2)

On/ Off

Off

Off

(2)(9)

On/ Off

Off

Off

(2)(9)

Thermal shutdown TSD2

Thermal shutdown TSD1x for

OUT15 (P-channel HS)

On

On

On

On/ Off

(2)

Off

On/ Off

(2)

1. Supply the processor in low current mode.

2. According to SPI setting and DIR.

3. Unless disabled by SPI.

4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding of internal filter time (if wake-up by LIN or CAN is not disabled by SPI).

DS13220 Rev 5 77/198

197

Application information L99DZ200G

5. After power-on, the HS CAN transceiver is in CAN_TRX_SLEEP mode. It is activated by SPI command

(CAN_GO_TRX_RDY= 1).

6. ON, if cyclic sense is enabled or during wake-up request.

7. Cyclic activation = pulsed ON during cyclic sense.

8. In V1_Standby and VBAT_Standby modes OUT15 is ON only if it is not driven with an internally generated PWM signal.

9. ON in Fail-Safe mode; if standby mode is entered with active Fail-safe mode the output remains ON in standby mode.

Figure 22. Main operating modes

Flash Mode (LIN/CAN)

Functionality as in Active Mode

Watchdog: OFF

CAN Flash Mode:

CAN TRX RDY=1, RXEN=1, TXEN=1

LIN Flash Mode:

LIN_HS_en=1

V

TXDL

> V flash

OR

V

TXDC

> V flash

V

TXDL

> V flash

OR

V

TXDC

> V flash

V

TXDL

> V flash

OR

V

TXDC

> V flash

V

TXDL

< V flash

AND

V

TXDC

< V flash

SPI command

OR

7x Thermal Shutdown 2

OR

V1 short to GND

(V1 < 2V for 4ms after switch ON)

OR

15 x WD Failure

Active

Mode

V1: ON

Reset Generator: active

Watchdog: active

Vs > Vpor

Vbat startup

All registers

Set to default,

Chip Reset bit (RSTB)

= 1

Wake-up

Event

SPI command

Wake-up

Event

4.6

Vbat Standby

Mode

V1: OFF

Reset Generator: OFF(Nreset=low)

Watchdog: OFF

V1 Standby

Mode

V1: ON

Reset Generator: active

Watchdog:

OFF (if Iv1<I cmp

or ICMP = 1)

7x Thermal Shutdown TSD2

OR

15 x WD fail

GAPG0408151614CFT

Configurable Window Watchdog

During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle.

After power-on or standby mode, the watchdog is started with a timeout (Long Open Window t LW ). The timeout allows the microcontroller to run its own setup and then to start the window watchdog by setting TRIG (CR1, Config Reg (e) ) =1. Subsequently, the microcontroller has to

78/198 e. TRIG bits in CR1 and Config Reg are mirrored; either can be used for triggering the watchdog.

DS13220 Rev 5

L99DZ200G Application information

serve the watchdog by alternating the watchdog trigger bit TRIG (CR1, Config Reg (e) ) within

the safe trigger area T SWX .

The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately start the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off for t V1OFF . After 7 additional watchdog failures the V1 regulator is turned off permanently and the device goes into Forced VBAT_Standby mode. The status bit FORCED_SLEEP_WD (SR

1) is set. A wake-up is possible by any activated wake-up source.

After wake-up from Forced VBAT_Standby mode and the watchdog trigger still fails, the device enters Forced VBAT_Standby mode again after one Long Open Window.

This actually produces an additional watchdog failure but the watchdog fail counter will remain at maximum value of 15 failures.

This sequence is repeated until a valid watchdog trigger event is performed by writing TRIG

= 1. In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit WDFAIL (SR1) is set to 1. A reset pulse is generated at NReset output and the device enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe low-side switches are turned on. Please refer to

Section 4.7: Fail Safe Mode

for more details.

The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are split into 3 parts. The first diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior

. Figure 25: Watchdog in Flash mode

shows the transition in and

out of Flash modes. Watchdog in normal operating mode (no errors) Figure 23: Watchdog in normal operating mode (no errors)

,

Figure 24: Watchdog with error conditions and

Figure 25:

Watchdog in Flash mode can be overlapped to get all the possible state transitions under all

circumstances. For a better readability, they were split in normal operating, operating with errors and Flash mode.

DS13220 Rev 5 79/198

197

Application information

Figure 23. Watchdog in normal operating mode (no errors)

L99DZ200G

Active mode

TRIG = ‚1'

Wake-up

( V1 > V

RTx

) long open window

Go Vbat stby

Or

Go V1 stby AND I(v1) < Icmp

WD

OFF

Go V1 stby propper trigger in

Window mode

Window

Mode

Active mode go Vbat stby

Vbat standby mode

V1 Standby (I(V1) < ICMP)

GAPG0408151639CFT

Figure 24. Watchdog with error conditions

Fail-Safe

Event long open window

Active mode

V1 > Vrth forced Vbat stby

*)

V1 < Vrth

TRIG = ‚1' Fail-Safe

Event

WD

OFF

Vbat standby mode

Lorem ipsum

V1 < Vrth propper trigger in

Window mode

Window

Mode

Active mode

*) forced VBAT: 15x WD fail

7x TSD2

Short V1

GAPG0408151640CFT

80/198 DS13220 Rev 5

L99DZ200G

Active mode

Application information

Figure 25. Watchdog in Flash mode long open window

Exit from

FLASH / Debug mode

Enter

FLASH / Debug mode

WD

OFF

FLASH / Debug mode

Note:

4.6.1

4.7

4.7.1

Active mode

Window

Mode

Enter

FLASH / Debug mode

GAPG0408151643CFT

Whenever the device is operated without servicing the mandatory watchdog trigger events, a sequence of 15 consecutive reset events is performed and the device enters the Forced

VBAT_Standby mode with bit FORCED_SLEEP_WD in SR1 set. If the device is woken up after such a forced VBAT_Standby condition and the watchdog is still not serviced, the device, after one long open watchdog window will re-enter the same Forced VBAT_Standby mode until the next wake up event. In this case, an additional watchdog failure is generated, but the fail counter is not cleared, keeping the maximum number of 15 failures. This sequence is repeated until a valid watchdog trigger event is performed by writing TRIG = 1.

Change Watchdog timing

The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config

Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command.

Fail Safe Mode

Temporary Failures

The devices enter Fail-safe mode in case of:

 Watchdog failure

 V1 failure (V1 < V RTxfalling for t > t V1FS )

 Thermal Shutdown TSD2

The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode the Fail Safe mode is entered in the following cases:

 V1 failure (V1 < V RTxfalling for t > t V1FS )

 Watchdog failure (if watchdog still running due to I V1 > I cmp_fal )

 Thermal Shutdown TSD2

DS13220 Rev 5 81/198

197

Application information L99DZ200G

In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated to the system in the Global Status Byte. The conditions during Fail Safe mode are:

 All outputs beside LSA_FSO and LSB_FSO are turned off

 All Control Registers are set to fail safe default values except the GEN_MODE_EN

 Write operations to Control Registers are blocked until the Fail Safe condition is cleared. The following bits are not WRITE protected:

– TRIG (CR1<bit 0>, Config Register <bit 0>): watchdog trigger bit

– V2_x (CR1<bit 4:5>): Voltage Regulator V2 control

– CAN_GO_TRX_RDY (CR1<bit 8>): activation of CAN bus biasing

– CR2 (bit <8:23>): Timer1 and Timer2 settings

– OUT15_x (CR6<bit 8:11>): OUT15 configuration

– PWMx_freq_y (CR12): PWM frequency configuration

– PWMx_DC_y (CR13 – CR16): PWM duty cycle configuration

 LIN and SPI remain on (transmitters are deactivated in case of thermal shutdown TSD1

(TSD1 cluster 5 or 6 in cluster mode)

 Corresponding Failure Bits in Status Registers are set

 FS Bit (Global Status Byte) is set

 LSA_FSO and LSB_FSO will be turned on

 Charge pump is switched off

If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the actions to exit Fail safe mode are shown in the following table.

Failure source

Table 64. Temporary failures description

Failure condition Diagnosis Exit from Fail-safe mode

Microcontroller

(oscillator)

V1

Temperature

Watchdog early write failure or expired window

Undervoltage

T j

> T

SD2

FS (Global Status Byte) =1; WDFAIL

(SR 1) =1; WDFAIL_CNT_x (SR 1)

= n+1

TRIG (CR 1) = 1 during long open window Read&Clear

SR1

FS (Global Status Byte) = 1; V1UV

(SR 1) = 1; V1fail (SR 2) = 1

(1)

FS (Global Status Byte) = 1; TW

(SR 2) = 1;

TSD1 (SR 1) =1;

TSD2 (SR 1) =1

V1 >V

RTrising

; Read&Clear

SR1

T j

< T

SD2

;

Read&Clear

SR1

1. If V1 < V1 fail

(for t > t

V1fail

). The Fail-safe Bit is located in the Global Status Register.

4.7.2 Non-recoverable failures – forced VBAT_Standby mode

If the Fail-safe condition persists and all attempts to return to normal system operation fail, the devices enter the forced VBAT_Standby mode in order to prevent damage to the system.

The forced VBAT_Standby mode can be terminated by any wake-up source (HS-CAN as well as LIN and WU pin). The root cause of the forced VBAT_Standby mode is indicated in the

SPI Status Registers. In forced VBAT_standby mode and with Fail Safe conditions still present at wake-up, the Fails safe low side outputs LSy_FSO (y = A, B) are switched OFF for 25 µs after the wake up event.

82/198 DS13220 Rev 5

L99DZ200G Application information

In Forced VBAT_Standby mode, all Control Registers are set to power-on default values.

The Forced VBAT_Standby mode is entered in case of:

 Multiple watchdog failures: FORCED_SLEEP_WD (SR 1) = 1 (15 x watchdog failure)

 Multiple thermal shutdown 2: FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 (7 x TSD2)

 V1 short at turn-on (V1 < V1 fail for t > t V1short ): 

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

 SGND Loss: SGND_LOSS (SR 1) = 1

V1

Temperature

SGND Loss

Failure source Failure condition

Microcontroller

(Oscillator)

15 consecutive

Watchdog Failures

Table 65. Non-recoverable failure

Diagnosis

FS (Global Status Byte) = 1;

WDFAIL (SR 1) = 1;

FORCED_SLEEP_WD (SR 1) = 1

Short at turn-on

7 times TSD2

Ground Loss at pin

SGND

FS (Global Status Byte) = 1;

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

FS (Global Status Byte) =1;

TW (SR 2) = 1;

TSD1 (SR 1) = 1;

TSD2 (SR 1) = 1;

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

FS (Global Status Byte) = 1;

SGND_LOSS (SR 1) = 1

Exit from Fail-safe mode

Wake-up;

TRIG (CR 1) = 1 during long open window;

Read&Clear SR1

Wake-up; Read&Clear SR1

Wake-up; Read&Clear SR1

Wake-up; Read&Clear

SR1

In Forced VBAT_Standby mode:

 when Vs OV is detected, in case of non recoverable conditions ( WD, TSD2, V1 short or SGND loss ), the device will stay in Temporary Fail Safe state;

 during this state ( VSOV + failure conditions ), diagnosis will be set ( FS, WDFAIL or

TW, TSD1, TSD2 or FORCED_SLEEP_TSD2/VS1SC or SGND_LOSS ) even if the device is not in Forced VBAT_Standby mode;

 as soon Vs OV disappears, the device will enter in Forced VBAT_Standby mode.

DS13220 Rev 5 83/198

197

Application information

4.8 Reset output (NReset)

Figure 26. NReset pin

V1 ESD prot

L99DZ200G

20 kOhms

Data Out

Data In Digital logic

GND GND

GAPG2608151608CFT

If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is pulled up to V1 by an internal pull-up resistor after a reset delay time (t V1R ). This is necessary for a defined start of the microcontroller when the application is switched on.

Since the NReset output is realized as an open drain output it is also possible to connect that, instead of the 5V_1, to an external voltage source (it has to be compatible with a 5V rail). As soon as the NReset is released by the devices the watchdog starts with a long open window.

A reset pulse is generated in case of:

 V1 drops below V RTxfalling (configurable by SPI) for t > t UV1

 Watchdog failure

After turn ON of the V1 regulator (VSREG Power-on or wake-up from VBAT_Standby mode), NReset is kept low for tv1r in order to keep the uC in reset until supply voltage is stable.

84/198 DS13220 Rev 5

L99DZ200G

4.9 LIN Bus Interface

Figure 27. RxD_L pin

V1 ESD prot

Application information

Data In

Enable

Digital logic

Data Out

4.9.1

GND GND

GAPG2608151615CFT

Features

 LIN 2.2a compliant (SAEJ2602 compatible) transceiver

 LIN Cell has been designed according to “Hardware requirements for transceivers

(version 1.3)”

 Bit rate up to 20 kbit/s

 Designed according to SAE J2962-1 (July 2019)

 Dedicated LIN Flash mode with bit rate up to 100 kbit/s

 GND disconnection fail safe at module level

 Off mode: does not disturb network

 GND shift operation at system level

 Microcontroller Interface with CMOS-compatible I/O pins

 Internal pull-up resistor

 Receive-only mode

 ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

 Matched output slopes and propagation delay

 Wake-up behavior according to LIN2.2a and Hardware Requirements for LIN, CAN and

Flexray Interfaces (version 1.3)

At V SREG > V POR (i.e. V SREG power-on reset threshold), the LIN transceiver is enabled. The

LIN transmitter is disabled in case of the following errors:

 Dominant TxD_L time out

 LIN permanent recessive

 Thermal shutdown 1

 V SREG overvoltage/ undervoltage

The LIN receiver is not disabled in case of any failure condition.

DS13220 Rev 5 85/198

197

Application information

4.9.2

4.9.3

L99DZ200G

The default bit rate of the transceiver allows communication up to 20 kbit/s. To enable fast flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit

LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode.

Error Handling

The devices LIN transceiver provides the following 3 error handling features.

Dominant TxD_L time out

If TXD_L is in dominant state (low) for t > t dom(TXDL) the transmitter will be disabled, the status bit LIN_TXD_DOM (SR 2) will be set.

The transmitter remains disabled until the status bit is cleared.

The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0).

Permanent recessive

If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < t LIN the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set.

The transmitter remains disabled until the status bit is cleared.

Permanent dominant

If the bus state is dominant (low) for t > t dom(bus) a bus permanent dominant failure will be detected. The status bit LIN_PERM_DOM (SR 2) will be set.

The transmitter will not be disabled.

Wake up from Standby Modes

In low power modes (V1_Standby mode and VBAT_Standby mode) the devices can receive two types of wake up signals from the LIN bus (configurable by SPI bit LIN_WU_CONFIG

(Config Reg)):

 Recessive-Dominant-recessive pattern with t > t dom_LIN (default, according to LIN 2.2a)

 State Change recessive-to-dominant or dominant-to-recessive (according to LIN 2.1)

86/198 DS13220 Rev 5

L99DZ200G Application information

Pattern Wake-up (default)

Figure 28. Wake-up behavior according to LIN 2.2a

Voltage at LIN-Pin of LIN Physical Layer device

LIN recessive t dom LIN

0.4 V

Supply

LIN dominant sleep mode

0.6 V

Supply standby mode

GAPG0508151156CFT

4.9.4

Status change wake-up - Recessive-to-dominant

Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high) state. A dominant level at LIN for t > t LINBUS , will switch the devices in

Active mode.

Status change wake-up - Dominant-to-recessive

If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for t > t LINBUS , will switch the devices in Active mode.

Receive-only mode

The LIN transmitter can be disabled in Active mode by setting the bit LIN_REC_ONLY

(CR2). In this mode it is possible to listen to the bus but not sending to it.

DS13220 Rev 5 87/198

197

Application information

4.10 High-speed CAN bus transceiver

Figure 29. RxD_C pin

V1 ESD prot

Data In

Enable

Digital logic

Data Out

L99DZ200G

GND GND

GAPG2608151615CFT

4.10.1 Features

 ISO 11898-2:2003 and ISO 11898-5:2007 compliant

 CAN High Speed Transceiver Conformance Test according to «Interoperability test specification for high-speed CAN transceiver or equivalent devices IOPT.CAN v02d00»

 HS-CAN cell has been designed according to “Hardware requirements for transceivers

(version 1.3)”

 Supports pretended networking

 Listen mode (transmitter disabled)

 Enhanced Voltage Biasing according to ISO 11898-6:2013

 SAE J2284 compliant

 Bit rate up to 1Mbit/s

 Designed according to SAE J2962-2 (July 2019)

 Function range from -27 V to +40 V DC at CAN pins.

 GND disconnection fail safe at module level.

 GND shift operation at system level.

 Microcontroller Interface with CMOS compatible I/O pins.

 ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

 Matched output slopes and propagation delay

88/198 DS13220 Rev 5

L99DZ200G Application information

4.10.2 CAN Transceiver operating modes

Figure 30. CAN transceiver state diagram

SBC

Active

Power-Up Reset

TRX Sleep

1 )

PNW EN=1 wake-up pattern CAN

(WUP)

Flag: WUP

Interrupt: RxDC, NINT

Communication

Time out

Flag: CANTO

Interrupt: RxDC

2)

PNW EN=1

GO2TRXRDY = 1

SPI cmd:

Enable Vbat Stby Mode

TRX BIAS

SPI cmd:

Enable V1 Stby Mode /

Wake by SPI if GO2TRXRDY=0

PNW_EN=0: 1)

Wake-up pattern (WUP)

Flags: WUP, WAKE CAN

Interrupt: RxDC, NINT

Or

Wake by SPI if GO2TRXRDY=1

GO2TRXRDY = 0

TRX Ready

PNW_EN=0:

1)

Wake-up pattern (WUP)

Flags: WUP

Interrupt: RxDC

Or

GO2TRXRDY = 1

SPI cmd:

Enable VBAT stby mode

SPI cmd:

Enable VBAT stby mode

TRX Sleep

PNW EN=1

1)

Wake-up pattern

(WUP)

Flag: WUP

Interrupt: RxDC, NINT

TRX BIAS

CAN Communication

Time out

Flag: CANTO

Interrupt: RxDC, NINT 2)

SPI cmd:

Enable V1 Stby Mode

Wake-up pattern

(WUP)

Flags: WUP, WAKE CAN

(Interrupt: None)

TRX BIAS

CAN

Communication

Time out

Flag: CANTO

TRX Sleep

SBC

V1 Standby

Note 1): In Pretended Networking configuration (PNW_EN=1) a WUP leads to:

•Transceiver transition into TRX BIAS mode, no SBC mode transition

•Interrupt at RxDC and NINT

Note 2): CANTO Interrupt on RxDC and NINT can be masked by SPI (CR1 <CANTO IRQ EN>)

SBC

Vbat Standby

GAPG0508151158CFT

TRX Ready State

In this state the bus-biasing is on.

The transmitter and receiver can be configured by SPI (RXEN, TXEN) as follows:

 TRX Standby (default): transmitter and receiver disabled

 TRX Listen: transmitter disabled, receiver enabled

 TRX Normal: transmitter enabled, receiver enabled

DS13220 Rev 5 89/198

197

Application information L99DZ200G

TRX BIAS State

In this transceiver state the bus biasing is on and the Automatic Voltage Biasing is active (i.e. transceiver enters TRX_Sleep at t > t Silence and turns off the biasing).

The CAN transmitter is disabled. The receiver can be configured by SPI (RXEN) as follows:

 TRX Standby (default): receiver disabled

 TRX Listen: receiver enabled

The CAN receiver is capable of detecting a wake-up pattern (WUP). In V1_Standby mode and

Active mode, a wake-up is indicated to the micro-controller by an interrupt signal and the transceiver enters TRX_Ready State (receiver and transmitter according to setting of TXEN and RXEN). After serving the interrupt, the microcontroller can enable the receiver and transmitter by setting TXEN = 1 and RXEN = 1.

TRX SLEEP State

After Power-on the CAN transceiver enters TRX_Sleep state. In this state, the CAN transceiver is disabled and the biasing is turned off. Transmitter and receiver are disabled

(TRX_Standby state). After the detection of CAN communication (WUP), an interrupt signal is generated and the transceiver enters TRX_Ready state (if PNWEN = 0) or TRX_BIAS state (if

PNWEN = 1). Receiver and transmitter are configured according to setting of TXEN and

RXEN.

TRX_Sleep state is entered automatically after a CAN communication timeout (see

Section 4.10.3: Automatic Voltage Biasing

).

4.10.3 Automatic Voltage Biasing

The Automatic Voltage Biasing is described in ISO 11898-6:2013. This feature is active in all transceiver low-power modes independent of the SBC operating modes.

If there has been no activity on the bus for longer than t

Silence

, the bus lines are biased towards 0V via the receiver input resistors R in . If wake-up activity on the bus lines is detected (Wake-up pattern, WUP), the bus lines are biased to V CANHrec respectively

V CANLrec via the internal receiver input resistors R in . The biasing is activated not later than t

Bias

.

4.10.4 Wake up by CAN

The device supports only the wake-up by any bus activity according to ISO 11898-2:2003/-

5:2007.

The default setting for the wake up behavior after Power-on reset is the wake-up by regular communication on the CAN bus according to ISO 11898-5:2007. When the CAN transceiver is in a low power mode (TRX_BIAS or TRX_Sleep) the device can be woken up by sending 2 consecutive dominant bits separated by a recessive bit.

A wake-up can be detected if the CAN transceiver was set in standby mode while the CAN bus was in recessive (high) state or dominant (low) state (see

Figure 31

).

90/198 DS13220 Rev 5

L99DZ200G Application information

CANRX

STATE ACTIVE

Figure 31. CAN wake up capabilities t filter

< t wake t filter t filter

STANDBY

CAN pattern wakeup

< t wake t filter t filter t filter

ACTIVE

CANRX

STATE ACTIVE STANDBY ACTIVE

CAN pattern wake-up with dominant state before Standby

GAPG0508151203CFT

For details, see Figure 30

.

4.10.5 CAN looping

If CAN_LOOP_EN (CR 2) is set the TxD_C input is mapped directly to the RxD_C pin. This mode can be used in combination with the CAN Receive-only mode, to run diagnosis for the

CAN protocol handler of the microcontroller.

4.10.6 Pretended Networking

To support pretended networking concepts, the devices can be configured as follows:

 V1_Standby mode or Active mode (if watchdog is required)

 Pretended Networking enabled (PNW_EN (CR 2) = 1)

In this configuration, the microcontroller is supplied by V1 in low current mode. The CAN

Automatic Voltage Biasing is active. Upon incoming CAN messages, the biasing is turned on

(TRX_BIAS State) and an interrupt is generated. If the device is in V1_Standby mode it remains in this mode.

The incoming CAN frames are passed to the microcontroller via the RxD_C signal line for decoding.

4.10.7 CAN Error Handling

The devices provide the following four error handling features. After Power-on Reset (V S >

V POR ) the CAN transceiver is disabled. The transceiver is enabled by setting

CAN_GO_TRX_RDY (CR 1) = 1. The CAN transmitter will be disabled automatically in case of the following errors:

 Dominant TxD_C time out

 CAN permanent recessive

 RxD_C permanent recessive

 Thermal Shutdown 1

DS13220 Rev 5 91/198

197

Application information L99DZ200G

The CAN receiver is not disabled in case of any failure condition.

Dominant TxD_C time out

If TXD_C is in dominant state (low) for t > t dom (TxDC) the transmitter will be disabled,

CAN_TXD_DOM (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.

CAN Permanent Recessive

If TXD_C changes to dominant (low) state but CAN bus does not follow for 4 times, the transmitter will be disabled, CAN_PERM_REC (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.

CAN Permanent Dominant

If the bus state is dominant (low) for t > t CAN a permanent dominant status will be detected.

CAN_PERM_DOM (SR 2) will be latched and can be read and optionally cleared by SPI.

The transmitter will not be disabled.

RxD_C Permanent Recessive

If RxD_C pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RXD_C does not follow TXD_C for 4 times the transmitter will be disabled. CAN_RXD_REC (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.

4.11 Serial Peripheral Interface (ST SPI Standard)

A 32-bit SPI is used for bi-directional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output pins and one input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag

(fault condition) of the device.

 Chip Select Not (CSN) 

The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started.



The state during CSN = 0 is called a communication frame.



If CSN = low for t > t

CSNfail the DO output is switched to high impedance in order to not block the signal line for other SPI nodes.

 Serial Data In (DI) 

The input Pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register is transferred to Data Input Register. The writing to the selected Data Input Register is only

92/198 DS13220 Rev 5

L99DZ200G

Note:

Application information enabled if exactly 32 bits are transmitted within one communication frame (i.e. CSNlow).

If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

 Serial Data Out (DO) 

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN

Pin will transfer the content of the selected status register into the data out shift register.

Each subsequent falling edge of the CLK will shift the next bit out.

 Serial Clock (CLK) 

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 4 MHz.

4.12 Power Supply Fail

4.12.1 Vs supply failure

Vs overvoltage

If the supply voltages V S reaches the overvoltage threshold V SOV :

 LIN remains enabled

 CAN remains enabled

 OUT1 to OUT14 are turned off (default).

The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR 3) = 0)

 Charge pump is disabled (and is switched on automatically in case the supply voltage recovers to normal operating voltage)

 H-bridge gate driver and heater MOSFET gate driver are switched into sink condition

 ECV is switched in high impedance state and ECDR is discharged by R ECDRDIS (to ensure the gate of the external MOSFET is discharged => EC mode considered as off)

 Recovery of outputs after overvoltage condition is configurable by SPI:

– VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2).

– VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after V S overvoltage condition has recovered.

 The overvoltage bit VS_OV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered.

DS13220 Rev 5 93/198

197

Application information L99DZ200G

Vs undervoltage

If the supply voltage V S drops below the under voltage threshold voltage (V SUV ):

 LIN remains enabled

 CAN remains enabled

 OUT1 to OUT14 are turned off (default).



The shutdown of outputs may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0)

 H-bridge drivers A and B are turned off (default). The shutdown of H-bridge drivers may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0)

 Heater MOSFET gate driver is switched into sink condition

 ECV is switched in high impedance state and ECDR is discharged by R ECDRDIS (to ensure the gate of the external MOSFET is discharged => EC mode considered as off)

 Recovery of outputs and H-bridge drivers after undervoltage condition is configurable by

SPI:

– VS_LOCK_EN (CR 3) = 1: outputs and H-bridge drivers are off until Read&Clear

VS_UV (SR 2).

– VS_LOCK_EN (CR 3) = 0: outputs and H-bridge drivers turned on automatically after

V S undervoltage condition has recovered.

 The undervoltage bit VS_UV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The undervoltage bit is removed automatically if VS_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.

4.12.2 Vsreg supply failure

Vsreg Overvoltage

If the supply voltages V SREG reaches the overvoltage threshold V

SREG_OV

:

 LIN transmitter is switched to high impedance

 CAN remains enabled

 OUT15 is turned off (default).

The shutdown of outputs may be disabled by SPI (VSREG_OV_SD_EN (CR 3) = 0)

 Recovery of outputs after overvoltage condition is configurable by SPI:

– VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_OV

2).

(SR

– VSREG_LOCK_EN (CR 3) = 0: outputs turned on automatically after V SREG overvoltage condition has recovered.

 The overvoltage bit VSREG_OV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage bit is reset automatically if VSREG_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered.

Vsreg Undervoltage

If the supply voltage V SREG drops below the under voltage threshold voltage (V SREG_UV ):

 LIN transmitter is switched to high impedance

 CAN remains enabled

 OUT15 is turned off (default).

94/198 DS13220 Rev 5

L99DZ200G Application information

The shutdown of outputs may be disabled by SPI (VSREG_UV_SD_EN (CR 3) = 0)

 Recovery of outputs after undervoltage condition is configurable by SPI:

– VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_UV (SR

2).

– VSREG_LOCK_EN (CR 3) = 0: Outputs turned on automatically after V SREG undervoltage condition has recovered.

 The undervoltage bit VSREG_UV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The undervoltage bit is removed automatically if VSREG_LOCK_EN (CR 3)

= 0 and the undervoltage condition has recovered.

DS13220 Rev 5 95/198

197

Application information

4.13 Temperature warning and thermal shut-down

Figure 32. Thermal shutdown protection and diagnosis

L99DZ200G

7x TSD2

TSD2

All outputs and V2: off

V1: off for t = t

TSD

Diagnosis: TSD2=1

Wake-up event

Tj > TSD2 t > t

TSD

TSD1

All outputs and V2: off 1)

V1: on

Diagnosis: TSD1=1

Tj > TSD1

Forced

Vbat_standby

Mode

Power-on reset

‚Read and Clear’

OR

Power-on reset

Temperature

Warning

Diagnosis: TW=1

‚Read and Clear’

OR

Power-on reset

Tj > Tw

Active

Mode

Standby Modes

(during cyclic sense)

Note:

Vs > Vpor

Power On Reset

All outputs incl V1 off

Note 1): In thermal cluster mode (TSD Config = 1), only the concerned output cluster will be switched off

GAPG0408151633CFT

The Thermal State machine will recover the same state where it was before entering Standby mode. In case of a TSD2 it will enter TSD1 state.

96/198 DS13220 Rev 5

L99DZ200G Application information

4.14 Power Outputs OUT1…15

Note:

The component provides a total of 4 half bridges outputs OUT1, OUT2, OUT3 and OUT6 to drive motors and 7 stand alone high-side outputs OUT7, OUT8, OUT9, OUT10, OUT13,

OUT14 and OUT15 to drive e.g. LED’s, bulbs or to supply contacts. All high-side outputs beside OUT15 are supplied by the pin VS and OUT15 is supplied by the buffered supply

V SREG . Beside OUT15 the high-side switches can be activated only in case of running charge pump.

OUT15 can be activated also in standby modes, except if OUT15 is driven by an internally generated PWM.

All high-side and low-side outputs switch off in case of:

 V S (V SREG ) overvoltage and undervoltage (depending on configuration, see

Section 4.12.2: Vsreg supply failure

)

 Overcurrent (depending on configuration, auto recovery mode (see below)

 Overtemperature (TSD1x/ cluster or single mode)

 Fail safe event

 Loss of GND at SGND pin

In case of overcurrent or overtemperature (TSD1_CLx (SR 6)) condition, the drivers will switch off. The relative status bit will be latched and can be read and optionally cleared by

SPI. The drivers remain off until the status is cleared. In case overvoltage/ undervoltage condition, the drivers will be switched off. The relative status bit will be latched and can be read and optionally cleared by SPI. If VSREG_LOCK_EN (CR 3) respectively

VS_LOCK_EN (CR 3) are set, the drivers remain off until the status is cleared. If the

VS_LOCK_EN or VSREG_LOCK_EN bit is set to 0, the drivers will switch on automatically if the error condition disappears. Undervoltage and overvoltage shutdown can be disabled by

SPI. In case of open-load condition, the relative status register will be latched. The status can be read and optionally cleared by SPI. The high and low-side outputs are not switched off in case of open-load condition.

For OUT1, OUT2, OUT3 and OUT6, OUT7, OUT8 and OUT15 the auto recovery feature

(OUTx_OCR (CR 7)) can be enabled. If these bits are set to 1 the driver will automatically restart from an overload condition. This overload recovery feature is intended for loads which have an initial current higher than the overcurrent limit of the output (e.g. Inrush current of cold light bulbs). The SPI bits OUTx_OCR_ALERT (SR4) indicate that the output reached auto-recovery condition.

The maximum voltage and current applied to the High-side Outputs is specified in the

‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to respect these limits under application conditions.

Each of the 7 standalone high-side driver outputs from OUT7 to OUT15 can be driven with an internally generated PWM signal, an internal Timer or through the DIR signal.

Moreover, for OUT7, OUT8 and OUT9 high-side driving LEDs, it is also available the CCM

(Constant Current Mode) feature, which is configurable by SPI (CR9) and conceived to

provide a constant current to the related output (see more detail in Section 4.21: Constant current mode

).

Table 66: Power output settings

summarizes the possible configurations for the high-side outputs.

DS13220 Rev 5 97/198

197

Application information L99DZ200G

0

1

1

0

1

0

0

0

1

1

1

1

1

OUTx_3 OUTx_2 OUTx_1

0

0

0

0

0

0

0 0 1

0

0

0

1

0

1

1

1

1

1

0

1

1

1

0

1

1

0

0

0

1

0

1

1

0

1

1

0

1

0

0

1

0

1

0

1

0

1

Table 66. Power output settings

OUTx_0 Description

0

1

0

1

OFF

ON

Timer1 output is controlled by timer1; starting with ON phase after timer restart

Timer2 output is controlled by timer2; starting with ON phase after timer restart

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

Not applicable

Not applicable

Not applicable

DIR

Not applicable

4.15 Auto-recovery alert and thermal expiration

The thermal expiration feature provides a robust protection against possible microcontroller malfunction, switching off a given channel if continuously driven in auto-recovery. If the temperature of the related cluster increases by more than 30 °C after reaching the auto- recovery time t AR , the channel is switched off. The thermal expiration status bit

OUTx_TH_EX (f) (SR 3) is set.

During auto-recovery condition, OUTx_OCR_ALERT

(f)

(SR 4) is set. The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.

The thermal expiration feature can be activated only in combination with Over Current

Recovery (or Auto-recovery) mode, by setting to 1 both the OUTx_OCR

(f)

(CR7) and the

OUTx_OCR_THX_EN (f)

(CR8) bits.

98/198 f.

For x = 1, 2, 3, 6, 7, 8, 15.

DS13220 Rev 5

L99DZ200G Application information

Figure 33. Example of long auto-recovery on OUT7. Temperature acquisition starts after t

AR

, thermal expiration occurs after ∆=30°

Figure 34. Block diagram of physical realization of AR alert and thermal expiration

μC

ON command

Diagnostic

Gate driver

Batt. supply

Current

Sense

Power

MOS

Ith

Overcurrent comp.

HS_Enab

Temp. sense

Amp

ADC

Digital state machine OC

T_data

AR limit reached

OSC

Lamp Driver IC

GAPG0508151221CFT

DS13220 Rev 5 99/198

197

Application information

CLK

L99DZ200G

4.16 Charge Pump

The charge pump uses two external capacitors, which are switched with f CP . The output of the charge pump has a current limitation. In standby mode and after a thermal shutdown has been triggered the charge pump is disabled. If the charge pump output voltage remains too low for longer than T CP , the power-MOS outputs and the EC-control are switched off.

The H-bridge MOSFET gate drivers and the Heater MOSFET gate driver are switched to resistive low and CP_LOW (SR 2) is set. This bit has to be cleared to reactivate the drivers. If the bit CP_LOW_CONFIG (Configuration Register 0x3F) is set to ‘1’, CP_LOW (SR2) behaves as a ‘live’ bit and the outputs are re-activated automatically upon recovery of the charge pump output voltage.

In case of reaching the overvoltage shutdown threshold V SOV the charge pump is disabled and automatically restarted after V S recovered to normal operating voltage.

Figure 35. Charge pump low filtering and start up implementation

CP -

+

Filter Time ( T typ. 64μs

CP

)

D

CPlow

V

C Plow

Start Up Blan king

Time (t set _CP

) typical 75 0μs

Power Stage Disable

* All power stage (beside P-Channe l) disabled

* Gate Drive Outputs disabled

GAPG0508151227CFT

4.17 Inductive Loads

Each of the half bridges is built by internally connected high-side and low-side power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1...OUT6 without external freewheeling diodes. The high-side drivers OUT7. OUT15 are intended to drive resistive loads only. Therefore only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition.

For inductive loads (L > 100 μH) an external freewheeling diode connected between GND and the corresponding output is required. The low-side driver at ECV does not have a freewheel diode built into the device.

4.18 Open-load detection

The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for t > t OL_OUT the corresponding open- load bit OUTx_OL_STAT (SR 5) is set in the status register.

4.19 Overcurrent Management: Recovery or Latch

All the embedded outputs of the L99DZ200G, from OUT1 to OUT15, come with the Over

Current Detection (Latch); this feature is enabled by default and in case of overcurrent, the corresponding driver switches OFF to reduce the power dissipation and to protect the integrated circuit.

100/198 DS13220 Rev 5

L99DZ200G Application information

For the 7 outputs from OUT1 to OUT8 and OUT15, besides the Over Current protection feature, a mode called Over Current Recovery (OCR) or Auto Recovery is implemented.

The Over Current Recovery allows to automatically switch ON the Outputs that have been switched OFF after an Over Current detection; this method is needed when loads with startup currents higher than the Over Current limits need to be driven.

If the outputs are not configured in Over Current Recovery mode, once the load current reaches the Over Current threshold, after the time interval (t

OCR

), the corresponding status bit in SR 3 is latched and the driver is switched OFF too; in this case the microcontroller has to Read & Clear the according status bits in order to reactivate the corresponding output driver.

If the outputs (from OUT1 to OUT8 and OUT15) are configured in Over Current Recovery mode, once the Over Current condition is detected (i.e. the load current reaches the Over

Current threshold), the corresponding driver is switched OFF and hence automatically switched ON after a certain time interval. The Over Current Recovery mode can be individually enabled for a given output, i.e. for each of the Half Bridges (OUT1, OUT2, OUT3 and OUT6) and for each of the High Side drivers (OUT7, OUT8 and OUT15) by setting the corresponding OUTx_OCR (CR7) bit.

Figure 36. Example of programmable soft start function for inductive loads and incandescent bulbs

The Activation sequence of a specific Output driver (switch OFF / switch ON) can be seen as composed by the following 3 timings:

 t

BLK

 t

OCR

 t

OFF

The t

BLK time, has been designed to be 40 μs (typ); the t

OCR current needs to be above the OC threshold for t > t

OCR time is the filter time (i.e. to detect an OC condition).

The t

OFF is the time interval in which the output driver is switched OFF.

4.20 Overcurrent Recovery and Short-Circuit detection

Over-Current threshold (latch or auto recovery with thermal expiration) is always active. This condition is detected after a blanking time of t

BLK

and, in case of auto recovery (OUTx_OCR

= 1 for x = 1, 2, 3, 6, 7, 8, 15), also after a filter time t

OCR

, depending on

DS13220 Rev 5 101/198

197

Application information L99DZ200G

OUTxx_OCR_TON_0 (1) (where xx = HB, 7, 8, 15) settings configured in CR8. However, in case of a Short Circuit faster than t

OCR

or occurring during t

BLK

, the over-current threshold could not be triggered and the device is not protected. To this aim, for all half-bridges output

(OUT1-6), a Short Circuit threshold, higher than the previous one, is also available (see example in

Figure 37 ). This condition is detected after a filter time of t

FSC

and is indicated by the related status bit OUTx_HS_SHORT, OUTx_LS_SHORT (x = 1, 2, 3, 6) in SR4. In case of Short Circuit, the corresponding driver switches off in order to reduce the power dissipation and to protect the integrated circuit (see

Figure 38 ).

Short Circuit thresholds can be disabled via SPI (OUTx_SHORT_DIS, in CR7, [12...9])

In case of short circuit detection, a global status bit FE is set (see

Table 89 )

For all the half bridges outputs, when the OCR is enabled, the Short Circuit detection must be enabled or the software strategy described in

Figure 40

of

Section 4.25

must be applied.

Figure 37. Typical working current for a motor connected to OUT1 and OUT6 in low on resistance and related over-current and short circuit thresholds

102/198 DS13220 Rev 5

L99DZ200G Application information

Figure 38. Triggering cases of over-current and short circuit thresholds t

FSC

SC threshold t

BLK

= 40 μs

OC threshold

DRIVER

OUTPUT

CURRENT

Period = 1/frequency

HS_ON

OC t

OCR

= 48 μs t

ON t

OFF t

OFF

= Period - t

ON

Red peak Current: device shutoff as per SC threshold

Black peak Current: device cycling as per auto-recovery setting

4.21 Constant current mode

For the OUT7, OUT8 and OUT9 high side drivers, it is available the CCM (Constant Current

Mode) feature, which is conceived to provide a constant current to the related output.

The CCM feature is configurable via SPI, by setting the OUTx_CCM_EN bit (x = 7, 8, 9) in

CR9; these bits can be set only if the related driver is in OFF state and when the CCM is enabled, the overcurrent and short circuit detection of the related output is switched OFF while its open load detection is always ON.

The CCM is automatically disabled after an expiration time t

CCMtimeout

.

The allowed sequences are:

 Set OUTx_CCM_EN bit, then turn ON the related driver by SPI or by direct input DIR

(the other configurations of the OUTx_3-2-1

are ignored, see Table 102 ): driver starts in

CCM for 10ms, then it switches to ON mode or DIR mode and the OUTx_CCM_EN bit is automatically cleared after this 10 ms;

 If OUTx_CCM_EN = 1, the configurations other than “OFF”, “ON” or “DIR” of the

OUTx3-2-1-0 (see

Table 102

) are ignored; in that case, the OUTx3-2-1-0 bits are kept

DS13220 Rev 5 103/198

197

Application information L99DZ200G unchanged (at either “0000”=OFF, “0001”=ON or “1110”=DIR) and the SPI_INV_CMD bit (SR2 – 0x32) is set to 1 in order to indicate an invalid setting;

 If OUTx_CCM_EN bit is cleared by the microcontroller before timeout, then the driver is itched to ON mode or DIR mode;

 If OUTx_CCM_EN bit is set after driver has been started in ON, PWM, Timer or DIR modes, then the OUTx_CCM_EN bit is ignored (i.e. OUTx_CCM_EN = 0); in that case

OUTx_CCM_EN remains ‘0’ and the SPI_INV_CMD bit (SR2 - 0x32) is set to ‘1’ in order to indicate an invalid setting.

The Short Circuit and Over Current detection are enabled in ON, PWM, timer and DIR modes, but not in Constant Current Mode.

The default value for the OUTx_CCM_EN bit is 0, i.e. the CCM is disabled by default.

Figure 39. Constant current mode

Vout (V)

0

0 t (ms)

Iout (A)

I

CCMx

I loadn

I load3

I load2

I load1

I load

0

0 t

CCMtimeout

Constant current mode t (ms)

Normal high-side driver mode

4.22 Current monitor and direct drive input

The current monitor sources a current image of the power stage output current at the current monitor pin CM, which has a fixed ratio (I CMr ) of the instantaneous current of the selected high-side driver. The signal at output CM is blanked for t cmb after switching on the driver until correct settlement of the circuitry. The bits CM_SELx (CR 7) define which of the outputs is multiplexed to the current monitor output CM. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- load or overload condition. For example, it can be used to detect the motor state (starting, free running, stalled). The current monitor output is enabled after the current-monitor blanking time, when the selected output is switched on. If this output is off, the current monitor output is in high impedance mode.

Current monitor output pin is shared with the Direct Input Drive (DIR) and the activation of the two functionalities is obtained by changing the CM_DIR_CONF_x bit (CR7, x = 0, 1).

Four different modalities are identified and detailed in the following

Table 67 .

104/198 DS13220 Rev 5

L99DZ200G Application information

CM_DIR_CONF_1

0

0

1

1

Table 67. Current Monitor/Direct configurations

CM_DIR_CONF_0 Description

0 CM all the time

1

0

1

DIR in Standby mode and

CM in Active mode

DIR all the time

OFF

Pin direction

Output

Input / Output

Input

4.23 PWM-Mode of the Power-Outputs

Description see

Section 7.3: Status register overview .

4.24 Cross-current protection

The four half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned off, the activation of the other driver of the same half bridge will be automatically delayed by the crosscurrent protection time. After the crosscurrent protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior, it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct.

4.25 Programmable soft-start function to drive loads with higher inrush current

Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors) can be driven by using the programmable soft-start function (i.e. overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit

OUTx_OCR (CR 7). If this bit is set, the device automatically switches the outputs on again after a programmable recovery time. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency is defined by CR7<8:12> setting.

The device itself cannot distinguish between a real overload (e.g. short-circuit condition) and a load characterized by operation currents exceeding the over-current threshold.

Examples are non-linear loads like a light bulb used on the HS outputs or a motor used on the half bridge output with inrush and stall currents that shall be limited by the auto recovery feature.

For the bulb, a real overload condition can only be qualified by time. For overload detection the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first e.g. 50 ms. After clearing the recovery bit, the output will be switched off automatically if the overload condition remains.

For the half bridges the high current can be present during all motor activation and another

SW strategy must be applied to identify a SC to GND or Supply. Before running the motor e.g. with a first SPI command all bridge LS are switched on (without auto recovery functionality /

DS13220 Rev 5 105/198

197

Application information L99DZ200G

BEGIN

SW Routine cleared overcurrent recovery bit), all HS are switched off and a SC to Battery can be diagnosed. With a next SPI command, all HS are switched on (without auto recovery functionality/ cleared overcurrent recovery bit) and all LS are switched off. In this sequence, a short to GND can be diagnosed. If in both sequences no overload condition is identified, the motor can be run by switching on the relative HS and LS each configured in auto recovery mode (see

Figure 40: Software strategy for half bridges before applying auto-recovery mode

).

Such sequence can be applied before any motor activation to identify SC just before operating the motor (in case the delay due to the 2 additional SPI commands is not limiting the application) or in case of power up of the system respectively applied on a certain time base.

Figure 40. Software strategy for half bridges before applying auto-recovery mode

Vbat Vbat

VS VS VS VS

OUTxHS

OFF

? ?

OUTyHS

OFF

OUTx

M

OUTy

ON

OUTxLS

L99DZ200G

GND

ON

OUTyLS

L99DZ200G

GND

AR OFF

SW Step 1: Short to battery detection

SW Step 1

HS OFF

LS ON

Short to Vs?

N

Y

OUTxHS

ON

OUTyHS

ON

OFF

OUTxLS

L99DZ200G

GND

OUTx

M

OUTy

OFF

? ?

OUTyLS

L99DZ200G

GND

SW Step 2: Short to ground detection

SW Step 2

HS ON

LS OFF

Short to GND?

N

Y

Set AR ON

Keep AR OFF

Switch HS OFF

Keep AR OFF

Switch LS OFF

END

SW Routine

GAPG0408151459CF

As soon as an output reaches auto-recovery condition, OUTx_OCR_ALERT (SR 4) is set.

The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.

4.26 H-bridge control

The PWMH1y, PWMH2y inputs and the DIRHy bits (DIRHA in CR10, DIRHB in CR21) control the drivers of the external H-bridge transistors (y = A, B); independently from the PWMH frequency (f

PWMH

) applied by the µC to control the H-bridges A and B, the PWMH On-time shall be higher than 250ns. In Single Motor mode, bit DMy (Config Reg = 0), the motor direction can be chosen with the control bit (DIRHy), the duty cycle and frequency with the

PWMH1y input. With the SPI bits SD1y (CR 10) and SDS1y (CR 10) four different

106/198 DS13220 Rev 5

L99DZ200G Application information

Control pins freewheeling modes (via drivers in the active cases or via diodes in the passive cases) can be selected using the high-side or the low-side transistors.

Alternatively, the external H-bridges can be driven in half bridge mode (Dual mode). By setting the dual mode bit DMy (Config Reg) = 1, both the half-bridges of the H-bridge y can be controlled independently.

Table 68. H-bridge y (y = A, B) control truth table in Single mode (DMy = 0)

Control bits

Failure bits Output pins

Nb x

1 x x x x

5

6

1

2

3

4

7 0 x x x x x x x x

0 x x x x x

0

1

1

1 x x x

0 x x

0 x x

0 x x x x x x x x x x x

1

0

0 x

0 x

1

1 0 x x x x

1 0 x x x x

0 0

0 0

1 0 0 0 x x 0 0

1

0 x

0 x

0

0

0 x

0 x

0

0 0 x

0

1

0

0

0

L

L

(1)

RL RL

RL RL

RL RL

L

L (1) L (1)

RL

RL

RL

L

L H H

RL H-bridge y disabled

RL Charge pump voltage too low

RL Thermal shutdown

L Overvoltage

L (1)

Short-circuit

(1)

L Bridge y H2/L1 on

0 L H L H Active freewheeling LS1 and LS2 on

8

9

0

0

10 1

11 0 x x x x

0

1

1 x

1 0 0 1 x x 0 0

1 0 0 1 x x 0 0

1 0 x x

1 0 1 0 x x x x

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

L

L

H

H

H

L

L

L

L

L

L

H

L

H

Passive freewheeling through LS2 diode

Passive freewheeling through LS1 diode

H Bridge y H1/L2 on

L Active freewheeling HS1 and HS2 on

12 0 x 0 1 0 1 1 x x 0 0 0 0 0 L L H L

Passive freewheeling through HS1 diode

13 0 x 1 1 0 1 1 x x 0 0 0 0 0 H L L L

Passive freewheeling through HS2 diode

1. Only the half bridge (low-side and high-side), in which one MOSFET is in short-circuit condition is switched off. Both

MOSFETs of the other half bridge remain active and driven by DIRHy control bit and PWMHy pin.

DS13220 Rev 5 107/198

197

Application information L99DZ200G

Control pin

Table 69. H-bridge y (y = A, B) control truth table in Dual Mode (DMy = 1) for the leg x (x= 1, 2)

Control bits

Failure bits Output pin Comment

Nb

4

5

6

1

2

3

7

8

1

0

1

0

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1 x x x x x x x x

1

0

0

0

0

1

1

1

0

1

1

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

L

L

H

L

H

H

L

L

H

L

L

H

L

L

L

H

Active freewheeling LS

DRIVE HS

Active freewheeling HS

DRIVE LS

Passive freewheeling

DRIVE HS

Passive freewheeling

DRIVE LS

During watchdog long-open window, the H-bridge drivers are forced off until the first valid watchdog trigger in window mode (setting TRIG = 0 during safe window). The Control

Registers remain accessible during long open window.

4.27 H-Bridge Driver Slew-Rate Control

The rising and falling slope of the drivers for the external high-side Power-MOS can be slew rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this Power-MOS is below the switch threshold. The current is programmed using the bits SLEW_x<4:0> (CR 10), which represent a binary number. This number is multiplied by the minimum current step. This minimum current step is the maximum source-/sink-current (I GHxrmax / I GHxfmax ) divided by 31. Programming SLEW_x

<4:0> to 0 disables the slew rate control and the output is driven by the low-impedance output driver switch.

108/198 DS13220 Rev 5

L99DZ200G

Figure 41. H-bridge GSHx slope

Application information

V

GSHx

V

DSHx

Current

Controlled

Low-Resistive

Switch

Controlled

Current

Controlled t

GAPG0508151242CFT t

4.28 Resistive low

The resistive output mode protects the devices and the two H-bridges in the standby mode and in some failure modes (thermal shutdown TSD1 (SR 1), charge pump low CP_LOW (SR 2) and DI pin stuck at ‘1’ SPI_INV_CMD (SR 2). When a gate driver changes into the resistive output mode due to a failure a sequence is started. In this sequence the concerning driver is switched into sink condition for 32 μs to 64 μs to ensure a fast switch-off of the H-bridge transistor. If slew rate control is enabled, the sink condition is slew-rate controlled. Afterwards the driver is switched into the resistive output mode (resistive path to source).

4.29 Short circuit detection / drain source monitoring

The Drain - Source voltage of each activated external MOSFET of the H-bridges A and B is monitored by comparators to detect shorts to ground or battery. If the voltage-drop over the external MOSFET exceeds the configurable threshold voltage V SCd_HB (DIAG_A_x (CR 10) for H-bridge A and DIAG_B_x (CR23) for H-bridge B) for longer t > t SCd_HB the corresponding gate driver switches off the external MOSFET and the corresponding drain source monitoring flag DS_MON_x (SR 2) is set. The DSMON_x bits have to be cleared through the SPI to reactivate the gate drivers. This monitoring is only active while the corresponding gate driver is activated. If a drain-source monitor event is detected, the corresponding gate-driver remains activated for at maximum the filter time.

When the gate driver switches on, the drain-source comparator requires the specified settling time until the drain-source monitoring is valid. During this time, this drain-source

DS13220 Rev 5 109/198

197

Application information L99DZ200G monitor event may start the filter time. The threshold voltage V SCd_HB can be programmed using the SPI bits DIAG_A_x (CR 10) or DIAG_B_x (CR 23).

Figure 42. H-bridge diagnosis

Vs

VS

DS-Monitoring HS

Gate Driver HS V

Thres

20k

GH1

SH1

Gate Driver LS

DS-Monitoring LS

OL-Monitoring

V

Thres

20k

GL1

M

VS

GH2

20k

V

Thres

DS-Monitoring HS

Gate Driver HS

SH2

GL2

20k

V

Thres

DS-Monitoring LS

OL-Monitoring

Gate Driver LS

GAPG0408151656CFT

4.30 H-Bridge-Monitoring in Off-Mode

The drain source voltages of the two H-bridges A and B driver external transistors can be monitored, while the transistors are switched off. If either bit OL_H1L2_X or OL_H2L1_X

(CR 10 for X=A, CR23 for X=B) is set to 1, while bit HEN_X (CR 1) = 1, the H-drivers X (A or

B) enter resistive low mode and the drain-source voltages can be monitored. Since the pullup resistance is equal to the pull-down resistance on both sides of the bridge , a voltage of

2/3 V S on the pull-up high side and 1/3 V S on the low- side is expected, if they drive a lowresistive inductive load (e.g. motor). If the drain source voltage on each of these Power-

MOS is less than 1/6 V S , the drain-source monitor bit of the associated driver is set. The open-load filter time is t OL_HB .

110/198 DS13220 Rev 5

L99DZ200G Application information

Figure 43. H-bridge open-load-detection (no open-load detected)

Vs

DSM = 0

V

T

20k

Vs/3

=Vs/6

M m

Vs/3

20k 20k

V

T

=Vs/6

DSM = 0

Figure 44. H-bridge open-load-detection (open-load detected)

Vs

DSM = 0

V

T

20k

Vs/2

=Vs/6

M m

Open

20k 20k

V

T

=Vs/6

DSM = 1

DS13220 Rev 5 111/198

197

Application information L99DZ200G

Figure 45. H-bridge open-load-detection (short to ground detected)

Vs

DSM = 1

20k

GND

M m

V

T

20k

=Vs/6

Short 20k

GND

V

T

=Vs/6

DSM = 1

Figure 46. H-bridge open-load-detection (short to Vs detected)

Vs

Short

20k

Vs M m

Vs

DSM = 1 DSM = 1

20k

V

T

=(5/6)Vs

20k

V

T

=(5/6)Vs

In this specific case the outputs of the 2 comparators are inverted to be compliant to

Table 70: H-bridge monitoring in off-mode

(Nb = 9).

Table 70. H-bridge monitoring in off-mode

Control bits Failure bits

Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2

Comments

1

2

3

4

0

1

1

1

0

0

0

0

0 x

0

0

0

0

0

1

0

0

1

1

Drain-Source monitor disabled

No open-load detected

Open-load SH2

Short to GND

112/198 DS13220 Rev 5

L99DZ200G Application information

Table 70. H-bridge monitoring in off-mode (continued)

Control bits Failure bits

Nb OL H1L2 OL H2L1

7

8

5

6

9

1

0

0

0

0

1

1

0

1

1

Comments

H OLTH High DSMON LS1 DSMON LS2

0

0

1 x

1

1

0

1

1

1

1

0

0

1

1

Short to VS

No open-load detected

Open-load SH1

Short to GND

Short to VS

What reported in this chapter applies only to single motor H-bridge configuration; i.e. in the case one H-bridge drives only one motor.

4.31 Programmable cross current protection

The external Power MOSFETs transistors in H-bridge A and B (two half-bridge for each Hbridge) configuration are switched on with an additional delay time t CCP to prevent cross current in the half bridge. The cross current protection time t CCP can be programmed with the

SPI bits COPT_x_A<3:0> (CR 10 for H-bridge A) or COPT_x_B <3:0> ( CR 15 for H-bridge

B). The timer is started when the gate driver is switched on in the device.

The PWMH module has 2 timers to configure locking time for high-side and freewheeling low-side. The programmable time t CCP-TIM1 / t CCP-TIM2 is the same. Sequence for switching in PWM mode is the following:

 HS switch off after locking t CCP-TIM1

 LS switch on after 2nd locking t CCP-TIM1

HS switch on after locking t CCP-TIM2 which starts with rising edge on PWM input.

Figure 47. PWMH cross current protection time implementation t pp

< 2 x t ccp t pp

< t ccp t pp

> 2 x t ccp

PWM

Input

Lorem ipsum t

CCP-TIM1 t

CCP-TIM1 t

CCP-TIM1 t

CCP-TIM1 t

CCP-TIM1 t

CCP-TIM1

HS Logic

LS Logic t

CCP-TIM2

Active

Free Wheeling t

CCP-TIM2

Passive

Free Wheeling t

CCP-TIM2

DS13220 Rev 5

Passive

Free Wheeling

GAPG0303161056CFT

113/198

197

Application information L99DZ200G

4.32 Power window H-bridge safety switch off block

The two LS Switches LSA_FSO and LSB_FSO are intended to be used to switch off the gates of the two external high-side MOSFETs in the power window h-bridges (A and B) if a fatal error happens. This block must work also in case the MOSFET driver and the relative control blocks on the chip are destroyed. Therefore, it is necessary to have a complete separated safety block on the device, which has its own supply and GND connection, separated from the other supplies and GNDs. In the block, an own voltage regulator and an oscillator are implemented.

The safety block is surrounded by a GND isolation ring realized by deep trench isolation.

The LS driver must work down to a lower voltage than the other circuits. The block has its own internal supply and an own oscillator for monitoring the failure signals (WWD, V1 fail,

SPI fail & Tj) which are Manchester encoded and decoupled by high ohmic resistances. In case of fail-safe event, both LS switches LSA_FSO and LSB_FSO are switched on.

In case of entering V1_Standby mode or VBAT_Standby mode both fail safe low-side switches are switched on to minimize the current drawn by the fail-safe block (e.g. oscillator is switched off and Manchester Encoding is deactivated). Short circuit protection to V S is active in both standby modes limiting the current to I OLimit for a filter of t SCF .

After this filter time the fail-safe switches are switched off and LSx_FSO_OC (SR 3) is set. To reactivate the low-side functionality this bit has to be set back by a read and clear command.

In case of V S loss the fail-safe switches are biased by their own output voltage to turn on the low-side switches down to VOUT_max.

To allow verification of the Fail-Safe path, the low-side switches LSA_FSO and LSB_FSO can be turned on by SPI (Configuration Register 0x3F bit 4: FS_FORCED).

114/198 DS13220 Rev 5

L99DZ200G Application information

Figure 48. LSx_FSO: low-side driver “passively” turned on, taking supply from output pin (if main supply fails), can guarantee VLSx_FSO < VOUT_max

Complete IC

Supply

CLEAR LSx_FSO_OC

Watchdog Fail

V1 Failures

Over Temp

TSD2

Clock

LSA_FSO_OC

&

LSB_FSO_OC

Fail Safe Block

Filters

& State

Machine

Low Side

Driver 1

LSB_FSO_OC

Low Side

Driver 2

LSB_FSO

VREG

Enable

GND

Figure 49. Safety concept

Tx Signal

Manchester Encoded

Signals

Clock

Rx Signal

Normal Operation Fail Safe Clock Failure Data Failure

DS13220 Rev 5 115/198

197

Application information L99DZ200G

4.33 Generator mode

Generator mode allows the L99DZ200G h-bridge drivers to autonomously switch ON all the external LS MOSFETs of both h-bridges (A and B) when an overvoltage on the VS line is detected. Main purpose of these concurrent activations is to immediately block at the same time both the DC motors connected to the 2 external full bridges (braking function).

Generator Mode is by default enabled at the startup of the device and it is controlled by the

GENERATOR_MODE_EN bit in CR22 (0x16); in case the VS OV occurs during standby modes and the generator mode is enabled, the VS_OV_WAKEUP bit in the SR1 (0x31) identifies the OV as source of the wakeup.

Generator mode works when L99DZ200G is in Active, in V1_Standby and in VBAT_Standby modes. Fail safe low side circuitry has not to be activated/connected if the Generator mode will be used

4.33.1 Generator Mode in Active Mode

The below reported Table 71

shows the wake UP True table for the Generator Mode when the device is in active mode:

Table 71. Wake UP for Generator Mode

L99DZ200G Status GENERATOR _MODE_EN LS MOSFETs state after V

S

OV condition

Active

1

0

ON if V

S

> V

SOV

Controlled by the h-bridge drv if V

S

< V

SOV

Controlled by the h-bridge drv

Notes

Monitoring is done by the "Vs Monitor"

In Active Mode, Generator Mode is a live functionality, i.e. the Vs is continuously monitored by a "V

S

Monitor". In case the V

S

OV is detected, GL1y and GL2y (y = A, B) are switched

ON; they are switched OFF as soon as the V

S

OV is no more detected.

When the Generator Mode is enabled (GENERATOR_MODE_EN=1), the configuration of the h-bridge drivers A and B can be changed even when the V

S

OV is occurring. The hbridges A and B will recover the normal h-bridge drive once the V

S during this V

S or a Fail Safe event occurs.

OV ends; moreover,

OV situation the LS MOSFETs continues to be ON even if a TSD1 or a TSD2

4.33.2 Generator Mode in Standby Modes

In V1_Standby or in VBAT_Standby modes, a "V

S

OV Detector" is used to detect the occurrence of a Vs OV; in this case the thresholds are V

SOV_DET

A.186 and A.187 in

Table 7

).

(see parameters A.185,

When Vs > V

S_OVDET

the device is firstly put in Active mode and then the "Vs Monitor" is activated; all this sequence lasts (t

OVUV_FILT oscillator at V

SOV_DET

+ t

FOV

) plus the time needed to start the

threshold (around 10 µs) plus the time needed to stabilize the reference voltage (around 10 µs). This means that the V

SOV

shall be present for a minimum of 148 µs to start the braking function and set the VS_OV_WAKEUP bit (SR1).

The below reported Table 72: Wake UP for Generator Mode

shows the Wake UP True table for the Generator Mode when the device is in V1_Standby or in VBAT_Standby mode:

116/198 DS13220 Rev 5

L99DZ200G Application information

Table 72. Wake UP for Generator Mode

L99DZ200G Status GENERATOR _MODE_EN

Wake UP when a

V

S

OV occurs

LS MOSFETs state after V

S

OV condition (V

S

> V

SOV_det

)

Notes

V1_Standby or

VBAT_Standby

1 Yes

0 No

1. Generator Mode wake up at Vs OverVoltage by VS OV Detector (low consumption, 1 µA)

OFF

(1)

OFF added around 1 µA conso

In Standby modes:

 if the Vs OV is detected, SPI writing to enter in Standby modes will be ignored and a

SPI Error will be generated; in this case the SPI_INV_CMD bit (SR2 - 0x32) is set to 1 in order to indicate an invalid setting;

 if the Vs OV disappears, a new SPI access will be needed to enter in Standby modes.

4.34 Heater MOSFET Driver

The Heater MOSFET Driver stage is controlled by control bit GH (CR 5). The driver contains two diagnosis features to indicate short-circuit in active mode (external MOSFET switched on) and open-load in off state (External MOSFET switched off).

Short circuit detection in on state is realized by monitoring the drain source voltage of the activated external MOSFET by a comparator to detect a short-circuit of SH heater to ground. If the voltage-drop over the external MOSFET exceeds the programmed threshold voltage

V SCd_HE for longer than the drain-source monitor filter time t SCd_HE the gate driver switches off the external MOSFET and the corresponding drain source monitoring flag

DSMON_HEAT (SR 5) is set. The drain source-monitoring bit has to be cleared by SPI to reactivate the gate driver. The drain source monitoring is only active while the gate driver is activated. If a drain source monitoring event is detected, the gate-driver remains activated for the maximum filter time. The threshold voltage can be programmed by SPI bits GH_THx

(CR 10).

Open-load detection in off state is realized by monitoring the voltage difference between

SH heater and GND and supplying SH heater by a pull up current source that can be controlled by SPI bit GH_OL_EN (CR 11). When no load is connected to the external MOSFET source, the voltage will be pulled to V S and in case of exceeding the threshold V OLheater for a time longer than the open-load filter time t OL_He the open-load bit GH_OL (SR 5) will be set.

DS13220 Rev 5 117/198

197

Application information L99DZ200G

Figure 50. Heater MOSFET open-load and short-circuit to GND detection

Vs

DSMON_HEAT

CP

V

Thres

SPI

I

OLheater

GH

Heater

SH

Heater Gate Driver

Heater MOSFET

GH_OL

V

OLheater

Control bit

Table 73. Heater MOSFET control truth table

Failure bits Output pin

Nb GH ON/OFF CP_LOW VS_OV VS_UV DS

6

7

4

5

1

2

3 x x x

1 x

1

0

1

0

0

0

0

0

0 x x

1

0

0

0

0 x x x x

1

0

0

0

0

1

0 x x x

TSD1

0

0

0

0 x

1

0

Comment

GH heater

H

L

L

L

RL

RL

L

Charge pump voltage too low

Thermal shutdown

Overload

Short-circuit condition

Undervoltage

Heater MOSFET driver

Heater MOSFET driver

Note: RL = resistive low, L = active low, H = active high.

4.35 Controller of electro-chromic glass

The voltage of an electro-chromic element connected at pin ECV can be controlled to a target value, which is set by the bits EC_x <5:0> (CR 11). Setting bit ECON (CR 11) enables this function. An on-chip differential amplifier and an external MOS source follower (with its gate connected to pin ECDR) driving the electro-chrome mirror voltage at pin ECV, form the control loop. The drain of the external MOS transistor is supplied by OUT10. A diode from pin ECV

(anode) to pin ECDR (cathode) has been placed on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to be added to pin ECDR for loop-stability.

118/198 DS13220 Rev 5

L99DZ200G Application information

The target voltage is binary coded with a full-scale range of 1.5 V. If bit ECV_HV (Config Reg) is set to 0, the maximum controller output voltage is clamped to 1.2 V without changing the resolution of bits EC_x<5:0> (CR 11). When programming the ECV low-side driver ECV_LS

(CR 11) to on-state, the voltage at pin ECV is pulled to ground by a 1.6 Ω low-side switch until the voltage at pin ECV is less than d VECVhi higher than the target voltage (fast discharge).

The status of the voltage control loop is reported via SPI. Bit ECV_VHI (SR 6) is set, if the voltage at pin ECV is higher, whereas Bit ECV_VNR (SR 6) is set, if the voltage at pin ECV is lower than the target value. Both status bits are valid, if they are stable for at least the filter time t FECVNR and t FECVHI . Since OUT10 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched off). In electro-chrome mode, OUT10 cannot be controlled by

PWM mode. For EMS reasons, the loop capacitor at pin ECDR as well as the capacitor between ECV and GND have to be placed to the respective pins as close as possible (see

Figure 51: Electro-chrome control block

for details).

Pin ECDR is pulled resistively (R ECDRDIS ) to ground while not in electro-chrome mode. EC glass control behavior in case of failure on OUT10:

ECON (CR11) = 1 (EC glass control enabled)

 OUT10 is turned ON

 OUT10 settings in CR5 are ignored (PWM, DIR, TIMERx)

 OUT10 settings in CR5 are recovered when ECON is set to 0.

In case of a failure on OUT10 while ECON = 1 (overcurrent, V S overvoltage /undervoltage,

TSD1)

 OUT10 is turned OFF (regardless of VS_OV_SD_EN and VS_UV_SD_EN in CR3)

 DAC is reset: EC_x (CR11) set to ‘000000’

 ECDR pin is pulled to GND

 ECON (CR11) remains ‘1’

 ECV_LS (CR11) remains as programmed Re-start of EC control after OUT10 failure

 Read&Clear or automatic restart (if CR3 Vs_LOCK_EN = 0)

 Write EC_x (CR11)

DS13220 Rev 5 119/198

197

Application information

SPI Logic

1 0 1 0 1 1

Voltage not reached

Voltage too high

L99DZ200G

Figure 51. Electro-chrome control block

VS

Ÿ

VS compatible

OUT10

All components must be placed close together and connected with a very low impedance

ECDR

5 nF

EC-Mirror

VS compatible

Ÿ

ECV

200 nF

GND

GAPG0408151702CFT

4.36 Temperature warning and shutdown

If any of the cluster (see Section 4.37

) junction temperatures rises above the temperature warning threshold TW, the temperature warning flag TW (SR 2) is set after the temperature warning filter time t jtft and can be read via SPI. If the junction temperature increases above the temperature shutdown threshold (TSD1), the thermal shutdown bit TSD1 (SR 1) is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter time. The gates of the H-bridge and the heater MOSFET are discharged by the ‘Resistive Low’ mode. After these bits have been cleared, the output stages are reactivated. If the temperature is still above the thermal warning threshold, the thermal warning bit is set after t jtft . Once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after t jtft and the outputs are switched off. Therefore, the minimum time after which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermal shutdown threshold is twice the thermal warning/ thermal shutdown filter time t jtft .

4.37 Thermal clusters

In order to provide an advanced on-chip temperature control, the power outputs are grouped in six clusters with dedicated thermal sensors. The sensors are suitably located on the device (see

Figure 52: Thermal clusters identification

). In case the temperature of an output cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster are shut down (all other outputs remain active). Each output cluster has a dedicated temperature warning and shutdown flag (SR 6) and the cluster temperature can be read out by SPI.

Hence, the thermal cluster concept allows to identify a group of outputs in which one or more channels are in overload condition.

120/198 DS13220 Rev 5

L99DZ200G

Note:

Application information

If thermal shutdown has occurred within an output cluster, or if temperature is rising within a cluster, it may be desired to identify which of the output (s) is (are) determining the temperature increase. An additional evaluation, based on current monitoring and cluster temperature read-out, supports identification of the outputs mainly contributing to the temperature increase. The cluster temperatures are available in SR 7, SR 8 and SR 9 and can be calculated from the binary coded register value using the following formula:

Decimal code = (350 – Temp) / 0.488

Example:

T = -40 °C => decimal code is 799 (0x31F) T = 25 °C => decimal code is 666 (0x29A)

Thermal clusters can be configured using bit TSD_CONFIG (Config Reg):

 Standard mode (default): as soon as any cluster reaches thermal threshold the device is switched off. V1 regulator remains on and is switched off reaching TSD2.

 Cluster mode: only the cluster that reaches shutdown temperature is switched off.

If Cluster Th_CL6 (global) or Cluster Th_CL5 (Voltage Regulators) reaches TSD1, the whole device is OFF (beside V1).

Clusters related to power outputs (clusters 1 to 4, see

Figure 52: Thermal clusters identification

) will be managed digitally only, by means of the ADC conversion of related thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators) since ADC can be off, e.g. in V1_Standby mode. Temperature reading provided by ADC may differ from real junction temperature of a specific output due to spatial placement of thermal sensor. Such an effect is more visible during fast thermal increases of junction temperature.

For some of the Power outputs, located between two different sensors, it may happen that temperature raising also affects the adjacent Cluster.

DS13220 Rev 5 121/198

197

Application information

Figure 52. Thermal clusters identification

L99DZ200G

WU

CL1B

SH1B

GH1B

GH2B

SH2B

GL2B

CP2M

CP2P

CP

CP1P

CP1M

GHheater

SHheater

LSA_FSO

LSB_FSO

11

12

13

14

15

16

6

7

4

5

1

2

3

8

9

10

Tab

L99DZ200G

LQFP-64

37

36

35

34

33

41

40

39

38

45

44

43

42

48

47

46

PWMH1B

NINT

RxD_C/NINT

TxD_C

RxD_L/NINT

TxD_L

CSN

DI

DO

CLK

CM/DIR

SGND

VSREG

OUT15

ECDR

ECV

Thermal cluster 1

Thermal cluster 2

Thermal cluster 3

Thermal cluster 4

Thermal cluster 5

GAPG0508151137CFT

Th_CL1 Th_CL2

Table 74. Thermal cluster definition

Th_CL3 Th_CL4 Th_CL5 Th_CL6

OUT14+OUT15

Mirror-x+ Mirror-y

+ OUT8

Folder

(OUT1+OUT6)

10W driver high ohmic channels

VREG 1

VREG 2

Global

TW & TSD1 Both digitally managed

TW & TSD1 Both digitally managed

TW & TSD1 Both digitally managed

TW & TSD1 Both digitally managed

TW digitally managed TSD1

& TSD2

Both analog managed

TW digitally managed TSD1

Analog managed

4.38 V

S compensation (duty cycle adjustment) module

All stand-alone HS outputs can be programmed to calculate some internal duty cycle adjustment to adapt the duty cycle to a changing supply voltage at V S . This feature is aimed at avoiding LED brightness flickering in case of alternating supply voltage. The correction of the duty cycle is based on the following formula:

122/198 DS13220 Rev 5

L99DZ200G Application information

Equation 1 Duty cycle correction

DutyCycle =

V

V bat

–

–

V

V led

  nom

V th = Duty cycle reference voltage: defined as 10 V

V bat = Reference voltage: defined as voltage at pin VS V LED = Voltage drop on the external

LED

DC nom = Nominal Duty Cycle programmed by SPI< PWMx DCx>

To be compatible to different LED load characteristics the value for V LED can be programmed for each output by a dedicated control register OUT7_VLED … OUT15_VLED (CR 17 to CR

20). Auto compensation features can be activated for all HS outputs each by setting

OUTx_AUTOCOMP_EN (CR 17 to CR 20).

The programmed LED voltage (OUTx_VLED (CR17 to CR20)) must be lower than V th (10

V).

Figure 53. Block diagram Vs compensation (duty cycle adjustment) module

ADC / VS

10 Register Duty Cycle HS

10 Bit accuracy / Nominal

Voltage @ 10V

SPI

1 0 1 1 1 0 1 1 0 0

1 0 1 1 1 0 1 1 0 0

SPI

Internal

Adjustment

ON / OFF

1

HS Assignment and Load Adaption

1 1 0 1 1 0 1 1 0 1

10 BIT V

LED voltage level

(0V ..10V)

VS Compensation

Calculation

10 Register adjusted

Duty Cycle HS / 10 Bit accuracy

1 0 1 1 1 0 1 1 0 0

1 0 1 1 1 0 1 1 0 0

HS1

HS2

HS9

HS10

GAPG0508151603CFT

4.39 Analog digital converter

Voltage signals V S , V SREG , V WU and TH_CL1...6 are read out sequentially. The voltage signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, sampled at f

ADC frequency which is obtained dividing by 4 the main clock f clk2

.

Each channel will be converted with a conversion time t con , therefore an update of the ADC value is available every t con * 9. In case of WU is directly connected to V

Protected

(refer to

Figure 61

), the input must be protected by a series resistance of typical 1 kΩ to sustain reverse battery condition.

DS13220 Rev 5 123/198

197

Application information L99DZ200G

Figure 54. Sequential ADC Read Out for VSREG, VS, WU and THCL1... THCL6

3.3V

Vin

1000k

WU

VSREG

VS

100k

VREF = 2V

10pF

9 Channel

Mux

THCL1

THCL2

THCL3

THCL4

THCL5

THCL6

SPI Register

10 Bit

SAR

Note:

GAPG0408151647CFT

As best practice, in order to release valid temperature or voltage information, it is strongly recommended to filter out sequential reading of a relevant channel (i.e. reading from 3 to 5

ADC conversions, excluding a potential outlier, and then weight the remaining data).

124/198 DS13220 Rev 5

L99DZ200G

5 Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI)

Note:

A 32-bit SPI is used for bi-directional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output Pins and one input

Pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin will reflect the global error flag (fault condition) of the device.

 Chip Select Not (CSN) 

The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame. If CSN = low for t > t CSNfail the DO output will be switched to high impedance in order not to block the signal line for other SPI nodes.

 Serial Data In (DI) 

The input Pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

 Serial Data Out (DO) 

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN

Pin will transfer the content of the selected status register into the data out shift register.

Each subsequent falling edge of the CLK will shift the next bit out.

 Serial Clock (CLK) 

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK frequency up to

4 MHz.

5.1 ST SPI 4.0

The ST-SPI is a standard used in ST Automotive ASSP devices.

This chapter describes the SPI protocol standardization. It defines a common structure of the communication frames and defines specific addresses for product and status information.

DS13220 Rev 5 125/198

197

Serial Peripheral Interface (SPI)

5.1.1

L99DZ200G

The ST-SPI allows the use of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular product. In addition, failsafe mechanisms are implemented to protect the communication from external influences and wrong or unwanted usage.

The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0.

Physical Layer

Figure 55. SPI pin description

μC

SPI Master

CSN

SCK

SDI

SDO

L99DZ200G

5.2 Signal description

 Chip Select Not (CSN) 

The communication interface is de-selected, when this input signal is logically high. A falling edge on CSN enables and starts the communication while a rising edge finishes the communication and the sent command is executed when a valid frame was sent.

During communication start and stop the Serial Clock (SCK) has to be logically low.



The Serial Data Out (SDO) is in high impedance when CSN is high or a communication timeout was detected.

 Serial Clock (SCK) 

This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are shifted out to Serial Data Out

(SDO).

 Serial Data Input (SDI) 

This input is used to transfer data serially into the device. Data is latched on the rising edge of Serial Clock (SCK).

 Serial Data Output (SDO) 

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK).

126/198 DS13220 Rev 5

L99DZ200G Serial Peripheral Interface (SPI)

Figure 56. SDO pin

V1 ESD prot

Data In

Enable

Digital logic

Data Out

GND GND

GAPG2608151615CFT

5.2.1 Clock and data characteristics

The ST-SPI can be driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0

CPHA = 0

Figure 57. SPI signal description

CSN

SCK

SDI

SDO

MSB

MSB

LSB

LSB

GAPG2209151345CFT

The communication frame starts with the falling edge of the CSN (Communication Start).

SCK has to be low.

The SDI data is then latched at all the subsequent rising SCK edges into the internal shift registers. After Communication Start the SDO will leave 3-state mode and present the MSB of the data shifted out to SDO. At the subsequent SCK falling edges, data are shifted out to

SDO through the internal shift registers. The communication frame is finished with the rising edge of CSN. If a valid communication took place (e.g. correct number of SCK cycles,

DS13220 Rev 5 127/198

197

Serial Peripheral Interface (SPI)

5.2.2

L99DZ200G access to a valid address), the requested operation according to the Operating Code will be performed (Write or Clear operation).

Communication Protocol

SDI Frame

The devices Data-In Frame consist of 32-bit (OpCode (2 bits) + Address (6 bits) + Data Byte 3

+ Data Byte 2 + Data Byte 1). The first two transmitted bits (MSB, MSB-1) contain the

Operation Code which represents the instruction which will be performed. The following 6 bits (MSB-2 to MSB-7) represent the address on which the operation will be performed. The subsequent bytes contain the payload.

Figure 58. SDI Frame

OPCODE

OC1 OC0

MSB

ADDRESS

A5 A4 A3 A2 A1 A0

DATA Byte 3

23 22 21 20 19 18 17 16 time

DATA Byte 2

15 14 13 12 11 10 9 time

DATA Byte 1

8

7 6 5 4 3 2 1 0 time

LSB

GAPG2209151357CFT

OC1

0

0

1

1

Operating Code

The operating code is used to distinguish between different access modes to the registers of the slave device.

OC0

0

1

0

1

Table 75. Operating Codes

Description

Write Operation

Read Operation

Read & Clear Operation

Read Device Information

A Write Operation will lead to a modification of the addressed data by the payload if a write access is allowed (e.g. Control Register, valid data). Beside this a shift out of the content

(data present at Communication Start) of the registers is performed.

A Read Operation shifts out the data present in the addressed register at Communication

Start. The payload data will be ignored and internal data will not be modified. In addition a

Burst Read can be performed.

128/198 DS13220 Rev 5

L99DZ200G

Note:

Note:

Serial Peripheral Interface (SPI)

A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by address, secondly by payload bits set to ‘1’. Beside this a shift out of the content (data present at Communication Start) of the registers is performed.

Status registers that change status during communication could be cleared by the actual

Read & Clear Operation and are neither reported in actual communication nor in the following communications. To avoid a loss of any reported status it is recommended just clear status registers which are already reported in the previous communication (Selective

Bitwise Clear).

Advanced Operation Codes

To provide beside the separate write of all control registers and the bitwise clear of all status registers, two Advanced Operation Codes can be used to set all control registers to the default value and to clear all status registers. A ‘set all control registers to default’ command is performed when an OpCode ‘11’ at address b’111111 is performed.

Please consider that potential device specific write protected registers cannot be cleared with this command as a device Power-on-Reset is needed.

A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.

Data-In Payload

The Payload (Data Byte 1 to Data Byte 3) is the data transferred to the devices with every

SPI communication. The Payload always follows the OpCode and the Address bits. For

Write access the Payload represents the new data written to the addressed register. For

Read & Clear operations the Payload defines which bits of the addressed Status Register will be cleared. In case of a ‘1’ at the corresponding bit position the bit will be cleared.

For a Read Operation the Payload is not used. For functional safety reasons it is recommended to set unused Payload to ‘0’.

SDO Frame

The data-out frame consists of 32-bits (GSB + Data Byte 1 to 3).

The first eight transmitted bits contain device related status information and are latched into the shift register at the time of the Communication Start. These 8-bits are transmitted at every

SPI transaction. The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK edge. This could lead to an inconsistency of data between the GSB and Payload due to different shift register load times. Anyhow, no unwanted Status Register clear should appear, as status information should just be cleared with a dedicated bit clear after.

DS13220 Rev 5 129/198

197

Serial Peripheral Interface (SPI) L99DZ200G

Figure 59. SDO frame

Global Status Byte (GSB)

GSBN RSTB SPIE PLE

MSB

FE DE GW FS time

DATA Byte 3

23 22 21 20 19 18 17 16 time

DATA Byte 2

15 14 13 12 11 10 9 8

Bit 31

GSBN time

DATA Byte 1

7 6 5 4 3 2 1 0 time

LSB

GAPG2209151401CFT

Global Status Byte (GSB)

The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the Status

Registers. Therefore no direct Read & Clear can be performed on these bits inside the GSB.

Bit 30

RSTB

Bit 29

Table 76. Global Status Byte

Bit 28 Bit 27 Bit 26

SPIE PLE FE DE

Bit 25

GW

Bit 24

FS

Global Status Bit Not (GSBN)

The GSBN is a logically NOR combination of Bit 24 to Bit 30. This bit can also be used as

Global Status Flag without starting a complete communication frame as it is present directly after pulling CSN low .

Reset Bit (RSTB)

The RSTB indicates a device reset. In case this bit is set, specific internal Control Registers are set to default and kept in that state until the bit is cleared. The RSTB bit is cleared after a

Read & Clear of all the specific bits in the Status Registers which caused the reset event.

SPI Error (SPIE)

The SPIE is a logical OR combination of errors related to a wrong SPI communication.

Physical Layer Error (PLE)

The PLE is a logical OR combination of errors related to the LIN and HS CAN transceivers.

Functional Error (FE)

The FE is a logical OR combination of errors coming from functional blocks (e.g. High-side overcurrent).

130/198 DS13220 Rev 5

L99DZ200G

5.2.3

Serial Peripheral Interface (SPI)

Device Error (DE)

The DE is a logical OR combination of errors related to device specific blocks (e.g. VS overvoltage, overtemperature).

Global Warning (GW)

The GW is a logical OR combination of warning flags (e.g. thermal warning).

Fail Safe (FS)

The FS bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal errors (e.g. Watchdog failure, Voltage regulator failure).

Data-Out Payload

The Payload (Data Bytes 1 to 3) is the data transferred from the slave device with every SPI communication to the master device. The Payload always follows the OpCode and the address bits of the actual shifted in data (In-frame-Response).

Address Definition

Table 77. Device application acces s

Operating Code

OC1

0

0

1

OC0

0

1

0

RAM Address

3FH

OC1

1

Table 78. Device information read access

Operating Code

OC0

1

Table 79. RAM address range

Description

Configuration Register

Access

R/W

3CH

…

32H

31H

…

Status Register 12

…

Status Register 2

Status Register 1

…

R/C

R/C

R/C

DS13220 Rev 5 131/198

197

Serial Peripheral Interface (SPI)

RAM Address

22H

1DH

…

02H

Table 79. RAM address range (continued)

Description

Control Register 34

Control Register 29

…

Control Register 2

Access

R/W

R/W

R/W

L99DZ200G

ROM Address

…

06H

05H

04H

11H

10H

…

0AH

03H

02H

01H

00H

16H

15H

14H

13H

12H

3FH

3EH

…

20H

Table 80. ROM address range

Description

<Advanced Op.>

<GSB Options>

<SPI CPHA test>

<WD bit pos. 4>

<WD bit pos. 3>

<WD bit pos. 2>

<WD bit pos. 1>

<WD Type 2>

<WD Type 1>

<SPI mode>

<Silicon Ver.>

Access

W

R

R

R

R

R

R

R

R

R

R

<Device No.5>

<Device No.4>

<Device No.3>

<Device No.2>

<Device No.1>

<Device Family>

<Company Code>

R

R

R

R

R

R

R

Information registers

The Device Information Registers can be read by using OpCode ‘11’. After shifting out the

GSB the 8-bit wide payload will be transmitted. By reading Device Information Registers a communication width which is minimum 16-bit plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the SDO.

132/198 DS13220 Rev 5

L99DZ200G Serial Peripheral Interface (SPI)

06H

05H

04H

03H

02H

01H

00H

10H

…

0AH

…

14H

13H

12H

11H

ROM

Address

3FH

3EH

…

20H

16H

15H

Description

<Advanced Op.>

<GSB Options>

<SPI CPHA test>

<WD bit pos. 4>

<WD bit pos. 3>

<WD bit pos. 2>

<WD bit pos. 1>

<WD Type 2>

<WD Type 1>

<SPI mode>

<Silicon Ver.>

<Device No.5>

<Device No.4>

<Device No.3>

<Device No.2>

<Device No.1>

<Device Family>

<Company Code>

Table 81. Information Registers Map

Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

0

0

0

1

0

0 major revision

0 0

1

C0H

7FH

C0H

41H

91H

28H

B0H

0

L99DZ200G: 00H

4BH

46H

42H

55H

01H

00H

0

1

0

0 minor revision

0

1

Device Identification Registers

These registers represent a unique signature to identify the device and silicon version.

<Company Code>: 00H (STMicroelectronics)

<Device Family>: 01H (BCD Power Management)

<Device No. 1>: 55H

<Device No. 2>: 42H

<Device No. 3>: 46H

<Device No. 4>: 4BH

<Device No. 5>: 00H

SPI Modes

By reading out the <SPI Mode> register general information of SPI usage of the Device

Application Registers can be read.

DS13220 Rev 5 133/198

197

Serial Peripheral Interface (SPI)

Bit

BR

7 Bit 6

DL2

Bit

5

DL1

Table 82. SPI Mode Register

Bit 4 Bit 3 Bit 2

DL0 0 0

1 0 1 1 0 0

L99DZ200G

Bit

S1

1 Bit

S0

0

0 0

134/198

<SPI Mode>: B0H (Burst Mode read available, 32 bit, no data consistency check)

SPI Burst Read

Bit 7

0

1

Table 83. Burst Read Bit

Description

BR not available

BR available

Bit 6

DL2

0

0

0

0

1

The SPI Burst Read bit indicates if a burst read operation is implemented. The intention of a

Burst Read is e.g. used to perform a device internal memory dump to the SPI Master.

The start of the Burst Read is like a normal Read Operation. The difference is, that after the

SPI Data Length the CSN is not pulled high and the SCK will be continuously clocked. When the normal SCK max count is reached (SPI Data Length) the consecutive addressed data will be latched into the shift register. This procedure is performed every time when the SCK payload length is reached.

In case the automatic incremented address is not used by the device, undefined data is shifted out. An automatic address overflow is implemented when address 3FH is reached.

The SPI Burst Read is limited by the CSN low timeout.

SPI Data Length

The SPI Data Length value indicates the length of the SCK count monitor which is running for all accesses to the Device Application Registers. In case a communication frame with an

SCK count not equal to the reported one will lead to a SPI Error, the data will be rejected.

Table 84. SPI Data Length

Bit 5 Bit 4

DL1

0

0

1

1

DL0

0

1

0

1

1 1 invalid

16-bit SPI

24-bit SPI

32-bit SPI

…

64-bit SPI

Description

DS13220 Rev 5

L99DZ200G Serial Peripheral Interface (SPI)

Bit 1

S1

0

0

1

1

Data Consistency Check (Parity/CRC)

Table 85. Data Consistency Check

Bit 0

1

0

S0

0

1 not used

Parity used

CRC used

Invalid

Description

Watchdog Definition

In case a watchdog is implemented the default settings can be read out via the Device

Information Registers .

<WD Type 1/2>

Bit 7

WD1

0

Table 86. WD Type/Timing

Bit 6 Bit 5 Bit 4 Bit 3

WD0

0

Bit 2

Register is not used

Bit 1 Bit 0

<WD Type 1> 0 1

1

<WD Type 2> 1

1

0

0

WT5

1

WT4

0

WT3

1

WT2

0

WT1

0

Watchdog Timeout / Long Open Window WT[5:0] * 5ms

WT0

0

OW2

0

OW1

1

OW0

0

Open Window OW[2:0] * 5ms

CW2

0

CW1

0

CW0

1

Closed Window CW[2:0] * 5ms

<WD Type 1/2> 1 1 Invalid

<WD Type 1>: 28H (Long Open Window: 200 ms)

<WD Type 2>: 91H (Open Window. 10 ms, Closed Window: 5 ms)

<WD Type 1> indicates the Long Open Window (timeout) which is opened at the start of the watchdog. The binary value of WT[5:0] times 5 ms indicates the typical value of the Timeout

Time.

<WD Type 2> describes the default timing of the window watchdog.

The binary value of CW[2:0] times 5 ms defines the typical Closed Window time and OW[2:0] times 5 ms defines the typical Open Window time.

DS13220 Rev 5 135/198

197

Serial Peripheral Interface (SPI) L99DZ200G t

= correct trigger timing

= early trigger timing

= missing trigger

LOW t

CW t

OW t

CW t

CW t

OW

Figure 60. Window watchdog operation t

OW t

LOW t

CW t

LOW t

CW

= long open window

= closed window t

OW t

OWF

= open window

= t

CW

+ t

OW

= open window fail t

OWF t

LOW

WD-

Trigger normal operation missing trigger early write

GAPG2708150909CFT

The watchdog trigger bit location is defined by the <WD bit pos. X> registers.

<WD bit pos. X>

Bit 7

WB1

0

Bit 6

Table 87. WD bit position

Bit 5 Bit 4 Bit 3

WB0

0

Bit 2

Register is not used

Bit 1

<WD bit pos. X>

<WD bit pos. 1>

<WD bit pos. 3>

<WD bit pos. X>

0

0

0

1

1

1

1

0 time

Bit 0

WBA5

0

1

WBA4

0

1

WBA3

0

1

WBA2

0

1

WBA1

0

1

Defines the register addresses of the WD trigger bits

WBA0

1

1

WBA5 WBA4 WBA3 WBA2 WBA1 WBA0

Defines the stop address of the address range (previous

<WD bit pos. X> is a WB = ‘01’). The consecutive <WD bit pos. X> has to be a WB = ‘11’

<WD bit pos. X>

<WD bit pos. 2>

<WD bit pos. 4>

1

1

1

1

1

1

0 WBP 4 WBP3 WBP2 WBP1 WBP0

0 0 0 0 0 0

0 0 0 0 0 0

Defines the binary bit position of the WD trigger bit within the register

136/198 DS13220 Rev 5

L99DZ200G

5.2.4

Serial Peripheral Interface (SPI)

< WD bit pos 1>: 41H; watchdog trigger bit located at address 01H ( CR1 )

<WD bit pos 2>: C0H; watchdog trigger bit location is bit0

<WD bit pos 3>: 7FH; watchdog trigger bit located at address 3FH (Config Register)

<WD bit pos 4>: C0H; watchdog trigger bit location is bit0

Device Application Registers (RAM)

The Device Application Registers are all registers accessible using OpCode ‘00’, ‘01’ and

‘10’. The functions of these registers are defined in the device specification.

Protocol Failure Detection

To realize a protocol which covers certain failsafe requirements a basic set of failure detection mechanisms are implemented.

Clock monitor

During communication (CSN low to high phase) a clock monitor counts the valid SCK clock edges. If the SCK edges do not correlate with the SPI Data Length an SPIE is reported with the next command and the actual communication is rejected.

By accessing the Device Information Registers (OpCode = ‘11’) the Clock Monitor is set to a minimum of 16 SCK edges plus a multiple by 8 (e.g. 16, 25, 32 …). Providing no SCK edge during a CSN low to high phase is not recognized as an SPIE. For a SPI Burst Read also the

SPI Data Length plus multiple numbers of Payloads SCK edges are assumed as a valid communication.

SCK Polarity (CPOL) check

To detect the wrong polarity access via SCK the internal Clock monitor is used. Providing first a negative edge on SCK during communication (CSN low to high phase) or a positive edge at last will lead to an SPI Error reported in the next communication and the actual data is rejected.

SCK Phase (CPHA) check

To verify, that the SCK Phase of the SPI master is set correctly a special Device Information

Register is implemented. By reading this register the data must be 55H. In case AAH is read the CPHA setting of the SPI master is wrong and a proper communication cannot be guaranteed.

CSN timeout

By pulling CSN low the SDO is set active and leaves its 3-state condition. To ensure communication between other SPI devices within the same bus even in case of CSN stuck at low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After timer end is reached the actual communication is rejected and the SDO is set to 3-state condition.

SDI stuck at GND

As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be distinguished between a valid command and a SDI stuck at GND this communication is not

DS13220 Rev 5 137/198

197

Serial Peripheral Interface (SPI) L99DZ200G allowed. Nevertheless, in case a stuck at GND is detected the communication will be rejected and the SPIE will be set with the next communication.

SDI stuck at HIGH

As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be distinguished between a valid command and a SDI stuck at HIGH this communication is not allowed. In case a stuck at HIGH is detected the communication will be rejected and the

SPIE will be set with the next communication.

SDO stuck @

The SDO stuck at GND and stuck at HIGH has to be detected by the SPI master. As the definition of the GSB guarantees at least one toggle, a GSB with all-‘0’ or all –‘1’ reports a stuck at error.

138/198 DS13220 Rev 5

L99DZ200G

6 Application

Figure 61. Typical application diagram

Application

DS13220 Rev 5 139/198

197

SPI registers

7 SPI registers

7.1

Bit 31

1 (R)

GSBN

Global

Status Bit

Inverted

Global Status Byte GSB

Bit 30

0 (R)

RSTB

Reset

Table 88. Global Status Byte (GSB)

Global Status Byte GSB

Bit 29

0 (R)

SPIE

SPI Error

Bit 28

0 (R)

PLE

Physical

Layer Error

(CAN,LIN)

Bit 27

0 (R)

FE

Bit 26

0 (R)

DE

Functional

Error

Device Error

Bit 25

0 (R)

GW

Global

Warning

L99DZ200G

Bit 24

0 (R)

FS

Fail Safe

Bit

31

30

29

Name

GSBN

RSTB

SPIE

(2)

Table 89. Global Status Byte (GSB) description

Description

Global Status Bit Inverted 

The GSBN is a logically NOR combination of GSB Bits 24 to Bit 30

(1)

.

This bit can also be used as Global Status Flag without starting a complete communication frame as it is present at SDO directly after pulling CSN low.

0: error detected (1 or several GSB bits from 24 to 30 are set)

1: no error detected (default after Power-on)

Specific failures may be masked in the Configuration Register 0x3F. A masked failure will still be reported in the GSB by the related failure flag, however it is not reflected in the GSBN (bit

31).

Reset 

The RSTB indicates a device reset and it is set in case of the following events:

– VPOR (SR1 - 0x31)

– WDFAIL (SR1 - 0x31)

– V1UV (SR1 - 0x31)

– FORCED_SLEEP_TSD2/V1SC (SR1 - 0x31)

0: no reset signal has been generated (default)

1: Reset signal has been generated

RSTB is cleared by a

Read & Clear command to all bits in

Status Register 1 causing the Reset event.

SPI Error Bit 

The SPIE indicates errors related to a wrong SPI communication.

– SPI_INV_CMD (SR2 - 0x32)

– SPI_SCK_CNT (SR2 - 0x32)

The bit is also set in case of an SPI CSN Time-out detection

0: no error (default)

1: error detected

SPIE is cleared by a valid SPI command.

140/198 DS13220 Rev 5

L99DZ200G

Bit

28

27

SPI registers

Name

PLE

(2)

FE

Table 89. Global Status Byte (GSB) description (continued)

Description

Physical Layer Error

The PLE is a logical OR combination of errors related to the LIN and CAN transceivers.

– LIN_PERM_DOM (SR2 - 0x32)

– LIN_TXD_DOM (SR2 - 0x32)

– LIN_PERM_REC (SR2 - 0x32)

– CAN_RXD_REC (SR2 - 0x32)

– CAN_PERM_REC (SR2 - 0x32)

– CAN_PERM_DOM (SR2 - 0x32)

– CAN_TXD_DOM (SR2 - 0x32)

– SYSERR (SR12 - 0x3C)

– FDERR (SR12 - 0x3C)

0: no error (default) 1: error detected

PLE is cleared by a Read & Clear command to all related bits in Status Registers 2 and 12.

Functional Error Bit 

The FE is a logical OR combination of errors coming from functional blocks.

– V2SC (SR2 - 0x32)

– DSMON_HSx_y (x = 1, 2 and y = A, B) (SR2 - 0x32 and SR3 – 0x33)

– DSMON_LSx_y (x = 1, 2 and y = A, B) (SR2 - 0x32 and SR3 – 0x33)

– OUTx_HS_OC_TH_EX (x = 1, 2, 3, 6) (SR3 - 0x33)

– OUTx_LS_OC_TH_EX (x = 1, 2, 3, 6) (SR3 - 0x33)

– OUTx_OC_TH_EX (x = 7, 8, 15) (SR3 - 0x33)

– OUTx_OC_STAT (x = 9, 10, 13, 14) (SR3 - 0x33)

– LSy_FSO_OC (y= a, b) (SR3 - 0x33)

– OUTx_HS_SHORT (x = 1, 2, 3, 6) (SR4 - 0x34)

(3)

– OUTx_LS_SHORT (x = 1, 2, 3, 6) (SR4 - 0x34)

(3)

– ECV_OC (SR5 - 0x35)

– DSMON_HEAT (SR5 - 0x35)

– OUTx_HS_OL (x = 1, 2, 3, 6) (SR5 - 0x35) (4)

– OUTx_LS_OL (x = 1, 2, 3, 6) (SR5 - 0x35)

– OUTx_OL_STAT (x = 7, 8, 9,10, 13, 14, 15) (SR5 - 0x35)

– GH_OL (SR5 - 0x35)

– ECV_OL (SR5 - 0x35)

0: no error (default)

1: error detected

FE is cleared by a Read & Clear command to all related bits in Status Registers 2, 3, 4, 5

DS13220 Rev 5 141/198

197

SPI registers L99DZ200G

Bit Name

Table 89. Global Status Byte (GSB) description (continued)

Description

26

25

24

DE

GW

FS

(2)

Device Error Bit 

DE is a logical OR combination of global errors related to the device.

– VS_OV (SR2 - 0x32)

– VS_UV (SR2 - 0x32)

– VSREG_OV (SR2 - 0x32)

– VSREG_UV (SR2 - 0x32)

– CP_LOW (SR2 - 0x32)

– TSD1_CLx (SR6 - 0x36)

0: no error (default)

1: error detected

DE is cleared by a Read & Clear command to all related bits in Status Registers 2 and 6

Global Warning Bit 

GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions.

– VSREG_EW (SR2 - 0x32)

– V1_FAIL (SR2 - 0x32)

– V2_FAIL (SR2 - 0x32)

– CAN_SUP_LOW (SR2 - 0x32)

– TW (3) (SR2 - 0x32)

– SPI_INV_CMD (SR2 - 0x32)

– SPI_SCK_CNT (SR2 - 0x32)

0: no error (default)

1: error detected

GW is cleared by a Read & Clear command to all related bits in Status Register 2.

Fail Safe 

The FS bit indicates the device was forced into a safe state due to the following failure conditions:

– WDFAIL (SR1 - 0x31)

– V1UV (SR1 - 0x31)

– TSD2 (SR1 - 0x31)

– FORCED_SLEEP_TSD/V1SC (SR1 - 0x31) or SGND_LOSS (SR1 – 0x31)

All Control Registers are set to default

Control Registers are blocked for WRITE access except the following bits:

– TRIG (CR1 - 0x01)

– V2_0 (CR1 - 0x01)

– V2_1 (CR1 - 0x01)

– GoTRXRDY (CR1 - 0x01)

– Timer settings (bits 8…23) (CR2 - 0x02)

– OUT15_x (bits 0…3) (CR6 - 0x06)

– CR12 (0x0C) to CR17 (0x11); PWM frequency and duty cycles

0: Fail Safe inactive (default)

1: Fail Safe active

FS is cleared upon exit from Fail-Safe mode (refer to chapter ‘Fail-Safe mode’)

1. Individual failure flags may be masked in the Configuration Register (0x3F).

2. Bit may be masked in the Configuration Register (0x3F), i.e. the bit will not be included in the Global Status Bit (GSB).

142/198 DS13220 Rev 5

L99DZ200G SPI registers

3. The detection of this error does not set the GSBN.

4. Open load status flags may be masked in the Configuration register (0x3F), i.e. the open load flag will be included in the FE flag, but will not set the GSB. TW failure status flags may be masked in the Configuration register (0x3F), i.e. the TW flag will be included in the GW flag, but will not set the GSB .

DS13220 Rev 5 143/198

197

7.2 Control register overview

Table 90. Control register overview

29 28 27 Bit

Global Status

Control Register

Addr.

0x00

0x01

0x02

0x03

CR1

CR2

CR3 bits

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

31

GSBN

23

15

7

30

RSTB

22

14

6

SPIE

21

13

5

PLE

20

12

4

FE

19

11

3

Reserved

Reserved

Reserved

RES WU_EN

TIMER_NINT_

WAKE_SEL

TIMER_NINT_EN

HENA HENB

T1_RESTART T1_DIR

T2_RESTART T2_DIR

LIN_REC_ON

LY

LIN_TXD_TOUT_E

N

VSREG_LOCK

_EN

VS_LOCK_EN

RES

LIN_WU_EN

V2_1

T1_ON_2

T2_ON_2

CAN_LOOP_EN

VSREG_OV_

SD_EN

WU_PU

CAN_WU_EN

V2_0

T1_ON_1

T2_ON_1

PNW_EN

VSREG_UV_SD

_EN

RES

RES

CANTO_IRQ_EN

PARITY

T1_ON_0

T2_ON_0

V1_RESET_1

VS_OV_SD_EN

RES RES RES RES

VSREG_EWT

H_7

VSREG_EWTH_6 VSREG_EWTH_5 VSREG_EWTH_4 VSREG_EWTH_3

26

DE

18

10

2

RES

CAN_RXEN

STBY_SEL

T1_PER_2

T2_PER_2

V1_RESET_0

25

GW

17

9

1

WU_FILT_1

CAN_TXEN

GO_STBY

T1_PER_1

T2_PER_1

WD_TIME_1

24

FS

16

8

0

WU_FILT_0

CAN_GO_TRX_

RDY

TRIG

T1_PER_0

T2_PER_0

WD_TIME_0

VS_UV_SD_EN RES RES

RES VSREG_EWTH_9

VSREG_EWTH_

8

VSREG_EWTH_2 VSREG_EWTH_1

VSREG_EWTH_

0

Mode

R

R/W

R/W

R/W

0x04 CR4

0x05 CR5

0x06 CR6

0x07 CR7

0x08 CR8

0x09 CR9

0x0A

CR1

0

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

Table 90. Control register overview (continued)

OUT1_HS OUT1_LS RES RES RES

RES

RES

OUT7_3

RES

RES

OUT9_3

OUT14_3

RES

OUT1_OCR

RES

RES

RES

RES

OUT7_2

RES

RES

OUT9_2

OUT14_2

RES

OUT2_OCR

RES

OUT3_HS

RES

OUT7_1

RES

RES

OUT9_1

OUT14_1

RES

OUT3_OCR

RES

OUT3_LS

RES

OUT7_0

RES

GH

OUT9_0

OUT14_0

RES

OUT6_OCR

RES

RES

OUT8_3

OUT10_3

RES

OUT13_3

OUT15_3

RES

OUT7_OCR

RES

RES

OUT8_2

OUT10_2

RES

OUT13_2

OUT15_2

RES

OUT8_OCR

OUT2_HS

RES

OUT6_HS

OUT8_1

OUT10_1

RES

OUT13_1

OUT15_1

RES

OUT15_OCR

OUT1_SHORT_DIS OUT2_SHORT_DIS OUT3_SHORT_DIS OUT6_SHORT_DIS

OUT2_LS

RES

OUT6_LS

OUT8_0

OUT10_0

RES

OUT13_0

OUT15_0

RES

RES

RES

RES RES CM_DIR_CONF_1 CM_DIR_CONF_0 CM_SEL_3 CM_SEL_2 CM_SEL_1 CM_SEL_0

OUT1_OCR_T

HX_EN

OUT2_OCR_THX_

EN

OUT3_OCR_THX_

EN

OUT6_OCR_THX_

EN

OUT7_OCR_THX_E

N

OUT8_OCR_THX_E

N

OUT15_OCR_THX_

EN

RES

OUT7_OCR_T

ON_1

OUT7_OCR_TON_

0

OUT8_OCR_TON_

1

OUT8_OCR_TON_

0

OUT15_OCR_TON_

1

OUT15_OCR_TON_

0

OUTHB_OCR_TON

_1

OUTHB_OCR_T

ON_0

OUT7_OCR_F

REQ_1

OUT7_OCR_FREQ

_0

OUT8_OCR_FREQ

_1

OUT8_OCR_FREQ

_0

OUT15_OCR_FREQ

_1

OUT15_OCR_FREQ

_0

OUTHB_OCR_FRE

Q_1

OUTHB_OCR_F

REQ_0

OUT8_RDSO

N

OUT7_RDSON OUT1_6_RDSON OUT9_CCM_EN OUT8_CCM_EN OUT7_CCM_EN RES RES

RES OUT15_OL OUT14_OL OUT13_OL RES RES OUT10_OL OUT9_OL

RES

DIAG_2_A

SD2A

H_OLTH_HIG

H_A

OUT15_OC

DIAG_1_A

SDS2A

OL_H1L2_A

OUT14_OC

DIAG_0_A

SD1A

OL_H2L1_A

OUT13_OC

DIRHA

SDS1A

SLEW_4_A

RES

SD2B

COPT_3_A

SLEW_3_A

RES

SDS2B

COPT_2_A

SLEW_2_A

OUT10_OC

SD1B

COPT_1_A

SLEW_1_A

OUT9_OC

SDS1B

COPT_0_A

SLEW_0_A

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x0B

CR1

1

0x0C

CR1

2

0x0D

CR1

3

0x0E

CR1

4

0x0F

CR1

5

0x10

CR1

6

0x11

CR

17

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

Table 90. Control register overview (continued)

RES RES RES RES RES RES

GH_TH_1

RES

PMW1_FREQ

_1

PMW5_FREQ

_1

RES

RES

GH_TH_0

RES

PMW1_FREQ_0

PMW5_FREQ_0

RES

RES

PWM1_DC_3

PWM2_DC_7

RES

PWM3_DC_3

PWM4_DC_7

RES

PWM5_DC_3

PWM6_DC_7

PWM1_DC_2

PWM2_DC_6

RES

PWM3_DC_2

PWM4_DC_6

RES

PWM5_DC_2

PWM6_DC_6

ECV_LS

EC_5

PMW2_FREQ_1

PMW6_FREQ_1

RES

PWM1_DC_9

PWM1_DC_1

PWM2_DC_5

PWM3_DC_9

PWM3_DC_1

PWM4_DC_5

PWM5_DC_9

PWM5_DC_1

PWM6_DC_5

RES

PWM7_DC_3

RES

RES

RES

PWM7_DC_2

PWM7_DC_9

PWM7_DC_1

RES

OUT7_AUTOCOMP

_EN

RES

OUT7_VLED_9

OUT7_VLED_

3

OUT8_VLED_

7

OUT7_VLED_2

OUT8_VLED_6

OUT7_VLED_1

OUT8_VLED_5

ECV_OCR

EC_4

PMW2_FREQ_0

PMW6_FREQ_0

RES

PWM1_DC_8

PWM1_DC_0

PWM2_DC_4

PWM3_DC_8

PWM3_DC_0

PWM4_DC_4

PWM5_DC_8

PWM5_DC_0

PWM6_DC_4

PWM7_DC_8

PWM7_DC_0

RES

OUT7_VLED_8

OUT7_VLED_0

OUT8_VLED_4

RES

EC_3

PMW3_FREQ_1

PMW7_FREQ_1

RES

PWM1_DC_7

RES

PWM2_DC_3

PWM3_DC_7

RES

PWM4_DC_3

PWM5_DC_7

RES

PWM6_DC_3

PWM7_DC_7

RES

RES

OUT7_VLED_7

RES

OUT8_VLED_3

RES

EC_2

PMW3_FREQ_0

PMW7_FREQ_0

RES

PWM1_DC_6

RES

PWM2_DC_2

PWM3_DC_6

RES

PWM4_DC_2

PWM5_DC_6

RES

PWM6_DC_2

PWM7_DC_6

RES

RES

OUT7_VLED_6

OUT8_AUTOCOMP

_EN

OUT8_VLED_2

GH_OL_EN

RES

EC_1

GH_TH_2

ECON

EC_0

PMW4_FREQ_1 PMW4_FREQ_0

RES

RES

PWM1_DC_5

PWM2_DC_9

PWM2_DC_1

PWM3_DC_5

PWM4_DC_9

PWM4_DC_1

PWM5_DC_5

PWM6_DC_9

PWM6_DC_1

PWM7_DC_5

RES

RES

OUT7_VLED_5

OUT8_VLED_9

OUT8_VLED_1

RES

RES

PWM1_DC_4

PWM2_DC_8

PWM2_DC_0

PWM3_DC_4

PWM4_DC_8

PWM4_DC_0

PWM5_DC_4

PWM6_DC_8

PWM6_DC_0

PWM7_DC_4

RES

RES

OUT7_VLED_4

OUT8_VLED_8

OUT8_VLED_0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x12

CR

18

0x13

CR

19

0x14

CR

20

0x15

CR

21

0x16

CR

22

0x3F

Con f

Reg

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

Table 90. Control register overview (continued)

RES

RES

OUT9_AUTOCOMP

_EN

OUT9_VLED_

3

OUT10_VLED

_7

OUT9_VLED_2

OUT10_VLED_6

OUT9_VLED_9

OUT9_VLED_1

OUT10_VLED_5

OUT13_AUTOCOM

P_EN

OUT13_VLED_9

OUT9_VLED_8

OUT9_VLED_0

OUT10_VLED_4

OUT13_VLED_8

OUT9_VLED_7

RES

OUT10_VLED_3

OUT13_VLED_7

OUT9_VLED_6

OUT10_AUTOCOM

P_EN

OUT10_VLED_2

OUT13_VLED_6

OUT13_VLED

_3

OUT14_VLED

_7

OUT13_VLED_2

OUT14_VLED_6

OUT13_VLED_1

OUT14_VLED_5

OUT13_VLED_0

OUT14_VLED_4

RES

OUT14_VLED_3

OUT14_AUTOCOM

P_EN

OUT14_VLED_2

RES

OUT15_AUTOCOM

P_EN

OUT15_VLED_9 OUT15_VLED_8 OUT15_VLED_7 OUT15_VLED_6

OUT15_VLED

_3

RES

OUT15_VLED_2

RES

OUT15_VLED_1

RES

OUT15_VLED_0

RES

RES

RES

RES

RES

DIAG_2_B DIAG_1_B DIAG_0_B DIRHB RES RES

OUT9_VLED_5 OUT9_VLED_4

OUT10_VLED_9 OUT10_VLED_8

OUT10_VLED_1 OUT10_VLED_0

OUT13_VLED_5 OUT13_VLED_4

OUT14_VLED_9 OUT14_VLED_8

OUT14_VLED_1 OUT14_VLED_0

OUT15_VLED_5 OUT15_VLED_4

RES

RES

RES

RES

RES

RES

RES RES RES COPT_3_B COPT_2_B COPT_1_B COPT_0_B RES

H_OLTH_HIG

H_B

RES

RES

RES

OL_H1L2_B

RES

RES

RES

OL_H2L1_B

RES

RES

RES

SLEW_4_B

RES

RES

GENERATOR_MO

DE_EN

SLEW_3_B

RES

RES

DEBUG_EXIT

SLEW_2_B

RES

RES

CP_OFF

SLEW_1_B

RES

RES

ICMP

SLEW_0_B

RES

RES

WD_EN

WU_CONFIG LIN_WU_CONFIG LIN_HS_EN TSD_CONFIG ECV_HV V2_CONFIG ICMP_CONFIG_EN

WD_CONFIG_E

N

MASK_OL_HS

1

MASK_OL_LS1 MASK_TW

CP_OFF_EN CP_LOW_CONFIG CP_DITH_DIS RES

MASK_EC_OL

FS_FORCED

MASK_OL

RES

MASK_SPIE

DMA

MASK_PLE

DMB

MASK_GW

TRIG

R/W

R/W

R/W

R/W

R/W

R/W

7.3 Status register overview

29

Table 91. Status register overview

28 27

Global Status

Status Register

Addr.

0x31

0x32

0x33

0x34

0x35

SR1

SR2

SR3

SR4

SR5 bit bits

MSB

LSB

31

GSBN

23

15

7

VS_OV_WAKEUP

V1UV

30

RSTB

22

14

6

WU_STATE

SPIE

21

13

5

SGND_LOSS

PLE

20

12

4

WU_WAKE

FE

19

11

3

WAKE_CAN

V1_ RESTART_2 V1_ RESTART_1 V1_ RESTART_0 WDFAIL_ CNT_3

26

DE

18

10

2

WAKE_LIN

WDFAIL_

CNT_2

25

GW

17

9

1

WAKE_TIMER

WDFAIL_ CNT_1

24

FS

16

8

0

DEBUG_ACTIVE

WDFAIL_

CNT_0

LSB

DEVICE_

STATE_1

DEVICE_

STATE_0

TSD2 TSD1

FORCED_

SLEEP_WD

WDFAIL VPOR

MSB

LSB

MSB

LIN_PERM_ DOM LIN_TXD_DOM LIN_PERM_ REC CAN_RXD _REC

CAN_PERM

_REC

SPI_INV_CMD

CAN_PERM

_DOM

SPI_SCK_CNT

CAN_TXD _DOM CAN_SUP_LOW

DSMON_HS2_A DSMON_HS1_A DSMON_LS2_A DSMON_LS1_A CP_LOW TW

V2SC V2FAIL V1FAIL VSREG_EW VSREG_OV VSREG_UV VS_OV

OUT1_HS_OC_T

H_EX

OUT1_LS_OC_TH

_EX

OUT2_HS_OC_T

H_EX

OUT2_LS_OC_T

H_EX

OUT3_HS_OC_T

H_EX

OUT3_LS_OC_TH

_EX

OUT6_HS_OC_TH_

EX

VS_UV

OUT6_LS_OC_TH_EX

OUT7_OC_TH_E

X

OUT8_OC_TH_E

X

OUT9_OC_STAT

OUT10_OC_STA

T

OUT13_OC_STAT OUT14_OC_STAT OUT15_OC_TH_EX RES

LSB

FORCED_

SLEEP_

TSD2/V1SC

MSB

LSB

RES DSMON_HS2_B DSMON_HS1_B DSMON_LS2_B DSMON_LS1_B RES LSB_FSO_OC LSA_FSO_OC

OUT1_HS_OCR_

ALERT

OUT1_LS_OCR_A

LERT

OUT2_HS_OCR_

ALERT

OUT2_LS_OCR_

ALERT

OUT3_HS_OCR_

ALERT

OUT3_LS_OCR_A

LERT

OUT6_HS_OCR_AL

ERT

OUT6_LS_OCR_ALERT

OUT7_OCR_ALE

RT

OUT8_OCR_ALE

RT

OUT15_OCR_AL

ERT

RES RES RES RES

OUT1_HS_SHOR

T

OUT1_LS_SHORT

OUT2_HS_SHO

RT

OUT2_LS_SHOR

T

OUT3_HS_SHOR

T

OUT3_LS_SHORT OUT6_HS_SHORT

RES

OUT6_LS_SHORT

MSB OUT1_HS_OL OUT1_LS_OL OUT2_HS_OL OUT2_LS_OL OUT3_HS_OL OUT3_LS_OL OUT6_HS_OL

OUT7_OL_STAT OUT8_OL_STAT OUT9_OL_STAT OUT10_OL_STAT OUT13_OL_STAT OUT14_OL_STAT OUT15_OL_STAT

ECV_OL RES RES RES RES RES DSMON_HEAT

OUT6_LS_OL

GH_OL

ECV_OC

Mode

R

R

R

R

R

R

0x36

0x37

0x38

0x39

SR6

SR7

SR8

SR9

0x3A SR10

0x3B SR11

0x3C SR12

MSB

WD_TIMER_STATE_

1

WD_TIMER_STATE_

0

RES RES

LSB

MSB

RES

RES

TEMP_CL2_3

RES

RES

TEMP_CL2_2

LSB

MSB

TEMP_CL1_7

RES

TEMP_CL1_6

RES

TEMP_CL4_3

TEMP_CL3_7

TEMP_CL4_2

TEMP_CL3_6 LSB

MSB RES RES

LSB

TEMP_CL6_3

TEMP_CL5_7

TEMP_CL6_2

TEMP_CL5_6

RES RES

VSREG_3

RES

RES

VS_3

VWU_7

RES

RES

RES

VSREG_2

RES

RES

VS_2

VWU_6

RES

RES

RES

Table 91. Status register overview (continued)

RES RES RES RES

TEMP_CL6_1

TEMP_CL5_5

VSREG_9

VSREG_1

RES

VS_9

VS_1

VWU_5

RES

RES

CAN_SILENT

TW_CL6

TSD1_CL6

TEMP_CL2_9

TEMP_CL2_1

TEMP_CL1_5

TEMP_CL4_9

TEMP_CL4_1

TEMP_CL3_5

TEMP_CL6_9

TEMP_CL6_0

TEMP_CL5_4

VSREG_8

VSREG_0

RES

VS_8

VS_0

VWU_4

RES

RES

RES

TW_CL5

TSD1_CL5

TEMP_CL2_8

TEMP_CL2_0

TEMP_CL1_4

TEMP_CL4_8

TEMP_CL4_0

TEMP_CL3_4

TEMP_CL6_8

RES

TEMP_CL5_3

VSREG_7

RES

RES

VS_7

RES

VWU_3

RES

RES

CANTO

TW_CL4

TSD1_CL4

TEMP_CL2_7

RES

TEMP_CL1_3

TEMP_CL4_7

RES

TEMP_CL3_3

TEMP_CL6_7

RES

TEMP_CL5_2

VSREG_6

RES

RES

VS_6

RES

VWU_2

RES

RES

WUP

TW_CL3

TSD1_CL3

TEMP_CL2_6

RES

TEMP_CL1_2

TEMP_CL4_6

RES

TEMP_CL3_2

TEMP_CL6_6

ECV_VNR

TEMP_CL5_9

TEMP_CL5_1

VSREG_5

RES

RES

VS_5

VWU_9

VWU_1

RES

RES

RES

TW_CL2

TSD1_CL2

TEMP_CL2_5

TEMP_CL1_9

TEMP_CL1_1

TEMP_CL4_5

TEMP_CL3_9

TEMP_CL3_1

TEMP_CL6_5

ECV_VHI

TEMP_CL5_8

TEMP_CL5_0

VSREG_4

RES

RES

VS_4

VWU_8

VWU_0

RES

RES

RES

TW_CL1

TSD1_CL1

TEMP_CL2_4

TEMP_CL1_8

TEMP_CL1_0

TEMP_CL4_4

TEMP_CL3_8

TEMP_CL3_0

TEMP_CL6_4

R

R

R

R

R

R

SPI registers

7.4

7.4.1

L99DZ200G

Control registers

Control Register CR1 (0x01)

Figure 62. Control Register CR1

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0

Access R

R/

W

R

R/

W

R R/W

1. Either LIN or CAN must be enabled as wake-up source. Setting both bits 12 and 13 to '0' is an invalid setting; in this case, both bits, WU_EN (bit 22 in CR1) will be set to '1' (wake-up enabled; default) and the SPI Error Bit (SPIE) in the Global Status

Byte will be set.

Bit

23

22

21

20

19:18

17

16

15

Name

Reserved

WU_EN

Reserved

WU_PU

Table 92. CR1 signals description

Description

—

Wake-up Input 1 (WU) enable (1)

0: WU disabled

1: WU enabled (default)

—

Wake-up Input1 Pull-up/down configuration: configuration of internal current

source

(1)

0: pull-down (default)

1: pull-up

--Reserved

WU_FILT_1

WU_FILT_0

Wake-up Input1 Filter configuration Bits: configuration of input filter

Table 93: Wake-up input1 filter configuration

(1)

See

TIMER_NINT_WAKE_SEL

Select Timer for NINT / Wake: select timer for periodic interrupt in standby modes

0: Timer 2 (default)

1: Timer 1

150/198 DS13220 Rev 5

L99DZ200G

Bit

14

13

12

11

5

4

10

9

8

7

6

SPI registers

Name

LIN_WU_EN

(2)

CAN_WU_EN

(2)

CAN_ RXEN

CAN_TXEN

HENA

HENB

V2_1

V2_0

Table 92. CR1 signals description (continued)

Description

TIMER_NINT_EN

CANTO_IRQ_EN

CAN_GO_TRX_RDY

Timer NINT enable: enable timer interrupt in standby modes

0: timer interrupt disabled (default)

1: timer interrupt enabled

V1_Standby mode: periodic NINT pulse generated by timer (NINT pulse at start of timer on-phase)

VBAT_Standby mode: device wakes up after timer expiration and generates

NReset

LIN Wake-up enable: enable wake-up by LIN (3)

0: disabled

1: enabled (default)

CAN Wake-up enable: enable wake-up by CAN

(4)

0: disabled

1: enabled (default)

CANTO Interrupt enable: enables interrupt signal in case of CAN timeout

0: CAN TO interrupt disabled

1: CAN TO interrupt enabled (default)

CAN transceiver configuration

See

Table 94: CAN transceiver mode

CAN Transceiver transition into TRX READY mode.

0: CAN transceiver in TRX BIAS mode (default)

1: CAN transceiver is sent into TRX READY mode

At Exit from TRX READY mode, this bit is set to '0' automatically. CAN Flash mode: CAN_GO_TRX_RDY is set to '1' automatically

After power-on, this bit should be set to ’0’ and a clear command should be sent to status registers.

Enable H-bridge A

0: H-bridge A disabled (default)

1: H-bridge A enabled

Enable H-bridge B

0: H-bridge B disabled (default)

1: H-bridge B enabled

Refer to chapter

H-bridge Control for details

Voltage Regulator V2 Configuration

See

Table 95: Voltage regulator V2 configuration

DS13220 Rev 5 151/198

197

SPI registers

Bit

3

2

1

L99DZ200G

Name

PARITY

STBY_SEL

Table 92. CR1 signals description (continued)

Description

GO_STBY

PARITY: Standby Command Parity Bit STBY SEL: Select Standby mode

GO_STBY: Execute transition into Standby mode

The STBY_SEL and GO_STBY bits are protected by a parity check.

The bits STBY_SEL, GO_STBY and PARITY must represent an even number of '1', otherwise the command is ignored and the SPI_INV_CMD bit is set.

Table 96: Standby transition configuration

shows the valid settings. All other settings are invalid; command will be ignored and SPI_INV_CMD will be set.

The GO_STBY bit is not cleared automatically after wake-up.

0 TRIG Watchdog Trigger Bit

1. Setting is only valid if input is configured as wake-up input in Configuration Register (0x3F).

2. Either LIN or CAN must be enabled as wake-up source. Setting both bits 12 and 13 to '0' is an invalid setting. In this case, both bits will be set to '1' (wake-up enabled; default) and the SPI Error Bit (SPIE) in the Global Status Byte will be set.

3. The wake-up behavior is configurable in the Configuration Register (0x3F).

4. Wake-up occurs at a wake –up event according to ISO 11898-5:2007.

WU_FILT_1

0

0

1

1

WU_FILT_0

Table 93. Wake-up input1 filter configuration

Description

0

1

0

1

Wake-up inputs monitored in static mode (filter time t

WU_stat

) (default)

Wake- up inputs monitored in cyclic mode with Timer2 (filter time: t

WU_cyc

; blanking time 80% of timer ON time)

Wake- up inputs monitored in cyclic mode with Timer1 (filter time: t

WU_cyc

; blanking time 80% of timer ON time)

Invalid setting; command will be ignored and SPI_INV_CMD will be set

CAN_RXEN CAN_TXEN

Table 94. CAN transceiver mode

Description

0

0

1

1 x x

0

1

TRX Standby: Receiver disabled, Transmitter disabled

TRX Listen: Receiver enabled, Transmitter disabled

TRX Normal

(1)

: Receiver enabled, Transmitter enabled

1. CAN Flash mode: TRX Normal Mode functionality is configured automatically but SPI registers are not updated.

V2_1

0

0

V2_0

0

1

Table 95. Voltage regulator V2 configuration

Description

V2 OFF in all modes (default)

V2 ON in Active mode; OFF in Standby modes

152/198 DS13220 Rev 5

L99DZ200G

V2_1 V2_0

Table 95. Voltage regulator V2 configuration (continued)

Description

1 0 V2 ON in Active and V1_Standby; OFF in VBAT_Standby mode

1 1 V2 ON in all modes

(1)

1. In VBAT_Standby mode, if V1 is OFF, V2 cannot be a tracker regulator (V2_CONFIG=0 in Config Reg).

SPI registers

PARITY

0

1

0

1

STBY_SEL

1

0

0

1

Table 96. Standby transition configuration

GO_STBY Description

1

1

0

0

Go to V1_Standby

Go to VBAT_Standby

No transition to standby

7.4.2 Control Register CR2 (0x02)

Figure 63. Control Register CR2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

22

21

20

19

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

R/W

Bit

23

Name

T1_RESTART

Table 97. CR2 signals description

Description

Timer 1 Restart: Restart of Timer 1

0: timer is running with period and on-time according to configuration (default)

1: restart of timer at CSN low to high transition; starting with ON phase

(1)

Bit is automatically reset with next SPI frame.

T1_DIR

T1_ON_2

T1_ON_1

T1_ON_0

T1_DIR: Timer 1 Direct Drive by DIR T1_ON_x: Timer 1 On-Time Bits

Configuration of Timer 1 on-time, for details see

Table 98

and Figure 64

DS13220 Rev 5 153/198

197

SPI registers L99DZ200G

11

10

9

14

13

12

Bit

18

17

16

15

8

7

6

5

4

Table 97. CR2 signals description (continued)

Name

T1_PER_2

T1_PER_1

T1_PER_0

T2_RESTART

Description

Configuration of Timer 1 Period

000: T1 (default)

001: T2

010: T3

011: T4

100: T5

101: T6

110: T7

111: T8

Timer 2 Restart: restart of timer 2

0: timer is running with period and on-time according to configuration (default) 1: restart of timer at CSN low to high transition; starting with ON phase (1)

Bit is automatically reset with next SPI frame.

T2_DIR

T2_ON_2

T2_ON_1

T2_ON_0

T2_PER_2

T2_PER_1

T2_DIR: Timer 2 Direct Drive by DIR T2_ON_x: Timer 2 On-Time Bits

Configuration of Timer 2 on-time, for details see

Table 98

and

Figure 64

T2_PER_0

Configuration of Timer 2 Period

000: T1 (default)

001: T2

010: T3

011: T4

100: T5

101: T6

LIN_REC_ONLY

110: T7

111: T8

LIN Transceiver Receive Only mode

0: LIN receive only mode disabled (default) 1: LIN receive only mode enabled

LIN_TXD_TOUT_EN

LIN TxD Timeout Enable

0: LIN TxD timeout detection disabled

1: LIN TxD timeout detection enabled (default)

CAN_LOOP_EN

CAN Loop Enable: CAN Looping of TxD_C to RxD_C 0: CAN looping disabled

(default)

1: CAN looping enabled

PNW_EN

CAN Pretended Networking mode

A WUP leads to transition into TRX Bias mode and an interrupt is generated. 0: pretended networking disabled (default)

1: pretended networking enabled This bit can only be set to '1' if CAN RXEN = 1

154/198 DS13220 Rev 5

L99DZ200G SPI registers

Table 97. CR2 signals description (continued)

Bit

3

2

Name

V1_RESET_1

V1_RESET_0

Description

Voltage Regulator V1 Reset Threshold

(2)

00: Vrt4 (default)

01: Vrt3

10: Vrt2

11: Vrt1 thresholds are monitored in Active mode and V1_Standby mode

1

0

WD_TIME_1

WD_TIME_0

Watchdog Trigger Time 00: TSW1 (default)

01: TSW2

10: TSW3

11: TSW4

Writing to WD_TIME_x is blocked unless WD CONFIG EN = 1.

The modified WD Trigger Time is valid immediately after the Write command (CSN transition low-high).

The watchdog timer is reset when the trigger time is modified (restart at CSN transition low-high).

1. Timer restart behavior:

Write to CR2 when Tx_ON_x and Tx_PERx remain unchanged: 

Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time

Tx_RESTART = 0: write operation to CR2 has no effect on timers

Write to CR2 when Tx_ON_x and Tx_PERx are modified

Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time and according to new setting (ON time and period)

Tx_RESTART = 0: behavior is not defined; if a predictable behavior is needed, it is recommended to set Tx_RESTART = 1

2. When V2 voltage regulator is configured in Tracking mode (V2_CONFIG=1 in Config Reg configured to be the VRT1 (V1_RESET_1=1, V1_RESET_0=1 in CR2).

) , the V1 Reset Threshold shall be

Tx_DIR

0

0

0

0

1

(1)

0

0

0

0

1 (1)

1 (1)

1 (1)

1 (1)

Tx_ON_2

1

1

1

1

0

0

0

0

0

0

0

0

1

Table 98. Configuration of Timer x on-time

Tx_ON_1 Tx_ON_0 Description

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0 ton 1 (default) ton 2 ton 3 ton 4 ton 5

Invalid setting; command will be ignored and

SPI_INV_CMD will be set ton 1 controlled by DIR input signal (logical AND) ton 2 controlled by DIR input signal (logical AND) ton 3 controlled by DIR input signal (logical AND) ton 4 controlled by DIR input signal (logical AND) ton 5 controlled by DIR input signal (logical AND)

DS13220 Rev 5 155/198

197

SPI registers L99DZ200G

Tx_DIR Tx_ON_2

Table 98. Configuration of Timer x on-time (continued)

Tx_ON_1 Tx_ON_0 Description

1 (1)

1 (1)

1 (1)

1

1

1

0

1

1

1

0

1

Invalid setting; command will be ignored and

SPI_INV_CMD will be set

1. Tx_DIR = 1 is only valid for OUT7-8-9-10-13-14-15 control; the DIR signal has no influence for WU monitoring if WU is monitored by timer.

Figure 64. Timer_x controlled by DIR

TxDIR1 = 1

Tx tonx

Timer X

DIR1

OUTx

GAPG2708150914CFT

7.4.3 Control Register CR3 (0x03)

Figure 65. Control Register CR3

23 22 21 20 19 18 17 16 15 14 13 12 11 1 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

156/198 DS13220 Rev 5

L99DZ200G SPI registers

Bit Name

Table 99. CR3 signals description

Description

23 VSREG_LOCK_EN

V

SREG lockout enable: Lockout of V

SREG related outputs after V

SREG overvoltage/ undervoltage shutdown

0: V

SREG related Outputs are turned on automatically and status bits (VSREG_UV,

VSREG_OV) are cleared

1: V

SREG related Outputs remain turned off until status bits (VSREG_UV,

VSREG_OV) are cleared (default)

Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions

22 VS_LOCK_EN

V

S lockout enable: Lockout of V

S related outputs after V

S over/undervoltage shutdown

0: V

S related Outputs

(1)

VS_OV) are cleared

are turned on automatically and status bits (VS_UV,

1: V

S

related Outputs

(1)

remain turned off until status bits (VS_UV, VS_OV) are

cleared (default)

Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions

21 VSREG_OV_SD_EN

V

SREG overvoltage shutdown enable: shutdown of V

SREG related outputs in case of

V

SREG overvoltage

0: no shutdown of V

SREG related outputs in case of V

SREG overvoltage

1: shutdown of V

SREG related outputs in case of V

SREG overvoltage (default)

20 VSREG_UV_SD_EN

V

SREG undervoltage shutdown enable: shutdown of V

SREG related outputs in case of V

SREG undervoltage

0: no shutdown of V

SREG related outputs in case of V

SREG undervoltage

1: shutdown of V

SREG related outputs in case of V

SREG undervoltage (default)

In case of V1 undervoltage due to VSREG_UV, the device enters Fail-Safe mode and the outputs are turned off

19

18

17:10

VS_OV_SD_EN

VS_UV_SD_EN

Reserved

V

S overvoltage shutdown enable: shutdown of V

S related outputs in case of V

S overvoltage

0: no shutdown of V

S related outputs in case of V

S overvoltage if charge pump output voltage is still sufficient (until CPLOW threshold is reached)

1: shutdown of V

S related outputs in case of V

S overvoltage (default)

V

S undervoltage shutdown enable: shutdown of V

S related outputs in case of V

S undervoltage

0: no shutdown of V

S

related Outputs

(1)

in case of V

S undervoltage

1: shutdown of V

S related Outputs

(1)

in case of V

S undervoltage (default)

In case of V1 undervoltage due to VS_UV, the device enters Fail-Safe mode and the outputs are turned off

---

DS13220 Rev 5 157/198

197

SPI registers L99DZ200G

Bit Name

Table 99. CR3 signals description (continued)

Description

4

3

6

5

2

1

9

8

7

VSREG_EW_TH_9

VSREG_EW_TH_8

VSREG_EW_TH_7

VSREG_EW_TH_6

VSREG_EW_TH_5

VSREG_EW_TH_4

VSREG_EW_TH_3

VSREG_EW_TH_2

VSREG_EW_TH_1

VSREG early warning threshold.

At VSREG < VSREG_EW_TH, an interrupt is generated at NINT and status bit

VSREG_EW in SR2 is set (in Active mode)

0000000000: 0 V (default) feature deactivated

...

1111111111: V

AINVS

0 VSREG_EW_TH_0

1. "Vs related outputs" are OUT1 to OUT14 and H-bridge drivers (both A and B)

7.4.4 Control Register CR4 (0x04)

Figure 66. Control Register CR4

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W

Bit

23:22

Name

Reserved

21

20

19:18

OUT1_HS

OUT1_LS

Reserved

Table 100. CR4 signals description

Description

Reserved

OUT1 High-Side Driver control

0: OUT1_HS is turned off (default)

1: OUT1_HS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously.

OUT1 Low-Side Driver control

0: OUT1_LS is turned off (default)

1: OUT1_LS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously.

Reserved

158/198 DS13220 Rev 5

L99DZ200G

Bit

17

16

15:14

13

12

11:2

1

0

SPI registers

Name

OUT2_HS

OUT2_LS

Reserved

OUT3_HS

OUT3_LS

Reserved

OUT6_HS

OUT6_LS

Table 100. CR4 signals description (continued)

Description

OUT2 High-Side Driver control

0: OUT2_HS is turned off (default)

1: OUT2_HS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT2 are switched on simultaneously.

OUT2 Low-Side Driver control

0: OUT2_LS is turned off (default)

1: OUT2_LS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT2 are switched on simultaneously.

Reserved

OUT3 High-Side Driver control

0: OUT3_HS is turned off (default)

1: OUT3_HS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT3 are switched on simultaneously.

OUT3 Low-Side Driver control

0: OUT3_LS is turned off (default)

1: OUT3_LS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT3 are switched on simultaneously.

--

OUT6 High-side Driver control

0: OUT6_HS is turned off (default)

1: OUT6_HS is turned on

An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously.

OUT6 Low-side Driver control

0: OUT6_LS is turned off (default)

1: OUT6_LS is turned on

An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously.

7.4.5 Control Register CR5 (0x05)

Figure 67. Control Register CR5

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

DS13220 Rev 5 159/198

197

SPI registers

Bit

18

17

16

15:12

11

10

9

8

7:5

23

22

21

20

19

4

3:0

Name

Table 101. CR5 signals description

Description

OUT7_3

OUT7_2

OUT7_1

OUT7_0

OUT8_3

OUT7 Configuration Bits: High-Side Driver OUT7 Configuration

For OUT7 bits configuration see

Table 102: OUTx Configuration bits

OUT8_2

OUT8_1

OUT8_0

OUT8 Configuration Bits: High-Side Driver OUT8 Configuration

For OUT8 bits configuration see

Table 102: OUTx Configuration bits

Reserved —

OUT10_3

OUT10_2

OUT10 Configuration Bits: High-Side Driver OUT10 Configuration

For OUT10 bits configuration see Table 102: OUTx Configuration bits

OUT10_1

OUT10_0

Reserved —

GH

Gate Heater Control: Control of gate driver for external heater MOSFET

0: GH_heater is turned off (default)

1: GH_heater is turned on

Reserved —

L99DZ200G

OUTx_3

0

0

0

0

0

0

0

1

1

0

1

1

OUTx_2

1

1

1

0

0

0

0

0

0

1

0

0

Table 102. OUTx Configuration bits

OUTx_1 OUTx_0 Description

0

0

1

1

1

0

0

0

1

1

0

1

0

1

0

0

1

0

1

1

0

1

0

1

Off (default)

On

Timer1

Timer2

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

Not Applicable

160/198 DS13220 Rev 5

L99DZ200G SPI registers

OUTx_3

1

1

1

1

OUTx_2

1

1

1

1

Table 102. OUTx Configuration bits (continued)

OUTx_1 OUTx_0 Description

0

0

1

1

0

1

0

1

Not Applicable

Not Applicable

DIR

Not Applicable

7.4.6 Control Register CR6 (0x06)

Figure 68. Control Register CR6

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W

Bit

11

10

9

15

14

13

12

8

7:0

19

18

17

16

23

22

21

20

Name

Table 103. CR6 signals description

Description

OUT9_3

OUT9_2

OUT9_1

OUT9_0

OUT13_3

OUT13_2

OUT13_1

OUT13_0

OUT9 Configuration Bits: High-Side Driver OUT9 Configuration

For OUT9 bits configuration see

Table 102: OUTx Configuration bits

OUT13 Configuration Bits: High-Side Driver OUT13 Configuration

For OUT13 bits configuration see

Table 102: OUTx Configuration bits

OUT14_3

OUT14_2

OUT14_1

OUT14_0

OUT15_3

OUT15_2

OUT15_1

OUT14 Configuration Bits: High-Side Driver OUT14 Configuration

For OUT14 bits configuration see

Table 102: OUTx Configuration bits

OUT15 Configuration Bits: High-side Driver OUT15 Configuration

For OUT15 bits configuration see

OUT15_0

Reserved —

Table 102: OUTx Configuration bits

DS13220 Rev 5 161/198

197

SPI registers

7.4.7 Control Register CR7 (0x07)

L99DZ200G

Figure 69. Control Register CR7

23 22 21 20 19 18 17 16

1

5

1

4

13 12 11

1

0

9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

16:13

12

11

10

9

8:6

20

19

18

17

23

22

21

5

4

Name

Table 104. CR7 signals description

Description

OUT1_OCR

OUT2_OCR

OUT3_OCR

OUT6_OCR

OUT7_OCR

OUT8_OCR

OUT15_OCR

Overcurrent recovery for OUTx

0: overcurrent recovery is turned off (default)

1: overcurrent recovery is turned on

Reserved

OUT1_SHORT_DIS

—

OUT2_SHORT_DIS

OUT3_SHORT_DIS

OUTx short circuit threshold disable

0: short circuit threshold is enabled (default)

1: short circuit threshold is disabled

OUT6_SHORT_DIS

Reserved —

CM_DIR_CONF_1 Current Monitor output or DIR input choice.

CM_DIR_CONF_1 CM_DIR_CONF_0

CM_DIR_CONF_0

00: CM all the time (default)

01: DIR when in Standby mode and CM when in Active mode

10: DIR all the time

162/198 DS13220 Rev 5

L99DZ200G

Bit

3

2

1

0

SPI registers

Name

Table 104. CR7 signals description (continued)

Description

CM_SEL_3

CM_SEL_2

CM_SEL_1

CM_SEL_0

Current Monitor Select Bits.

A current image of the selected binary coded output is multiplexed to the CM output. If a corresponding output does not exist, the current monitor is deactivated.

CM_SEL_3 CM_SEL_2 CM_SEL_1 CM_SEL_0

0000: OUT1

0001: OUT2

0010: OUT3

0011: NOT AVAILABLE

0100: NOT AVAILABLE

0101: OUT6

0110: OUT7

0111: OUT8

1000: OUT9

1001: OUT10

1010: NOT AVAILABLE

1011: NOT AVAILABLE

1100: OUT13

1101: OUT14

1110: OUT15

1111: NOT AVAILABLE

7.4.8 Control Register CR8 (0x08)

Figure 70. Control Register CR8

23 22 21 20 19 18 17 16 15

1

4

13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0

R/W

DS13220 Rev 5 163/198

197

Bit

23

22

21

20

19

18

17

16

15

SPI registers

14

13

12

11

10

9

8

L99DZ200G

Table 105. CR8 signals description

Name

OUT1_OCR_THX_EN

Description

OUT2_OCR_THX_EN

OUT3_OCR_THX_EN

OUT6_OCR_THX_EN

OUT7_OCR_THX_EN

OUT8_OCR_THX_EN

OUT15_OCR_THX_EN

Enable Overcurrent Recovery with Thermal Expiration for OUTx.

0: Overcurrent Recovery with Thermal Expiration is off

1: Overcurrent Recovery with Thermal Expiration is on (default). The output is turned off after Thermal Expiration.

Reserved

OUT7_OCR_TON_1

OUT7_OCR_ TON _0

OUT8_OCR_ TON _1

OUT8_OCR_ TON _0

—

Auto-recovery programmable ON time for OUT7

OUT7_OCR_TON_1 OUT7_OCR_TON_0

00: 88 µs

01:80 µs (default)

10: 72 µs

11: 64 µs

Auto-recovery programmable ON time for OUT8

OUT8_OCR_TON_1 OUT8_OCR_TON_0

00: 88 µs

01: 80 µs (default)

10: 72 µs

11: 64 µs

OUT15_OCR_TON _1

OUT15_OCR_TON _0

Auto-recovery programmable ON time for OUT15

OUT15_OCR_ TON _1 OUT15_OCR_ TON _0

00: 88 µs

01: 80 µs (default)

10: 72 µs

11: 64 µs

OUTHB_OCR_ TON _1 Auto-recovery programmable ON time for HB (OUT1, OUT2, OUT3,

OUT6)

OUTHB_OCR_ TON _1 OUTHB_OCR_TON_0

00: 88 µs

OUTHB_OCR_TON_0 01: 80 µs (default)

10: 72 µs

11: 64 µs

164/198 DS13220 Rev 5

L99DZ200G SPI registers

Bit

7

6

5

4

Table 105. CR8 signals description (continued)

Name Description

OUT7_OCR_FREQ_1

OUT7_OCR_FREQ_0

OUT8_OCR_FREQ_1

OUT8_OCR_FREQ_0

Auto-recovery programmable frequency for OUT7

OUT7_OCR_FREQ_1 OUT7_OCR_FREQ_0

00: 1.7 kHz (default)

01: 2.2 kHz

10: 3.0 kHz

11: 4.4 kHz

Auto-recovery programmable frequency for OUT8

OUT8_OCR_FREQ_1 OUT8_OCR_FREQ_0

00: 1.7 kHz (default)

01: 2.2 kHz

10: 3.0 kHz

11: 4.4 kHz

3

2

1

0

OUT15_OCR_FREQ_1

Auto-recovery programmable frequency for OUT15

OUT15_OCR_FREQ_1 OUT15_OCR_FREQ_0

00: 1.7 kHz (default)

01: 2.2 kHz

10: 3.0 kHz

11: 4.4 kHz

OUT15_OCR_FREQ_0

OUTHB_OCR_ FREQ_1

(1)

OUTHB_OCR_ FREQ_0

(1)

Auto-recovery programmable frequency for OUTHB (OUT1, OUT2,

OUT3, OUT6)

OUTHB_OCR_FREQ_1 OUTHB_OCR_FREQ_0

00: 1.7 kHz (default)

01: 2.2 kHz

10: 3.0 kHz

11: 4.4 kHz

1. For OUT1 and OUT6, in case the Short Circuit detection is disabled and the OCR is enabled, the OCR configurations with frequency 3.0 kHz and 4.4kHz (whatever is the configured Ton value) are NOT allowed .

DS13220 Rev 5 165/198

197

SPI registers L99DZ200G

7.4.9 Control Register CR9 (0x09)

Figure 71. Control Register CR9

23 22 21 20 19 18 17 16 15

1

4

13 12

1

1

10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 0 0 0

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

23

22

21

20

19

18

17:15

Name

Table 106. CR9 signals description

Description

OUT8_RDSON

Select Rdson for OUT8

0: ron_low (default)

1: ron_high

OUT7_RDSON

OUT1_6_RDSON

Select Rdson for OUT7

0: ron_low (default)

1: ron_high

Select Rdson for both OUT6 and OUT1

0: ron_low (default)

1: ron_high

OUT9_CCM_EN

OUT8_CCM_EN

OUT7_CCM_EN

Reserved

Enable Constant Current Mode for OUT9

0: Disable (default)

1: Enable

Enable Constant Current Mode for OUT8

0: Disable (default)

1: Enable

Enable Constant Current Mode for OUT7

0: Disable (default)

1: Enable

—

166/198 DS13220 Rev 5

L99DZ200G SPI registers

Bit

14

13

12

11:10

9

8

7

6

5

4

3:2

1

0

Table 106. CR9 signals description (continued)

Name Description

OUT15_OL

OUT14_OL

OUT13_OL

Reserved

OUT10_OL

OUT9_OL

Reserved

OUT15_OC

OUT14_OC

OUT13_OC

Reserved

OUT10_OC

Open-load Threshold for OUTx

0: I

OLD1

; high-current mode (default)

1: I

OLD1

; low-current mode

—

Overcurrent Threshold for OUTx

0: I

OC

; high-current mode (default)

1: I

OC

; low-current mode

OUT9_OC

7.4.10 Control Register CR10 (0x0A)

Figure 72. Control Register CR10

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

Access R/W

Bit

23

Name

DIAG_2_A

Table 107. CR10 signals description

Description

Drain-source monitoring threshold for external H-bridge A

DIAG_2_A DIAG_1_A DIAG_0_A

DS13220 Rev 5 167/198

197

20

15

14

13

12

11

19

18

17

16

10

9

SPI registers

Bit

22

21

8

7

6

5

Name

Table 107. CR10 signals description (continued)

Description

DIAG_1_A

DIAG_0_A

DIRHA

000: V

SCd1_HB

001: V

SCd2_HB

010: V

SCd3_HB

011: V

SCd4_HB

100: V

SCd5_HB

101: V

SCd6_HB

110: V

SCd7_HB

111: V

SCd7_HB

(default)

Direction of the H-Bridge A

0: HS2a and LS1a are ON; HS1a and LS2a are OFF (default)

1: HS1a and LS2a are ON; HS2a and LS1a are OFF

Slow decay for leg 2 of the H-bridge B

Slow decay Single for leg 2 of the H-bridge B

Slow decay for leg 1 of the H-bridge B

Slow decay Single for leg 1 of the H-bridge B

SD2B

SDS2B

SD1B

SDS1B

SD2A

SDS2A

SD1A

SDS1A

COPT_3_A

COPT_2_A

COPT_1_A

COPT_0_A

Slow decay for leg 2 of the H-bridge A

Slow decay Single for leg 2 of the H-bridge A

Slow decay for leg 1 of the H-bridge A

Slow decay Single for leg 1 of the H-bridge A

Cross current protection time (H-Bridge A)

COPT_3_A COPT_2_A COPT_1_A COPT_0_A

0000: tccp

0000

0001: tccp

0001

0010: tccp

0010

0011: tccp

0011

0100: tccp

0100

0101: tccp

0101

0110: tccp

0110

0111: tccp

0111

1000: tccp

1000

1001: tccp

1001

1010: tccp

1010

1011: tccp

1011

1100: tccp

1100

1101: tccp

1101

1110: tccp

1110

1111: tccp

1111

(default)

H_OLTH_HIGH_A H-bridge A OL high threshold (5/6 * V

S

) select

OL_H1L2_A Test open-load condition between H1 and L2 of the H-Bridge A

OL_H2L1_A Test open-load condition between H2 and L1 for H-bridge A

L99DZ200G

168/198 DS13220 Rev 5

L99DZ200G SPI registers

Bit

2

1

4

3

0

Name

SLEW_4_A

SLEW_3_A

SLEW_2_A

SLEW_1_A

SLEW_0_A

Table 107. CR10 signals description (continued)

Description

Binary coded slew rate of H-bridge A

SLEW_4_A SLEW_3_A SLEW_2_A SLEW_1_A SLEW_0_A

(bit0 = LSB; bit4 = MSB)

00000: Control disabled (default)

11111: I

GHxmax

7.4.11 Control Register CR11 (0x0B)

23 22 21

2

0

Figure 73. Control Register CR11

19 18 17 16 15

1

4

13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved Reserved

Reset 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W

Bit

23:18

17

16

15

14

13

Name

Reserved

GH_OL_EN

Table 108. CR11 signals description

Description

—

Control open-load diagnosis for Gate Heater output

0: open-load diagnosis off (default)

1: open-load diagnosis on

GH_TH_2

GH_TH_1

GH_TH_0

Drain source monitoring threshold voltage for external heater MOSFET

GH_TH_2 GH_TH_1 GH_TH_0

000: V

SCd1_HE

001: V

SCd2_HE

010: V

SCd3_HE

011: V

SCd4_HE

100: V

SCd5_HE

101: V

SCd6_HE

110: V

SCd7_HE

111: V

SCd8_HE

(default)

ECV_LS

Control of ECV low-side switch

0: ECV low-side switch off (default)

1: ECV low-side switch on

DS13220 Rev 5 169/198

197

7:6

5

4

3

2

1

0

SPI registers

Bit

12

11:9

8

L99DZ200G

Table 108. CR11 signals description (continued)

Name Description

ECV_OCR

Overcurrent recovery for output ECV

0: overcurrent recovery is turned off (default)

1: overcurrent recovery is turned on

Reserved

ECON

Reserved

EC_5

EC_4

EC_3

EC_2

EC_1

EC_0

—

Electro-chrome Control

The electro-chrome control enables the driver at pin ECDR and switches

OUT10 directly on ignoring the control bits OUT10_x in CR5

0: Electro-chrome control off (default)

1: Electro-chrome control on

—

EC Reference Voltage Bits

The reference voltage for the electro-chrome voltage controller at pin ECV is binary coded.

(bit0 = LSB; bit5 = MSB) 00 0000: V

ECV

= 0 V xx xxxx: V

ECV

= V

CTRLmax

/63 x register value

11 1111: V

ECV

= V

CTRLmax

For ECV_HV (Configuration Register) = 0, the maximum EC control

voltage is clamped at lower value (see Section 3.4.20: Electro-chrome mirror driver

)

EC_x bits are set to 0 after wake-up from VBAT_Standby mode

7.4.12 Control Register CR12 (0x0C)

Figure 74. Control Register CR12

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W

170/198 DS13220 Rev 5

L99DZ200G

Bit

23

22

21

12

11

16

15

20

19

18

17

14

13

10

9:0

Name

Table 109. CR12 signals description

Description

PMW1_FREQ_1 Frequency of PWM channel PWM1

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW1_FREQ_0

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW2_FREQ_1 Frequency of PWM channel PWM2

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW2_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

PMW3_FREQ_1 Frequency of PWM channel PWM3

00: f

PWMx

(00) (default)

PMW3_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW4_FREQ_1 Frequency of PWM channel PWM4

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW4_FREQ_0 10: f

PWMx

(10)

11: f PWMx (11)

PMW5_FREQ_1 Frequency of PWM channel PWM5

00: f PWMx (00) (default)

PMW5_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW6_FREQ_1 Frequency of PWM channel PWM6

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW6_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

PMW7_FREQ_1 Frequency of PWM channel PWM7

00: f

PWMx

(00) (default)

PMW7_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

Reserved —

SPI registers

DS13220 Rev 5 171/198

197

SPI registers L99DZ200G

7.4.13 Control Register CR13 (0x0D) to CR16 (0x10)

Figure 75. Control Register CR13 to CR16

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W where: x = 1 + (z * 2), z = 0 to 3  y = 2 + (z * 2), z = 0 to 2

Name

Reserved

PWMx_DC_9

PWMx_DC_8

PWMx_DC_7

PWMx_DC_6

PWMx_DC_5

PWMx_DC_4

PWMx_DC_3

PWMx_DC_2

PWMx_DC_1

PWMx_DC_0

Reserved

PWMy_DC_9

PWMy_DC_8

PWMy_DC_7

PWMy_DC_6

PWMy_DC_5

PWMy_DC_4

PWMy_DC_3

PWMy_DC_2

PWMy_DC_1

PWMy_DC_0

4

3

2

1

0

6

5

8

7

Bit

15

14

13

12

23:22

21

20

19

18

17

16

11:10

9

—

Table 110. CR13 to CR16 signals description

Description

Binary coded on-duty cycle of PWM channel PWMx (bit12 = LSB; bit21 = MSB)

00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1024 x register value 11 1111 1111. duty cycle 99,9%

(1)

—

Binary coded on-duty cycle of PWM channel PWMy (bit0 = LSB; bit9 = MSB)

00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/ 1024 x register value 11 1111 1111. Duty cycle 99,9%

(1)

Binary coded on-duty cycle of PWM channel PWMy

1. To have Duty Cycle equal to 100% for the Output X (where X = 7, 8, 9, 10, 13, 14, 15), the related Output Configuration shall be set in ON mode (OUTX_3-2-1-0 = 0001; see

Table 102: OUTx Configuration bits ).

172/198 DS13220 Rev 5

L99DZ200G SPI registers

7.4.14 Control Register CR17 (0x11) to CR20 (0x14)

Figure 76. Control Registers CR17-CR20

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Bit

23

22

21

20

19

18

13

12

11

10

17

16

15

14

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W where: x = 7 + (z * 2), z = 0, 1, 3, 4 y = 8 + (z * 2), z = 0, 1, 3

Table 111. CR17 to CR20 signals description

Name

Reserved —

Description

OUTx_AUTOCOMP_EN Setting this bit to ‘1’ enables the automatic V

S compensation for OUTx

OUTx_VLED_9

OUTx_VLED_8

OUTx_VLED_7

OUTx_VLED_6

OUTx_VLED_5

OUTx_VLED_4

OUTx_VLED_3

OUTx_VLED_2

Binary coded nominal LED voltage of OUTx (bit12 = LSB; bit21 = MSB)

00 0000 0000: V

LED

= 0 V (default) xx xxxx xxxx: V

01 1101 0000: V

V

LED

LED

= V

LED

AINVS

= V

AINVS

/1024 x register value is clamped at 10 V (0x1D0h)

OUTx_VLED_1

OUTx_VLED_0

Reserved —

OUTy_AUTOCOMP_EN Setting this bit to ‘1’ enables the automatic V

S compensation for OUTy

DS13220 Rev 5 173/198

197

SPI registers L99DZ200G

5

4

7

6

Bit

9

8

3

2

1

0

Table 111. CR17 to CR20 signals description (continued)

Name

OUTy_VLED_9

OUTy_VLED_8

Description

OUTy_VLED_7

OUTy_VLED_6

OUTy_VLED_5

OUTy_VLED_4

OUTy_VLED_3

OUTy_VLED_2

OUTy_VLED_1

OUTy_VLED_0

Binary coded nominal LED voltage of OUTy (bit0 = LSB; bit9 = MSB)

00 0000 0000: V

LED

= 0 V (default) xx xxxx xxxx: V

LED

= V

AINVS

/1024 x register value

01 1101 0000: V

LED

= V

AINVS

V

LED is clamped at 10 V (0x1D0h)

7.4.15 Control Register CR21 (0x15)

Figure 77. Control Register CR21

23 22 21 20 19 18 17 16 15 14 13

1

2

11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

Access R/W

174/198 DS13220 Rev 5

L99DZ200G

Bit

23

22

21

20

19:12

Name

DIAG_2_B

DIAG_1_B

DIAG_0_B

DIRHB

Reserved

Table 112. CR21 signals description

Description

Drain-source monitoring threshold for external H-bridge B

DIAG_2_B DIAG_1_B DIAG_0_B

000: V

SCd1_HB

001: V

SCd2_HB

010: V

SCd3_HB

011: V

SCd4_HB

100: V

SCd5_HB

101: V

SCd6_HB

110: V

SCd7_HB

111: V

SCd7_HB

(default)

Direction of the H-bridge B

0: HS2b and LS1b are ON; HS1b and LS2b are OFF (default)

1: HS1b and LS2b are ON; HS2b and LS1b are OFF

—

SPI registers

11

10

9

8

COPT_3_B

COPT_2_B

COPT_1_B

COPT_0_B

Cross current protection time (H-bridge B)

COPT_3_B COPT_2_B COPT_1_B COPT_0_B

0000: tccp

0000

0001: tccp

0001

0010: tccp

0010

0011: tccp

0011

0100: tccp

0100

0101: tccp

0101

0110: tccp

0110

0111: tccp

0111

1000: tccp

1000

1001: tccp

1001

1010: tccp

1010

1011: tccp

1011

1100: tccp

1100

1101: tccp

1101

1110: tccp

1110

1111: tccp

1111

(default)

7

6

5

H_OLTH_HIGH_B H-bridge B OL high threshold (5/6 * V

S

) select

OL_H1L2_B

OL_H2L1_B

Test open-load condition between H1 and L2 of the H-Bridge B

Test open-load condition between H2 and L1 for H-bridge B

DS13220 Rev 5 175/198

197

Bit

4

3

2

1

0

SPI registers

Name

SLEW_4_B

SLEW_3_B

SLEW_2_B

SLEW_1_B

SLEW_0_B

Table 112. CR21 signals description (continued)

Description

Binary coded slew rate of H-bridge B

SLEW_4_B SLEW_3_B SLEW_2_B SLEW_1_B SLEW_0_B

(bit0 = LSB; bit4 = MSB)

00000: Control disabled (default)

11111: I

GHxmax

L99DZ200G

7.4.16 Control Register CR22 (0x16)

Figure 78. Control Register CR22

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

Access R/W

Bit

23:5

4

3

2

Name

Table 113. CR22 signals description

Description

Reserved —

GENERATOR_MODE_EN

Generator Mode control enable:

0: Generator Mode is disabled

1: Generator Mode is enabled (default)

DEBUG_EXIT

CP_OFF

SW-Debug mode exit

0: stay in SW-Debug mode (default)

1: exit from SW Debug mode

When exiting from SW-Debug mode, the watchdog starts with a Long Open

Window.

This bit has only effect in SW-Debug mode (no effect in Normal mode)

Charge pump control

0: Enabled; charge pump on in active mode (default)

1: Disabled; charge pump off in active mode setting CP_OFF = 1 is only possible when CP_OFF_EN = 1

176/198 DS13220 Rev 5

L99DZ200G

Bit

1

0

SPI registers

Name

Table 113. CR22 signals description (continued)

Description

ICMP

WD_EN

V1 load current supervision

0: Enabled; Watchdog is disabled in V1 Standby when I

V1

< I

CMP

(default)

1: Disabled; watchdog is disabled upon transition into V1_Standby mode setting ICMP = 1 is only possible when ICMP_CONFIG_EN = 1

Watchdog Enable

0: Watchdog disabled

1: Watchdog enabled (default)

Writing to this bit is only possible during CAN Flash mode (V

TxDL

> V flash

)

7.4.17 Configuration Register (0x3F)

Figure 79. Configuration Register

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W

Bit

23

22

21

20

Name

Table 114. Configuration Register signals description

Description

WU_CONFIG

LIN_WU_CONFIG

LIN_HS_EN

TSD_CONFIG

Configuration of input pin WU Input configured as wake-up input

0: WU configured as wake-up input

1: WU configured for input voltage measurement (default)

Configuration of LIN wake-up behavior

0: wake up at recessive - dominant - recessive with t dom

> t dom_LIN

(default)

(according to LIN 2.2a and Hardware Requirements for Transceivers version

1.3)

1: wake up at recessive - dominant transition

Configuration of LIN transceiver bit rate

0: LIN transceiver in normal communication mode (20kbit/s) (default)

1: LIN transceiver in high speed mode for fast Flashing (115kbit/s)

Configuration of thermal shutdown behavior

0: in case of TSD1 all power stages are switched off (default)

1: selective shut down of power stage cluster

DS13220 Rev 5 177/198

197

SPI registers

Bit

19

18

17

16

15

14

13

12

11

10

L99DZ200G

Table 114. Configuration Register signals description (continued)

Name Description

ECV_HV

V2_CONFIG

ICMP_CONFIG_EN

WD_CONFIG_EN

MASK_OL_HS1

MASK_OL_LS1

MASK_TW

MASK_EC_OL

MASK_OL

MASK_SPIE

Configuration of maximum voltage of electrochrome controller (see electrical parameter V

CTRLmax

)

0: maximum electrochrome controller voltage clamped to 1.2V (typ); (default)

1: maximum electrochrome controller voltage set to 1.5V (typ)

Configuration of V2

0: V2 is Voltage Regulator (default)

1: V2 is Voltage Tracker of V1

ICMP configuration Enable

0: writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default)

1: writing ICMP = 1 is possible with next SPI command bit is automatically reset to 0 after next SPI command

Watchdog configuration Enable

0: writing to WD Configuration (CR2 [0:1] is blocked (default)

1: writing to WD Configuration Bits is possible with next SPI command bit is automatically reset to 0 after next SPI command

Mask Open-load HS1

0: Open-load condition at HS1 is not masked (default)

1: Open-load condition at HS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask Open-load LS1

0: Open-load condition at LS1 is not masked (default)

1: Open-load condition at LS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask Thermal Warning

0: Thermal warning is not masked (default)

1: Thermal warning is masked i.e. it is reported as a Global Warning (GSB bit 1) but not as a Global Error

(GSB bit 7)

Mask Electro-chrome Open-load

0: Open-load condition at ECV and OUT10 is not masked (default)

1: Open-load condition at ECV and OUT10 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask open-load

0: Open-load condition at all outputs are not masked (default)

1: Open-load condition at all outputs are masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask SPI error

0: SPI errors are not masked (default)

1: SPI errors are masked i.e. reported as an SPI Error (GSB bit 5) but not as a Global Error (GSB bit 7)

178/198 DS13220 Rev 5

L99DZ200G

Bit

9

8

7

6

5

4

3

2:1

0

SPI registers

Table 114. Configuration Register signals description (continued)

Name Description

MASK_PLE

MASK_GW

CP_OFF_EN

CP_LOW_CONFIG

CP_DITH_DIS

FS_FORCED

Reserved

DMA

DMB

TRIG

Mask physical layer error

0: Physical Layer Errors are not masked (default)

1: Physical Layer Errors are masked i.e. reported as a Physical Layer Error (GSB bit 4) but not as a Global Error

(GSB bit 7)

Mask global warning

0: Global Warning conditions are not masked (default)

1: Global Warning conditions are masked i.e. reported as a Global Warning (GSB bit 1) but not as a Global Error (GSB bit

7)

Charge pump control enable

0: writing CP_OFF = 1 is blocked (writing CP OFF = 0 is possible); (default)

1: writing CP_OFF = 1 is possible with next SPI command

Bit is automatically reset to 0 after next SPI command

Charge pump low configuration

0: CP_low (SR 2, bit 9) is latched and outputs are off until R&C; (default)

1: CP_low (SR 2, bit 9) is a ‘live’ bit; outputs are re-activated automatically upon recovery of the charge pump output voltage

Charge pump clock dithering

0: CP clock dithering is enabled; (default)

1: CP clock dithering is disabled

Force LSx_FSO ON

LSx_FSO low-side outputs are forced ON (to allow diagnosis of the fail-safe path)

0: LSx_FSO outputs are controlled by the Fail-safe logic (default)

1: LSx_FSO outputs are forced ON and the device enters Fail-Safe mode; no

NReset is generated

—

H-bridge A configuration

0: single motor mode (default)

1: dual motor mode

H-bridge B configuration

0: single motor mode (default)

1: dual motor mode

Watchdog Trigger bit

DS13220 Rev 5 179/198

197

SPI registers

7.5

7.5.1

L99DZ200G

Status registers

Status Register SR1 (0x31)

Figure 80. Status Register SR1 (0x31)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R

Bit

23

22

21

20

19

18

R/C R R/C

Name

VS_OV_WAKEUP

WU_STATE

SGND_LOSS

WU_WAKE

WAKE_CAN

WAKE_LIN

Table 115. SR1 signals description

Description

Wake-up by VS OV: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

State of WU input

0: input level is low

1: input level is high

The bit shows the momentary status of WU and cannot be cleared (“Live bit”)

Note: The status is only valid if WU is configured as wake-up input in

Configuration Register (0x3F). Otherwise this bit is read at its previous logic state

SGND Loss: shows the Signal GND loss

1: SGND Loss

Bit is latched until a “Read and clear” command

Wake-up by WU: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

Wake-up by CAN: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

Wake-up by LIN: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

180/198 DS13220 Rev 5

15

9

8

11

10

7

14

13

12

L99DZ200G

Bit

17

16

6

5

4

3

2

SPI registers

Name

Table 115. SR1 signals description (continued)

Description

WAKE_TIMER

DEBUG_ACTIVE

V1UV

V1_RESTART_2

V1_RESTART_1

V1_RESTART_0

WDFAIL_CNT_3

WDFAIL_CNT_2

WDFAIL_CNT_1

WDFAIL CNT_0

DEVICE_STATE_1

Wake-up by Timer: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

Debug Mode Active: indicates Device is in Debug mode

1: Debug mode

The bit shows the momentary status and cannot be cleared (“Live bit”)

Indicates undervoltage condition at voltage regulator V1 (V1 < V

RTx

)

1: undervoltage

Bit is latched until a “Read and clear” command

Indicates the number of TSD2 events which caused a restart of voltage regulator V1

Bits cannot be cleared; counter will be cleared automatically if no additional

TSD2 event occurs within 1 minute.

Indicates number of subsequent watchdog failures.

Bits cannot be cleared; will be cleared with a valid watchdog trigger

DEVICE_STATE_0

State from which the device woke up

00: Active mode, after Read&Clear command or after Flash mode state

01: Active mode after wake-up from V1_Standby mode (before Read&Clear command)

10: in Active mode after Power-on or after wake-up from VBAT_Standby mode

(before Read&Clear command)

11: Flash mode (LIN Flash or CAN Flash mode)

Bit is latched until a “Read and clear” command

After a “read and clear access”, the device state will be updated

TSD2

TSD1

FORCED_SLEEP_

TSD2/V1SC

Thermal Shutdown 2 was reached

Bit is latched until a "Read and clear" command

Thermal Shutdown 1 was reached (Logical Or combination of all TSD1_CLx; see status register SR6).

This bit cannot be cleared directly. It is reset if the corresponding TSD1_CLx bits in SR6 are cleared.

Device entered Forced VBAT_Standby mode due to:

Thermal shutdown or

Short circuit on V1 during startup

Bit is latched until a "Read and clear" command

FORCED_SLEEP_WD

Device entered Forced VBAT_Standby mode due to multiple watchdog failures

Bit is latched until a "Read and clear" command

DS13220 Rev 5 181/198

197

SPI registers

Bit

1

0

L99DZ200G

Name

Table 115. SR1 signals description (continued)

Description

WDFAIL

VPOR

Watchdog failure

Bit is latched until a "Read and clear" command

V S Power-on Reset threshold (VPOR) reached Bit is latched until a "Read and clear" command

7.5.2 Status Register SR2 (0x32)

Figure 81. Status Register SR2 (0x32)

23 22 21 20 19 18 17 16 1 14 13 1 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R R/C

Bit

23

22

21

20

19

18

17

Name

Table 116. SR2 signals description

Description

LIN_PERM_DOM

LIN_TXD_DOM

LIN_PERM_REC

CAN_RXD_REC

LIN bus signal is dominant for t > t dom(bus)

Bit is latched until a “Read and clear” command

TxD_L pin is dominant for t > t dom(TXDL)

The LIN transmitter is disabled until the bit is cleared Bit is latched until a “Read and clear” command

LIN bus signal does not follow TxD_L within t

LIN

The LIN transmitter is disabled until the bit is cleared Bit is latched until a “Read and clear” command

RxD_C has not followed TxD_C for 4 times

The CAN transmitter is disabled until the bit is cleared Bit is latched until a “Read and clear” command

CAN_PERM_REC

CAN_PERM_DOM

CAN_TXD_DOM

CAN bus signal did not follow TxD_C for 4 times

The CAN transmitter is disabled until the bit is cleared Bit is latched until a “Read and clear” command

CAN bus signal is dominant for t > t

CAN

Bit is latched until a “Read and clear” command

TxD_C pin is dominant for t > t dom(TXDC)

The CAN transmitter is disabled until the bit is cleared Bit is latched until a “Read and clear” command

182/198 DS13220 Rev 5

16

15

14

13

12

L99DZ200G

Bit

11

10

9

8

7

6

5 V1FAIL

SPI registers

Name

CAN_SUP_LOW

Table 116. SR2 signals description (continued)

Description

Voltage at CAN supply pin reached the CAN supply low warning threshold V CANSUP

< V

CANSUPlow

Bit is latched until a “Read and clear” command

DSMON_HS2_A

DSMON_HS1_A

DSMON_LS2_A

DSMON_LS1_A

Drain-Source Monitoring for H-bridge A

‘1’ indicates a short-circuit or open-load condition was detected Bit is latched until a

“Read and clear” command

SPI_INV_CMD

SPI_SCK_CNT

CP_LOW

TW

V2SC

Invalid SPI command

‘1’ indicates one of the following conditions was detected:

– access to undefined address

– Write operation to Status Register

– DI stuck at '0' or '1'

– CSN timeout

– Parity failure

– invalid or undefined setting

– SPI access during VS_OV conditions (when Generator_Mode_EN = 1)

The SPI frame is ignored

Bit is latched until a “Read and clear” command

SPI clock counter

‘1’ indicates an SPI frame with wrong number of CLK cycles was detected Bit is latched until a valid SPI frame

Charge pump voltage low

‘1’ indicates that the charge pump voltage is too low Bit is latched until a “Read and clear” command

Thermal warning

‘1’ indicates the temperature has reached the thermal warning threshold (logical

OR combination of bits TW_CLx in SR6)

Bit is latched until a “Read and clear” command

V2 short circuit detection

‘1’ indicates a short circuit to GND condition of V2 at turn-on of the regulator (V2 <

V2_fail for t > t v2_short

)

Bit is latched until a “Read and clear” command

V2FAIL

V2 failure detection

‘1’ indicates a V2 fail event occurred since last readout (V2 < V2_fail for t > t v2_fail

)

Bit is latched until a “Read and clear” command

V1 failure detection

‘1’ indicates a V1 fail event occurred since last readout (V1 < V1_fail for t > t v1_fail

)

Bit is latched until a “Read and clear” command

DS13220 Rev 5 183/198

197

SPI registers

Bit

4

3

2

1

0

L99DZ200G

Name

VSREG_EW

VSREG_OV

VSREG_UV

VS_OV

VS_UV

Table 116. SR2 signals description (continued)

Description

V

SREG early warning

‘1’ indicates the voltage at V

SREG has reached the early warning threshold

(configured in CR3)

In Active mode, an interrupt pulse is generated at NINT Bit is latched until a “Read and clear” command.

Bit needs a "Read and clear" command after wake-up from standby modes

V

SREG overvoltage

‘1’ indicates the voltage at V

SREG has reached the overvoltage threshold Bit is latched until a “Read and clear” command

V

SREG undervoltage

‘1’ indicates the voltage at V

SREG has reached the undervoltage threshold Bit is latched until a “Read and clear” command

V

S overvoltage

‘1’ indicates the voltage at V

S has reached the overvoltage threshold Bit is latched until a “Read and clear” command

V

S undervoltage

‘1’ indicates the voltage at V

S has reached the undervoltage threshold Bit is latched until a “Read and clear” command

7.5.3 Status Register SR3 (0x33)

Figure 82. Status Register SR3 (0x33)

23 22 21 20 19 18 17 16 15 14 1 12 11 1 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R R/C

184/198 DS13220 Rev 5

L99DZ200G SPI registers

Bit

12

11

10

16

15

14

13

20

19

18

17

23

22

21

9

8:7

6

5

4

3

2

1

0

Name

OUT1_HS_OC_TH_EX

OUT1_LS_OC_TH_EX

OUT2_HS_OC_TH_EX

OUT2_LS_OC_TH_EX

OUT3_HS_OC_TH_EX

OUT3_LS_OC_TH_EX

OUT6_HS_OC_TH_EX

OUT6_LS_OC_TH_EX

OUT7_OC_TH_EX

OUT8_OC_TH_EX

OUT9_OC_STAT

OUT10_OC_STAT

OUT13_OC_STAT

OUT14_OC_STAT

Table 117. SR3 signals description

Description

Overcurrent shutdown for (OUT1-2-3-6-7-8)

‘1’ indicates the output was shut down due to overcurrent condition. If

Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):

Bit is set upon overcurrent condition and output is turned off. If Overcurrent

Recovery is enabled (CR7: OUTx_OCR = 1):

In case of overcurrent condition this bit is not set. The output goes into

Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1' In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):

Bit is set after thermal expiration and output is turned off Bit is latched until a

“Read and clear” command

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition. Bit is latched until a “Read and clear” command

OUT15_OC_TH_EX

Overcurrent shutdown for OUT15

‘1’ indicates the output was shut down due to overcurrent condition. If

Overcurrent Recovery is disabled (CR7: OUT15_OCR = 0):

Bit is set upon overcurrent condition and output is turned off. If Overcurrent

Recovery is enabled (CR7: OUT15_OCR = 1):

In case of overcurrent condition this bit is not set. The output goes into

Overcurrent Recovery mode and OUT15_OCR_ALERT in SR4 is set to '1' In case of Thermal Expiration enabled (CR8: OUT15_OCR_THX_EN = 1):

Bit is set after thermal expiration and output is turned off Bit is latched until a

“Read and clear” command

--Reserved

DSMON_HS2_B

DSMON_HS1_B

DSMON_LS2_B

DSMON_LS1_B

Reserved

Drain-Source Monitoring for H-bridge B

‘1’ indicates a short-circuit or open-load condition was detected Bit is latched until a “Read and clear” command

LSB_FSO_OC

LSA_FSO_OC

---

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition. Bit is latched until a “Read and clear” command

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition. Bit is latched until a “Read and clear” command

DS13220 Rev 5 185/198

197

SPI registers

7.5.4 Status Register SR4 (0x34)

L99DZ200G

Figure 83. Status Register SR4 (0x34)

23 22 21 20 19 18 17 1 1 14 13 1 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R R/C

Bit

19

18

17

16

23

22

21

20

13

12:8

7

6

15

14

5

4

3

2

1

0

Name

OUT1_HS_OCR_ALERT

OUT1_LS_OCR_ALERT

OUT2_HS_OCR_ALERT

OUT2_LS_OCR_ALERT

OUT3_HS_OCR_ALERT

OUT3_LS_OCR_ALERT

OUT6_HS_OCR_ALERT

OUT6_LS_OCR_ALERT

OUT7_OCR_ALERT

OUT8_OCR_ALERT

OUT15_OCR_ALERT

Reserved

OUT1_HS_SHORT

OUT1_LS_SHORT

OUT2_HS_SHORT

OUT2_LS_SHORT

OUT3_HS_SHORT

Table 118. SR4 signals description

Description

Auto recovery Alert

‘1’ indicates that the output reached the overcurrent threshold and is in auto recovery mode

Bit is not latched and cannot be cleared.

--

Short circuit Threshold Alert

‘1’ indicates that the output reached the short circuit threshold

Bit is latched and can be cleared with Read&Clear command

OUT3_LS_SHORT

OUT6_HS_SHORT

OUT6_LS_SHORT

186/198 DS13220 Rev 5

L99DZ200G

7.5.5

SPI registers

Status Register SR5 (0x35)

Figure 84. Status Register SR5 (0x35)

23 22 21 20 19 18 17 16 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0

Bit name

Bit

12

11

10

9

16

15

14

13

8

7

6:2

19

18

17

23

22

21

20

1

Access

0

R/C R R/C

Name

OUT1_HS_OL

OUT1_LS_OL

OUT2_HS_OL

OUT2_LS_OL

OUT3_HS_OL

OUT3_LS_OL

OUT6_HS_OL

OUT6_LS_OL

OUT7_OL_STAT

OUT8_OL_STAT

OUT9_OL_STAT

OUT10_OL_STAT

OUT13_OL_STAT

OUT14_OL_STAT

OUT15_OL_STAT

GH_OL

ECV_OL

Reserved

DSMON_HEAT

ECV_OC

Table 119. SR5 signals description

Description

Open-load

‘1’ indicates an open-load condition was detected at the output

Bit is latched until a “Read and clear” command

--

Drain-Source Monitoring Heater output

‘1’ indicates a short-circuit condition was detected

Bit is latched until a “Read and clear” command

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition. Bit is latched until a “Read and clear” command

DS13220 Rev 5 187/198

197

SPI registers

7.5.6 Status Register SR6 (0x36)

L99DZ200G

Figure 85. Status Register SR6 (0x36)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Access R R/C R R/C

15:14

13

12

9

8

11

10

7:6

Bit

23

22

21:18

17

Table 120. SR6 signals description

Name

WD_TIMER_STATE_1 Watchdog timer status

00: 0 - 33%

WD_TIMER_STATE_0 01: 33 - 66%

11: 66 - 100%

Reserved —

Description

ECV_VNR

Electrochrome Voltage Not Reached: electrochrome voltage status '1' indicates the electrochrome voltage is not reached. Bit is not latched

16 ECV_VHI

Electrochrome Voltage HIgh: electrochrome voltage status '1' indicates the electrochrome voltage is higher than the target value. Bit is not latched

— Reserved

TW_CL6

TW_CL5

TW_CL4

TW_CL3

TW_CL2

TW_CL1

Reserved

Thermal warning for Cluster x

‘1’ indicates Cluster x has reached the thermal warning threshold Bit is latched until a “Read and clear” command

—

188/198 DS13220 Rev 5

Bit

2

1

0

5

4

3

L99DZ200G SPI registers

Name

TSD1_CL6

TSD1_CL5

TSD1_CL4

TSD1_CL3

TSD1_CL2

TSD1_CL1

Table 120. SR6 signals description (continued)

Description

Thermal shutdown of Cluster x

‘1’ indicates Cluster x has reached the thermal shutdown threshold (TSD1) and the output cluster was shut down

Bit is latched until a “Read and clear” command

7.5.7 Status Register SR7 (0x37) to SR9 (0x39)

Figure 86. Status Register SR7 (0x37) to SR9 (0x39)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Bit

18

17

16

15

23:22

21

20

19

14

13

12

11:10

Access R/C R R/C R where: x = 2 + (z * 2), z = 0 to 2 y = 1 + (z * 2), z = 0 to 2

Table 121. SR7 to SR9 signals description

Description

—

Name

Reserved

TEMP_CLx_9

TEMP_CLx_8

TEMP_CLx_7

TEMP_CLx_6

TEMP_CLx_5

TEMP_CLx_4

TEMP_CLx_3

TEMP_CLx_2

TEMP_CLx_1

TEMP_CLx_0

Reserved

Temperature Cluster x: Binary coded voltage of temperature diode for cluster x

(bit12 = LSB; bit21 = MSB) (see

Section 4.37

)

Bits cannot be cleared.

—

DS13220 Rev 5 189/198

197

Bit

6

5

4

9

8

7

1

0

3

2

SPI registers L99DZ200G

Name

Table 121. SR7 to SR9 signals description (continued)

Description

TEMP_CLy_9

TEMP_CLy_8

TEMP_CLy_7

TEMP_CLy_6

TEMP_CLy_5

TEMP_CLy_4

TEMP_CLy_3

TEMP_CLy_2

TEMP_CLy_1

TEMP_CLy_0

Temperature Cluster y: binary coded voltage of temperature diode for cluster y

(bit0 = LSB; bit9 = MSB) (see

Section 4.37

)

Bits cannot be cleared.

7.5.8 Status Register SR10 (0x3A)

Figure 87. Status Register SR10 (0x3A)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Access R/C R R/C

Bit

23:22

21

20

19

18

17

16

15

14

13

12

11:0

Name

Table 122. SR10 signals description

Description

Reserved —

VSREG_9

VSREG_8

VSREG_7

VSREG_6

VSREG_5

VSREG_4

VSREG_3

VSREG_2

VSREG_1

VSREG_0

Reserved —

Binary coded voltage at V

SREG pin (bit12 = LSB; bit21 = MSB)

00 0000 0000: 0V xx xxxx xxxx: VAINVS/1024 x register value 

11 1111 1111: VAINVS

Bits cannot be cleared.

190/198 DS13220 Rev 5

L99DZ200G

7.5.9

SPI registers

Status Register SR11 (0x3B)

Figure 88. Status Register SR11 (0x3B)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R R/C R

Bit

11:10

9

8

7

15

14

13

12

19

18

17

16

23

21

20

4

3

6

5

2

1

0

Name

Table 123. SR11 signals description

Description

Reserved —

VS_9

VS_8

VS_7

VS_6

VS_5

VS_4

Binary coded voltage at V

S pin (bit12 = LSB; bit21 = MSB)

00 0000 0000: 0V xx xxxx xxxx: V

AINVS

/1023 x register value 

11 1111 1111: V

AINVS

Bits cannot be cleared.

VS_3

VS_2

VS_1

VS_0

Reserved —

VWU_9

VWU_8

VWU_7

VWU_6

VWU_5

VWU_4

VWU_3

VWU_2

VWU_1

VWU_0

Binary coded voltage at WU pin (bit0 = LSB; bit9 = MSB)

00 0000 0000: 0V xx xxxx xxxx: V

AINVS

/1023 x register value 

11 1111 1111: V

AINVS

Bits cannot be cleared.

DS13220 Rev 5 191/198

197

SPI registers L99DZ200G

7.5.10 Status Register SR12 (0x3C)

Figure 89. Status Register SR12 (0x3C)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R

Bit

23:6

5

4

3

2

1:0

Name

Reserved

CAN_SILENT

Reserved

Table 124. SR12 signals description

Description

—

Online monitoring bit to see if there is silence on the bus for longer than t Silence

This flag shows the actual status of the CAN bus (activity/silence). A microcontroller in Stop mode may check this flag periodically

--

CANTO

CAN communication timeout

Bit is set if there is no communication on the bus for t > t

Silence

CANTO indicates that there was a transition from TRX BIAS to TRX Sleep Bit is latched until a read and clear access

WUP

Wake up flag for Wake up Pattern

Bit is latched until a read and clear access

Reserved --

192/198 DS13220 Rev 5

L99DZ200G

8 Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

8.1 LQFP-64 package information

Figure 90. LQFP-64 package dimension

Symbol

Θ

Θ1

Θ2

Θ3

GAPG2907151212CFT

Table 125. LQFP-64 mechanical data

Millimeters/Degrees

Min.

0º

0º

11º

11º

Typ.

3.5°

9°

12°

12°

DS13220 Rev 5

Max.

6°

12°

13°

13°

193/198

197

Symbol

E

E1

E2

E3

D1

D2

D3 e b1 c c1

D

A

A1

A2 b

R1

R2

S

L

L1

N aaa bbb ccc ddd

Package information

Table 125. LQFP-64 mechanical data (continued)

Millimeters/Degrees

Min.

Typ.

0.05

1.35

0.17

0.09

0.09

1.40

0.20

0.127

12.00 BSC

10.00 BSC

5.7

0.50 BSC

12.00 BSC

10.00 BSC

3.3

0.45

0.60

1.00

64

0.08

0.08

0.20

Tolerance of form and position

0.20

0.20

0.08

0.08

L99DZ200G

Max.

1.60

0.15

1.45

0.27

0.23

0.20

0.16

6.85

4.79

0.75

0.20

194/198 DS13220 Rev 5

L99DZ200G

Figure 91. LQFP-64 footprint

Package information

8.2 LQFP-64 marking information

Figure 92. LQFP-64 marking information

Marking area

Marking area or

Special function digits

ES: Engineering sample

<blank>: Commercial sample

GAPG2907151243CFT

LQFP-64 TOP VIEW

(not in scale)

GADG1105161103MAG

Parts marked as ES are not yet qualified and therefore not approved for use in production.

ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

DS13220 Rev 5 195/198

197

Order code

9 Order code

Package

LQFP-64 epad

L99DZ200G

Table 126. Ordering information

Order codes

Tape & Reel

L99DZ200GTR

Tray

L99DZ200G

196/198 DS13220 Rev 5

L99DZ200G

10 Revision history

Revision history

Date

16-Jan-2020

08-Oct-2020

23-Nov-2020

26-Mar-2021

06-Apr-2021

Revision

Table 127. Document revision history

Changes

1

2

3

4

5

Initial release.

Updated:

– Figure 3: Activation profile ;

–

Figure 4: Activation profile (first cycle)

;

–

Figure 7: Watchdog timing

–

Figure 19: Sequence to disable/enable the watchdog in CAN Flash mode

;

–

Figure 61: Typical application diagram

;

– Table 112: CR21 signals description .

Minor text changes.

Updated Table 5: Temperature Warning and Thermal Shutdown ,

Table 10: Voltage regulator V1 , Table 18: Power outputs switching times

,

Table 19: Current monitoring

,

Table 27: Electro-chrome mirror driver

,

Figure 61: Typical application diagram

,

Table 122: SR10 signals description

,

Table 123: SR11 signals description

.

Updated:

–

Features

–

Table 3: ESD protection

–

Section 4.9.1: Features

–

Section 4.10.1: Features

– Add Section 9: Order code

Changed Figure 61

Typos.

DS13220 Rev 5 197/198

197

L99DZ200G

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2021 STMicroelectronics – All rights reserved

198/198 DS13220 Rev 5