STMicroelectronics SPSB081 Datasheet

SPSB081
Datasheet
Automotive power management IC with LIN and CAN-FD
Features
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Prerelease product(s)
QFN32L 5x5
Product status link
SPSB081
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Product summary
SPSB0815-TR
Order code
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SPSB0813-TR
SPSB081C5-TR
SPSB081C3-TR
Package
QFN32L
Packing
Tape and reel
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AEC-Q100 qualified
One 5 V (or 3.3 V for SPSB0813 and SPSB081C3) low drop voltage regulator
(V1) for microcontroller and peripheral supply
One configurable 5 V or 3.3 V low drop voltage regulator V2 selectable via SPI,
tracker for V1
Minimum current limitation of 450 mA for V1 and 400 mA for V2
No electrolytic capacitor required on regulator outputs
Very low quiescent current in standby modes (typ. 15 µA)
Programmable reset generator for power-on and undervoltage
Configurable Window Watchdog
LIN transceivers ISO 17987-4/2016 and SAE J2962-1 (draft nov. 2017)
compliant (only for SPSB0815 and SPSB0813)
CAN-FD transceiver (ISO 11898-2/2016, SAE J2284 and SAE J2962-2 (draft
nov. 2017) compliant) with local failure and bus failure diagnosis
Complete 2-channel contact monitoring interface (WU1 and WU2 input pins)
with programmable cyclic sense functionality. WU2 also with DIR functionality
Programmable periodic system wake-up feature
STM standard serial peripheral interface (32Bit / ST-SPI)
4 HS drivers for 0.14A (RON = 7 Ω) suitable to drive external LED modules with
high input capacitance value or to also supply external contacts
Internal 10bit PWM timer for each stand-alone high-side driver
Buffered supply for all voltage regulators
DIAGN output pin for fail-safe signalization
Current monitor output for all internal high-side drivers
Open-load diagnosis for all outputs
Overcurrent protection for all outputs
V1 overvoltage detection and protection
Device contains temperature warning and protection
Thermal cluster
Limited documentation available for customers that need support when dealing
with ASIL requirements as per ISO 26262
Applications
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Body control modules (BCM)
Gateway applications
Telematic control unit
Passive keyless entry and start modules
Control panel
Heating, ventilation and air conditioning (HVAC)
Seat control modules
Sunroof modules
Tailgate modules
DS14048 - Rev 1 - October 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
SPSB081
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Door modules
Light control modules
Gear shifters
Steering column
Fuel pump
Description
Prerelease product(s)
The SPSB081 is a power management system IC providing electronic control modules with enhanced
power management functionality, including various standby modes to minimize the power consumption with
programmable local and remote wake-up capability, as well as LIN (only for SPSB0815 and SPSB0813) and
CAN FD physical communication layers. The device has one low-drop voltage regulator to supply the system
microcontroller and one voltage tracker to supply external peripheral loads such as sensors. V1 is available with
a fixed rail (5 V or 3.3 V) and V1 overvoltage detection and protection solution, while V2 is a tracker voltage
regulator of V1, programmable by SPI with 5 V or 3.3 V. Moreover, the device features four high-side drivers to
supply LEDs and sensors. All outputs are short-circuit (SC) protected and implement open-load diagnosis. The
ST standard SPI interface allows control and diagnosis of the device and enables generic software development.
DS14048 - Rev 1
page 2/135
SPSB081
Block diagram and pin description
1
Block diagram and pin description
1.1
Block diagram
Prerelease product(s)
Figure 1. Functional block diagram of SPSB0815 and SPSB0813
DS14048 - Rev 1
page 3/135
SPSB081
Block diagram
Prerelease product(s)
Figure 2. Functional block diagram of SPSB081C5 and SPSB081C3
DS14048 - Rev 1
page 4/135
SPSB081
Pin description
1.2
Pin description
NC
VSREG
NC
CAN_L
VCANSUP
CAN_H
LIN
32
PGND
Figure 3. Pin connection SPSB0815 and SPSB0813 (top view)
1
WU1
V1
DIR/WU2
NRESET
V2
CSN
OUT4
DI
OUT3
DO
OUT2
CLK
Prerelease product(s)
NINT
CM
DIAGN
TxD_L
SGND
TxD_C
RxD_C
NC
RXD_L
VS
DEBUG
OUT1
NC
VSREG
NC
VCANSUP
CAN_L
CAN_H
NC
32
PGND
Figure 4. Pin connection SPSB081C5 and SPSB081C3 (top view)
1
WU 1
V1
DIR/WU2
NRESET
V2
CSN
OUT4
DI
OUT3
DO
OUT2
CLK
OUT1
NC
RxD_C
NINT
CM
DIAGN
NC
SGND
TxD_C
NC
DEBUG
VS
Table 1. Pin function
DS14048 - Rev 1
Pin SPSB081x
Pin SPSB081Cx
Pin name
1
1
WU1
2
2
3
Description
I/O type
Wake-up inputs 1: Input pin for static or cyclic
monitoring of external contacts
I
DIR/WU2
DIR -> direct HS drive; WU2 -> input pin for static or
cyclic monitoring of external contacts
I
3
V2
Voltage regulator 2 or tracker 2 output: 5 V or 3.3V
supply for external loads or CAN FD transceiver. V2
pin is protected against reverse supply
O
4
4
OUT4
High-side-driver output to drive LEDs, sensors or to
supply contacts
O
5
5
OUT3
High-side-driver output to drive LEDs, sensors or to
supply contacts
O
6
6
OUT2
High-side-driver output to drive LEDs, sensors or to
supply contacts
O
7
7
OUT1
High-side-driver output to drive LEDs, sensors or to
supply contacts
O
page 5/135
SPSB081
Pin description
Prerelease product(s)
Pin SPSB081x
Note:
DS14048 - Rev 1
Pin SPSB081Cx
Pin name
Description
I/O type
8
8
VS
Power supply voltage for power stage outputs
OUT1, OUT2, OUT3, and OUT4 (external reverse
battery protection required). For this input, a
ceramic capacitor as close as possible to GND is
recommended.
9
9
NC
Not connected
10
10
Debug
Debug input to deactivate the window watchdog (high
active)
I
11
11
SGND
Signal ground
P
12
12
TxD_C
CAN transmit data input
I
13
-
TxD_L
LIN transmit data input
I
Current monitor output: depending on the selected
multiplexer bits of the control register this output
sources an image of the instant current through the
corresponding high side driver with a fixed ratio
O
Logical error indication output. Active low
O
P
14
14
CM
15
15
DIAGN
16
16
NINT
indicates device errors, warning, and local/remote
wake-up events
O
17
17
RxD_C
CAN receive data output (push pull output stages)
O
18
-
RxD_L
RxDL -> LIN receive data output (only for SPSB0815
and SPSB0813)
O
19
19
CLK
SPI: serial clock input
I
20
20
DO
SPI: serial data output (push pull output stage)
O
21
21
DI
SPI: serial data input
I
22
22
CSN
SPI: chip select not input
I
23
23
NRESET
NReset output to microcontroller; internal pull-up of
typical 25 kΩ (active low output stage)
O
24
24
V1
Voltage regulator 1 output: 5 V or 3.3V supply, e.g.,
microcontroller, CAN FD transceiver
O
25
25
NC
Not connected
Power supply voltage to feed the internal voltage
regulators; all internal regulated voltages for analog
and digital functionality; LIN transceiver; CAN
transceiver and the wake-up features (external
reverse battery protection required / diode). For this
input, a ceramic capacitor as close as possible
to GND and an electrolytic backup capacitor are
recommended.
26
26
VSREG
P
27
27
NC
28
28
VCANSUP
29
29
CAN_L
CAN low level voltage I/O
I/O
30
30
CAN_H
CAN high level voltage I/O
I/O
31
31
PGND
Power ground
32
-
LIN
LIN bus line
-
-
TAB
Ground connection
Not connected
CAN supply input; to allow external CAN supply from
V1, V2 or other external power supply
P
P
I/O
Not connected pins must be connected to ground.
page 6/135
SPSB081
Maximum ratings
2
Maximum ratings
2.1
Operating range
Within the operating range, the part operates as specified and without parameter deviations. The device may not
operate properly if maximum operating conditions are exceeded.
Once taken beyond the operative ratings and returned back within, the part recovers with no damage or
degradation.
Additional supply voltage and temperature conditions are given separately at the beginning of each electrical
specification table.
All the voltages are related to the potential at substrate ground.
2.1.1
Supply voltage ranges
Prerelease product(s)
All SPI communication, logic, and oscillator parameters work down to VSREG = 3.5V and are specified
accordingly.
2.2
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SPI thresholds
Oscillator frequency (delay times correctly elapsed)
Internal register status correctly kept (reset at default values for Vs< VPOR)
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Reset threshold correctly detected
Absolute maximum ratings
Maximum ratings are absolute ratings; exceeding any one of these values may cause permanent damage to the
integrated circuit.
All voltages are related to the potential at substrate ground.
Table 2. Absolute maximum ratings
Symbol
VS
DS14048 - Rev 1
Parameter
DC supply
voltage
Condition
Min
Jump start
Typ
Max
Unit
-0.3
28
V
Single pulse /
tmax < 400 ms
“transient load
dump”
-0.3
40
V
Jump start
-0.3
28
V
Single pulse /
tmax < 400 ms
“transient load
dump”
-0.3
40
V
V1 < VSREG
-0.3
6.5
V
VSreg
DC supply
voltage
V1
Stabilized supply
voltage, logic
supply
V2
Stabilized supply
voltage(1)
-0.3
28
V
VDI
Logic input
-0.3
V1+0.3
V
VCLK
Logic input
-0.3
V1+0.3
V
VCSN
Logic input
-0.3
V1+0.3
V
VDO
Logic output
-0.3
V1+0.3
V
VRXDL
Logic output
-0.3
V1+0.3
V
VRXDC
Logic output
-0.3
V1+0.3
V
VNRESET
Logic output
-0.3
V1+0.3
V
page 7/135
SPSB081
Prerelease product(s)
Absolute maximum ratings
DS14048 - Rev 1
Symbol
Parameter
VCM
Output voltage
range
VDIAGN
Condition
Min
Typ
Max
Unit
-0.3
V1+0.3
V
Logic output
-0.3
V1+0.3
V
VTXDC
Logic input
-0.3
V1+0.3
V
VTXDL
Logic input
-0.3
V1+0.3
V
Vdebug
Debug input pin
voltage range
-0.3
V1+0.3
V
VWU1
DC wake-up
input voltage
-0.3
VSreg +0.3
V
VDIR/WU2
DC wake-up
input voltage
-0.3
VSreg +0.3
V
VLIN
LIN bus I/O
voltage range
-27
40
V
IInput
Current injection
into Vs related
input pins
20
mA
Iout_inj
Current injection
into vs related
outputs
20
mA
VCANSUP
CAN supply
-0.3
5.25
V
VCANH
CAN bus I/O
voltage range
-27
40
V
VCANL
CAN bus I/O
voltage range
-27
40
V
VCANH - VCANL
Differential CANBus voltage
-5
10
V
VOUT1
Output voltage
-0.3
VS+0.3
V
VOUT2
Output voltage
-0.3
VS+0.3
V
VOUT3
Output voltage
-0.3
VS+0.3
V
VOUT4
Output voltage
-0.3
VS+0.3
V
IVS
Maximum
cumulated
current at VS
drawn by OUT1;
OUT2; OUT3;
OUT4
-1.25
1.25
A
IVSREG
Maximum
cumulated
current at
VSREG drawn
by LDO1; LDO2;
LIN;
CAN@Wake-up
-1.25
1.25
A
IOUT1
Output current (2)
-1.25
1.25
A
IOUT2
Output current (2)
-1.25
1.25
A
IOUT3
Output current (2)
-1.25
1.25
A
IOUT4
Output current (2)
-1.25
1.25
A
ISGND
Maximum current
at SGND(2)
-1.25
1.25
A
page 8/135
SPSB081
Absolute maximum ratings
Symbol
Parameter
IPGND
Maximum current
at PGND(2)
GND pins
PGND versus
SGND
Condition
Min
Typ
Max
Unit
-1.25
1.25
A
-0.3
0.3
V
1. SPSB081 is protected against V2 shorted to VSREG and V2 reverse biasing when VSREG is higher than 3.5 V.
2. Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power
dissipation or other limits.
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible
damage of the integrated circuit!
Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents
only. If external loads are connected to different grounds, the current load must be limited to this nominal current.
Prerelease product(s)
Table 3. ESD protection
Item
Parameter
Condition
Values
Unit
Pins
All pins
HBM (1)
+/-2
kV
Power output pin
OUT1
HBM (2)
+/-4
kV
OUT2
HBM
(2)
+/-4
kV
Power output pin
OUT3
HBM(2)
+/-4
kV
Power output pin
OUT4
HBM(2)
+/-4
kV
Air discharge (3)
+/-25
kV
HBM (2)
+/-8
kV
Indirect ESD(4)
+/-8
kV
+/-6
kV
+/-15
kV
HBM l (2)
+/-8
kV
Direct ESD (5)
+/-6
kV
Air discharge (6)
+/-15
kV
HBM(2)
+/-8
kV
+/-6
kV
+/-500 / (+/-750)
V
Power output pin
Transceiver
LIN
Direct
ESD(5)
Air discharge
Transceiver
Transceiver
CAN_H
CAN_L
Direct
Pins
(7)
Corner pins
(6)
ESD(5)
CDM (values for corner pins in brackets)
1. HBM (human body model, 100pF, 1.5 kW) according to AEC-Q100-002
2. HBM with all none zapped pins grounded
3. Air discharge for LIN (according to SAE J2962-1 (DRAFT. Nov. 2017)) C = 150pF, R = 2 kΩ.
4. Indirect ESD test according to IEC 61000-4-2 (150pF, 330Ω) and ‘Hardware requirements for LIN, CAN and Flexray
interfaces in automotive applications’ (version 1.3, 2012-05-04)
5. Direct ESD test according to IEC 61000-4-2 (150pF, 330Ω) and ‘Hardware requirements for LIN, CAN and Flexray
interfaces in automotive applications’ (version 1.3, 2012-05-04)
6. Air discharge for CAN (according to SAE J2962-2) C = 330pF, R = 2 KΩ
7. CDM (charged device model) according to AEC-Q100-011
DS14048 - Rev 1
page 9/135
SPSB081
Temperature ranges and thermal data
Table 4. Transient immunity ratings according to ISO 7637-2
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PARAMETER
ISO 7637-2 and IEC 62215-3 transients
immunity according to
“OEM_HW_Requirements_For_CAN_LIN_
FR-Interfaces_V1.3_2012” and IBEE EMC
test specifications (1) (LIN and CAN)
VALUE
UNIT
Pulse1
-100
V
Pulse2a
+75
V
Pulse3a
-150
V
Pulse3b
+100
V
1. ISO 7637 is a system level transient test. Different system level configurations may lead to different results.
2.3
Temperature ranges and thermal data
Prerelease product(s)
Table 5. Temperature ranges and thermal data
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
Tamb
Operating temperature
(ECU environment)
-
-40
-
125
°C
F.019
Tj
Operating junction
temperature
-
-40
-
175
°C
F.020
Tstg
Storage temperature
-
-55
-
150
°C
F.021
TW ON
Thermal over
temperature warning
threshold
-
140
-
160
°C
F.022
TSD1 OFF (1)
Thermal shut-down
junction temperature 1
-
165
-
185
°C
F.023
TSD2 OFF (1)
Thermal shut-down
temperature
-
175
-
195
°C
F.024
TSD12hys (1)
Thermal shut-down
temperature hysteresis
-
-
5
-
°C
F.025
tfTjTW
Thermal warning / shut
down filter time
Tested by scan
24
32
43
µs
F.026
RTh jamb (2)
Thermal resistance
junction-to-ambient
-
-
38
-
°C/W
F.027
1. Non-overlapping
2. The values quoted are for PCB 129 mm x 60 mm x 1.6 mm, FR4, four layers; Cu thickness 0.070 mm (outer layers). Cu
thickness 0.035 mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness
on vias 0.025 mm, footprint dimension 3.5 mm x 3.5 mm
All parameters are guaranteed in the temperature range from -40 to 50°C (unless otherwise specified); the device
is still operative and functional at higher temperatures (up to 175°C).
Parameters limits at higher temperatures than 150°C may change with respect to what is specified as per the
standard temperature range.
Device functionality at high temperature is guaranteed by characterization.
SPSB081 embeds a multitude of junctions housed in a relatively small piece of silicon. The devices contain,
among all the described features, four high-sides, two voltage regulators (one of which can work as voltage
tracker). For this reason, using the thermal impedance of a single junction (that is, voltage regulator or major
power dissipation contributor) does not allow to predict thermal behavior of the whole device and therefore it is
not possible to assess if a device is thermally suitable for a given activation profile and loads characteristics.
Some representative and realistic worst-case thermal profiles are described in the below paragraph. The following
measurement methods can be easily implemented, by final user, for a specific activation profile.
Activation profile battery voltage: 16 V, ambient temperature starts at 85°C.
DC activation:
DS14048 - Rev 1
•
V1 (3.3V) charged with 70 mA; Rdson = 470 Ω (DC activation)
•
V2 (3.3V) charged with 50 mA; Rdson = 680 Ω (DC activation)
page 10/135
SPSB081
Temperature ranges and thermal data
•
OUT1: Iload = 50 mA; Rdson = 330 Ω (DC activation)
•
OUT2: Iload = 50 mA; Rdson = 330 Ω (DC activation)
•
OUT3: Iload = 50 mA; Rdson = 330 Ω (DC activation)
•
OUT4: Iload = 50 mA; Rdson = 330 Ω (DC activation)
•
CAN-LIN not relevant
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation” sequence is applied. The
device operates always without triggering the thermal warning threshold.
Prerelease product(s)
Figure 5. QFN32L 5x5 4-layers
Note:
DS14048 - Rev 1
PCB 129 mm x 60 mm x 1.6 mm, FR4, four layers; Cu thickness 0.070 mm (outer layers). Cu thickness 0.035
mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on
vias 0.025 mm, footprint dimension 3.5 mm x 3.5 mm.
page 11/135
SPSB081
Functional description
3
Functional description
3.1
Supply Vs, Vsreg
VSREG supplies voltage regulators V1 and V2, all internal regulated voltages for analog and digital functionality,
LIN, CAN and the wake-up features. P-channel high side switches OUT1, OUT2, OUT3, OUT4 and fail-safe block
are supplied by VS. In case of VSREG pin disconnected, all power devices connected to VS are automatically
switched OFF.
Note:
After device startup, it is suggested to perform a status registers read&clear command to clean any spurious
error flags.
3.2
Voltage regulators
Prerelease product(s)
The SPSB081 contains one fully protected low drop voltage regulator (V1) and one low dropout tracking regulator
(V2), which are designed for very fast transient response and do not require electrolytic output capacitors for
stability. The two low drops out voltage regulators can provide 5 V or 3.3 V; the following table summarizes the
possible configurations of the two LDOs:
Table 6. Voltage regulators configuration
Configuration
P/N
1
SPSB0813
2
SPSB081C3
3
SPSB0815
4
SPSB081C5
V1 output voltage
(linear case)
3.3 V
5.0 V
V2 output voltage
(linear case)
V2 output voltage
(tracking case)
V2_TKR
3.3 V(1)
YES
0 or 1
5.0 V
Not available
only 0
3.3 V
Not available
only 0
5.0 V
YES
0 or 1
1. In this case, the CAN transceiver embedded inside the SPSB0813 shall be supplied by an external VREG at 5V via the CAN
supply pin.
The voltage regulator V2 can be configured by means of the V2_TKR bit in CR2 as a linear independent LDO
(V2_TKR=0, default) or as a tracker of the V1 voltage regulator (V2_TKR=1).
3.2.1
Voltage regulator: V1
The V1 voltage regulator provides 5 V (for SPSB0815 and SPSB081C5) or 3.3 V (for SPSB0813 and
SPSB081C3) supply voltage (configurable by OTP) and up to 250 mA continuous load current to supply
the system microcontroller and the integrated CAN transceiver. The V1 regulator is embedded in the power
management and fail-safe functionality of the device and operates according to the selected operating mode. The
V1 voltage regulator is supplied by pin VSREG.
In addition, the V1 regulator supplies the device internal loads. The voltage regulator is protected against overload
and overtemperature. An external reverse current protection must be provided by the application circuitry to
prevent the input capacitor from being discharged by negative transients or low input voltage. Current limitation
of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load
capacitors ≥ 1µF.
In case the device temperature exceeds the TSD1 threshold, all outputs (OUTx, V2, LIN, CAN) are deactivated
except V1 regulator, which remains on. LIN and CAN transceivers are forced in "receive only" mode. Hence, the
microcontroller has the possibility for interaction or error logging. If the chip temperature exceeds TSD2 threshold
(TSD2>TSD1), V1 is deactivated and all wake-up sources (CAN, LIN, WU1, WU2, and timer) are disabled. After
tTSD, the voltage regulator will restart automatically. If the restart fails seven times within one minute the SPSB081
is forced into VBAT_standby mode. The status bit in SR1 Forced_Sleep_TSD2/V1SC is set.
In case of overvoltage an internal pulldown circuit is activated to limit the current accumulated in the external
capacitor.
DS14048 - Rev 1
page 12/135
SPSB081
Voltage regulators
3.2.2
Voltage regulator: V2
The SPSB081 embeds one 5 V or 3V3 (configurable by V2_RAIL bit in CR2) low dropout tracking regulator
designed to provide an output voltage that closely tracks (±20 mV) the V1 reference input while delivering on the
V2 output pin up to 100 mA. The voltage regulator V2 can be configured by means of the V2_TKR bit in CR2 as a
linear independent LDO (V2_TKR=0, default) or as a tracker of the V1 voltage regulator (V2_TKR=1).
The V2 can be configured as tracker of the V1 only at the same voltage output level 5 V for SPSB0815 and
SPSB081C5 (Conf #4 in Table 6) and 3.3 V for the SPSB0813 and SPSB081C3 (Conf #1 in Table 6). The tracking
regulator is protected against:
•
•
•
•
3.2.3
overload
overtemperature
short-circuit (short to ground and battery supply voltage)
reverse biasing
Voltage regulator failure
Prerelease product(s)
The V1 and V2 regulators output voltages are monitored.
In case of a drop below the V1, V2 fail thresholds (V1,2 < V1,2fail, for t > tV1,2fail), the failure bits V1FAIL, V2FAIL
(SR 2) are latched. The fail bits can be cleared by a dedicated SPI command.
3.2.4
Short to ground detection
At turn-on of the V1 and V2 regulators, a short to GND condition is detected by monitoring the regulator output
voltage.
If V1 or V2 is below the V1fail,(V2fail) thresholds for t>tv1short (t>tV2short) after turn-on, the SPSB081 will identify a
short-circuit condition at the related regulator output and the regulator will be switched off.
In case of V1 short to GND the device enters VBAT_standby mode automatically.
Bits FORCED_SLEEP_TSD2/V1SC (SR1) and V1FAIL (SR2) are set.
In case of a V2 short to GND failure the V2SC (SR2) and V2FAIL (SR2) bits are set.
Once the output voltage of the corresponding regulator exceeds the V1fail (V2fail) thresholds the short-to-ground
detection is disabled. In case of a short-to-ground condition, the regulator is switched off due to thermal
shutdown.
DS14048 - Rev 1
page 13/135
SPSB081
Operating modes
3.2.5
Voltage regulator behavior
Prerelease product(s)
Figure 6. Voltage regulator behavior and diagnosis during supply voltage ramp-up / ramp-down
conditions
3.3
Operating modes
The device can be operated in four different operating modes:
•
•
•
•
3.3.1
Active mode: normal operating mode
SW-debug mode: software debugging
V1_standby mode: low power mode
VBAT_standby mode: ultralow power mode
Active mode
All functions are available, and the device is controlled by SPI.
3.3.2
SW-debug mode
To allow software debugging, the watchdog can be deactivated by applying an external voltage to the DEBUG
input pin (Vdebug > VdiH).
In debug mode, all device functionality is available, including CAN, which is enabled by default. The watchdog is
deactivated.
At exit from debug mode (Vdebug < VdiL) the watchdog starts with a long open window.
Note:
DS14048 - Rev 1
The device includes a test mode that is activated by a dedicated sequence including, among others, a high
voltage at the debug pin; debug mode is not intended for normal applicative conditions.
page 14/135
SPSB081
Operating modes
Prerelease product(s)
3.3.3
V1_standby mode
The transition from active mode to V1_standby mode is controlled by SPI (STBY_SEL bit and GO_STBY bit in
CR2).
To supply the microcontroller in a low power mode, the V1 voltage regulator remains active.
After the V1_standby command (CSN low to high transition), the device enters V1_standby mode immediately
and the watchdog starts a long open window (tLW). The watchdog is deactivated as soon as the V1 load current
drops below the icmp threshold (Iv1 < Icmp).
The V1 load current monitoring can be deactivated by setting ICMP=1. In this configuration, the watchdog is
deactivated upon transition into V1_standby mode without monitoring the V1 load current.
Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting ICMP_CONFIG_EN (Config
Reg) = 1. The ICMP_CONFIG_EN bit is reset to ‘0’ automatically with next SPI command.
LIN and CAN transmitters are switched off in V1_standby mode.
OUT1, OUT2, OUT3, and OUT4 remain in the configuration programmed before the standby command.
V2 voltage regulator remains in the configuration programmed before the standby command. Even though LIN
and CAN transceivers are switched off, they can still wake up the micro (see Table 7. Wake-up source).
In V1_standby mode various wake-up sources can be individually programmed. Normally a wake-up event puts
the device into active mode and forces the NINT pin to a low level indicating the wake-up condition to the
microcontroller. Writing IWK (CR 34) = 1 a wake-up event on CAN and wake up pins forces NINT pin to a low
level indicating the wake-up condition to the microcontroller. However, no change in the SBC mode occurs.
3.3.4
Interrupt
The interrupt signal on NINT pin is generated to communicate a specific event to the microcontroller. NINT is
pulled low after a reaction time when one of the following events occurs.
In active mode, this event can be related to each one of the status flags latched in the global status byte register
(GSBN bit).
A bit register is available to mask each one of these flags:
•
•
•
•
•
RSTB: MASK_RSTB (0x3F)
PLE: MASK_PLE (0x3F)
FE: MASK_FE (0x3F)
DE: MASK_DE (0x3F)
GW: MASK_GW (0x3F)
These masks are common for the generation of GSBN, NINT, and DIAGN (in extended mode).
NINT pulse can also be related to the CAN communication timeout event (no CAN communication for t > tSilence).
The CANTO flag is set. This interrupt can be masked by CANTO_NINT_MASK SPI bit.
In V1 standby mode, it can also be related to the following events:
•
•
CAN communication timeout (no CAN communication for t > tSilence). The CANTO flag is set. This interrupt
can be masked by CANTO_NINT_MASK SPI bit.
Wake-up from V1_standby mode by any wake-up source (WU1, WU2, LIN, CAN, TIMER1/2, SPI). This
interrupt can be masked by WU_NINT_MASK SPI bit.
In case of increasing V1 load current during V1_standby mode (Iv1 > Icmp), the device remains in standby mode
and the watchdog starts with a long open window. No interrupt signal is generated.
NINT pin is an open drain structure to allow multiple connections.
DS14048 - Rev 1
page 15/135
SPSB081
Wake-up from standby modes
Figure 7. Interrupt pin
V1
ESD prot
110KΩ
Data Out
Data In
Digital
logic
GND
GND
GAPG1609151103CFT
Prerelease product(s)
3.3.5
VBAT_standby mode
The transition from active mode to VBAT_standby mode is initiated by an SPI command (STBY_SEL bit and
GO_STBY bit in CR2).
In VBAT_standby mode, the voltage regulators V1 and V2, the power outputs as well as LIN and CAN
transmitters are switched off.
An NReset pulse is generated and last asserted low upon wake-up from VBAT_standby mode and until 2ms after
LDO1 is fully operative.
3.4
Wake-up from standby modes
A wake-up from standby mode switches the device to active mode. This can be initiated by one or more of the
following events:
Table 7. Wake-up source
Wake-up source
Description
LIN bus activity
It can be disabled by SPI
CAN bus activity
It can be disabled by SPI
Level change of WU
IV1 > Icmp
It can be configured or disabled by SPI
The device remains in V1_standby mode but watchdog is enabled (if ICMP = 0).
No interrupt is generated.
Programmable by SPI:
- V1_standby mode:
Timer interrupt /
Wake-up of μC by TIMER
device wakes up and interrupt signal is generated at NINT when
programmable time-out has elapsed
- VBAT_standby mode: device wakes up after programmable timer expiration. V1 regulator
is turned on and NReset signal is generated when programmable time-out has elapsed
SPI access
Always active (except in VBAT_standby mode)
Wake-up event: CSN falling edge
To prevent the system from a deadlock condition (no wake-up from standby possible) a configuration where all
wake-up is disabled, is not allowed.
Accordingly, if the following condition is set by SPI:
•
•
•
•
CAN_WU_EN = 0
LIN_WU_EN = 0
WU1_EN = 0
WU2_EN = 0
The effect is to put all these register bits in their default condition:
•
DS14048 - Rev 1
CAN_WU_EN = 1
page 16/135
SPSB081
Wake-up from standby modes
•
•
•
LIN_WU_EN = 1
WU1_EN = 1
WU2_EN = 1
For SPSB081C devices (without LIN), at least one of these WU sources has to be kept (CAN, WU1 or WU2).
All wake-up sources are configured to default values in case of such invalid setting. The SPI error bit (SPIE) in the
global status register is set.
3.4.1
Wake-up inputs
The WU1 and WU2 inputs can be configured as wake-up sources. Each wake-up input is sensitive to any
level transition (positive and negative edge) and can be configured for static or cyclic monitoring of the input
voltage level by suitable setting of CR1 [8..11] bits (WUx_FILT_0 and WUx_FILT_1) which allows to choose the
monitoring among static, cyclic with timer 1 or cyclic with timer 2. When the configuration of a timer is changed,
the timer is automatically restarted using the new configuration.
For static contact monitoring, a filter time of tWU_stat is implemented. The filter is started when the input voltage
passes the specified threshold Vwuthp. Wake-up status bit (WUx_STATE bit in SR5 [18..19]) is set only if this
threshold is passed for more than tWU_stat.
Prerelease product(s)
Cyclic contact monitoring, conceived to reduce the quiescent current of the device, allows instead periodical (not
threshold dependent) activation of the wake-up input to read the status of the external contact. The periodical
activation is driven by timer 1 or timer 2 whose settings (on-time and period) can be configured through CR2
[8..13] and [16..21] bits (Tx_PER_y and Tx_ON_y bit). The input signal is filtered with a filter time of tWU_cyc after
a delay (80% of the configured timer on-time). A wake-up will be processed if the status has changed versus
the previous cycle, therefore wake-up status bit (WUx_STATE bit in SR5 [18..19]) is set only if status during
consecutive on-time is different, after the configured delay and tWU_cyc.
The buffered outputs OUT1, OUT2, OUT3, and OUT4 can be used to supply the external contacts with the timer
setting according to the cyclic monitoring of the wake-up input.
I n pu t Vol t ag e
at WUx
Figure 8. Static monitoring: wake-up occurs if threshold is greater than the filter time
No Wake Up
Event
t < 64µs
0.55 * VS
t = 64 µ s
t = 64 µ s
1V
SS
Reduced Quiescent Current!
SS
t
Internal Wake-up requests identified
 Start to oscillator and precise comparator
SS
200µA
(typ)
7µA
(typ)
WU In p u t
St at u s B it
SS
SS
SS
SS
t
GAPG1009151518CFT
DS14048 - Rev 1
page 17/135
SPSB081
Functional overview (truth table)
Prerelease product(s)
Figure 9. Cyclic monitoring: the external contacts are supplied periodically by the internal timer
In standby modes, the inputs are configurable with an internal pull-up or pull-down current source according to
the setup of the external contact. Moreover, in case of cyclic sensing, an internal pull-down resistor (RWU_act) is
periodically activated on each rising edge of the TIMER_ON. RWU_act is activated also for static wake-up, but in
this case it occurs just after WU request (see the figure above), keeping this condition for at least the filter time
tWU_stat (or more, if the WU is valid and the device enters in active mode).
In active mode, the inputs have in fact only the internal pull-down resistor and the input status can be read by SPI.
Static sense should be configured before the read operation is started to reflect the actual input level.
Being DIR/WU2_EN enable bit, in config register (0x3F), set to 0 by default, the DIR/WU2 pin is configured
as wake-up function. If DIR/WU2_EN enable bit is set to 1 the DIR/WU2 pin is a low voltage direct driving of
OUT1..4. Threshold is set in this case at 1.5 V.
3.5
Functional overview (truth table)
Table 8. Functional overview
Operating modes
Version
DS14048 - Rev 1
Function
Comments
Active mode
V1_standby static
mode (cyclic
sense)
VBAT_standby
static mode
(cyclic sense)
3.4.1
Voltage regulator
V1
VOUT=5V/3V3
On
On (1)
Off
3.4.2
Voltage regulator
V2
VOUT=5V/3V3
On/Off
On (2)/Off
On (2)/ Off
3.4.3
Reset generator
On
On
Off
3.4.4
Window watchdog
On
Off (On if IV1 >
Icmp and ICMP =
0)
Off
V1 monitor
page 18/135
SPSB081
Functional overview (truth table)
Operating modes
Prerelease product(s)
Version
Function
Comments
Active mode
V1_standby static
mode (cyclic
sense)
VBAT_standby
static mode
(cyclic sense)
Off
Active
Active(3)
Oscillator time
base
On/Off
On (2)/Off
On (2)/Off
LIN 2.2a
On (2)
Off
Off(4)
CAN FD
On/Off
Off(4)
Off(4)
3.4.9
Oscillator
On
On/Off
On/Off(6)
3.4.10
Vs monitor
On
On/Off (7)
On/Off (7)
3.4.11
OUT1 (P-channel
HS)
On/Off(2)
On/Off(2)
On/Off(2)
3.4.12
OUT2 (P-channel
HS)
On/Off(2)
On/Off(2)
On/Off(2)
3.4.13
OUT3 (P-channel
HS)
On/Off(2)
On/ Off(2)
On/ Off(2)
3.4.14
OUT4 (P-channel
HS)
On/Off(2)
On/ Off(2)
On/ Off(2)
3.4.15
Thermal shutdown
TSD2
On
On
Off
3.4.16
Thermal shutdown
TSD1x (for Pchannel HS)
On
On (8)
On/Off(2)
3.4.5
Wake-up
3.4.6
HS-cyclic supply
3.4.7
LIN
3.4.8
1. Supply the processor in low current mode.
2. According to SPI setting
3. Unless disabled by SPI
4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding
of internal filter time (if wake up by LIN or CAN is not disabled by SPI).
5. After power-on, the CAN FD transceiver is in ‘CAN Trx standby’ mode. It is activated by SPI command (CAN_ACT = 1)
6. ON, if is enabled at least one of the following: Cyclic sense, OUT1, OUT2, OUT3, OUT4, V2.
7. ON when at least one OUTx is enabled and OFF when OUTx are disabled.
8. V1, V2, OUT1, OUT2, OUT3, and OUT4 are thermal monitored.
DS14048 - Rev 1
page 19/135
SPSB081
Configurable window watchdog
Prerelease product(s)
Figure 10. Main operating modes
3.6
Configurable window watchdog
During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle.
After power-on or standby mode, the watchdog starts with a timeout (long open window tLW). The timeout allows
the microcontroller to run its own setup and then to start the window watchdog by setting TRIG=1. Later, the
microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area Tswx.
The trigger time is configurable by SPI.
A correct watchdog trigger signal will immediately start the next cycle.
After eight watchdog failures in sequence, the V1 regulator is switched off for tv1off. After seven additional
watchdog failures the V1 regulator is turned off permanently and the device is forced into VBAT_standby mode.
The status bit FORCED_SLEEP_WD (SR1) is set. A wake-up is possible by any activated wake-up source.
In case of a watchdog failure, the power outputs and V2 are switched off and the device enters fail-safe mode. All
control registers are set to their fail-safe values.
The following diagrams illustrate the watchdog behavior of the device. The diagrams are split into 3 parts. The
first diagram shows the functional behavior of the watchdog without any error. The second diagram covers the
behavior covering all the error conditions, which can affect the watchdog behavior. The third diagram shows the
transition in and out of debug mode. All three diagrams can be overlapped to get all the possible state transitions
under all circumstances. For a better readability, they were split in normal operating, operating with errors and
debug mode.
DS14048 - Rev 1
page 20/135
SPSB081
Configurable window watchdog
Prerelease product(s)
Figure 11. Watchdog in normal operating mode (no errors)
Figure 12. Watchdog with error conditions
DS14048 - Rev 1
page 21/135
SPSB081
Fail safe mode
Prerelease product(s)
Figure 13. Watchdog in debug mode
Note:
3.6.1
Whenever the device is operated without servicing the mandatory watchdog trigger events, a sequence
of 15 consecutive reset events is performed and the device is forced into Vbat_Stby mode with bit
FORCED_SLEEP_WD in SR1 set.
If the device is woken up after such a forced Vbat_Stby condition and the watchdog is still not serviced, the
device, after one long open watchdog window is reforced into the same Vbat_Stby mode until the next wake-up
event. In this case, an additional watchdog failure is generated, but the fail counter is not cleared, keeping the
maximum number of 15 failures. This sequence is repeated until a valid watchdog trigger event is performed by
writing TRIG=1.
Change watchdog timing
The watchdog trigger time can be configured by setting the WD_TIME (CR 2) bit. Writing to these bits is
only possible with the first SPI command after setting WD_CONFIG_EN = 1 (Config register (0x3F)). The
WD_CONFIG_EN bit is reset to 0 automatically with next SPI command.
When FAIL_SAFE is active, these SPI registers are not accessible. Therefore, the FAIL_SAFE status needs to be
cleared. In case of a WD_FAIL, the clear is performed by starting a long open window.
When a new configuration has been programmed, the watchdog behaves with the old configuration until the next
trig event.
The new value of WD_TIME is loaded in the watchdog module on the next trig event after the SPI configuration.
The following watchdog cycle uses the new programmed value.
3.7
Fail safe mode
3.7.1
Temporary failures
SPSB081 enters fail-safe mode in case of:
•
•
Watchdog failure
V1 failure (V1 < VRTx for t > tV1FS)
•
Thermal shutdown TSD2
The fail-safe functionality is also available in V1_Standby mode. During V1_Standby mode the fail-safe mode is
entered in the following cases:
•
•
Watchdog failure (if watchdog still running due to Iv1 > Icmp)
V1 failure (V1 < VRTx for t > tV1FS)
•
Thermal shutdown TSD2
In fail-safe mode, the device returns to a fail-safe state. The fail-safe condition is indicated to the system in the
global status byte. The conditions during the fail-safe mode are:
DS14048 - Rev 1
page 22/135
SPSB081
Fail safe mode
Prerelease product(s)
•
•
•
•
•
•
•
•
All outputs and V2 are turned off
All control registers are set to default values
Write operations to control registers are blocked until the fail-safe condition is cleared (see table below).
Only the following bits are not write-protected:
–
CR1 (0x01):
–
◦
TRIG
◦
CAN_ACT
CR2 (0x02):
–
◦
Timer settings (bits 8…13 and bits 16…21)
CR5 (0x05):
–
◦
OUT1_x (bits 0…2)
◦
OUT2_x (bits 4…6)
◦
OUT3_x (bits 8…10)
◦
OUT4_x (bits 12…14)
CR9 (0x09) to CR11 (0x0B)
–
◦
PWM frequency and duty cycles
Config register (0x3F)
◦
V2_0
◦
V2_1
LIN transmitter remains on
CAN FD transceiver remains on
Wake-up is enabled
Corresponding failure bits in status registers are set.
FS bit (bit 0 global status byte) is set
If the fail-safe mode was entered, it keeps active until the fail-safe condition is removed and the fail-safe was read
by SPI. Depending on the root cause of the fail-safe operation, the actions to exit fail-safe mode are as shown in
the following table.
Table 9. Temporary failures conditions
Failure source
Microcontroller
(oscillator)
Failure condition
Diagnosis
Watchdog
FS (global status byte) =1
Early write failure or expired
window
WDFAIL (SR1) =1
undervoltage
TRIG=1 during long open window
Read&Clear SR1
WDFAIL_CNT_x (SR1) = n+1
FS (global status byte) =1
V1
Exit from fail-safe mode
V1UV (SR1)=1 (1)
V1FAIL (SR2)=1 (2)
V1 > VRTx
Read&Clear SR1
FS (global status byte) =1
Temperature
Tj > TSD2
TW (SR2) =1
Tj < TSD2
TSD1 (SR1) =1
Read&Clear SR1
TSD2 (SR1) =1
1. bit V1UV in SR1 is set for t > tuv1 (16 µs). Fail-Safe bit GSR/FS is set only after trd (NRESET low pulse).
2. If V1 < V1fail (for t > tv1fail). The fail-safe bit is located in the global status register.
3.7.2
Non recoverable failures –Forced in VBAT_standby mode
If the fail-safe condition persists and all attempts to return to normal system operation fail, the SPSB081 is forced
into VBAT_standby mode to prevent damage to the system. The VBAT_standby mode can be terminated by any
wake-up source. The root cause of the VBAT_standby is indicated in the SPI status registers.
In VBAT_standby mode, all control registers are set to power on default.
The VBAT_standby mode is entered in case of:
DS14048 - Rev 1
page 23/135
SPSB081
Reset output (NRESET)
•
•
•
Multiple watchdog failures: FORCED_SLEEP_WD = 1 (15x watchdog failure)
Multiple thermal shutdowns 2: FORCED_SLEEP_TSD2/V1SC = 1 (7x TSD2)
V1 short at turn-on (V1 < V1fail for t > tv1short): FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
•
Loss of ground: SGNDLOSS(SR6) = 1
Table 10. Non recoverable failures conditions
Failure source
Microcontroller
(oscillator)
Failure condition
15 consecutive
watchdog failures
Diagnosis
FS (global status byte) =1
Wake-up
WDFAIL (SR 1) =1
TRIG=1 during long open
window Read&Clear SR1
FORCED_SLEEP_WD (SR 1) =1
FS (global status byte) =1
V1
Short at turn-on
V1FAIL=1
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Prerelease product(s)
V1
Overvoltage
Exit from fail-safe mode
Wake-up
Read&Clear SR1
FS (global status byte) =1
Wake-up
FORCED_SLEEP_V1OV (SR2) =1
Read&Clear SR2
FS (global status byte) =1
TW (SR 2) =1
Temperature
7 times TSD2
Wake-up
TSD1 (SR 1) =1
Read&Clear SR1
TSD2 (SR 1) =1
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
SGND
3.8
Loss of ground at SGND FS (global status byte) =1
pin
SGNDLOSS (SR 6) = 1
Wake-up
Read&Clear SR6
Reset output (NRESET)
At power-up, the reset signal is low. When Vs>VPOR, the RSTB bit is set and SPI registers are set to default
values. If V1 is turned on and the voltage exceeds the V1 reset programmable threshold VRTx by SPI, the reset
output “NRESET” is pulled up by internal pull-up resistor to V1 voltage after a reset delay time (trd). This is
necessary for a defined start of the microcontroller when the application is switched on. As soon as the NRESET
is released, the watchdog timing starts with a long open window. At power down, the device is reset, and control
registers are set to default values and RSTB bit is set to “1” (see the following figure).
Figure 14. NReset pin
110 kΩ
Data out
Data in
GAPG1609151103CFT
A reset pulse is generated in case of:
•
DS14048 - Rev 1
V1 drops below VRTx (configurable by SPI) for t > tuv1
page 24/135
SPSB081
DIAGN output
•
•
3.9
Watchdog failure
Turn-on of the V1 regulator (VSREG power-on or wake-up from VBAT_standby mode)
DIAGN output
Figure 15. DIAGN pin
110 kΩ
Data out
Prerelease product(s)
Data in
GAPG1609151103CFT
DIAGN pin can be directly connected to the microcontroller and it is pulled up to V1 voltage by internal pull-up
resistor.
DIAGN pin can be configured by DIAGN_EXT bit in normal mode or extended mode.
In default DIAGN configuration (DIAGN_EXT =0), DIAGN pin is set low if a failure considered in fail safe mode
occurs (for example, watchdog failure; V1 failure; thermal shutdown TSD2).
As soon as the FS error source is cleared, the signal is pulled up to V1 voltage.
In extended DIAGN configuration (DIAGN_EXT =1), DIAGN pin reflects one or more errors such as reported in
the GLOBAL STATUS BYTE register by global status bit not (GSBN) and it is set to low if at least one error
condition occurs.
A bit register is available to mask each one of GSBN flags:
•
•
•
•
•
RSTB: MASK_RSTB (0x3F)
PLE: MASK_PLE (0x3F)
FE: MASK_FE (0x3F)
DE: MASK_DE (0x3F)
GW: MASK_GW (0x3F)
Note:
DIAGN is automatically configured in normal mode (DIAGN_EXT =0) after a reset event.
3.10
V1 overvoltage detection
SPSB081 protects the MCU against voltages over 5 V (or 3V3) that could harm its functionalities. For this
purpose, to sink the exceeding current accumulated in the external capacitor usually directed to the MCU, the
SPSB081 uses an internal pulldown circuit, where output current flows through the pulldown resistor to ground.
If the bit V1_OVP=1 in CR2 the overvoltage protection circuits is enabled. If V1_OVP =0 there is no overvoltage
protection anymore.
DS14048 - Rev 1
page 25/135
SPSB081
V1 overvoltage detection
Prerelease product(s)
Figure 16. Overvoltage protection on V1
Two thresholds run the overvoltage event.
When SPSB081 detects an overvoltage event on the V1 pin:
•
•
If V1ov_th1≤ V1 < V1ov_th2 => V1_OV status flag is raised after tfilter1 and in the same time NINT is pulled low
for 56 μs.
If V1ov_th2 ≤ V1 < 6.5 V => It causes a Non Recoverable Failure and the device is forced to Vbat standby
mode (V1 is switched OFF and FORCED_SLEEP_V1OV (SR2) is raised after tOV1filter2). The internal
pull-down transistor which will discharge the decoupling capacitor through the Rdischarge is activated
If the Vbat stdby is caused by an output overvoltage on V1, the status flag stays set (V1_OV=1).
DS14048 - Rev 1
page 26/135
SPSB081
LIN bus interfaces (only for SPSB0815 and SPSB0813)
Prerelease product(s)
Figure 17. Overvoltage detection V1 = 5 V
3.11
3.11.1
LIN bus interfaces (only for SPSB0815 and SPSB0813)
Features
•
•
•
•
•
•
•
•
•
•
•
•
LIN ISO 17987-4/2016 compliant transceiver
Designed according to SAE J2962-1 (draft nov. 2017)
Meet OEM hardware requirements for CAN and LIN FR-Interfaces (version 1.3 2012)
Data rate up to 20 kbit/s
GND disconnection fail-safe at module level
Off mode: does not disturb network
GND shift operation at system level
Microcontroller interface with CMOS compatible I/O pins
Internal pull-up resistor
Transients immunity and ESD according to ISO7637-2, ISO 62215-3 and EN / IEC 61000-4-2.
Matched output slopes and propagation delay
Wake up behavior according to LIN2.2a and ‘Hardware requirements for LIN, CAN and Flexray interfaces
(version 1.3)
At VSREG > Vpor (that is, VSREG power-on reset threshold), the LIN transceiver is enabled.
The LIN transmitter is disabled in case of the following errors:
•
•
•
Dominant TxD_L time out
LIN permanent recessive
Thermal shutdown 1
–
with thermal sensor “Global” in mode “no cluster”
or with thermal sensor “Th_CL4” in mode “cluster”
•
•
VSREG overvoltage / undervoltage
V1 undervoltage
The LIN receiver is not disabled in case of any failure condition.
(it is reactivated in case of FS by thermal shutdown)
DS14048 - Rev 1
page 27/135
SPSB081
LIN bus interfaces (only for SPSB0815 and SPSB0813)
3.11.2
Error handling
Prerelease product(s)
The device LIN transceiver provides the following three error handling features.
3.11.2.1
Dominant TxD_L time out
If TXD_L is in dominant state (low) for t > tdom(TXDL) the transmitter is disabled, the related status bit
LIN_TXD_DOM (SR2) is set.
The transmitter remains disabled until the status bit is cleared.
The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN =0).
3.11.2.2
Permanent recessive
If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < tLIN the transmitter is
disabled, the status bit LIN_PERM_REC (SR2) is set.
The transmitter remains disabled until the status bit is cleared.
3.11.2.3
Permanent dominant
If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure is detected. The status bit
LIN_PERM_DOM (SR2) is set.
The transmitter is not disabled.
3.11.3
Wake-up from standby modes
In low power modes (V1_standby mode and VBAT_standby mode) the SPSB081 can receive two types of
wake-up signals from the LIN bus (configurable by SPI bit LIN_WU_config):
•
Recessive-Dominant-Recessive pattern with t > tdom_LIN (default, according to LIN 2.2a)
A dominant time of at least 150us must be identified as a wake-up. Shorter dominant times may wake up the
device.
•
State change recessive-to-dominant or dominant-to-recessive (according to LIN 2.1)
Note:
Dominant levels having duration less than a glitch filter time (it is defined 28 µs minimum, according to OEM
requirements version 1.3) have to be filtered and therefore they cannot wake up the device.
3.11.3.1
Pattern wake-up (default)
Figure 18. Wake-up behavior according to LIN 2.2a
3.11.3.2
DS14048 - Rev 1
Status change wake-up - Recessive-to-dominant
Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high)
state. A dominant level at LIN for tLINBUS switches the device to active mode.
page 28/135
SPSB081
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CAN FD bus transceiver
3.11.3.3
Status change wake-up - Dominant-to-recessive
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for
tLINBUS, switches the device to active mode.
3.12
CAN FD bus transceiver
3.12.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
3.12.2
ISO 11898-2:2016 compliant
CAN-FD cell has been designed according to “Hardware requirements for transceivers (version 1.3)”
Listen mode (transmitter disabled)
SAE J2284 compliant
Designed according to SAE J2962-2 (draft nov. 2017)
Supported bitrates of at least 2Mb/s for operation (5Mb/s max bit rate)
Function range from -27V to +40V DC at CAN pins.
GND disconnection Fail-Safe at module level.
GND shift operation at system level.
Micro controller Interface with CMOS compatible I/O pins.
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
Matched output slopes and propagation delay
CAN transceiver supply
The two low drops out voltage regulators (V1 and V2) are able to supply the CAN FD transceiver when configured
as a 5 V LDO (see Table 6. Voltage regulators configuration).
CAN FD supply is monitored, only in active mode, assuring the properly rail:
if VCANSUP < VCANSUPlow then after the filter time tCANSUPvalid:
•
•
•
CAN_SUP_LOW flag is set to 1
CAN bus is biased by internal regulator
The transmitter is disabled
When VCANSUP pin > VCANSUPvalid then after the filter time tCANSUPvalid:
•
•
•
CAN_SUP_LOW flag can be cleared
CAN bus is biased by VCANSUP pin
The transmitter is enabled.
When VCANSUP is connected to V2, and V2 is OFF during standby mode, the CAN_SUP_LOW flag is triggered
when the device wakes up and goes back in ACTIVE mode.
When VCANSUP is connected to V1, and the device is put in VBAT_standby mode, the CAN_SUP_LOW flag is
triggered when the device wakes up and goes back in ACTIVE mode.
DS14048 - Rev 1
page 29/135
SPSB081
CAN FD bus transceiver
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Figure 19. CANFD transceiver supply
DS14048 - Rev 1
page 30/135
SPSB081
CAN FD bus transceiver
3.12.3
CAN transceiver operating modes
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Figure 20. Transceiver state diagram
TRX normal mode
Full functionality of the CAN-FD transceiver is available (transmitter and receiver) and the automatic voltage
biasing is enabled.
State transitions from TRX normal mode to VBAT_Standby mode and V1_Standby mode are possible. No
interrupt is generated in this mode.
CAN TRX STBY mode
The CAN-Transmitter is disabled in this mode and the RxD_C pin is kept at high (recessive) level. CAN-Receiver
is capable of detecting a wake-up pattern (WUP). In V1_standby mode and VBAT_Standby mode, a WUP is
indicated to the microcontroller by an interrupt signal.
There is no automatic state transition into TRX normal mode in case of a detected CAN wake up signal (WUP).
In active mode, the microcontroller can initiate a state transition into TRX normal mode by setting the SPI bit
CAN_ACT to '1' and can start communication after TBias.
Moreover, in this mode two further submodes are possible (“Bias ON” or “Bias OFF”), depending on
CAN_AUTO_BIAS bit (compliant with ISO 11898-2:2016) or timeout conditions. In any case, when entering CAN
TRX STBY mode, transition is always to the state “Bias ON”.
3.12.4
CAN error handling
The devices provide the following four error handling features.
After power-on reset (VSREG > VPOR), the CAN transceiver is disabled. The transceiver is enabled by setting
CAN_ACT = 1.
The CAN transmitter is disabled automatically in case of the following errors:
DS14048 - Rev 1
page 31/135
SPSB081
CAN FD bus transceiver
•
•
•
•
•
Dominant TxD_C time out
CAN permanent recessive
RxD_C permanent recessive
Thermal shutdown 1
Can supply low
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The CAN receiver is not disabled in case of any failure condition.
3.12.4.1
Dominant TxDC time out
If TXD_C is in a dominant state (low) for t > tdom(TxDC) the transmitter is disabled, the status bit is latched and
can be read and optionally cleared by SPI (CAN_TXD_ DOM in SR2). The transmitter remains disabled until the
status register is cleared.
3.12.4.2
CAN bus permanent recessive
If TXD_C changes to dominant (low) state but CAN bus does not follow for four times, the transmitter is
disabled, the status bit is latched and can be read and optionally cleared by SPI (CAN_PERM_REC in SR2).
The transmitter remains disabled until the status register is cleared.
3.12.4.3
CAN Permanent Dominant
If the bus state is dominant (low) for t > tCAN a permanent dominant status will be detected. The status bit will be
latched and can be read and optionally cleared by SPI (CAN_PERM_DOM in SR2). The transmitter will not be
disabled.
3.12.4.4
RXDC permanent recessive
If RXD_C pin is clamped to a recessive (high) state, the controller is not able to recognize a bus dominant state
and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if
RXD_C does not follow TXD_C for four times the transmitter is disabled. The status bit is latched and can be read
and optionally cleared by SPI (CAN_RXD_REC in SR2). The transmitter remains disabled until the status register
is cleared.
3.12.5
Wake-up by CAN
The default setting for the wake-up behavior after power-on reset is the wake-up by regular communication on the
CAN bus. When the CAN transceiver is in a standby mode (CAN TRX STBY), the device can be woken-up by
sending two consecutive dominant bits separated by a recessive bit.
For any activity on the CAN, CAN pattern wake-up option is enabled and the CAN transceiver was set in standby
mode (CAN TRX STBY) while CAN bus was in recessive state or dominant state. In order to wake up the device,
the following criteria must be fulfilled:
Note:
DS14048 - Rev 1
•
The CAN interface wake-up receiver must receive a series of two consecutive valid dominant pulses, each
of which must be longer than tfilter.
•
The distance between two pulses must be longer than tfilter.
•
The two pulses must occur within a time frame of twake.
•
Wake-up occurs when the duration of a second pulse becomes longer than tfilter.
A wake-up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the
application back to normal operation mode.
page 32/135
SPSB081
Power supply fail
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Figure 21. CAN wake up capabilities
Note:
The figures above illustrate the wake-up behavior from V1_standby mode. For wake-up from VBAT_standby
mode the NRESET signal (with 2 ms timing) is generated instead of the RXD_L(Interrupt) signal.
3.12.6
CAN receive only mode
During TRX normal mode, with the CAN _REC_ONLY bit in CR1 it is possible to disable the CAN transmitter. In
this mode it is possible to listen to the bus but not to send to it. The receiver termination network is still activated
in this mode.
3.12.7
CAN looping mode
If the CAN_LOOP_EN (configuration register) is set, the TxD_C input is mapped directly to the RxD_C pin. This
mode can be used in combination with the CAN receive-only mode, to run diagnosis for the CAN protocol handler
of the microcontroller.
Note:
To guarantee the correct behavior of the CAN_FD transceiver and to get its optimized electrical performances,
the VCANSUP pin must be connected to V1, V2, or Vext pin (see Table 6. Voltage regulators configuration).
3.13
Power supply fail
3.13.1
Vs supply failure
Vs overvoltage
If the supply voltage Vs reaches the over voltage threshold VSOV:
•
•
•
•
LIN remains enabled
CAN remains enabled
OUT1, OUT2, OUT3, and OUT4 are turned off (default).
The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR3) =0)
Recovery of outputs after over-voltage condition is configurable by SPI:
–
–
DS14048 - Rev 1
VS_LOCK_EN (CR3) = 1: Outputs are off until Read&Clear VS_OV (SR2).
VS_ LOCK_EN (CR3) = 0: Outputs turned on automatically after Vs over-voltage condition has
recovered.
page 33/135
SPSB081
Power supply fail
•
The overvoltage bit VS_OV (SR2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage
bit is reset automatically if VS_LOCK_EN (CR3) = 0 and the overvoltage condition has recovered.
Vs undervoltage
If the supply voltage Vs drops below the under voltage threshold voltage (VSUV):
•
•
Note:
LIN remains enabled
CAN remains enabled
The functionality is not guaranteed in the range VPOR < VSREG < VSREGUV
•
•
OUT1, OUT2, OUT3, and OUT4 are turned off (default). The shutdown of outputs may be disabled by SPI
(VS_UV_SD_EN (CR3) =0)
Recovery of outputs after under-voltage condition is configurable by SPI:
–
–
•
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3.13.2
VS_LOCK_EN (CR3)= 1: Outputs are off until Read&Clear VS_UV (SR2)
VS_LOCK_EN (CR3)= 0: Outputs turned on automatically after Vs undervoltage condition has
recovered.
The undervoltage bit (VSUV) is set and can be cleared with a ‘read and clear’ command. The undervoltage
bit is removed automatically if VS_ LOCK_EN = 0 and the undervoltage condition has recovered.
Vsreg supply failure
Vsreg overvoltage
If the supply voltages Vsreg reaches the overvoltage threshold VSREGOV:
•
•
•
LIN is switched to high impedance (RX is still on)
CAN remains enabled
The over voltage bit VSREG_OV (SR2) is set and can be cleared with a ‘Read&Clear’ command. The
overvoltage bit is reset automatically if VSREG_ LOCK_EN (CR3) = 0 and the overvoltage condition has
recovered.
Vsreg undervoltage
If the supply voltage Vsreg drops below the under voltage threshold voltage (VSREG_UV):
•
Note:
The functionality is not guaranteed in the range VPOR < VSREG < VSREGUV
•
•
DS14048 - Rev 1
LIN is switched to high impedance (RX is still on).
CAN remains enabled
The undervoltage bit (VSREG_UV (SR2) is set and can be cleared with a ‘Read&Clear’ command. The
undervoltage bit is removed automatically if VSREG_LOCK_EN (CR3) = 0 and the undervoltage condition
has recovered.
page 34/135
SPSB081
Thermal state machine
3.14
Thermal state machine
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Figure 22. Thermal shutdown protection and diagnosis related to thermal cluster 1
DS14048 - Rev 1
page 35/135
SPSB081
Power outputs OUT1..4
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Figure 23. Thermal shutdown protection and diagnosis related to thermal cluster 2, 3 and 4
Note:
The thermal state machine recovers the same state where it was before entering standby mode. In case of a
TSD2 it enters TSD1 state.
3.15
Power outputs OUT1..4
The component provides a total of four standalone high side outputs OUT1, OUT2, OUT3, and OUT4 to drive, for
example, LED’s or to supply contacts. OUT1, OUT2, OUT3, and OUT4 are supplied by VS. OUT1, OUT2, OUT 3
and OUT4 are intended to be used as contact supply and can be activated in standby modes.
DS14048 - Rev 1
page 36/135
SPSB081
Open-load detection
All high side outputs switch off in case of:
•
•
•
•
•
VS overvoltage and undervoltage (depending on configuration, see Section 3.13 Power supply fail)
Overcurrent (only the impacted high-side)
Overtemperature (TSD1)
Fail-Safe event
Loss of ground at SGND pin
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In the case of overcurrent or overtemperature (TSD1 (SR1)) condition, the drivers will switch off. The related
status bit is latched and can be read and optionally cleared by SPI. The drivers remain off until the status is
cleared.
In case of overvoltage and undervoltage conditions, the drivers are switched off. The relative status bit is latched
and can be read and optionally cleared by SPI. If the VS_LOCK_EN bit is set to ‘1’, the drivers remain off
until the status is cleared. If the VS_LOCK_EN bit is set to ‘0’, the drivers switch on automatically if the error
condition disappears. Under-voltage and over-voltage shutdown can be disabled by setting < VS_UV_SD_EN >
respectively < VS_OV_SD_EN > to ‘0’. In case of open load condition, the appropriate status register (in SR4) is
set. The status can be read and optionally cleared by SPI. The high side outputs are not switched off in case of
open load condition.
Note:
The maximum voltage and current applied to the high-side outputs are specified in the ‘absolute maximum
ratings’. Appropriate external protection may be required in order to respect these limits under application
conditions.
Each of the standalone high-side driver outputs OUT1..4 can be also driven either with an internal generated
PWM signal or with an internal timer. OUT1..4 can be also directly driven with DIR/WU2 pin.
3.16
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load current is below
the open- load detection threshold (IOLDx) for at least tFOL the corresponding open-load bit is set in the status
register.
3.17
Overcurrent detection
In the case of an overcurrent condition, a status flag is set in the corresponding status register. If the overcurrent
signal is valid for at least tBLK, the overcurrent flag is set and the corresponding driver switches off to reduce the
power dissipation and to protect the integrated circuit. If the overcurrent recovery bit of the output is cleared, the
microcontroller has to clear the status bits to reactivate the corresponding driver.
3.18
Current monitor
The current monitor sources a current image of the power stage output current at the current monitor pin, which
has fixed ratio (ICMr see Table 34. Watchdog) of the instantaneous current of the selected high-side driver. The
signal at output CM is blanked after switching on the driver until correct settlement of the circuitry. The bits
CM_SEL_x (CR6) define which of the outputs is multiplexed to the current monitor output CM. The current
monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open
or overload condition. The current monitor output is enabled after the current-monitor blanking time, when the
selected output is switched on. If this output is off, the current monitor output is in high-impedance mode. The
current monitor can be turned on or off by selecting the corresponding setting for the CM on / off bit.
3.19
Constant current mode
For the OUT1, OUT2, OUT3, and OUT4 high-side drivers, it is available the CCM (constant current mode)
feature, which is conceived to provide a constant current to the related output. The CCM feature is configurable
via SPI, by setting the OUTx_CCM_EN bit (x = 1, 2, 3,4) in CR20; these bits can be set only if the related driver
is in OFF state and when the CCM is enabled, the overcurrent and short circuit detection of the related output is
switched OFF while its open load detection is always ON.
The CCM is automatically disabled after an expiration time tCCMtimeout.
The allowed sequences are:
•
DS14048 - Rev 1
Set OUTx_CCM_EN bit, then turn ON the related driver by SPI (the other configurations of the OUTx_y in
CR5 are ignored): driver starts in CCM for tCCMtimeout, then it switches to ON mode and the OUTx_CCM_EN
bit is automatically cleared;
page 37/135
SPSB081
Temperature warning and shutdown
•
•
If OUTx_CCM_EN = 1, after driver has been started in ON, PWM, timer modes then CCM bit is ignored;
If OUTx_CCM_EN bit is cleared by the microcontroller before timeout, then the driver is switched to ON
mode;
The short-circuit and overcurrent detection are enabled in ON, PWM, timer and DIR modes, but not in constant
current mode. The default value for the OUTx_CCM_EN bit is 0, that is, the CCM is disabled by default.
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Figure 24. Constant current mode
3.20
Temperature warning and shutdown
If any of the cluster junction temperatures rises above the temperature warning threshold (TW ON), a temperature
warning flag is set after the temperature warning filter time (tfTjTW) and can be read via SPI. If the junction
temperature increases above the temperature shutdown threshold (TSD1 OFF), the thermal shutdown bit is set
and the power transistors of all output stages are switched off to protect the device after the thermal shutdown
filter time. The temperature warning and thermal shutdown flags are latched and must be cleared by the
microcontroller. This is done by a read and clear command on the relevant status register (TSD1 is bit 4 in
status register 1 while TW is bit 8 in status register 2).
After these bits have been cleared, the output stages are reactivated. If the temperature is still above the thermal
warning threshold, the thermal warning bit is set after tfTjTW. Once this bit is set and the temperature is above the
temperature shutdown threshold, temperature shutdown is detected after tfTjTW and the outputs are switched off.
Therefore, the minimum time after which the outputs are switched off after the bits have been cleared in case the
temperature is still above the thermo shutdown threshold is twice the thermo warning/shutdown filter time tfTjTW.
DS14048 - Rev 1
page 38/135
SPSB081
Thermal clusters
3.21
Thermal clusters
To provide an advanced on-chip temperature control, the power outputs are grouped in four clusters with
dedicated thermal sensors. The sensors are suitably located on the device. In case the temperature of a cluster
reaches the thermal shutdown threshold, the outputs assigned to this cluster are shut down (all other outputs
remain active). Each output cluster has a dedicated temperature warning and shutdown flag (SR7 & SR8). Hence,
the thermal cluster concept identifies a group of outputs in which one or more channels are in overload condition.
If thermal shutdown has occurred within an output cluster, or if temperature is rising within a cluster, it may be
desired to identify which of the output(s) is (are) determining the temperature increase.
Thermal clusters can be configured using bit TSD_CLUSTER_EN (CR20):
•
Standard mode (default): as soon as any cluster reaches thermal threshold the device is switched off. V1
regulator remains on and is switched off reaching TSD2.
All the thermal sensors are put in “OR”.
In fact, if one of these sensors reaches TSD1:
•
•
All outputs drivers and V2 are turned OFF.V1 remains on until TSD2.LIN and CAN transmitter are turned
OFF (but they are forced in "receive only" mode).
Cluster mode: only the cluster, which reached shutdown temperature is switched off.
In case cluster Th_CL1 reaches TSD1:
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•
V1 remains ON until TSD2
In case cluster Th_CL4 reaches TSD1.
•
•
All outputs drivers and V2 are turned OFF.V1 remains on until TSD2.
LIN and CAN transmitter are turned OFF (but they are forced in "receive only" mode).
Figure 25. Thermal clusters identification
Table 11. Thermal cluster definition
DS14048 - Rev 1
Th_CL1
Th_CL2
Th_CL3
Th_CL4
V1
V2
OUT1, OUT2, OUT3, OUT4
Global
TW & TSD1 TSD2
TW & TSD1
TW & TSD1
TW,
TSD1
page 39/135
SPSB081
Functional safety management
3.22
Functional safety management
Even if not designed as safety HW element, the device contains some features that can be used to support
application that needs to fulfill functional safety requirements. Analysis of the IC’s capability to reach the required
safety level, should be made at system level under user responsibility.
The following device safety requirements have been considered for a typical application:
Table 12. Safety requirement
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ID
Description
TSR1
SPSB081 shall guarantee the correct operation of the voltage regulator V1 as specified in
datasheet.
TSR2
SPSB081 shall guarantee the correct operation of the voltage regulator V2 as specified in
datasheet.
TSR3
SPSB081 shall assert the NRESET signal in case of WD failure.
TSR4
The SPI interface embedded in SPSB081 shall provide to microcontroller device diagnostic info.
TSR5
SPSB081 shall guarantee the correct functionality of HSD(s) as for the datasheet specification.
TSR6
SPSB081 shall ensure LIN physical layer operation as defined in datasheet.
TSR7
SPSB081 shall ensure CAN FD physical layer operation as defined in datasheet.
More details about functional safety can be found in the device safety manual, provided on customer request.
DS14048 - Rev 1
page 40/135
SPSB081
Serial peripheral interface (SPI)
4
Serial peripheral interface (SPI)
A 32-bit SPI is used for bidirectional communication with the microcontroller.
The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:
CPOL = 0 and CPHA = 0
For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed
from the high to low transition of CLK.
This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output pins and one
input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If
CSN = 0, the DO-Pin reflects the global error flag (fault condition) of the device.
•
Chip select not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high
impedance state. A low signal activates the output driver and a serial communication can be started. The state
during CSN = 0 is called a communication frame.
If CSN = low for t > tCSNfail, the DO output is switched to high impedance in order not to block the signal line for
other SPI nodes.
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•
Serial data in (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising
edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the
content of the shift register is transferred to data input register. The writing to the selected data input register is
only enabled if exactly 32 bits are transmitted within one communication frame (that is, CSN low). If more or less
clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to
avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality, a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI
bus by controlling the CSN signal of the connected IC's is recommended.
•
Serial data out (DO)
The data output driver is activated by a logical low level at the CSN input and it goes from high impedance to a
low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after
a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift
register. Each subsequent falling edge of the CLK shifts the next bit out.
•
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the
rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK signal. The SPI can be
driven with a CLK frequency up to 10 MHz.
4.1
ST SPI
The ST-SPI is a standard used in ST automotive ASSP devices.
This chapter describes the SPI protocol standardization. It defines a common structure of the communication
frames and defines specific addresses for product and status information.
The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to
adapt it to the individual functionality of a particular product. In addition, fail-safe mechanisms are implemented to
protect the communication from external influences and wrong or unwanted usage.
The device serial peripheral interface is compliant to the ST SPI standard.
DS14048 - Rev 1
page 41/135
SPSB081
Signal description
4.1.1
Physical layer
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Figure 26. SPI pin description
4.2
Signal description
Chip select not (CSN)
The communication interface is de-selected, when this input signal is logically high. A falling edge on CSN
enables and starts the communication while a rising edge finishes the communication and the sent command is
executed when a valid frame was sent. During communication starts and stops the serial clock (SCK) has to be
logically low. The serial data out (SDO) is in high impedance when CSN is high or a communication timeout was
detected.
Serial clock (SCK)
This SCK provides the clock of the SPI. Data present at serial data input (SDI) is latched on the rising edge of
serial clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are
shifted out to serial data out (SDO).
Serial data input (SDI)
This input is used to transfer data serially into the device. Data is latched on the rising edge of serial clock (SCK).
Serial data output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (SCK).
4.2.1
Clock and data characteristics
The ST-SPI can be driven by a microcontroller with its SPI peripheral running in following mode:
CPOL = 0
CPHA = 0
DS14048 - Rev 1
page 42/135
SPSB081
Signal description
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Figure 27. SPI signal description
The communication frame starts with the falling edge of the CSN (communication start). SCK has to be low.
The SDI data is then full latched following the rising SCK edges into the internal shift registers.
After communication start the SDO leaves 3-state mode and presents the MSB of the data shifted out to SDO, it
is then full latched following the falling SCK edges data and it is shifted out through the internal shift registers to
SDO.
The communication frame is finished with the rising edge of CSN. If a valid communication has taken place (for
example, correct number of SCK cycles, access to a valid address), the requested operation according to the
operating code will be performed (write or clear operation).
4.2.2
Communication protocol
4.2.2.1
SDI frame
The devices data-in frame consists of 32 bits (OpCode (2 bits) + address (6 bits) + data byte 3 + data byte 2 +
data byte 1).
The first two transmitted bits (MSB, MSB-1) contain the operation code which represents the instruction, which is
performed. The following 6 bits (MSB-2 to MSB-7) represent the address on which the operation is performed.
The subsequent bytes contain the payload.
DS14048 - Rev 1
page 43/135
SPSB081
Signal description
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Figure 28. SDI frame
4.2.2.2
Operating code
The operating code is used to distinguish between different access modes to the registers of the slave device.
Table 13. Operation codes
OC1
OC0
Description
0
0
Write operation
0
1
Read operation
1
0
Read & clear operation
1
1
Read device information
A write operation leads to a modification of the addressed data by the payload if a write access is allowed (for
example, control register, valid data). Beside this a shift out of the content (data present at communication start)
of the registers is performed.
A read operation shifts out the data present in the addressed register at communication start. The payload data
is ignored and internal data are not modified. In addition, a burst read can be performed.
A read & Clear Operation leads to a clear of addressed status bits. The bits to be cleared are defined first by
address, second by payload bits set to ‘1’. Beside this a shift out of the content (data present at communication
start) of the registers is performed.
Note:
Status registers, which change status during communication could be cleared by the actual read & clear
operation and are not reported in actual communication or in the following communications. To avoid a loss of
any reported status, that it is recommended just clear status registers, which are already reported in the previous
communication (selective bitwise clear).
4.2.2.3
Advanced operation codes
To provide beside the separate write of all control registers and the bitwise clear of all status registers, two
advanced operation codes can be used to set all control registers to the default value and to clear all status
registers.
A ‘set all control registers to default’ command is performed when an OpCode ‘11’ at address b’111111 is
performed.
Note:
Please consider that potential device specific write protected registers cannot be cleared with this command as
therefore a device Power-on-Reset is needed.
A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.
DS14048 - Rev 1
page 44/135
SPSB081
Signal description
Data-in payload
The Payload (data byte 1 to data byte 3) is the data transferred to the device with every SPI communication. The
Payload always follows the OpCode and the address bits.
For write access the Payload represents the new data written to the addressed register. For read & clear
operations the Payload defines which bits of the addressed status register is cleared. In case of a ‘1’ at the
corresponding bit position the bit will be cleared.
For a read operation, the Payload is not used. For functional safety reasons it is recommended to set unused
Payload to ‘0’.
4.2.2.5
SDO frame
The data-out frame consists of 32 bits (GSB + data byte 1 to 3).
The first eight transmitted bits contain device related status information and are latched into the shift register at
the time of the communication start. These 8 bits are transmitted at every SPI transaction.
The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK
edge.
This could lead to an inconsistency of data between the GSB and Payload due to different shift register load
times. Anyhow, no unwanted status register clear should appear, as status information should just be cleared with
a dedicated bit clear after.
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4.2.2.4
Figure 29. SDO frame
4.2.2.6
Global status byte (GSB)
The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the status registers. Therefore, no
direct read & clear can be performed on these bits inside the GSB.
Table 14. Global status byte
Bit 31
GSBN
Bit 30
RSTB
Bit 29
SPIE
Bit 28
PLE
Bit 27
FE
Bit 26
DE
Bit 25
GW
Bit 24
FS
Global status bit not (GSBN)
The GSBN is a logically NOR combination of bit 24 to bit 30. This bit can also be used as global status flag
without starting a complete communication frame as it is present directly after pulling CSN low.
Reset bit (RSTB)
The RSTB indicates a device reset. In case this bit is set, specific internal control registers are set to default and
kept in that state until the bit is cleared.
DS14048 - Rev 1
page 45/135
SPSB081
Address definition
Prerelease product(s)
The RSTB bit is cleared after a read & clear of all the specific bits in the status registers, which caused the reset
event.
SPI error (SPIE)
The SPIE is a logical OR combination of errors related to a wrong SPI communication.
Physical layer error (PLE)
The PLE is a logical OR combination of errors related to the LIN and CAN FD transceivers.
Functional error (FE)
The FE is a logical OR combination of errors coming from functional blocks (for example, high-side over current).
Device error (DE)
The DE is a logical OR combination of errors related to device specific blocks (for example, VS over voltage, over
temperature.
Global warning (GW)
The GW is a logical OR combination of warning flags (for example, thermal warning).
Fail-safe (FS)
The FS bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal
errors (for example, watchdog failure, voltage regulator failure).
4.2.2.7
Data-out payload
The payload (data bytes 1 to 3) is the data transferred from the slave device with every SPI communication to
the master device. The Payload always follows the OpCode and the address bits of the actual shifted in data
(In-frame-Response).
4.3
Address definition
Table 15. Device application access
Operating code
OC1
OC0
0
0
0
1
1
0
Table 16. RAM address range
DS14048 - Rev 1
RAM address
Description
Access
3FH
Configuration register
R/W
38H
Status register 8
R/C
…
…
32H
Status register 2
R/C
31H
Status register 1
R/C
…
…
22H
Control register 34
R/W
18H
Control register 24
R/W
…
…
02H
Control register 2
R/W
01H
Control register 1
R/W
00H
reserved
page 46/135
SPSB081
Address definition
Table 17. Device information read access
Operating code
OC1
OC0
1
1
Table 18. ROM address range
ROM address
Description
Access
3FH
<Advanced Op.>
W
3EH
<GSB options>
R
20H
<SPI CPHA test>
R
16H
<WD bit pos. 4>
R
15H
<WD bit pos. 3>
R
14H
<WD bit pos. 2>
R
13H
<WD bit pos. 1>
R
12H
<WD type 2>
R
11H
<WD type 1>
R
10H
<SPI mode>
R
<silicon Ver.>
R
05H
<device No.4>
R
04H
<device No.3>
R
03H
<device No.2>
R
02H
<device No.1>
R
01H
<device family>
R
00H
<company code>
R
Prerelease product(s)
…
…
0AH
…
4.3.1
Information registers
The device information registers can be read by using OpCode ‘11’. After shifting out the GSB the 8-bit wide
payload is transmitted. By reading device information registers a communication width, which is minimum 16 bits
plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is
shifted out at the SDO.
Table 19. SPSB081 information registers map
ROM address
Description
Access
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3FH
<Advanced Op.>
3EH
<GSB options>
R
→
0
0
0
0
0
0
0
0
20H
<SPI CPHA test>
R
→
0
1
0
1
0
1
0
1
16H
<WD bit pos. 4>
R
→
C0H
15H
<WD bit pos. 3>
R
→
7FH
14H
<WD bit pos. 2>
R
→
C0H
13H
<WD bit pos. 1>
R
→
41H
…
DS14048 - Rev 1
page 47/135
SPSB081
Address definition
ROM address
Description
Access
Bit 7
12H
<WD type 2>
R
→
91H
11H
<WD type 1>
R
→
3CH
10H
<SPI mode>
R
→
B0H
…
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
→
0AH
<silicon Ver.>
R
→
…
Prerelease product(s)
Bit 6
major revision
minor revision
→
05H
<device No.4>
R
→
50H
04H
<device No.3>
R
→
37H
03H
<device No.2>
R
→
52H
02H
<device No.1>
R
→
55H
01H
<device family>
R
→
01H
00H
<company code>
R
→
00H
4.3.1.1
Device identification registers
These registers represent a unique signature to identify the device and silicon version.
<Company Code>: 00H (STMicroelectronics)
<Device Family>: 01H (BCD power management)
<Device No. 1>: 55H (ASCII code for U)
<Device No. 2>: 52H (ASCII code for R)
<Device No. 3>: 37H (ASCII code for 7)
<Device No. 4>: 50H (ASCII code for P)
4.3.1.2
SPI modes
By reading out the <SPI mode> register general information of SPI usage of the device application registers can
be read.
Table 20. SPI mode register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BR
DL2
DL1
DL0
0
0
S1
S0
1
0
1
1
0
0
0
0
<SPI mode>: B0H (burst mode read available, 32 bit, no data consistency check).
4.3.1.3
SPI burst read
Table 21. Burst read bit
Bit 7
Description
0
BR not available
1
BR available
The SPI burst read bit indicates if a burst read operation is implemented. The intention of a burst read is, for
example, used to perform a device internal memory dump to the SPI master.
The start of the burst read is like a normal read operation. The difference is, that after the SPI data length the
CSN is not pulled high and the SCK is continuously clocked. When the normal SCK max count is reached (SPI
data length), the consecutive addressed data is latched into the shift register. This procedure is performed every
time when the SCK payload length is reached.
DS14048 - Rev 1
page 48/135
SPSB081
Address definition
In case the automatically incremented address is not used by the device, undefined data is shifted out. An
automatic address overflow is implemented when address 3FH is reached.
The SPI burst read is limited by the CSN low timeout.
4.3.1.4
SPI data length
The SPI data length value indicates the length of the SCK count monitor, which is running for all accesses to the
device application registers. In case a communication frame with an SCK count is not equal to the reported one, it
leads to a SPI error and the data are rejected.
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Table 22. SPI data length
Bit 6
Bit 5
Bit 4
Description
DL2
DL1
DL0
0
0
0
invalid
0
0
1
16-bit SPI
0
1
0
24-bit SPI
0
1
1
32-bit SPI
…
1
4.3.1.4.1
1
1
64-bit SPI
Data consistency check (Parity/CRC)
Table 23. Data consistency check
4.3.1.4.2
Bit 1
Bit 0
Description
S1
S0
0
0
not used
0
1
Parity used
1
0
CRC used
1
1
Invalid
Watchdog definition
For further information, see also Section 3.6 Configurable window watchdog.
In case a watchdog is implemented the default settings can be read out via the device information registers.
Table 24. WD Type/Timing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WD1
WD0
<WD type 1/2>
0
0
<WD type 1>
0
1
WT5
WT4
WT3
1
1
1
1
Bit 2
Bit 1
Bit 0
WT1
WT0
1
0
Register is not used
WT2
Watchdog timeout / Long open window WT[5:0] * 5ms
<WD type 2>
1
0
OW2
OW1
OW0
CW2
CW1
CW0
1
0
0
1
0
0
0
1
Open window OW[2:0] *5ms
<WD type 1/2>
1
1
Closed window CW[2:0] *5ms
Invalid
<WD type 1>: 3CH (long open window: 300 ms)
DS14048 - Rev 1
page 49/135
SPSB081
Address definition
<WD type 2>: 91H (open window. 10 ms, closed window: 5 ms)
<WD type 1> indicates the long open window (timeout) which is opened at the start of the watchdog. The binary
value of WT[5:0] times 5 ms indicates the typical value of the timeout time.
<WD type 2> describes the default timing of the window watchdog.
The binary value of CW[2:0] times 5 ms defines the typical closed window time (tCW) and OW[2:0] times 5 ms
defines the typical open window time (tOW). See figure below where tCW = TEFW and tOW = TLFW - TEFW
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Figure 30. Window watchdog operation
The watchdog trigger bit location is defined by the <WD bit pos. X> registers.
Table 25. WD bit position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WB1
WB0
<WD bit pos. X>
0
0
<WD bit pos. X>
0
1
WBA5
WBA4
WBA3
WBA2
WBA1
WBA0
<WD bit pos. 1>
0
1
0
0
0
0
0
1
<WD bit pos. 3>
0
1
1
1
1
1
1
1
Register is not used
Defines the register addresses of the WD trigger bits
<WD bit pos. X>
1
0
WBA5
WBA4
WBA3
WBA2
WBA1
WBA0
Defines the stop address of the address range (previous<WD bit pos. X> is
a WB = ‘01’). The consecutive <WD bitpos. X> has to be a WB = ‘11’
<WD bit pos. X>
1
1
0
WBP 4
WBP3
WBP2
WBP1
WBP0
<WD bit pos. 2>
1
1
0
0
0
0
0
0
<WD bit pos. 4>
1
1
0
0
0
0
0
0
Defines the binary bit position of the WD trigger bit within the
register
<WD bit pos 1>: 41H; watchdog trigger bit located at address 01H (CR1)
<WD bit pos 2>: C0H; watchdog trigger bit location is bit0.
<WD bit pos 3>: 7FH; watchdog trigger bit located at address 3FH (Config register)
<WD bit pos 4>: C0H; watchdog trigger bit location is bit0.
DS14048 - Rev 1
page 50/135
SPSB081
Protocol failure detection
4.3.2
Device application registers (RAM)
The device application registers are all registers accessible using OpCode ‘00’, ‘01’ and ‘10’. The functions of
these registers are defined in the device specification.
4.4
Protocol failure detection
To realize a protocol, which covers certain fail-safe requirements a basic set of failure detection mechanisms are
implemented.
4.4.1
Clock monitor
Prerelease product(s)
During communication (CSN low to high phase) a clock monitor counts the valid SCK clock edges. If the SCK
edges do not correlate with the SPI data length, an SPIE is reported with the next command and the actual
communication is rejected.
By accessing the device information registers (OpCode = ‘11’) the clock monitor is set to a minimum of 16 SCK
edges plus a multiple by 8 (for example, 16, 24, 32, …).
Providing no SCK edge during a CSN low to high phase is not recognized as an SPIE. For a SPI burst read also
the SPI data length plus multiple numbers of payloads SCK edges are assumed as a valid communication.
4.4.2
SCK polarity (CPOL) check
To detect the wrong polarity access via SCK, the internal clock monitor is used. Providing first a negative edge on
SCK during communication (CSN low to high phase) or a positive edge at last will lead to an SPI error reported in
the next communication and the actual data is rejected.
4.4.3
SCK phase (CPHA) check
To verify, that the SCK phase of the SPI master is set correctly a special device information register is
implemented. By reading this register the data must be 55H. In case AAH is read the CPHA setting of the
SPI master is wrong and a proper communication cannot be guaranteed.
4.4.4
CSN timeout
By pulling CSN low the SDO is set active and leaves its tristate condition. To ensure communication between
other SPI devices within the same bus even in case of CSN stuck @ low a CSN timeout is implemented. By
pulling CSN low an internal timer is started. After timer end is reached the actual communication is rejected and
the SDO is set to tristate condition.
4.4.5
SDI stuck at GND
As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be distinguished between a
valid command and a SDI stuck @ GND this communication is not allowed. Nevertheless, in case a stuck @ GND
is detected the communication will be rejected and the SPIE will be set with the next communication.
4.4.6
SDI stuck at HIGH
As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be distinguished between a
valid command and a SDI stuck @ HIGH this communication is not allowed. In case a stuck @ HIGH is detected
the communication will be rejected and the SPIE will be set with the next communication.
4.4.7
SDO stuck @
The SDO stuck @ GND and stuck @ HIGH has to be detected by the SPI master. As the definition of the GSB
guarantees at least one toggle, a GSB with all-‘0’ or all –‘1’ reports a stuck at error.
DS14048 - Rev 1
page 51/135
SPSB081
Electrical characteristics
5
Electrical characteristics
For an efficient and easy tracking, numbering has been added to each electrical parameter.
Device features are split into categories (see the following table), and each of them is represented by a letter
(A, B, C, etc.); all parameters are completely identified by a letter and a three-digit number (for example, B.125,
C.096…) for their whole lifetime.
New inserted parameters continue with the numbering of the related category, no matter of where they are placed.
To facilitate insertion, the last number inserted for each category is also reported in the second column of the
following table.
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Table 26. Electrical parameters numbering
Category
Parameters numbering
Analog I/O
A.xxx
Digital I/O
B.xxx
Voltage regulators
C.xxx
Outputs
D.xxx
Transceivers
E.xxx
Others
F.xxx
Due to these rules and taking into account that deleted parameter numbers are no more reassigned, numbering
inside each category may be not sequential.
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V <
VS< 28 V; 6 V < VSREG< 28 V, Tj = from -40°C to 150°C, unless otherwise specified.
Table 27. Supply
Symbol
Parameter
Condition
Min
Typ Max Unit
Item
VSUV
VS undervoltage threshold
VS decreasing
4.7
5.4
V
A.001
Vhyst_UV
Vs undervoltage hysteresis
VS increasing
0.04
0.1
0.2
V
A.002
VSOV_I
VS overvoltage threshold
VS increasing
19.95
21
22.5
V
A.003
VSOV_D
VS overvoltage threshold
VS decreasing
18.5
20
22.5
V
A.004
Vhyst_OV
Vs overvoltage hysteresis
VS decreasing
0.5
1.3
1.7
V
A.005
VSREGUV
VSREG undervoltage
threshold
VSREG decreasing
4.2
4.9
V
A.006
Vhyst_UV
VSREG undervoltage
hysteresis
VSREG increasing
0.04
0.1
0.2
V
A.007
VSREGOV_I
VSREG overvoltage
threshold
VSREG increasing
19.95
21
22.5
V
A.008
VSREGOV_D
VSREG overvoltage
threshold
VSREG decreasing
18.5
20
22.5
V
A.009
Vhyst_OV
VSREG overvoltage
hysteresis
0.5
1.3
1.7
V
A.010
tovuv_filt
Vs/ VSREG over-/
undervoltage filter time
45
64
80
µs
A.011
3
6
mA
A.012
Tested by scan
Vs=12V
IV(act)
Current consumption in
active mode
TxD CAN = high
TxD LIN = high
V1ON, V2OFF
DS14048 - Rev 1
page 52/135
SPSB081
Electrical characteristics
Symbol
Parameter
Condition
Min
Typ Max Unit
Item
15
A.055
HS driver OFF
CAN OFF
VS=12V Tj = 25°C
Current consumption in
VBAT_standby mode
IV(VBAT,25)
Both voltage regulators deactivated,
HS driver OFF
25
No CAN communication
µA
VS=12V Tj = 85°C
Current consumption in
VBAT_standby mode. (1)(2)
IV(VBAT,85)
Both voltage regulators deactivated,
HS driver OFF
25
30
A.013
42
53
A.056
No CAN communication
VS=12V Tj = 25°C
Current consumption in
VBAT-standby mode
Prerelease product(s)
IV(BAT)CS
with cyclic sense enabled
(1)
Both voltage regulators deactivated,
T=50 ms, ton=100 µs
µA
VS=12 V Tj = 85°C
Both voltage regulators deactivated,
48
60
A.014
42
55
A.057
T=50 ms, ton=100 µs
VS=12 V Tj = 25°C
Both voltage regulators deactivated
IV(BAT)CW
Current consumption in
VBAT-standby mode
In standby phase before wake-up on timer
expiration
with cyclic wake-up
enabled
VS=12V Tj = 85°C
(1)
µA
Both voltage regulators deactivated
In standby phase before wake- up on
timer expiration.
48
60
A.015
48
60
A.058
(3)
VS=12 V Tj = 25°C
Voltage regulator V1 active,
IV(V1stby,25)
Current consumption in
V1_standby mode (1)(2)
(Iv1 = 0) HS driver OFF; Wake-up OFF
except for LIN transceiver
Voltage regulator V1 active,
IV(V1stby,85)(3)
µA
VS=12 V Tj = 85°C
59
70
A.016
40
80
µA
A.059
48
96
µA
A.060
0.5
1.5
µA
A.061
(Iv1 = 0) HS driver OFF; Wake-up OFF
except for LIN transceiver
V1_standby
IV(V1stby_cc,25)(3)(4)
WDG = OFF
Current consumption for
cyclic sense enabled
IV(V1stby_cc,85)
(3)(4)
Tj = 25°C
V1_standby
WDG = OFF
Tj = 85°C
VBAT_standby;
(3)(4)
IV(VBAT_WU,25)
Current consumption for
Wake-up inputs
Voltage regulator V2 disabled; Wake-up
on;
NO CAN; NO LIN; no activity on wake-up
pins
Tj = 25°C
DS14048 - Rev 1
page 53/135
SPSB081
Electrical characteristics
Symbol
Parameter
Condition
Min
Typ Max Unit
Item
VBAT_standby;
(3)(4)
IV(VBAT_WU,85)
Current consumption for
Wake-up inputs
Voltage regulator V2 disabled; Wake-up
on;
NO CAN; NO LIN; no activity on wake-up
pins
0.7
2.5
10
15
µA
A.062
Tj = 85°C
Standby modes;
CAN wake-up = ON
IV(CANWU,25)(3)(4)
Current consumption for
CAN wake capability
(tsilence expired)
Prerelease product(s)
IV(CANWU 85)(3)(4)
ICAN, rec(4)
ICAN, dom(4)
ICAN, rom(4)
WK = off; voltage regulator V2 disabled; Tj
= 25°C
A.063
µA
Standby modes;
CAN wake-up = ON
10
15
A.064
4
7
10
mA
A.065
7
10
13
mA
A.066
4
6
9
mA
A.067
15
25
WK = off; voltage regulator V2 disabled; Tj
= 85°C
Current consumption for
CAN, recessive state
Current consumption for
CAN, dominant state
Current consumption for
CAN, receive only mode
Active mode or V1standby mode; CAN =
ON; VCANSUP = 5 V; VTXDC =
5 V; no external resistance on CAN
Active mode or V1standby mode; CAN =
ON; VCANSUP = 5 V; VTXDC =
GND; no external resistance on CAN
Active mode or V1standby mode; CAN in
receive mode; VCANSUP = 5 V; VTXDC =
5 V; no external resistance on CAN
VBAT_standby;
LIN wake-up = ON
IV(VBAT_LINWU,25)(3)
WK = off;
Current consumption for
LIN wake capability
CAN = OFF; Tj = 25°C
µA
VBAT_standby;
LIN wake-up = ON
IV(VBAT_LINWU,85)(3)
WK = off;
A.068
20
30
A.069
48
84
A.070
CAN = OFF; Tj = 85°C
VBAT_standby;
V2 On (Iv2 = 0)
(3)
IV(VBAT_V2,25)
CAN OFF;
Wake-up OFF
Current consumption for
Tj = 25°C
Voltage regulator V2 in
Vbat standby mode
VBAT_standby;
µA
V2 On (Iv2 = 0)
(3)
IV(VBAT_V2,85)
CAN OFF;
53
94
550
950
A.071
Wake-up OFF
Tj = 85°C
V1_standby
IV(V1stby _HS,25)(3)
Current consumption for
HS drivers
cyclic sense enabled;
HSx (x=3;4) ON;
µA
A.072
CAN OFF;
DS14048 - Rev 1
page 54/135
SPSB081
Oscillator
Symbol
Parameter
Condition
Min
Typ Max Unit
Item
Wake-up OFF except LIN transceiver;
Tj = 25°C
V1_standby
cyclic sense enabled; (5)
Current consumption for
HS drivers
µA
HSx (x=3;4) ON;
IV(V1stby _HS,85)(3)
570 1000
CAN OFF;
A.073
Wake-up OFF except LIN transceiver;
Tj = 85°C
Prerelease product(s)
1. Conditions for specified current consumption:
•
VLIN > (VSREG-1.5V)
•
(CAN_H – CAN_L) < 0.4V or (CAN_H – CAN_L) > 1.2V
•
VWU < 1V or VWU > (VSREG – 1.5 V)
•
LIN wake-up is possible, CAN wake up disabled, WUx_EN register set to 0
2. In SPSB081Cx it is mandatory to keep wake-up source capability (CANFD or wake-up pin) and in that case an additional
contribution of IV(VBAT_WU,x) or IV(CANWU,x) has to be considered.
3. Guaranteed by design.
4. Current consumption adders of features defined for SBC V1 stby mode or for SBC VBAT stby mode (unless otherwise
specified).
5. Current consumption adder while only one HS is turned on with no load.
5.1
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V <
VS< 28 V; 6 V < VSREG< 28 V; Tj = -40°C... 150°C, unless otherwise specified.
Table 28. Oscillator
Symbol
(1)(2)
FCLK1
FCLK2(1)
Parameter
Condition
Min
Typ
Max
Unit
Item
Oscillation frequency
-
0.80
1.0
1.20
MHz
A.018
Oscillation frequency
-
12.8
16.0
19.2
MHz
A.019
1. 1 MHz clock is used in standby mode. 16 MHz clock is used in active mode.
2. The clock frequency is further reduced in standby mode to sustain a very low quiescent current.
5.2
Power-on reset (VSREG)
All outputs open; Tj = from -40°C to 150°C, unless otherwise specified
Table 29. Power-on reset
Symbol
Parameter
Condition
VPOR_R
VPOR threshold
VSREG rising
VPOR_F
VPOR threshold
VSREG falling (1)
Min
2.3
Typ
Max
Unit
Item
3.45
4.5
V
A.020
3.55
V
A.021
1. This threshold is valid if VSREG had already reached VPOR_R(max) previously.
5.3
Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 <
VS< 28 V; 4.5V < VSREG< 28 V; Tj = from -40°C to 150°C, unless otherwise specified.
The same parameter values in both 5 V and 3.3 V conditions apply unless otherwise specified.
DS14048 - Rev 1
page 55/135
SPSB081
Voltage regulator V1
Table 30. Voltage regulator V1
Symbol
V1
V110mA
V1high_acc
V1250mA
Prerelease product(s)
V1ov_th1
Parameter
Output voltage including line
and load regulation
Output voltage tolerance (0 .. Icmp)
Condition
ILOAD = 100 µA to Icmp
VSREG = 13.5 V
ILOAD = Icmp to 100 mA, (active mode)
High accuracy mode
VSREG = 13.5 V
Output voltage tolerance (100 …
250mA)
ILOAD = 250mA,
V1ov_th2
OverVoltage threshold 2 for V1
Rdischarge
Resistance to be able to discharge
20 mA
VSREG = 13.5 V
ICCmax1
DS14048 - Rev 1
Drop-out voltage
V
Item
C.001
C.041
-2.5
+2.5
%
C.003
-2.5
+2.5
%
C.004
-3
+3
%
C.005
V1 rising
5.2
5.35
5.5
V1 falling–V1 13V5/100 uA
0.1
-
0.4
V1 rising
3.5
3.65
3.8
V1 falling–V1 13V5/100 uA
0.1
-
0.4
Define the test condition
5.5
5.65
5.8
3.9
4.05
4.2
V1 = 3.3 V
120
165
V1=5 V
130
200
ILOAD =50 mA, VSREG= 5 V (V1=5 V)
0.2
0.25
C.006
0.25 0.35
C.046
ILOAD =100 mA, VSREG= 5 V (V1=5 V)
and VSREG= 3.55 V (1) below 3.55 V,
the POR VSREG can be activated and
there is a device reset. (V1=3.3 V)
0.35
0.5
ILOAD=150 mA, VSREG= 5 V and
VSREG= 3.55 V (1) (V1=3.3 V); T= 25°C
0.35
0.5
C.042
V
C.066
V
Ω
V
C.043
C.067
C.044
C.045
C.007
C.008
Current limitation
450
750 1100
mA
C.010
Load capacitor1
Ceramic (+/- 20%)
1(3)
10(1)
µF
C.011
tTSD
V1 deactivation time after thermal
shut-down
Tested by scan
-
1.5
-
ICMP_ris
Current comp. rising threshold (to
GND)
Rising current ICMP_SET = 0
1
4
7
Rising current ICMP_SET = 1
6
12
18
ICMP_fal(4)
Current comp. falling threshold (to
GND)
Falling current ICMP_SET = 0
0.4
2.8
4.2
Falling current ICMP_SET = 1
4
10
15
ICMP_hys(4)
Current comp. hysteresis
V1fail
V1 fail threshold
tOV1filter1
Cload1(2)
Short circuit output current (to GND)
Max Unit
3.3
ILOAD =50 mA, VSREG= 3.55 V ((1)
V1=3.3 V)
VDP1
Typ
5.0
VSREG ≥ 6.5 V
Output voltage tolerance
OverVoltage threshold 1 for V1
Min
ICMP_SET = 0
ICMP_SET = 1
1.2
1
sec C.012
mA
mA
mA
C.013
C.047
C.014
C.048
C.015
2
4
V1 forced (V1=5 V)
2
3
V1 forced (V1=3.3 V)
1.3
2
V1 overvoltage filter time1
Tested by scan
20
30
µs
C.051
tOV1filter2
V1 overvoltage filter time2
Tested by scan
20
30
µs
C.052
tV1fail
V1 fail filter time
Tested by scan
6
13
20
µs
C.017
tV1short
V1 short filter time
Tested by scan
2
4
5
ms
C.018
V
C.049
C.016
C.050
page 56/135
SPSB081
Voltage regulator V2
Symbol
Parameter
Condition
Min
Typ
Max Unit
Item
tV1FS
V1 fail-safe filter time
Tested by scan
1.43
2
2.06
ms
C.019
tV1off
V1 deactivation time after 8
consecutive WD failures
Tested by scan
200
270
ms
C.020
1. Below 3.55 V, the POR VSREG can be activated and there is a device reset.
2. Guaranteed by design.
3. Nominal capacitor value required for stability of the regulator. Tested with 1 μF ceramic (+/- 20%). Capacitor must be located
close to the regulator output pin. A 2.2 uF capacitor value is recommended to minimize the DPI (Direct power injection)
stress in the application.
4. In active mode, V1 regulator is switched to high accuracy mode. Below the Icmp threshold, regulator switches in any case to
nominal accuracy mode (same behavior applies also in case of high current).
5.4
Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V
< VS< 28 V; 4.5 V < VSREG< 28 V; Tj = from -40°C to 150°C, unless otherwise specified.
Prerelease product(s)
The same parameter values in both 5 V and 3.3 V conditions apply unless otherwise specified.
Table 31. Voltage regulator V2
Symbol
V2
Parameter
Output voltage including line
and load regulation
Condition
ILOAD = 100 μA to 50mA, (active mode)
High accuracy mode
VSREG = 13.5 V
V2100mA
Output voltage tolerance (50 …
100mA)
ILOAD = 100 mA,
ΔVo
Output voltage tracking accuracy
(1)
Drop-out voltage
V
3.3
Item
C.053
C.054
-2.5
+2.5
%
C.055
-3
+3
%
C.056
Icc2 = 100 µA to 100 mA, Icc1=30 mA Vsreg -20
= 6.5 V to 28 V
20
mV
C.057
0.5
V
C.022
0.75 0.85
V
C.058
mA
C.023
10
μF
C.024
V
C.025
VSREG = 13.5 V
Iload =30 mA; VSREG =5.25 V (V2=5V) and
VSREG =3.55 V (V2=3.3 V)
VDP2
Max Unit
5.0
VSREG ≥ 6.5 V
Output voltage tolerance
V2high_acc
Min Typ
0.3
Iload =100 mA @ T= 25°C;
VSREG =5.0 V (V2 = 5.0 V) and
VSREG = 3.55 V (V2 = 3.3 V)
ICCmax2
Output current limitation
400 600 1200
Cload(2)(3)
Load capacitor
Ceramic (+/- 20%)
V2fail_5
V2 forced (V2 = 5 V)
2
3
V2fail_33
V2 short circuit voltage to switch
V2 off and set SPI bit
V2 forced (V2 = 3V3)
1.3
2
tV2fail
V2 fail filter time
Tested by scan
6
13
20
µs
C.068
tV2short
V2 short filter time
Tested by scan
-
4
-
ms
C.026
1
C.060
1. Output voltage tracking accuracy are guaranteed only in DC condition.
2. Nominal capacitor value required for stability of the regulator. Tested with 1µF ceramic (+/- 20%). Capacitor must be located
close to the regulator output pin. A 2.2 μF capacitor value is recommended to minimize the DPI stress in the application.
3. Guaranteed by design.
5.5
Reset output
The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 4 V ≤
VS ≤ 28 V; 4 V < VSREG< 28 V; Tj = from -40 to 150°C, unless otherwise specified.
DS14048 - Rev 1
page 57/135
SPSB081
DIAGN output
Table 32. Reset output
Symbol
VRT1_5
VRT1_33
VRT2_5
VRT2_33
VRT3_5
VRT3_33
VRT4-1_5
VRT4-1_33
VRT4-2_5
Prerelease product(s)
VRT4-2_33
5.6
Parameter
Reset threshold voltage1
Condition
Min
Typ
Max
VV1 decreasing (V1 = 5 V)
3.3
3.5
3.7
VV1 decreasing (V1 = 3.3 V0)
2.5
2.65
2.75
VV1 decreasing (V1 = 5 V)
3.6
3.8
4
VV1 decreasing (V1 = 3.3 V)
2.6
2.75
2.85
VV1 decreasing (V1 = 5 V)
3.8
4.0
4.2
VV1 decreasing (V1 = 3.3 V)
2.7
2.85
2.95
VV1 decreasing (V1 = 5 V)
4.4
4.6
4.8
VV1 decreasing (V1 = 3.3 V)
2.8
2.9
3.05
VV1 increasing (V1 = 5 V)
4.65
4.8
4.9
VV1 increasing (V1 = 3.3 V)
2.95
3.1
3.2
0.2
0.4
V
C.032
25
40
kΩ
C.033
40
μs
C.034
Reset threshold voltage2
Reset threshold voltage3
Reset threshold voltage4
Reset threshold voltage4
V1 > 1V, IRESET = 5 mA
Unit
V
V
V
V
V
Item
C.027
C.061
C.028
C.062
C.029
C.063
C.030
C.064
C.031
C.065
VRESET
Reset pin low output voltage
RRESET
Reset pull up int. resistor
tRR
Reset reaction time
Iload = 1 mA; tested by scan
6
tUV1
V1 under-voltage filter time
Tested by scan
6
12
20
μs
C.035
tRD
Reset pulse duration
Tested by scan
1.5
2.0
2.5
ms
C.036
10
DIAGN output
The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 4 V ≤
VS ≤ 28 V; 4 V < VSREG< 28 V; Tj = from -40 to 150°C, unless otherwise specified.
Table 33. DIAGN output
5.7
Symbol
Parameter
Condition
VDIAGN
DIAGN pin low
output voltage
V1 > 1V, IDIAGN = 5
mA
RDIAGN
DIAGN pulls up int.
resistor
Min
10
Typ
Max
Unit
Item
0.2
0.4
V
C.037
25
40
kΩ
C.038
Watchdog
For further information, see Section 3.6 Configurable window watchdog.
4.5 V < VS < 28 V; 4.5 V < VSREG< 28 V; Tj = from -40 to 150°C, unless otherwise specified
Table 34. Watchdog
DS14048 - Rev 1
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
tLW
Long open window
Tested by scan
240
300
360
ms
A.022
TEFW1
Early failure
window 1
Tested by scan
4.5
ms
A.023
TLFW1
Late failure window
1
Tested by scan
20
ms
A.024
TSW1
Safe window 1
Tested by scan
7.5
12
ms
A.025
TEFW2
Early failure
window 2
Tested by scan
22.3
ms
A.026
page 58/135
SPSB081
Watchdog
Symbol
Parameter
Condition
Min
TLFW2
Late failure window
2
Tested by scan
100
TSW2
Safe window 2
Tested by scan
37.5
Typ
Max
60
Unit
Item
ms
A.027
ms
A.028
Prerelease product(s)
Figure 31. Watchdog timing
DS14048 - Rev 1
page 59/135
SPSB081
Current monitor output (CM)
Prerelease product(s)
Figure 32. Watchdog early, late and safe windows
5.8
Current monitor output (CM)
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V <
VS< 28 V; 6 V < VSREG< 28 V; Tj = from -40 to 150 °C, unless otherwise specified
Table 35. Current monitor output (CM)
Symbol
Parameter
VCM
Functional voltage
range
ICMr
ICM/IOUT1,2,3,4
Condition
Min
Typ
V1-1 V
0
0V ≤ VCM ≤ V1-1 V
Max
Unit
V
1/990
Item
A.029
A.030
Ranges extracted
at the output:
ICM acc
Current monitor
accuracy
IOUT1,2,3,4
-8% - 4% FS
(1)
0
8% + 4%
FS(1)
A
A.031
22
32
39
µs
A.032
IOUTmin = 100 mA
IOUTmax = 130 mA
tcmb
Current monitor
blanking time
Tested by scan
1. FS (full scale) = IOUTmax *ICMr_typ.
5.9
Outputs OUT1 – OUT4
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤
VS ≤ 18 V, all outputs open; Tj = from -40°C... 150°C, unless otherwise specified.
DS14048 - Rev 1
page 60/135
SPSB081
Power outputs switching times
Table 36. Outputs OUT1–OUT4
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
7
9
Ω
D.001
14
20
Ω
D.002
VS = 13. 5 V, Tamb=+25°C
rON OUT1,2,3,4_25
on-resistance to supply
rON OUT1,2,3,4_125
IOUT1,2,3,4= -60mA
VS = 13.5 V, Tamb=+125°C
IOUT1,2,3,4 = -60mA
IQLH_stdby
switched-off output current
VOUT = 0 V, standby mode
-5
µA
D.003
IQLH_stdby_act
high side drivers of OUT1-4 (1)
VOUT = 0 V, active mode
-10
µA
D.004
1. Negative value: leakages internally sink from driver output pin to internal IC ground positive value: Leakage sourced from
internal driver output pin to external ground.
5.10
Power outputs switching times
Table 37. Power outputs switching times
Prerelease product(s)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
20
140
µs
D.005
10
60
µs
D.006
0.5
V/µs
D.007
Hz
D.008
-
Hz
D.009
100
%
D.010
Output delay time
td OFF H
high-side driver OFF
(OUT1,2,3,4) (delay
between CSN 50 % to
OUT at 20% of VS)
(figure 39)
VS= 13.5 V
V1= 5 V
Rload = 128 Ω
Output delay time
td ON H
high-side driver ON
(OUT1,2,3,4) (delay
between CSN 50% to
OUT at 80% of VS)
(figure 39)
VS= 13.5 V
V1= 5 V
Rload = 128 Ω
dVOUT/dt
Slew rate for drivers
OUT1…4
VS = 13.5 V(1)(2).
fPWM1
PWM switching
frequency
VS /VSREG = 13.5 V; tested
by scan
fPWM2
PWM switching
frequency
VS /VSREG = 13.5 V; tested
by scan
-
DC
SPI configurable duty
cycle for OUT1…4
0.1% steps; tested by scan
0.1
0.1
0.2
125
250
1. Rload = 128 Ω at OUT1,2,3 ,4, in high on-resistance mode.
2. Slope dVOUT/dt is measured between 20% and 80% of the final output voltage value
DS14048 - Rev 1
page 61/135
SPSB081
Output current threshold
Prerelease product(s)
Figure 33. Slew-rate of the drivers
5.11
Output current threshold
The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin.
6 V < VS< 28 V; 6 V < VSREG< 28 V; Tj = from -40 to 150 °C, unless otherwise specified
Table 38. Output current threshold
DS14048 - Rev 1
Symbol
Parameter
Condition
|IOC1|
over-current
threshold
HS1
VS = 13.5V,
|IOC2|
over-current
threshold
HS2
VS = 13.5V,
|IOC3|
over-current
threshold
HS3
VS = 13.5V,
|IOC4|
over-current
threshold
HS4
VS = 13.5V,
source
source
source
source
Min
Typ
Max
Unit
Item
0.14
0.35
A
D.011
0.14
0.35
A
D.022
0.14
0.35
A
D.023
0.14
0.35
A
D.024
|ICCM1|
Constant
current mode
VS = 13.5 V;
value for
OUT1 (high OUT1_CCM_EN =
1
on resistance
mode)
100
142
200
mA
D.012
|ICCM2|
Constant
current mode
VS = 13.5 V;
value for
OUT2 (high OUT2_CCM_EN =
1
on resistance
mode)
100
145
200
mA
D.025
page 62/135
SPSB081
Output current threshold
Symbol
Min
Typ
Max
Unit
Item
|ICCM3|
Constant
current mode
VS = 13.5 V;
value for
OUT3_CCM_EN
=
OUT3 (high
1
on resistance
mode)
100
145
200
mA
D.026
|ICCM4|
Constant
current mode
VS = 13.5 V;
value for
OUT4_CCM_EN
=
OUT4 (high
1
on resistance
mode)
100
145
200
mA
D.027
tCCMtimeout
Constant
OUTx_CCM_EN =
current mode
1 (x= 1 to 4);
expiration
tested by scan
time;
-
20
-
ms
D.013
Tested by scan
33
40
56
µs
D.015
xx_OCR_TON[0,1]
= 00; tested by
scan
76
88
116
µs
D.016
70
80
106
µs
D.017
64
72
96
µs
D.018
57
64
87
µs
D.019
0.2
0.65
1.5
mA
D.020
0.2
0.65
1.5
mA
D.028
0.2
0.65
1.5
mA
D.029
0.2
0.65
1.5
mA
D.030
155
200
270
µs
D.021
Prerelease product(s)
tBLK
Parameter
Blanking
time of overcurrent
signal in high
sides
tOCR00
tOCR01
tOCR10
TON time of xx_OCR_TON[0,1]
= 01; tested by
over-current
scan
signal
(including
xx_OCR_TON[0,1]
blanking time
= 10; tested by
tBLK)
scan
xx_OCR_
TON[0,1] = 11;
tested by scan
tOCR11
|(1)
|IOLD1
|IOLD2|(1)
|IOLD3|(1)
|IOLD4|(1)
tFOL
Condition
undercurrent
threshold
HS1
VS/VSREG = 13.5
V,
undercurrent
threshold
HS2
VS/VSREG = 13.5
V,
undercurrent
threshold
HS3
VS/VSREG = 13.5
V,
undercurrent
threshold
HS4
VS/VSREG = 13.5
V,
filter time of
open-load
signal
source
source
source
source
Duration of openload condition to
set the status bit;
tested by scan
1. IOLD parameters, in the range 8 V to 16 V, are guaranteed by design and characterization. Production Testing is done at
13.5 V.
DS14048 - Rev 1
page 63/135
SPSB081
Wake-up inputs (WU1, DIR/WU2)
5.12
Wake-up inputs (WU1, DIR/WU2)
The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V <
VSREG< 28 V; Tj = from ‑40 to 150°C, unless otherwise specified.
Table 39. Wake-up inputs
Prerelease product(s)
Symbol
Parameter
Condition
Min
Typ
Max
0.45
0.5
Unit
Item
V
A.033
VWUthp
Wake-up positive edge
threshold voltage
0.4
VsREG
VsREG
VsREG
VWUthn
Wake-up negative edge
threshold voltage
0.5
VsREG
0.55 VsREG
0.6
VsREG
V
A.034
VDIRth
DIR threshold voltage
0.5
1.5
2.5
V
A.035
VHYST
Hysteresis (1)
0.05
0.1
0.15
VsREG
VsREG
V
A.036
tWU_stat
Static wake filter time
-
64 (2)
-
µs
A.037
RWU_act
Input resistor to Gnd
in active mode and in
standby mode during
wake-up input sensing
80
160
300
kΩ
A.039
tWU_cyc
Cyclic wake filter time
12
16
20
µs
A.040
VsREG
Tested by
scan
Tested by
scan
1. In DIR configuration, no appreciable hysteresis is observed.
2. Guaranteed by design.
5.13
CAN FD transceiver
The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V
< VSREG< 18 V; 4.8 V < Vcansup < 5.2 V; Tjunction = from -40°C... 150°C, unless otherwise specified. -12 V ≤
(CANH+CANL)/2 ≤ 12 V
•
•
•
ISO 11898-2:2016 compliant
SAE J2284 compliant
SAE J2962-2 (draft Nov. 13, 2017) compliant
Table 40. CAN communication operating range
Symbol
Parameter
VSREG_Transmitter
Supply voltage
operating range for
CAN transmitter (1)
VSREG_Receiver
Supply voltage
operating range for
CAN receiver
Condition
Min
Typ
Max
Unit
Item
6.5
28
V
E.001
6.5
28
V
E.002
VV1 = VCANSUP
decreasing or
VCANSUPvalid
CAN supply valid
voltage flag
VV2 = VCANSUP
decreasing or
4.5
4.65
4.8
V
E.105
4.9
5.0
5.1
V
E.106
-
22
-
µs
E.107
External supply =
VCANSUP decreasing
DS14048 - Rev 1
VCANSUPext
External CAN supply
output voltage
tCANSUPvalid
CAN supply UV filter
time
Tested by scan
page 64/135
SPSB081
CAN FD transceiver
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
4.1
4.3
4.5
V
E.031
12
V
E.113
120
mA
E.003
120
mA
E.004
400
600
µA
E.005
10
50
µA
E.006
5
Mb/s
E.007
VV1 = VCANSUP
decreasing or
VCANSUPlow
CAN supply low
voltage flag
VV2 = VCANSUP
decreasing or
External supply =
VCANSUP decreasing
VCANHL, CM
Common mode Bus
voltage (VCANH +
VCANL) / 2
Measured with respect to
the ground of each CAN
transceiver
-12
Active mode:
RL=50 Ω … 65 Ω;
70% VRXDC (rising) - 30
% VRXDC (falling);
Prerelease product(s)
CRXD=15pF;
ITRCV
TXD rise and fall time =
10 ns (10% - 90%, 90% 10%);
Transceiver current
consumption during
normal mode
Test signal to be applied
on the TXD input of
the implementation is a
square wave signal with a
positive duty cycle of 1/6
and a period of six times
the nominal recessive bit
width
Rectangular pulse signal
TTXDC= 6*TBIT(2), high
pulse 1*TBIT, low pulse
5*TBIT
RL=50 Ω…65 Ω;
ITRCV_short
Transceiver current
consumption during
output short
ITRCVLPbias
Transceiver current
consumption; biasing
active
ITRCVLP
Transceiver current
consumption during
low-power mode;
biasing inactive
BR
Supported bitrates
VCANH=-3 V or VCANL=40
V
RL=50 Ω … 65 Ω;
VTXDC=VTXDCHIGH;
RL=50 Ω … 65 Ω;
VTXDC=VTXDCHIGH;
Supported bitrates at
which all requirements are
fulfilled
1. VAt VSREG < VSREG_Tranmitter(min) the transceiver shall enter high impedance state .
2. The bit time TBIT is the nominal bit time at a given bit rate (TBIT = 1/BR). E.g.: At BR=2 Mb/s => TBIT = 500 ns
Table 41. CAN transmit data input: Pin TxDC
Symbol
DS14048 - Rev 1
Parameter
Condition
Min
Typ
Max
Unit
Item
VTXDCLOW
Input voltage
dominant level
Active mode
1.0
1.45
2.0
V
E.008
VTXDCHIGH
Input voltage
recessive level
Active mode
1.2
1.85
2.3
V
E.009
VTXDCHYS
VTXDCHIGH-VTXDCLOW
Active mode
0.2
0.7
V
E.010
page 65/135
SPSB081
CAN FD transceiver
Symbol
Parameter
Condition
RTXDCPU
TXDC pull up resistor
td,TXDC(dom-rec)
TXDC - CANH,L
delay time dominant recessive
td,TXDC(rec-diff)
TXDC - CANH,L
delay time recessive dominant
tdom(TXDC)
TXDC dominant timeout
Active mode
Min
20
Typ
50
Max
110
Unit
Item
kΩ
E.011
120
ns
E.012
0
120
ns
E.013
0.8
2
ms
E.014
RL = 50 Ω.. 65 Ω; 70 %
VTXD – 30% VDIFF;
0
5.5V ≤ VSREG ≤ 18 V;
TXDC rise time = 10 ns
(10% - 90%)
RL = 50 Ω.. 65 Ω; 30 %
VTXD – 70% VDIFF;
5.5V ≤ VSREG ≤ 18 V;
TXDC fall time = 10 ns
(90% - 10%)
Tested by scan
5
Prerelease product(s)
Table 42. CAN receive data output: Pin RxDC
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
VRXDCLOW
Output voltage
dominant level
Active mode, IRXDC
= 2 mA
0
0.2
0.5
V
E.015
VRXDCHIGH
Output voltage
recessive level
Active mode, IRXDC
= -2 mA
V1-0.5
V1-0.2
V1
V
E.016
tr,RXDC
RxDC rise time
0
25
ns
E.017
tf,RXDC
RxDC fall time
0
25
ns
E.018
td, RXDC(dom-rec)
CANH,L – RxDC
delay time dominant recessive
td, RXDC(rec - dom)
CANH,L – RxDC
delay time recessive
- dominant
CL = 15 pF;
30% - 70% VRXDC
CL = 15 pF;
70% - 30% VRXDC(1)
CL = 15 pF;
30% VDIFF – 70%
VRXDC(1)
0
120
ns
E.019
0
120
ns
E.020
CL = 15 pF;
70% VDIFF – 30%
VRXDC(1)
1. Guaranteed by design.
Table 43. CAN transmitter dominant output characteristics
Symbol
Parameter
VCANHdom
Single ended CANH
voltage level in dominant
state
VCANLdom
VDIFF,dom
Single ended CANL
voltage level in dominant
state
Differential output voltage
in dominant state:
VCANHdomVCANLdom
DS14048 - Rev 1
Condition
Min
Typ
Max
Unit
Item
VTXDC =
VTXDCLOW;
2.75
3.5
4.5
V
E.021
0.5
1.5
2.25
V
E.022
1.5
2.0
3
V
E.023
RL = 50 Ω..65 Ω
VTXDC =
VTXDCLOW;
RL = 50 Ω..65 Ω
VTXDC =
VTXDCLOW;
RL = 50 Ω..65 Ω
page 66/135
SPSB081
CAN FD transceiver
Symbol
Parameter
Condition
Min
VDIFF_Arb
Differential output
voltage in dominant
state during arbitration:
VCANHdom-VCANLdom
VTXDC=VTXDCLOW
;
Differential output voltage
in dominant state on
extended bus load range:
VCANHdom-VCANLdom
VTXDC=VTXDCLOW
;
VDIFF,dom_ext
VDIFF,domVsLow
VDIFF,dom_ext_
Prerelease product(s)
VsLow
VSYM
Differential output voltage
in dominant state:
VCANHdom-VCANLdom at
low VSREG
V)
IOCANL,dom (18
V)
IOCANL,dom (40
V)
Item
1.5
5
V
E.024
1.4
3.3
V
E.025
1.35
3
V
E.026
1.25
3.3
V
E.027
VTXDC=VTXDCLOW
;
RL=50 Ω … 65 Ω;
5 V < VSREG < 5.5
V
with 45Ω … 70Ω load at
low VSREG
5 V < VSREG < 5.5
V (1)
Driver symmetry
RL = 60 Ω ± 1%;
RL=45 … 70 Ω;
fTXDC = 1MHz (3);
0.9
1
1.1
E.028
CSPLIT = 4.7 nF
(+-5%)
VCANSUP = 5 V (2)
IOCANH,dom (-3
Unit
RL=45 Ω … 70 Ω
VTXDC=VTXDCLO
W;
VCANL)/VCANSUP
Max
RL=2240 Ω
Differential output voltage
in dominant state:
VCANHdom -VCANLdom
VSYM = (VCANH +
Typ
CANH output current in
dominant state
CANL output current in
dominant state
CANL output current in
dominant state
VTXDC =
VTXDCLOW;
-115
115
mA
E.029
-115
115
mA
E.030
0
115
mA
E.032
VCANH= -3 V..18 V
VTXDC =
VTXDCLOW;
VCANL = -3 V..18
V
VTXDC =
VTXDCLOW;
VCANL = 40 V;
VSREG = 40 V
1. VSREG at device pin after reverse battery protection, while application is supplied with 6V. Operating condition has to be
adapted, if higher voltage drop occur in the application.
2. Put into the datasheet, if it is an internal voltage. If it is an external pin, it should be supplied externally.
3. Measurement equipment input load <20 pF, >1 MΩ, guaranteed by E.025, E.026, E.029, E.030, E.053, E.054
measurements.
Table 44. CAN transmitter recessive output characteristics, CAN normal mode
Symbol
DS14048 - Rev 1
Parameter
Condition
Min
Typ
Max
Unit
Item
VCANHrec
CANH voltage level
in recessive state
(normal mode)
VTXDC = VTXDCHIGH;
2
no load
2.5
3
V
E.033
VCANLrec
CANL voltage level
in recessive state
(normal mode)
VTXDC = VTXDCHIGH;
2
no load
2.5
3
V
E.034
VDIFF,recOUT
Differential output
voltage in recessive
state (normal mode):
VTXDC = VTXDCHIGH;
-50
no load
50
mV
E.035
page 67/135
SPSB081
CAN FD transceiver
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
Unit
Item
VCANHrec-VCANLrec
Note:
CAN normal mode: tested in TRX normal state while the device is in active mode.
Table 45. CAN receiver input characteristics during CAN normal mode
Prerelease product(s)
Symbol
Note:
Parameter
VTHdom
Differential receiver
threshold voltage
recessive to
dominant state
Vdom_range
Differential dominant
input level voltage
range
VTHrec
Differential receiver
threshold voltage
dominant to
recessive state
Vrec_range
Differential recessive
input level voltage
range
Condition
-12V≤VCANH≤12 V;
12 V≤VCANL≤12 V
-12 V ≤ VCANH ≤ 12
V;
Min
Typ
Max
0.5
0.9
V
E.036
0.9
10
V
E.037
0.5
0.9
V
E.038
-5
0.5
V
E.039
-12 V ≤ VCANL ≤ 12 V
12 V ≤ VCANH ≤ 12 V;
-12 V ≤ VCANL ≤ 12 V
-12 V ≤ VCANH ≤ 12
V;
-12V ≤ VCANL ≤ 12 V
CAN normal mode: tested in TRX normal state while the device is in active mode.
Table 46. CAN receiver input characteristics during CAN low power mode, biasing inactive
Symbol
Parameter
VTHdomLP
sferential receiver
threshold voltage
recessive to dominant
state
Vdom_range_LP
Differential dominant
input level voltage
range
VTHrecLP
Differential receiver
threshold voltage
dominant to recessive
state
Vrec_range_LP
Differential recessive
input level voltage
range
VCANHrecLP
VCANLrecLP
VDIFF,recOUTLP
Condition
12 V ≤ VCANH ≤
12 V;
Min
Typ
Max
Unit
Item
0.4
1.15
V
E.040
1.15
10
V
E.041
0.4
1.15
V
E.042
-5
0.4
V
E.043
CANH output voltage
in recessive state
-0.1
0.1
V
E.108
CANL output voltage in
recessive state
-0.1
0.1
V
E.109
-0.2
0.2
V
E.110
Differential output
voltage in recessive
state:
-12 V ≤ VCANL ≤
12 V
-12 V ≤ VCANH ≤
12 V;
-12 V ≤ VCANL ≤
12 V
12 V ≤ VCANH ≤
12 V;
-12 V ≤ VCANL ≤
12 V
-12 V ≤ VCANH ≤
12 V;
-12 V ≤ VCANL ≤
12 V
VCANHrecLP-VCANLrecLP
DS14048 - Rev 1
page 68/135
SPSB081
CAN FD transceiver
Note:
CAN low power mode, biasing inactive: Tested in CAN TRX STDBY (bias off) state while the device is in active
mode, V1_standby mode and Vbat_standby mode.
Table 47. CAN receiver input resistance
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
VTXDC = VTXDCHIGH; no load
Rdiff = RCANH + RCANL
Differential internal
resistance
-2,0 V ≤ VCANH ≤ +7,0 V;
Rdiff
12
100
kΩ
E.044
6
50
kΩ
E.045
-0.03
0.03
-2,0 V ≤ VCANL ≤ +7,0 V (1)
VTXDC = VTXDCHIGH; no load
Single ended
RCANH, CANL
internal resistance
-2,0 V ≤ VCANH ≤ +7,0 V;
Prerelease product(s)
-2,0 V ≤ VCANL ≤ +7,0
Internal
Resistance
matching
RCANH,CANL
mR
V(1)
Biasing active; VTXDC =
VTXDCHIGH; no load; mR = 2 x
(RCAN_H - RCAN_L) / (RCAN_H
+ RCAN_L)
E.046
10k resistor between CANHCANL pin with external 5 V
1. Voltage Range is taken from ISO CD 16845-2 (High-speed medium access unit - Conformance test plan).
Note:
CAN normal and low power mode, biasing active: Tested in TRX normal and CAN TRX STDBY (bias on) state
while the device is in active and V1_standby mode.
Table 48. CAN transceiver delay
Symbol
Parameter
Condition
Min
Typ
Max Unit
Item
255
ns
E.047
255
ns
E.048
350
ns
E.049
350
ns
E.050
5.5 V < VSREG < 18 V;
RL=60 Ω ±1%;
tLOOP,hl
Loop delay TXDC to
RXDC (high to low)
CL = 100pF;
30% VTXDC – 30% VRXDC;
TXDC fall time = 10ns (90% - 10%); CRXDC=15 pF
5.5 V < VSREG < 18 V;
RL=60 Ω ±1%;
tLOOP,lh
Loop delay TXDC to
RXDC (low to high)
CL = 100 pF;
70% VTXD – 70% VRXD ;
TXDC rise time = 10 ns (10% - 90%); CRXDC=15
pF
5.5 V < VSREG < 18 V;
tLOOP150,hl
Loop delay TXDC to
RXDC (high to low)
with 150Ω bus load
RL=150 Ω;
CL = 100 pF;
30% VTXDC – 30% VRXDC;
TXDC fall time = 10ns (90% - 10%); CRXDC=15 pF
5.5 V < VSREG < 18 V;
tLOOP150,lh
Loop delay TXDC to
RXDC (low to high)
with 150Ω bus load
RL=150 Ω;
CL = 100 pF;
70% VTXD – 70% VRXD ;
DS14048 - Rev 1
page 69/135
SPSB081
CAN FD transceiver
Symbol
Parameter
Condition
Min
Typ
Max Unit
Item
TXDC rise time = 10 ns (10% - 90%); CRXDC=15
pF
5.5 V < VSREG < 18 V;
RL=60 Ω ±1%;
70% VRXDC (rising) - 30% VTXDC (falling);
CL = 100pF; CRXD=15pF;
TXD rise and fall time = 10ns (10% - 90%, 90% 10%);
TBit(RXD) ≤ 1Mb/s
(1)
900 1000 1050
E.051
Test signal to be applied on the TXD input of the
implementation is a square wave signal with a
positive duty cycle of 1/6 and a period of six times
the nominal recessive bit width
Recessive bit
symmetry at RXDC
Prerelease product(s)
TBit(RXD)_150 ohm
≤ 1 Mb/s
Rectangular pulse signal TTXDC= 6000 ns, high
pulse 1000ns, low pulse 5000 ns
RL=150 Ω; other conditions as TBit(RXD) ≤ 1Mb/s;
value may be obtained by characterization only.
ns
800
1050
E.052
400 500
550
E.053
300
550
E.054
120 200
220
E.055
Conditions as TBit(RXD) ≤ 1 Mb/s
TBit(RXD) ≤ 2
Mb/s
Rectangular pulse signal TTXDC= 3000ns, high
pulse 500 ns, low pulse 2500 ns
RL=150 Ω; other conditions as TBit(RXD) ≤ 1 Mb/s;
TBit(RXD)_150 ohm
≤ 2Mb/s
value may be obtained by characterization only.
Conditions as TBit(RXD) ≤ 1 Mb/s
TBit(RXD) ≤ 5
Mb/s
Rectangular pulse signal TTXDC= 1200 ns, high
pulse 200ns, low pulse 1000 ns
5.5 V < VSREG < 18V;
RL=60 Ω ±1%;
VDIFF: 0.5 V(falling) - 0.9 V(rising);
CL = 100 pF; CRXD=15 pF;
TXD rise and fall time = 10 ns (10% - 90%, 90% 10%);
TBit(BUS) ≤ 1
Mb/s
Recessive bit
symmetry at CANBus
935 1000 1030
Test signal to be applied on the TXD input of the
implementation is a square wave signal with a
positive duty cycle of 1/6 and a period of six times
the nominal recessive bit width
E.056
ns
Rectangular pulse signal TTXDC= 6000 ns, high
pulse 1000 ns, low pulse 5000 ns
Conditions as TBit(BUS) ≤ 1 Mb/s
TBit(BUS) ≤ 2
Mb/s
Rectangular pulse signal TTXDC= 3000 ns, high
pulse 500 ns, low pulse 2500 ns
435 500
530
E.057
155 200
210
E.058
-65
40
-45
15
Conditions as TBit(BUS) ≤ 1 Mb/s
TBit(BUS) ≤ 5
Mb/s
Rectangular pulse signal TTXDC= 1200 ns, high
pulse 200 ns, low pulse 1000 ns
5.5 V < VSREG < 18 V; RL=60 Ω ±1%;
∆tREC ≤ 2 Mb/s
∆tREC ≤ 5 Mb/s
DS14048 - Rev 1
Receiver timing
symmetry (TBit(RXD) TBit(BUS))
CL = 100pF; CRXD=15 pF;
Rectangular pulse signal TTXDC= 3000ns, high
pulse 500 ns, low pulse 2500 ns
5.5 V < VSREG < 18 V; ; RL=60 Ω ±1%;
ns
E.059
E.060
page 70/135
SPSB081
CAN FD transceiver
Symbol
Parameter
Condition
Receiver timing
symmetry (TBit(RXD) TBit(BUS))
tCAN(2)
CAN permanent
dominant time out
tWUP-VCansup
time between WUP
on the CAN bus until
VCansup goes active
tWUP-RXD
tVCANSUPlow
Filter time needed to
display CANSUPlow
flag
Typ
Max Unit
Item
ns
Rectangular pulse signal TTXDC= 1200 ns, high
pulse 200 ns, low pulse 1000 ns
Tested by scan
time between WUP
on the CAN bus
until RXD is active
(i.e. the CAN signal
is represented at the
RXD output)
Min
CL = 100 pF; CRXD=15 pF;
Wake-Up-Pattern Wake-Up
70% VDIFF – 90% VCansup(min);
600 700
900
µs
E.061
0
200
µs
E.062
0
1
ms
E.063
µs
E.111
(3)
Wake-Up-Pattern Wake-Up
RXD output enabled; Tested by scan
Tested by SCAN
5
Prerelease product(s)
1. TBit(RXD) for the highest supported data rate has to be specified (1 Mb/s, 2 Mb/s or 5 Mb/s).
2. At the expiration of this filter time a flag is set.
3. Time starts with the end of last dominant phase of the WUP.
Table 49. CAN receiver input resistance
Symbol
Parameter
Condition
Min Typ Max Unit
Item
-10
10
µA
E.064
-12
12
µA
E.065
-10
10
µA
E.066
-12
12
µA
E.067
Unpowered device; VCANH=5 V; VCANL=5 V;
VSREG < VPOR_F (1);
ILeakage,
CANH,105
VSREG, VCANSUP (2) connected via 0Ω to GND
VSREG, VCANSUP
(2)
connected via 47 kΩ to GND
Tj-= -40 to 105 °C
Input leakage current
CANH
ILeakage,
CANH,130
Unpowered device; VCANH=5 V; VCANL=5 V;
VSREG < VPOR_F (1);
VSREG, VCANSUP(2) connected via 0 Ω to GND
VSREG, VCANSUP (2)
Tj-= 130 °C
Unpowered device;
VCANH=5 V; VCANL=5 V;
VSREG < VPOR_F(1);
ILeakage,
CANL,105
VSREG, VCANSUP (3)connected via 0 Ω to GND
VSREG, VCANSUP (4)
Tj-= -40 to 105 °C
Input leakage current
CANL
ILeakage,
CANL,130
Unpowered device;
VCANH=5 V; VCANL=5 V;
VSREG < VPOR_F (1);
VSREG, VCANSUP(3) connected via 0 Ω to GND
VSREG, VCANSUP connected via 47 kΩ to GND (4)
Tj-= 130 °C
DS14048 - Rev 1
page 71/135
SPSB081
LIN transceiver (only for SPSB0815 & SPSB0813)
1. VSREG not floating
2. Related to the external supply pin of the CAN-transceiver. If the transceiver supply is generated entirely inside of the device
the parameter is measured with respect to the supply of the device.
3. Related to the external supply pin of the CAN-transceiver. If the transceiver supply is generated entirely inside of the device
the parameter is measured with respect to the supply of the device; if the transceiver is supplied by its own supply pin, this
pin has to fulfill this specification as well as the supply that is used to generate the transceiver voltage in case it is on the
same device.
4. Related to the external supply pin of the CAN-transceiver. If the transceiver supply is generated entirely inside of the device
the parameter is measured with respect to the supply of the device; if the transceiver is supplied by its own supply pin, this
pin has to fulfill this specification as well as the supply that is used to generate the transceiver voltage in case it is on the
same device. It is connected via 47 kΩ to GND.
Table 50. Biasing control timings
Prerelease product(s)
Symbol
5.14
Parameter
Condition
Min
tfilter
CAN activity filter time
Tested by scan
0.5
twake
Wake-up time out
Tested by scan
0.8
tSilence
CAN timeout
Tested by scan
600
TBias
CAN bias reaction time
Typ
Max
Unit
Item
1.8
µs
E.068
1
5
ms
E.069
700
1200
ms
E.070
250
µs
E.112
LIN transceiver (only for SPSB0815 & SPSB0813)
LIN ISO 17987-6:2016 compliant
For data rates up to 20 Kbit/s
The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
6 V < VSREG< 18 V; Tjunction = from -40°C to 150°C unless otherwise specified.
Table 51. LIN transmit data input: Pin TxD
Symbol
Parameter
Condition
Min
Typ
VTXDLOW
Input voltage dominant level
Active mode
1.0
1.45
VTXDHIGH
Input voltage recessive level
Active mode
VTXDHYS
VTXDHIGH-VTXDLOW
Active mode
0.2
0.4
RTXDPU
TXD pulls up resistor
Active mode
13
29
1.85
Max
Unit
Item
V
E.071
V
E.072
V
E.073
kΩ
E.074
2.3
49
Table 52. LIN receive data output: Pin RxD
Symbol
Parameter
Condition
VRXDLOW
Output voltage dominant level
Active mode
VRXDHIGH
Output voltage recessive level
Active mode
Min
V1-0.5
Typ
Max
Unit
Item
0.2
0.5
V
E.075
V
E.076
V1-0.2
Table 53. LIN transmitter and receiver: Pin LIN
DS14048 - Rev 1
Symbol
Parameter
VTHdom
Receiver threshold voltage
recessive to dominant state
VBusdom
Receiver dominant state
VTHrec
Receiver threshold voltage
dominant to recessive state
0.5*
VSREG
VBusrec
Receiver recessive state
0.6*
VSREG
Condition
Min
Typ
Max
Unit
Item
0.4*
VSREG
0.45*
VSREG
0.5*
VSREG
V
E.077
0.4*
VSREG
V
E.078
0.6*
VSREG
V
E.079
V
E.080
0.55*
VSREG
page 72/135
SPSB081
LIN transceiver (only for SPSB0815 & SPSB0813)
Symbol
Parameter
VTHhys
Condition
Min
Typ
Max
Unit
Item
Receiver threshold hysteresis:
VTHrec -VTHdom
0.07*
VSREG
0.1*
VSREG
0.175*
VSREG
V
E.081
VTHcnt
Receiver tolerance center value:
(VTHrec +VTHdom)/2
0.475*
VSREG
0.5*
VSREG
0.525*
VSREG
V
E.082
VTHwkup
Receiver wakeup threshold
activation voltage (rising edge)
0.5*
VSREG
0.55*
VSREG
0.6*
VSREG
V
E.083
VTHwkdwn
Receiver wakeup threshold
activation voltage(falling edge)
0.4*
VSREG
0.45*
VSREG
0.5*
VSREG
V
E.084
tlinbus
LIN Bus wake-up dominant filter
time
Sleep mode; edge: recdom; tested by scan
40
64
80
μs
E.085
tdom_LIN
LIN Bus wake-up dominant filter
time
Sleep mode; edge: recdom-rec; tested by scan
28
μs
E.086
ILINDomSC
Transmitter input current limit in
dominant state
VTXD=VTXDLOW;
VLIN=VBAT=18 V
40
mA
E.087
Ibus_PAS_dom
Input leakage current at the
receiver incl. pull-up resistor
mA
E.088
20
μA
E.089
1
mA
E.090
30
μA
E.091
1.2
V
E.092
V
E.093
60
kΩ
E.094
30
pF
E.095
Max
Unit
Item
6
μs
E.096
100
180
Prerelease product(s)
VTXD=VTXDHIGH;
-1
VLIN=0 V; VBAT=12 V *)
*) slave mode
Ibus_PAS_rec
In standby modes;
VTXD=VTXDHIGH;
Transmitter input current in
recessive state
VLIN > 8 V
VBAT<18 V; VLIN>=VBAT
GND=VSREG;
Ibus_NO_GND
Input current if loss of GND at
device
0V<VLIN<18V;
-1
VBAT=12 V
Ibus
Input current if loss of VBAT at
device
VLINdom
LIN voltage level in dominant
state
VLINrec
LIN voltage level in recessive
state
RLINup
LIN output pulls up resistor
(1)
CLIN
GND=VSREG;
0V<VLIN<18 V
Active mode;
VTXD=VTXDLOW; Rbus =
500 Ω
Active mode;
VTXD=VTXDHIGH; ILIN=10
uA
0.8*
VSREG
VLIN=0 V
20
40
LIN input capacitance
1. Guaranteed by design.
Table 54. LIN transceiver timing
Symbol
Parameter
Condition
Min
Typ
tRXpd=max (tRXpdr,tRXpdf);
tRXpdf=t(0.5 VRXD)-t(0.45 VLIN);
tRXpd
Receiver
propagation
delay time
tRXpdr=t(0.5 VRXD)-t(0.55 VLIN);
VSREG=12 V; CRXD=20 pF;
Rbus = 1k Ω, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF; Rbus = 500 Ω, Cbus = 10nF
DS14048 - Rev 1
page 73/135
SPSB081
LIN transceiver (only for SPSB0815 & SPSB0813)
Symbol
Parameter
Condition
tRXpd_sym=tRXpdr-tRXpdf;
tRXpd_sym
Symmetry of
receiver
propagation
delay time
(rising vs.
falling edge)
VSREG=12 V;
Rbus = 1 kΩ, Cbus = 1 nF;
Min
Typ
-2
Max
Unit
Item
2
μs
E.097
CRXD=20 pF
THRec(max)=0.744*VSREG; THDom(max)=0.581*VSREG;
VSREG=7 ... 18V, tbit= 50us;
D1
Duty cycle 1
D1=tbus_rec(min)/(2xtbit);
Rbus = 1 kΩ, Cbus = 1nF;
0.396
E.098
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
THRec(min)=0.422*VSREG; THDom(min)= 0.284*VSREG;
VSREG=7.6...18 V, tbit= 50us;
Prerelease product(s)
D2
Duty cycle 2
D2=tbus_rec(max)/(2xtbit);
0.581
Rbus = 1 kΩ, Cbus = 1 nF;
E.099
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
THRec(max)=0.778*VSREG;
THDom(max)=0.616*VSREG;VSREG=7 ... 18 V, tbit= 96 us;
D3=tbus_rec(min)/(2xtbit);
D3
Duty cycle 3
Rbus = 1 kΩ, Cbus = 1nF;
0.417
E.100
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
THRec(min)=0.389*VSREG; THDom(min)=0.251*VSREG;
VSREG=7.6 ... 18 V, tbit=96 us;
D4
Duty cycle 4
D4=tbus_rec(max)/(2xtbit);
0.590
Rbus = 1 kΩ, Cbus = 1 nF;
E.101
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
DS14048 - Rev 1
tdom(TXDL)
TXDL dominant
time-out
Tested by scan
12
ms
E.102
tLIN
LIN permanent
recessive timeout
Tested by scan
40
μs
E.103
LIN Bus
permanent
Tdom(bus)
dominant timeout
Tested by scan
12
ms
E.104
page 74/135
SPSB081
SPI
Prerelease product(s)
Figure 34. LIN transmit, receive timing
5.15
SPI
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V <
VSREG < 18 V; all outputs open; Tj = from -40°C to 150°C, unless otherwise specified.
Table 55. Input: CSN
Symbol
Parameter
Condition
Min
Typ
Max
VCSNLOW
Input voltage low
level
Normal mode,
V1=5 V
1.0
1.45
VCSNHIGH
Input voltage high
level
Normal mode,
V1=5 V
VCSNHYS
VCSNHIGH VCSNLOW
Normal mode,
V1=5 V
0.2
0.4
ICSNPU
CSN pull up resistor
Normal mode,
V1=5 V
13
29
1.85
2.3
46
Unit
Item
V
B.001
V
B.002
V
B.003
kΩ
B.004
Table 56. Inputs: CLK, DI
Symbol
DS14048 - Rev 1
Parameter
Condition
Min
tset
delay time from
V1_standby mode
to active mode
Switching from V1_standby
mode to active mode using
SPI wake- up access.
Time until output drivers(pchannel) are enabled after
CSN going to high. Tested
by scan
Vin L
input low level
V1 = 5 V
Vin H
input high level
V1 = 5 V
Vin Hyst
input hysteresis
V1 = 5 V
0.2
0.4
I in
pull down current at
input
Vin = 1 V
5
30
Cin(1)
input capacitance at
input CSN, CLK, DI
and PWM1,2
0V < V1 < 5.3 V
10
1.0
Typ
Unit
Item
60
µs
B.005
1.45
V
B.007
V
B.008
V
B.009
60
µA
B.010
15
pF
B.011
1.8
Max
2.3
page 75/135
SPSB081
SPI
Symbol
Parameter
Condition
fCLK
SPI input frequency
at CLK
Tested by scan
Min
Typ
Max
Unit
Item
10
MHz
B.012
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Prerelease product(s)
Table 57. DI, CLK and CSN timing
Symbol
Parameter
Condition
Min
tCLK
clock period
V1 = 5 V; tested
by scan
tCLKH
clock high time
tCLKL
Unit
Item
100
ns
B.013
V1 = 5 V
40
ns
B.014
clock low time
V1 = 5 V
40
ns
B.015
tset CSN
CSN setup time, CSN
low before rising edge
of CLK
V1 = 5 V
150
ns
B.016
tset CLK
CLK setup time, CLK
high before rising edge
of CSN
V1 = 5 V
150
ns
B.017
tset DI
DI setup time
V1 = 5 V
25
ns
B.018
thold DI
DI hold time
V1 = 5 V
25
ns
B.019
tr in
tf in
rise time of input signal
DI, CLK, CSN
fall time of input signal
DI, CLK, CSN
Typ
Max
V1 = 5 V(1)
25
ns
B.020
V1 = 5 V (1)
25
ns
B.021
Max
Unit
Item
0.5
V
B.022
V
B.023
10
μA
B.024
10
15
pF
B.025
Typ
Max
Unit
Item
1. Guaranteed by design.
Table 58. Output: DO
Symbol
Parameter
Condition
VDOL
output low level
V1 = 5 V, IDO = -4mA
VDOH
output high level
V1 = 5 V, IDO = 4 mA
V1-0.5
IDOLK
tristate leakage
current
VCSN = V1, 0V < VDO
<´V1
-10
CDO (1)
tristate input
capacitance
VCSN = V1,
Min
Typ
0 V < V1 < 5.3 V
1. Guaranteed by design.
Table 59. DO timing
Symbol
Parameter
Min
tr DO
DO rise time
CL = 50 pF, Iload = -1
mA
25
ns
B.026
tf DO (1)
DO fall time
CL = 50 pF, Iload = 1
mA
25
ns
B.027
100
ns
B.028
DO enable time
ten DO tri L(1)
DS14048 - Rev 1
Condition
from tristate to low
level
CL = 50 pF, Iload = 1
mA
50
pull-up load to V1
page 76/135
SPSB081
SPI
Symbol
tdis DO L tri (1)
Parameter
Condition
DO disable time
from low level to 3state
CL = 50 pF, Iload = 4
mA
ten DO tri H (1)
DO enable time
from tristate to high
level
td DO (1)
DO delay time
Min
Typ
Max
Unit
Item
50
100
ns
B.029
50
100
ns
B.030
25
30
ns
B.031
pull-up load to V1
CL = 50 pF, Iload = -1
mA
pull-down load to
GND
VDO < 0.3 V1 or
VDO > 0.7 V1,
CL = 50 pF
1. Guaranteed by design.
Table 60. CSN timing
Prerelease product(s)
Symbol
tCSN_HI,min
tCSNfail (1)
Parameter
Minimum CSN HI time,
active mode
Condition
Min
Transfer of SPI-command to input register
0.5
CSN low timeout
20
Typ
35
Max
50
Unit
Item
μs
B.032
ms
B.033
1. Guaranteed by design.
Figure 35. SPI – transfer timing diagram
The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed
from the high to low transition of CLK.
DS14048 - Rev 1
page 77/135
SPSB081
SPI
Prerelease product(s)
Figure 36. SPI input timing
DS14048 - Rev 1
page 78/135
SPSB081
SPI
Prerelease product(s)
Figure 37. SPI output timing
DS14048 - Rev 1
page 79/135
SPSB081
SPI
Prerelease product(s)
Figure 38. SPI CSN - output timing
Figure 39. SPI–CSN low to high transition and global status bit access
DS14048 - Rev 1
page 80/135
SPSB081
Debug input
5.16
Debug input
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V ≤
VsREG ≤18 V, Tj = from -40°C to 150°C
Table 61. Debug input
5.17
Symbol
Parameter
Condition
Min
Typ
VdiL
Input voltage low
level
V1 = 3.3 V; 5 V
1
1.45
VdiH
Input voltage high
level
V1 = 3.3 V; 5 V
VdiHYS
Input hysteresis
V1 = 3.3 V; 5 V
Rin
Pull-down resistor
1.8
0.2
0.4
13
29
Max
2.3
45
Unit
Item
V
A.043
V
A.044
V
A.045
kΩ
A.046
Interrupt output
Prerelease product(s)
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin.
6 V ≤ VsREG ≤ 18 V, Tj = from -40°C to 150°C
Table 62. Interrupt output
5.18
Symbol
Parameter
Condition
Min
VINTL
output low level
V1 = 3.3 V; 5 V, IINT
= -4mA
VINTH
output high level
V1 = 3.3 V; 5 V, IINT
= 4 mA
V1-0.5
IINTLK
Tristate leakage
current
0 V < VINT <V1
-10
tInterrupt
Interrupt pulse
duration ( RxD_L)
Tested by scan
42
RNINT
NINT pull up int.
resistor
10
Typ
Max
Unit
Item
0.2
0.5
V
A.047
V
A.048
10
μA
A.049
56
70
μs
A.050
25
40
kΩ
A.074
V1-0.2
Timer1 and Timer2
6 V ≤ VsREG ≤ 18 V, Tj = from -40°C to 150°C.
Table 63. Timer1 and Timer2 values
DS14048 - Rev 1
Symbol
Parameter
Condition
ton1
Timer on time
Tested by scan
ton2
Timer on time
ton3
Min
Typ
Max
Unit
Item
0.1
ms
F.006
Tested by scan
0.3
ms
F.007
Timer on time
Tested by scan
1
ms
F.008
ton4
Timer on time
Tested by scan
10
ms
F.009
ton5
Timer on time
Tested by scan
20
ms
F.010
T1
Timer period
Tested by scan
10
ms
F.011
T2
Timer period
Tested by scan
20
ms
F.012
T3
Timer period
Tested by scan
50
ms
F.013
T4
Timer period
Tested by scan
100
ms
F.014
T5
Timer period
Tested by scan
200
ms
F.015
page 81/135
SPSB081
SGND loss comparator
5.19
Symbol
Parameter
Condition
T6
Timer period
Tested by scan
T7
Timer period
T8
Timer period
Min
Typ
Max
Unit
Item
500
ms
F.016
Tested by scan
1000
ms
F.017
Tested by scan
2000
ms
F.018
SGND loss comparator
Tj = from -40 °C to 150 °C, unless otherwise specified.
Table 64. SGND loss comparator
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Item
VSGNDloss
Input voltage low
level
VSREG = 13.5 V
200
400
600
mV
A.052
tSGNDloss
Filter time
VSREG = 13.5 V;
Tested by scan
µs
A.053
Prerelease product(s)
7
DS14048 - Rev 1
page 82/135
SPSB081
Application
6
Application
Prerelease product(s)
Figure 40. Typical application diagram
DS14048 - Rev 1
page 83/135
SPSB081
SPI registers
7
SPI registers
7.1
Global status byte (GSB)
Table 65. Global status byte (GSB)
Global status byte (GSB)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
1 (R)
0 (R)
0 (R)
0 (R)
0 (R)
0 (R)
0 (R)
0 (R)
GSBN
RSTB
SPIE
PLE
FE
DE
GW
FS
Global
status bit
inverted
Reset
SPI error Physical layer error (CAN, LIN) Functional error Device error Global warning Fail safe
Prerelease product(s)
Table 66. Global status byte (GSB) description
Bit
Name
Description
Global status bit inverted
The GSBN is a logically NOR combination of GSB bits 24 to bit 30.(1)
31
GSBN
This bit can also be used as global status flag without starting a complete communication frame as it
is present at SDO directly after pulling CSN low.
0 = error detected (1 or several GSB bits from 24 to 30 are set)
1 = no error detected (default after power on)
Reset
The RSTB indicates a device reset and is set in case of the following events:
SR1 (0x31)
30
RSTB
•
VPOR
•
WDFAIL
•
V1UV (when UV is more than tUV1)
•
FORCED SLEEP TSD2/V1SC
0 = no reset signal has been generated (default)
1 = reset signal has been generated
RSTB is cleared by a read & clear command to all bits in status register 1 causing the reset event.
SPI error bit
The SPIE indicates errors related to a wrong SPI communication.
SR7 (0x7)
29
SPIE (2)
•
SPI_INV_CMD
•
SPI_SCK_CNT
The bit is also set in case of an SPI CSN time-out detection
0 = no error (default)
1 = error detected
Physical layer error
The PLE is a logical OR combination of errors related to the LIN and CAN transceivers.
SR2 (0x32) and SR6 (0x36)
28
DS14048 - Rev 1
PLE (2)
•
LIN_PERM_DOM
•
LIN_TXD_DOM
•
LIN_PERM_REC
•
CAN_RXD_REC
page 84/135
SPSB081
Global status byte (GSB)
Bit
Name
Description
•
CAN_PERM_REC
•
CAN_PERM_DOM
•
CAN_TXD_DOM
0 = no error (default)
1 = error detected
PLE is cleared by a read & clear command to all related bits in status registers 2.
Functional error bit
The FE is a logical OR combination of errors coming from functional blocks.
SR2 (0x32):
•
V2SC
SR3 (0x33):
27
FE
•
OUTx OC
SR4 (0x34):(3)
•
OUTx OL
Prerelease product(s)
0 = no error (default)
1 = error detected
FE is cleared by a read & clear command to all related bits in status registers 2, 3, 4
Device error bit
DE is a logical OR combination of global errors related to the device.
SR1 (0x31):
•
TSD1
SR2 (0x32):
26
DE
•
VS_OV
•
VS_UV
•
VSREG_OV
•
VSREG_UV
•
V1_OV
0 = no error (default)
1 = error detected
DE is cleared by a read & clear command to all related bits in status registers 2
Global warning bit
GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change
or switch off of functions.
SR2 (0x32):
25
GW (2)
•
V1FAIL
•
V2FAIL
•
CAN_RXD_REC
•
TW (3)
•
SPI_INV_CMD
•
SPI SCK CNT
SR6 (0x36):
•
CAN_SUP_LOW
0 = no error (default)
1 = error detected
GW is cleared by a read & clear command to all related bits in status register 2.
Failsafe
24
FS
The FS bit indicates that the device was forced into a safe state due to the following failure conditions:
SR1 (0x31):
•
DS14048 - Rev 1
WDFAIL
page 85/135
SPSB081
Global status byte (GSB)
Bit
Name
Description
•
V1UV (when UV is more than 2ms)
•
TSD2
•
FORCED SLEEP TSD/V1SC
SR2(0x32)
•
FORCED SLEEP V1OV
SR6 (0x36):
•
SGNDLOSS
All control Registers are set to default
Control registers are blocked for WRITE access except the following bits:
CR1 (0x01):
•
TRIG
•
CAN_ACT
CR2 (0x02):
•
Timer settings (bits 8…13 and bits 16…21)
Prerelease product(s)
CR5 (0x05):
•
OUT1_x (bits 0…2)
•
OUT2_x (bits 4…6)
•
OUT3_x (bits 8…10)
•
OUT4_x (bits 12…14)
•
CR9 (0x09) to CR11 (0x0B) PWM frequency and duty cycles
Config register (0x3F)
•
V2_0
•
V2_1
0 = fail-safe inactive (default)
1 = fail-safe active
FS is cleared upon exit from fail-safe mode (refer to Section 3.7 Fail safe mode )
1. Individual failure flags may be masked in the CR1 (0x26).
2. Bit may be masked in the configuration register (0x3F), that is, the bit will not be included in the global status bit (GSB).
3. Open load status flags may be masked in the Configuration register (0x3F), i.e. the open load flag will be included in the FE
flag, but will not set the GSB. TW failure status flags may be masked in the Configuration register (0x3F), i.e. the TW flag
will be included in the GW flag, but will not set the GSB.
DS14048 - Rev 1
page 86/135
DS14048 - Rev 1
7.2
Control registers overview
Table 67. Global control registers
Bit
31
30
29
28
27
26
25
24
GSBN
RSTB
SPIE
PLE
FE
DE
GW
FS
Mode
R
Table 68. Control registers overview
Prerelease product(s)
Addr.
CR#
Bits
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WU1_PU
RES
RES
WU2_EN
WU1_EN
RES
WU2_FILT_1
WU2_FILT_0
WU1_FILT_1
WU1_FILT_0
TIMER_WU_ EN
TRIG
MSB
Reserved
0x00
Reserved
LSB
MSB
0x01
0x2
0x3
page 87/135
0x6
RES
RES
WU2_PU
RES
RES
RES
LSB
RES
CAN
_REC_ONLY
CAN_ACT
LIN_WU_ EN
CAN_WU_EN
TIME_ NINT
_SEL
MSB
RES
RES
T2_ON_2
T2_ON_1
T2_ON_0
T2_PER_2
T2_PER_1
T2_PER_0
RES
RES
T1_ON_2
T1_ON_1
T1_ON_0
T1_PER_2
T1_PER_1
T1_PER_0
LSB
V1_RESET_1
V1_RESET_0
V1_OVP
WD_TIME
V2_TKR
V2_RAIL
STBY_SEL
GO_STBY
MSB
VSREG_LOCK_
EN
VS_LOCK_EN
RES
RES
VS_OV_SD_EN
VS_UV_SD_EN
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
OUT4_2
OUT4_1
OUT4_0
RES
OUT3_2
OUT3_1
OUT3_0
LSB
RES
OUT2_2
OUT2_1
OUT2_0
RES
OUT1_2
OUT1_1
OUT1_0
MSB
RES
RES
RES
RES
RES
RES
RES
CR1
CR2
CR3
CR4
CR5
CR6
RES
R/W
R/W
R/W
R/W
R/W
R/W
SPSB081
0x5
Reserved
Control registers overview
0xa
Mode
DS14048 - Rev 1
Addr.
0x6
0x7
Prerelease product(s)
0x8
0x9
CR#
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
CM
RES
RES
RES
CM_SEL_1
CM_SEL_0
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
PWM4_FREQ
PWM3_FREQ
PWM2_FREQ
PWM1_FREQ
Bits
CR6
CR7
CR8
CR9
LSB
MSB
0x0A
0x0B
0x0C
0x32
PWM1_DC_9
PWM1_DC_8
PWM1_DC_7
PWM1_DC_6
PWM1_DC_5
PWM1_DC_4
PWM1_DC_1
PWM1_DC_0
RES
RES
PWM2_DC_9
PWM2_DC_8
LSB
PWM2_DC_7
PWM2_DC_6
PWM2_DC_5
PWM2_DC_4
PWM2_DC_3
PWM2_DC_2
PWM2_DC_1
PWM2_DC_0
MSB
RES
RES
PWM3_DC_9
PWM3_DC_8
PWM3_DC_7
PWM3_DC_6
PWM3_DC_5
PWM3_DC_4
PWM3_DC_3
PWM3_DC_2
PWM3_DC_1
PWM3_DC_0
RES
RES
PWM4_DC_9
PWM4_DC_8
LSB
PWM4_DC_7
PWM4_DC_6
PWM4_DC_5
PWM4_DC_4
PWM4_DC_3
PWM4_DC_2
PWM4_DC_1
PWM4_DC_0
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
-
-
PWM9_DC_9
PWM9_DC_8
PWM9_DC_7
PWM9_DC_6
PWM9_DC_5
PWM9_DC_4
PWM9_DC_3
PWM9_DC_2
PWM9_DC_1
PWM9_DC_0
-
-
PWM10_DC_9
PWM10_DC_8
LSB
PWM10_DC_7
PWM10_DC_6
PWM10_DC_5
PWM10_DC_4
PWM10_DC_3
PWM10_DC_2
PWM10_DC_1
PWM10_DC_0
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
CR11
CR12
CR5
CR13
CR14
LSB
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
SPSB081
page 88/135
0x0E
RES
PWM1_DC_2
R/W
Control registers overview
0x0D
RES
PWM1_DC_3
CR10
Mode
DS14048 - Rev 1
Addr.
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Bits
MSB
0x0F
0x10
Prerelease product(s)
CR#
23
0x11
0x12
0x13
0x14
0x3B
page 89/135
0x17
CR17
CR18
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
TSD_CLUSTER_
EN
OUT4_CCM_EN
OUT3_CCM_EN
OUT2_CCM_EN
OUT1_CCM_EN
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
-
-
-
-
-
-
-
HS0_3
HS0_2
HS0_1
HS0_0
HS15_3
HS15_2
HS15_1
HS15_0
LSB
HS14_3
HS14_2
HS14_1
HS14_0
HS13_3
HS13_2
HS13_1
HS13_0
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
CR19
CR20
CR14
CR21
CR22
CR23
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPSB081
0x16
CR16
R/W
Control registers overview
0x15
CR15
Mode
DS14048 - Rev 1
Addr.
0x17
Prerelease product(s)
0x22
0x3F
CR#
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
IWK
ICMP
ICMP_SET
MSB
CAN_LOOP_EN
WU_NINT_MASK
DIAGN_EXT
ICMP_CONFIG_
EN
WD_CONFIG_EN
MASK_RSTB
MASK_OL
RES
MASK_PLE
MASK_GW
CAN_AUTO_BIA
S
DIR/WU2_EN
V2_1
V2_0
RES
Bits
CR23
CR34
Conf
LIN_TXD_TOUT
CANTO_NINT_M
LIN_WU_config
_EN
ASK
MASK_TW
Reg
LSB
MASK_FE
MASK_DE
Mode
R/W
R/W
R/W
SPSB081
Control registers overview
page 90/135
DS14048 - Rev 1
7.3
Status register overview
Table 69. Global status registers
Bit
31
30
29
28
27
26
25
24
GSBN
RSTB
SPIE
PLE
FE
DE
GW
FS
Mode
R
Table 70. Status registers overview
Prerelease product(s)
Addr./
CR#
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
RES
WU2_WAKE
WU1_WAKE
WAKE_CAN
WAKE_LIN
WAKE_TIMER
DEBUG_ACTIVE
V1UV
V1_
RESTART_2
V1_
RESTART_1
V1_ RESTART_0
WDFAIL_CNT_3
WDFAIL_CNT_2
WDFAIL_CNT_1
WDFAIL_CNT_0
LSB
DEVICE_
STATE_1
DEVICE_
STATE_0
TSD2
TSD1
WDFAIL
VPOR
MSB
LIN_PERM_DO
M
LIN_TXD_DOM
LIN_PERM_REC
CAN_RXD_REC
CAN_PERM_RE
C
CAN_PERM
_DOM
CAN_TXD_ DOM
CANTO
FORCED_SLEE
P_V1OV
RES
RES
RES
SPI_INV_CMD
SPI_SCK_CNT
V1_OV
TW
LSB
V2SC
V2FAIL
V1FAIL
RES
VSREG_OV
VSREG_UV
VS_OV
VS_UV
MSB
RES
RES
OUT4_OC
OUT3_OC
OUT2_OC
OUT1_OC
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
OUT4_OL
OUT3_OL
OUT2_OL
OUT1_OL
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
WD_TIMER_ST
ATE_1
WD_TIMER_ST
ATE_0
RES
RES
WU2_STATE
WU1_STATE
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Bits
0x31
0x32
0x33
0x35
0x36
SR1
SR2
SR3
SR4
SR5
SR6
Forced_Sleep_TS FORCED_SLEEP
D2/V1SC
_WD
Mode
R
R
R
R
R
R
SPSB081
21
Status register overview
22
MSB
0x34
page 91/135
23
DS14048 - Rev 1
Addr./
0x36
0x37
0x38
CR#
SR6
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
RES
RES
SGNDLOSS
IP_SUP_LOW
CAN_SUP_LOW
RES
RES
RES
MSB
RES
RES
RES
RES
TSD1 CL4
TSD1 CL3
TSD1 CL2
TSD1 CL1
RES
RES
RES
RES
RES
RES
RES
RES
LSB
RES
RES
RES
RES
RES
RES
RES
RES
MSB
RES
RES
RES
RES
TW CL4
TW CL3
TW CL2
TW CL1
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Bits
SR7
SR8
R
R
R
Prerelease product(s)
LSB
Mode
SPSB081
Status register overview
page 92/135
SPSB081
Control registers
7.4
Control registers
15
14
13
12
11
10
9
8
RES
WU2_PU
WU1_PU
RES
RES
WU2_EN
WU1_EN
RES
RES
RES
RES
WU2_FILT_1
WU2_FILT_0
WU1_FILT_1
WU1_FILT_0
Bit
name
Access
0 (R)
0 (R/W)
0 (R)
1 (R/W)
0 (R)
0 (R/W)
7
6
5
4
3
2
0
(R)
0 (R/W)
1 (R/W)
1
0
TRIG
16
TIMER_WU _EN
17
TIMER_NINT _SEL
18
CAN_WU _EN
19
LIN_WU_EN
20
CAN_ACT
21
CAN _REC_ONLY
22
RES
23
RES
Table 71. Control register CR1 (0x01)
0 (R/W)
Prerelease product(s)
Table 72. CR1 signals description
Bit
Name
Description
23
RES
reserved
22
RES
reserved
21
WU2_PU
20
WU1_PU
19
RES
reserved
18
RES
reserved
17
WU2_EN
Wake-up Input x (WUx): configuration of internal current source
0 = pull-down (default)
1 = pull-up
Wake-up Input x (WUx) enable
0 = WUx disabled
16
WU1_EN
1 = WUx enabled (default)
Note:
For WU2 the setting is only valid if input is configured as wake-up input in Configuration Register (0x3F)
15
RES
reserved
14
RES
reserved
13
RES
reserved
12
RES
reserved
11
WU2_FILT_1
WUx FILT_1, 0
10
WU2_FILT_0
0 0: Wake-up inputs monitored in static mode (filter time tWU_stat) (default)
9
WU1_FILT_1
0 1: Wake-up inputs monitored in cyclic mode with Timer2 (filter time: tWU_cyclic; blanking time 80% of timer
ON time(1)))
8
WU1_FILT_0
1 0: Wake-up inputs monitored in cyclic mode with Timer1 (filter time: tWU_cyclic; blanking time 80% of timer
ON time(1)))
1 1: Invalid setting; command is ignored, and SPI INV CMD is set
7
RES
reserved
CAN Receive only Mode
6
CAN _REC_ONLY
0 CAN Receive Only Mode disabled (default)
1 CAN Receive Only Mode enabled (CAN Trx must be activated, see CAN_ACT bit)
5
CAN_ACT
DS14048 - Rev 1
CAN Transceiver activation
0 = CAN Trx Low Power Mode (default)
page 93/135
SPSB081
Control registers
Bit
Name
Description
1 = CAN Trx Active Mode
At Exit from Active Mode, this bit is set to ‘0’ automatically
Enable wake-up by LIN
0 = disabled
4
LIN_WU_EN(2)
1 = enabled (default)
Note:
The wake-up behavior is configurable in the Configuration Register (0x3F)
CAN Receive only Mode
3
CAN_WU_EN
(2)
0 CAN Receive Only Mode disabled (default)
1 CAN Receive Only Mode enabled (CAN Trx must be activated, see CAN_ACT bit)
CAN Transceiver activation
2
TIMER_NINT _SEL
0 = CAN Trx Low Power Mode (default)
1 = CAN Trx Active Mode
Enable wake-up by LIN
0 = disabled
1
TIMER_WU _EN
1 = enabled (default)
Note:
The wake-up behavior is configurable in the Configuration Register (0x3F)
CAN Receive only Mode
0
TRIG
0 CAN Receive Only Mode disabled (default)
1 CAN Receive Only Mode enabled (CAN Trx must be activated, see CAN_ACT bit)
1. Lower is the timer duration and major is the contribution of output tdON
2. For SPSB0815 and SPSB0813 either LIN, CAN or WUx must be enabled as wake-up source. For
SPSB081C devices (without LIN), the LIN_WU_EN is forced to 0. If DIR_WU2_EN is set to 0, setting
all bits 3, 4, 16 & 17 to ‘0’ is an invalid setting. If DIR_WU2_EN is set to 1, setting all bits 3, 4, 16 to ‘0’ is an
invalid setting. In case of invalid setting, all wake-up sources will be configured according to default setting
and SPI Error Bit (SPIE) in Global Status Register will be set.
17
16
15
14
13
12
11
10
9
8
7
6
T2 ON_2
T2 ON_1
T2 ON_0
T2 PER_2
T2 PER_1
T2 PER_0
RES
RES
T1 ON_2
T1 ON_1
T1 ON_0
T1 PER_2
T1 PER_1
T1 PER_0
V1 RESET_1
V1 RESET_0
Bit
name
Access
0 (R)
0 (R/W)
0 (R)
0 (R/W)
5
4
3
1
(R/
W)
2
1
0
GO STBY
18
STBY SEL
19
V2_RAIL
20
V2_TKR
21
WD_TIME
22
V1_OVP
23
RES
Table 73. Control register CR2 (0x02)
RES
Prerelease product(s)
At Exit from Active Mode, this bit is set to ‘0’ automatically
0 (R/W)
Table 74. CR2 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
T2 ON_2
Configuration of Timer 2 on-time(1):
20
T2 ON_1
0 0 0 ton1 (default)
DS14048 - Rev 1
Description
page 94/135
SPSB081
Control registers
Bit
Name
Description
0 0 1 ton2
0 1 0 ton3
19
T2 ON_0
0 1 1 ton4
1 0 0 ton5
1 0 1 invalid setting; command is ignored and SPI INV CMD is set
18
T2 PER_2
Configuration of Timer 2 Period (1):
17
T2 PER_1
0 0 0 T1 (default)
0 0 1 T2
0 1 0 T3
0 1 1 T4
16
T2 PER_0
1 0 0 T5
1 0 1 T6
1 1 0 T7
Prerelease product(s)
1 1 1 T8
15
RES
Reserved
14
RES
Reserved
13
T1 ON_2
Configuration of Timer 1 on-time(1):
12
T1 ON_1
0 0 0 ton1 (default)
0 0 1 ton2
0 1 0 ton3
0 1 1 ton4
11
T1 ON_0
1 0 0 ton5
1 0 1 invalid setting; command is ignored and SPI INV CMD is set
1 1 0 invalid setting; command is ignored and SPI INV CMD is set
1 1 1 invalid setting; command is ignored and SPI INV CMD is set
10
T1 PER_2
Configuration of Timer 1 Period(1):
9
T1 PER_1
0 0 0 T1 (default)
0 0 1 T2
0 1 0 T3
0 1 1 T4
8
T1 PER_0
1 0 0 T5
1 0 1 T6
1 1 0 T7
1 1 1 T8
7
V1 RESET_1
Voltage regulator V1 reset level:
0 0 : VRT4 (default)
6
V1 RESET_0
0 1 VRT3
1 0 VRT2
1 1 VRT1
Voltage Regulator V1 Overvoltage Protection set
5
V1_OVP
0 = disabled
1 = enabled (default)
4
WD_TIME
DS14048 - Rev 1
Window Watchdog Trigger Time
0 TSW1 (default)
page 95/135
SPSB081
Control registers
Bit
Name
Description
1 TSW2
Writing to WD_TIME is blocked unless WD CONFIG EN = 1.
The modified WD Trigger Time is valid only after the next trig event. Before it, old TSW value is kept.
Voltage Regulator V2 configurable as a linear independent LDO or a tracker of the V1 Voltage Regulator
3
V2_TKR
0 Linear independent LDO (default)
1 Tracker of the V1 voltage regulator
Voltage Regulator V2 rail configuration
2
V2_RAIL
0 V2 = 3.3V (default)
1 V2 = 5V
1
STBY SEL
Following are the valid settings:
1 1 : go to V1 standby
0
1 0 : No transition to standby
GO STBY
0 1 : Go to VBAT_standby
1. When the configuration of a timer is changed, the timer is automatically restarted using the new
configuration.
Access
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RES
VS_OV_SD_EN
VS_UV_SD_EN
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
1 (R/W)
DS14048 - Rev 1
0 (R)
1 (R/W)
0 (R)
1
0
RES
21
RES
22
RES
Bit
name
23
VS_LOCK_ENA
Table 75. Control register CR3 (0x03)
VSREG_LOCK_ENA
Prerelease product(s)
0 0 : No transition to standby (default)
0 (R)
page 96/135
SPSB081
Control registers
Table 76. CR3 signals description
Bit
Name
Description
Lockout of Vsreg related outputs after Vsreg over-/undervoltage shutdown
0 Vsreg related outputs are turned on automatically and
status bits (VSREG_UV, VSREG_OV) are cleared
23
VSREG_LOCK_EN
1 Vsreg related outputs remain turned off until status bits
(VSREG_UV, VSREG_OV) are cleared (default)
Note: lockout is always disabled in standby modes in order to ensure supply of external contacts and detect
wake-up conditions
Lockout of Vs related outputs after Vs over-/undervoltage shutdown
0 Vs related outputs are turned on automatically and
status bits (VS_UV, VS_OV) are cleared
22
VS_LOCK_EN
1 Vs related outputs remain turned off until status bits
Note: lockout is always disabled in standby modes in order to ensure supply of external contacts and detect
wake-up conditions
21
RES
reserved
20
RES
reserved
19
RES
reserved
18
RES
reserved
17
RES
16
RES
15
RES
14
RES
13
RES
12
RES
11
RES
reserved
10
RES
reserved
9
RES
reserved
8
RES
reserved
7
RES
reserved
6
RES
reserved
5
RES
reserved
4
RES
reserved
3
RES
reserved
2
RES
reserved
1
RES
reserved
0
RES
reserved
reserved
reserved
reserved
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
DS14048 - Rev 1
1
0
RES
21
RES
22
RES
Bit
name
23
RES
Table 77. Control register CR4 (0x04)
RES
Prerelease product(s)
(VS_UV, VS_OV) are cleared (default)
0 (R)
page 97/135
SPSB081
Control registers
Bit
Name
Description
23
RES
reserved
22
RES
reserved
21
RES
reserved
20
RES
reserved
19
RES
reserved
18
RES
reserved
17
RES
reserved
16
RES
reserved
15
RES
reserved
14
RES
reserved
13
RES
reserved
12
RES
reserved
11
RES
reserved
10
RES
reserved
9
RES
reserved
8
RES
reserved
7
RES
reserved
6
RES
reserved
5
RES
reserved
4
RES
reserved
3
RES
reserved
2
RES
reserved
1
RES
reserved
0
RES
reserved
0 (R/W)
0
(R)
0 (R/W)
0
(R)
4
0 (R/W)
3
2
0
(R)
1
0
OUT1_0
5
OUT1_1
6
OUT1_2
7
RES
8
OUT2_0
9
OUT2_1
10
OUT2_2
11
RES
OUT4_2
12
OUT3_0
RES
0 (R)
13
OUT3_1
14
OUT3_2
15
RES
16
OUT4_0
17
OUT4_1
18
RES
RES
Access
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 79. Control register CR5 (0x05)
RES
Prerelease product(s)
Table 78. CR4 signals description
0 (R/W)
Table 80. CR5 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
DS14048 - Rev 1
Description
page 98/135
SPSB081
Control registers
Bit
Name
Description
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
OUT4_2
High Side Driver OUT4 Configuration
13
OUT4_1
OUT4_2,1,0:
0 0 0 Off (default)
0 0 1 On
0 1 0 Timer 1
12
OUT4_0
0 1 1 Timer 2
1 0 0 PWM4
1 0 1 DIR/WU2
1 1 0 Off
Prerelease product(s)
1 1 1 Off
11
RES
Reserved
10
OUT3_2
High Side Driver OUT3 Configuration
9
OUT3_1
OUT3_2,1,0:
0 0 0 Off (default)
0 0 1 On
0 1 0 Timer 1
8
OUT3_0
0 1 1 Timer 2
1 0 0 PWM3
1 0 1 DIR/WU2
1 1 0 Off
1 1 1 Off
7
RES
reserved
6
OUT2_2
High Side Driver OUT2 Configuration
5
OUT2_1
OUT2_2,1,0:
0 0 0 Off (default)
0 0 1 On
0 1 0 Timer 1
4
OUT2_0
0 1 1 Timer 2
1 0 0 PWM2
1 0 1 DIR/WU2
1 1 0 Off
1 1 1 Off
3
RES
reserved
2
OUT1_2
High Side Driver OUT1 Configuration
1
OUT1_1
OUT1_2,1,0:
0 0 0 Off (default)
0 0 1 On
0
OUT1_0
0 1 0 Timer 1
0 1 1 Timer 2
1 0 0 PWM1
1 0 1 DIR/WU2
DS14048 - Rev 1
page 99/135
SPSB081
Control registers
Bit
Name
Description
1 1 0 Off
1 1 1 Off
16
15
14
13
12
11
10
9
8
7
6
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
5
4
3
1
(R/
W)
0 (R)
2
1
0
CM SEL_0
17
CM SEL_1
18
RES
19
RES
20
RES
21
CM
22
RES
Bit
name
23
RES
Table 81. Control register CR6 (0x06)
0 (R/W)
Prerelease product(s)
Table 82. CR6 signals description
Bit
Name
Description.
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
CM
Current monitor:
0 off (tristate)
1 on (default)
3
RES
Reserved
4
RES
Reserved
2
RES
Reserved
1
CM SEL_1
A current image of the selected binary coded output is multiplexed to the CM output.
CM SEL_1, 0, Selected Output:
0
CM SEL_0
0 0 OUT1 (default)
0 1 OUT2
DS14048 - Rev 1
page 100/135
SPSB081
Control registers
Bit
Name
Description.
1 0 OUT3
1 1 OUT4
RES
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
RES
1
0
RES
20
RES
RES
RES
21
RES
2
RES
RES
22
Access
RES
RES
RES
23
RES
RES
0
RES
RES
1
RES
RES
2
RES
RES
3
RES
RES
4
RES
RES
5
RES
RES
6
RES
RES
7
RES
RES
8
RES
RES
9
RES
RES
10
RES
11
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 83. Control register CR7 (0x07)
0 (R)
Prerelease product(s)
Table 84. CR7 signals description
Bit
Name
Description
23
RES
22
RES
21
RES
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
Reserved
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Table 85. Control register CR8 (0x08)
Bit
name
Access
DS14048 - Rev 1
0 (R)
page 101/135
SPSB081
Control registers
Bit
Name
Description
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
PMW4 FREQ
PMW3 FREQ
Access
0 (R)
1
0
PMW1 FREQ
21
PMW2 FREQ
22
RES
Bit
name
23
RES
Table 87. Control register CR9 (0x09)
RES
Prerelease product(s)
Table 86. CR8 signals description
0 (R/W)
Table 88. CR9 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
DS14048 - Rev 1
Description
page 102/135
SPSB081
Bit
Name
Description
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
Select PWM4 frequency
PWM4
3
0 fPWM1 =125 Hz (default)
_FREQ
1 fPWM2 =250 Hz
Select PWM3 frequency
PWM3
2
0 fPWM1 =125 Hz (default)
_FREQ
1 fPWM2 =250 Hz
Select PWM2 frequency
PWM2
1
0 fPWM1 =125 Hz (default)
_FREQ
1 fPWM2 =250 Hz
Select PWM1 frequency
PWM1
0
0 fPWM1 =125 Hz (default)
_FREQ
1 fPWM2 =250 Hz
Access
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PWM1 DC_8
PWM1 DC_7
PWM1 DC_6
PWM1 DC_5
PWM1 DC_4
PWM1 DC_3
PWM1 DC_2
PWM1 DC_1
PWM1 DC_0
RES
RES
PWM2 DC_9
PWM2 DC_8
PWM2 DC_7
PWM2 DC_6
PWM2 DC_5
PWM2 DC_4
PWM2 DC_3
PWM2 DC_2
0 (R)
0 (R/W)
0 (R)
1
0
PWM2 DC_0
21
PWM2 DC_1
22
PWM1 DC_9
Bit
name
23
RES
Table 89. Control register CR10 (0x0A)
RES
Prerelease product(s)
Control registers
0 (R/W)
Table 90. CR10 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
PWM1 DC_9
DS14048 - Rev 1
Description
Binary coded on-dutycycle of PWM channel PWMx
PWM1_DC_9,8...,0 duty cycle:
page 103/135
SPSB081
Control registers
Bit
Name
20
PWM1 DC_8
19
PWM1 DC_7
18
PWM1 DC_6
17
PWM1 DC_5
16
PWM1 DC_4
Description
0 0 0 0 0 0 0 0 0 0 Off
0 0 0 0 0 0 0 0 0 1 1*100/1024
0 0 0 0 0 0 0 0 1 0 2*100/1024
... ... ...
1 1 1 1 1 1 1 1 0 1 1021*100/1024
1 1 1 1 1 1 1 1 1 0 1022*100/1024
15
PWM1 DC_3
14
PWM1 DC_2
13
PWM1 DC_1
12
PWM1 DC_0
11
RES
Reserved
10
RES
Reserved
9
PWM2 DC_9
8
PWM2 DC_8
7
PWM2 DC_7
Binary coded on-dutycycle of PWM channel PWM2 (1)
6
PWM2 DC_6
PWM2_DC_9,8...,0 duty cycle:
5
PWM2 DC_5
0 0 0 0 0 0 0 0 0 0 Off
4
PWM2 DC_4
0 0 0 0 0 0 0 0 0 1 1*100/1024
3
PWM2 DC_3
2
PWM2 DC_2
1
PWM2 DC_1
0
PWM2 DC_0
Binary coded on-duty cycle of PWM channel PWM1 (see above)
Binary coded on-dutycycle of PWM channel PWM2 (see below)
0 0 0 0 0 0 0 0 1 0 2*100/1024
... ... ...
1 1 1 1 1 1 1 1 0 1 1021*100/1024
1 1 1 1 1 1 1 1 1 0 1022*100/1024
1 1 1 1 1 1 1 1 1 1 1023*100/1024
1. To have a Duty Cycle equal to 100%, the Output Configuration shall be set in ON mode
Access
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PWM1 DC_8
PWM1 DC_7
PWM1 DC_6
PWM1 DC_5
PWM1 DC_4
PWM1 DC_3
PWM1 DC_2
PWM1 DC_1
PWM1 DC_0
RES
RES
PWM2 DC_9
PWM2 DC_8
PWM2 DC_7
PWM2 DC_6
PWM2 DC_5
PWM2 DC_4
PWM2 DC_3
PWM2 DC_2
0 (R)
0 (R/W)
0 (R)
1
0
PWM2 DC_0
21
PWM2 DC_1
22
PWM1 DC_9
Bit
name
23
RES
Table 91. Control register CR11 (0x0B)
RES
Prerelease product(s)
1 1 1 1 1 1 1 1 1 1 1023*100/1024
0 (R/W)
Table 92. CR11 signals description
Bit
Name
Description
23
RES
Reserved
22
RES
Reserved
21
PWM1 DC_9
20
PWM1 DC_8
PWM1_DC_9,8...,0 duty cycle:
19
PWM1 DC_7
0 0 0 0 0 0 0 0 0 0 Off
18
PWM1 DC_6
0 0 0 0 0 0 0 0 0 1 1*100/1024
17
PWM1 DC_5
0 0 0 0 0 0 0 0 1 0 2*100/1024
DS14048 - Rev 1
Binary coded on-dutycycle of PWM channel PWMx
page 104/135
SPSB081
Control registers
Bit
Name
Description
... ... ...
16
1 1 1 1 1 1 1 1 0 1 1021*100/1024
PWM1 DC_4
1 1 1 1 1 1 1 1 1 0 1022*100/1024
15
PWM1 DC_3
14
PWM1 DC_2
13
PWM1 DC_1
12
PWM1 DC_0
11
RES
Reserved
10
RES
Reserved
9
PWM2 DC_9
8
PWM2 DC_8
7
PWM2 DC_7
Binary coded on-dutycycle of PWM channel PWM2 .(1)
6
PWM2 DC_6
PWM2_DC_9,8...,0 duty cycle:
5
PWM2 DC_5
0 0 0 0 0 0 0 0 0 0 Off
4
PWM2 DC_4
0 0 0 0 0 0 0 0 0 1 1*100/1024
3
PWM2 DC_3
2
PWM2 DC_2
1
PWM2 DC_1
0
PWM2 DC_0
Binary coded on-duty cycle of PWM channel PWM1 (see above)
Binary coded on-dutycycle of PWM channel PWM2 (see below)
0 0 0 0 0 0 0 0 1 0 2*100/1024
... ... ...
1 1 1 1 1 1 1 1 0 1 1021*100/1024
1 1 1 1 1 1 1 1 1 0 1022*100/1024
1 1 1 1 1 1 1 1 1 1 1023*100/1024
1. To have a Duty Cycle equal to 100%, the Output Configuration shall be set in ON mode.
11
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
10
9
8
7
6
5
4
3
2
1
0
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 93. Control register CR12 (0x0C)
RES
Prerelease product(s)
1 1 1 1 1 1 1 1 1 1 1023*100/1024
0 (R)
Table 94. CR12 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
DS14048 - Rev 1
Description
page 105/135
SPSB081
Bit
Name
Description
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
8
RES
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Reserved
11
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
10
9
8
7
6
5
4
3
2
1
0
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 95. Control register CR13 (0x0D)
RES
Prerelease product(s)
Control registers
0 (R)
Table 96. CR13 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
DS14048 - Rev 1
Description
page 106/135
SPSB081
Control registers
Bit
Name
Description
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
11
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
10
9
8
7
6
5
4
3
2
1
0
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 97. Control register CR14 (0x0E)
0 (R)
Prerelease product(s)
Table 98. CR14 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
DS14048 - Rev 1
Description
page 107/135
SPSB081
Control registers
RES
0
RES
RES
1
2
1
0
RES
RES
2
RES
RES
3
RES
RES
4
RES
RES
5
10
9
8
7
6
5
4
3
RES
RES
6
RES
RES
7
RES
RES
8
RES
RES
9
RES
RES
Access
10
RES
11
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 99. Control register CR15 (0x0F)
0 (R)
Bit
Name
Description
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
22
21
20
19
18
17
16
15
14
13
12
11
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Bit
name
23
RES
Table 101. Control register CR16 (0x10)
RES
Prerelease product(s)
Table 100. CR15 signals description
Access
0 (R)
Table 102. CR16 signals description
Bit
Name
23
RES
DS14048 - Rev 1
Description
Reserved
page 108/135
SPSB081
Bit
Name
Description
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
11
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
10
9
8
7
6
5
4
3
2
1
0
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 103. Control register CR19 (0x13)
RES
Prerelease product(s)
Control registers
0 (R)
Table 104. CR17 to CR19 signals description
Bit
Name
Description
23
Reserved
22
Reserved
21
Reserved
20
Reserved
19
Reserved
18
Reserved
17
Reserved
16
Reserved
15
Reserved
DS14048 - Rev 1
page 109/135
SPSB081
Control registers
Name
Description
14
Reserved
13
Reserved
12
Reserved
11
Reserved
10
Reserved
9
Reserved
8
Reserved
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
12
11
RES
TSD_Cluster EN
RES
RES
RES
RES
RES
RES
OUTHS_CCM
RES
RES
Bit
name
Access
10
9
8
7
6
5
4
3
2
1
0
OUT7_CCM
13
OUT8_CCM
14
OUT9_CCM
15
OUT10_CCM
16
OUT11_CCM
17
OUT12_CCM
18
OUT13_CCM
19
OUT14_CCM
20
OUT15_CCM
21
RES
22
RES
23
RES
Table 105. Control register CR20 (0x14)
RES
Prerelease product(s)
Bit
0 (R/W)
Table 106. CR20 signals description
Bit
Name
Description
23
Reserved
22
Reserved
21
Reserved
Enables thermal warning and shutdown of outputs by cluster
20
TSD_Cluster EN
0: TSD and TW by cluster off (default)
1: TSD and TW by cluster on
19
Reserved
18
Reserved
17
Reserved
16
Reserved
15
Reserved
14
Reserved
13
OUTHS_CCM
DS14048 - Rev 1
Constant current mode on OUT_HS enable(1):
0 Disabled (default)
page 110/135
SPSB081
Control registers
Bit
Name
Description
1 Enabled
12
Reserved
11
Reserved
10
Reserved
9
Reserved
Constant current mode on OUT15 enable(1):
8
OUT15_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT14 enable(1):
7
OUT14_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT13 enable(1):
OUT13_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT12 enable(1):
5
OUT12_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT11 enable(1):
4
OUT11_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT10 enable(1):
3
OUT10_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT9 enable(1):
2
OUT9_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT8 enable(1):
1
OUT8_CCM
0 Disabled (default)
1 Enabled
Constant current mode on OUT7 enable(1):
0
OUT7_CCM
0 Disabled (default)
1 Enabled
1. Refer to Power outputs OUT1...15 and OUT_HS for the correct sequence of constant current mode
activation
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Access
DS14048 - Rev 1
1
0
RES
21
RES
22
RES
Bit
name
23
RES
Table 107. CR21(0x15) to CR24 (0x18)
RES
Prerelease product(s)
6
0 (R)
page 111/135
SPSB081
Control registers
Bit
Name
Description
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
RES
RES
8
7
6
5
4
3
2
0 (R/W)
1
0
ICMP_SET
RES
9
ICMP
RES
10
IWK
RES
11
RES
RES
12
RES
RES
Access
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 109. Control register CR34 (0x22)
RES
Prerelease product(s)
Table 108. CR21(0x15) to CR24 (0x18) signals description
0 (R/W)
Table 110. CR34 signals description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
RES
Reserved
18
RES
Reserved
DS14048 - Rev 1
Description
page 112/135
SPSB081
Bit
Name
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
Description
Wake-up event on CAN and wake-up pins in V1standby mode
2
IWK
0 Device moves in Active Mode (default)
1 Device remains in V1standby mode. Interrupt generated on NINT pins
V1 load current supervision
1
0 Enabled ; Watchdog is disabled in V1_standby when Iv1< ICMP (default)
ICMP
1 Disabled; watchdog is disabled upon transition into v1stby mode
setting ICMP = 1 is only possible when ICMP_config_en = 1
Set thresholds for ICMP:
0
ICMP_SET
0 Low values for rising and falling (default)
1 High values for rising and falling
Access
RES
MASK_PLE
MASK_GW
0 (R/W)
0 (R)
7
6
5
4
3
2
1
0 (R/W)
0
RES
8
V2_0
9
V2_1
10
DIR/WU2_EN
11
CAN_AUTO_BIAS
12
?????
13
MASK_DE
14
MASK_FE
15
MASK_OL
IC
WU
MP
_NI DIA
_C
NT GN
ON
_M _E
FIG
AS XT
_E
K
N
16
MASK_RSTB
17
MASK_TW
18
RES
19
RES
1
(R/
W)
20
WD_CONFIG_EN
0
(R/
W)
21
CANTO_NINT_MASK
Bit
name
22
LIN_TXD_TOUT_EN
23
LIN_WU_config
Table 111. Configuration register (0x3F)
CAN_LOOP_EN
Prerelease product(s)
Control registers
0
(R)
Table 112. Configuration register signals description
Bit
Name
Description
CAN Looping of TxD_C to RxD_C
23
CAN_LOOP_EN
0 CAN looping disabled (default)
1 CAN looping enabled
DS14048 - Rev 1
page 113/135
SPSB081
Control registers
Bit
Name
22
LIN_TXD_TOUT_EN
Description
LIN TxD timeout detection
0 LIN TxD timeout detection disabled
1 LIN TxD timeout detection enabled (default)
Configuration of LIN wake-up behaviour
21
LIN_WU_config
0 wake-up at recessive - dominant - recessive with t_dom > 28us (default)
(according to LIN 2.2a and Hardware Requirements for Transceivers version 1.3)
1 wake-up at recessive - dominant or dominant - recessive transition
20
CANTO_NINT_MASK
19
WU_NINT_MASK
0 CAN communication timeout is not masked (default)
1 CAN communication timeout is masked
0 Wake-up is not masked (default)
1 Wake-up is masked
Fail safe output configuration by DIAGN pin
Prerelease product(s)
0 Only Fail Safe mode is considered (e.g. Watchdog failure; V1
18
DIAGN_EXT
failure; Thermal Shutdown TSD2) (default).
1 DIAGN pin reflects one or more errors such as reported in the
GLOBAL STATUS BYTE register by Global Status Bit Not
(GSBN)
0 writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default)
17
ICMP_CONFIG_EN
1 writing ICMP = 1 is possible with next SPI command
bit is automatically reset to 0 after next SPI command
0 writing to WD Configuration (CR2 [0:1] is blocked (default)
16
WD_CONFIG_EN
1 writing to WD Configuration Bits is possible with next SPI command
bit is automatically reset to 0 after next SPI command
15
RES
reserved
14
RES
reserved
0 Thermal warning is not masked (default)
13
MASK_TW
1 Thermal warning is masked
i.e. it is reported as a Global Warning (GSB bit 1) but not as a
Global Error (GSB bit 7)
0 V1_UV Reset condition is not masked (default)
12
MASK_RSTB
1 V1_UV Reset condition is masked
i.e. reported as a Reset (GSB bit 6) but not as a
Global Error (GSB bit 7)
0 Open load condition at all outputs are not masked (default)
11
MASK_OL
1 Open load condition at all outputs are masked
i.e. it is reported as a Functional Error (GSB bit 27) but not as a Global Error (GSB bit 31)
10
RES
reserved
0 Physical Layer Errors are not masked (default)
9
MASK_PLE
1 Physical Layer Errors are masked
i.e. reported as a Physical Layer Error (GSB bit 4) but not as a
Global Error (GSB bit 7)
0 Global Warning conditions are not masked (default)
8
MASK_GW
1 Global Warning conditions are masked
i.e. reported as a Global Warning (GSB bit 1) but not as a
DS14048 - Rev 1
page 114/135
SPSB081
Status registers
Bit
Name
Description
Global Error (GSB bit 7)
0 Functional Error conditions are not masked (default)
7
1 Functional Error conditions are masked
MASK_FE
i.e. reported as a Functional Error (GSB bit 27) but not as a
Global Error (GSB bit 31)
0 Device Error conditions are not masked (default)
6
1 Device Error conditions are masked
MASK_DE
i.e. reported as a Device Error (GSB bit 2) but not as a
Global Error (GSB bit 7)
5
RES
Reserved
4
CAN_AUTO_BIAS
CAN automatic biasing activation
0: auto biasing disabled (default)
1: auto biasing enabled
3
0 WU2 configured as wake-up input (default)
1 DIR function enabled
2
V2_1
Voltage regulator V2 configuration:
0 0 : V2 OFF in all Modes (default)
1
0 1 : V2 ON in Active Mode; OFF in Standby Modes
V2_0
1 0 : V2 ON in Active and V1 Standby Mode; OFF in VBAT_standby Mode
1 1 : V2 ON in all Modes
0
RES
7.5
reserved
Status registers
14
13
12
11
10
9
8
7
6
5
4
3
2
V1_RESTART_0
WDFAIL_CNT_3
WDFAIL_CNT_2
WDFAIL_CNT_1
WDFAIL_CNT_0
DEVICE_STATE_1
DEVICE_STATE_0
TSD2
TSD1
FORCED_SLEEP_TSD2/V1SC
FORCED_SLEEP_WD
Bit
name
Access
R
R&C
R
1
0
VPOR
15
WDFAIL
16
V1_RESTART_1
WAKE_CAN
17
V1_RESTART_2
WU1_WAKE
18
V1UV
19
DEBUG_ACTIVE
20
WAKE_TIMER
21
WAKE_LIN
22
WU2_WAKE
23
RES
Table 113. Status register SR1 (0x31)
RES
Prerelease product(s)
Enable DIR input for direct drive of OUT1..4
DIR/WU2_EN(1)
R&C
Table 114. SR1 description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
WU2 WAKE
DS14048 - Rev 1
Description
Shows wake-up source
page 115/135
SPSB081
Status registers
Bit
Name
Description
20
WU1 WAKE
19
WAKE CAN
‘1’ = wake-up
18
WAKE LIN
Bits are latched until a “Read and clear” command
17
WAKE TIMER
16
DEBUG _ACTIVE
Indicates device is in debug mode
‘1’ = debug mode
Bit is latched until a “Read and clear” command
Indicates undervoltage condition at voltage regulator V1 (V1 < VRTx)
15
V1UV
‘1’ = undervoltage
Prerelease product(s)
Bit is latched until a “Read and clear” command
14
V1_RESTART_2
Indicates that the number of TSD2 events that caused a restart of voltage regulator V1
13
V1_ RESTART_1
12
V1_ RESTART_0
Bits cannot be cleared; the counter is automatically cleared if no additional TSD2 event occurs within 1
minute.
11
WDFAIL_CNT_3
10
WDFAIL_CNT_2
Indicates number of subsequent watchdog failures.
9
WDFAIL_CNT_1
Bits cannot be cleared; they are cleared with a valid watchdog trigger
8
WDFAIL_CNT_0
7
DEVICE_STATE_1
0 0: Active mode after power-on, or after read&clear command
0 1: Active mode after wake-up from V_standby mode (before read&clear command)
1 0: Active mode after wake-up from VBAT_standby mode (before read&clear command)
6
DEVICE_STATE_0
1 1: Not used
Bit is latched until a read&clear command
After a “read and clear access”, the device state is updated
5
TSD2
4
TSD1
Thermal shutdown 2 was reached
Bit is latched until a “Read and clear” command for Cluster 4 (bit 22 in SR7)
Thermal shutdown 1 was reached
Bit is latched until a “Read and clear” command for all Clusters (bit 16-23 in SR7)
Device entered forced sleep mode due to:
3
FORCED_SLEEP_TS •
D2/V1SC
•
Thermal shutdown or
Short circuit on V1 during startup
Bit is latched until a read&clear command
2
FORCED_SLEEP_W Device entered forced sleep mode due to multiple watchdog failures
D
Bit is latched until a read&clear command
1
WDFAIL
0
VPOR
Watchdog failure
Bit is latched until a “Read and clear” command
VREG Power-on Reset threshold (VPOR)(1) reached
Bit is latched until a “Read and clear” command
1. If VPOR is set after a cold startup, the device comes from a Power-on Reset.
DS14048 - Rev 1
page 116/135
SPSB081
Status registers
5
4
3
2
R&C
R
1
0
VS UV
R
6
VS OV
R&
C
7
VSREG UV
8
VSREG OV
RES
9
RES
RES
R
10
V1FAIL
RES
R&C
11
V2FAIL
12
V2SC
13
TW
14
V1_OV
15
SPI_SCK_CNT
16
SPI_INV_CMD
17
FORCED_SLEEP_V1OV
CAN_RXD_REC
18
CANTO
LIN_PERM_REC
Access
19
CAN_TXD_DOM
20
CAN_PERM_DOM
21
CAN_PERM_REC
22
LIN_TXD_DOM
Bit
name
23
LIN_PERM_DOM
Table 115. Status register SR2 (0x32)
R&C
Prerelease product(s)
Table 116. SR2 description
Bit
Name
23
LIN_PERM_DOM
Description
LIN bus signal is dominant for t > Tdom(bus)
Bit is latched until a “Read and clear” command
TxD_L pin is dominant for t > tdom(TXDL)
22
LIN_TXD_DOM
The LIN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
LIN bus signal does not follow TxD_L within tLIN
21
LIN_PERM_REC
The LIN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
RxD_C has not followed TxD_C for 4 times
20
CAN_RXD_REC
The CAN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
CAN bus signal did not follow TxD_C for 4 times
19
CAN_PERM_REC
The CAN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
18
CAN_PERM_DOM
17
CAN_TXD_ DOM
CAN bus signal is dominant for t > tCAN
Bit is latched until a “Read and clear” command
TxD_C pin is dominant for t > tdom(TXDC)
The CAN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
CAN communication timeout
16
CANTO
Bit is set if there is no communication on the bus for t > tSilence
CANTO indicates that there was a transition from BIASON to BIASOFF
Bit is latched until a read and clear access
15
FORCED_SLEEP_V1 Device entered forced sleep mode due to an overvoltage occurrence on V1
OV
Bit is latched until a “Read and clear” command
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
SPI INV CMD
DS14048 - Rev 1
Invalid SPI command
‘1’ indicates one of the following conditions was detected:
page 117/135
SPSB081
Status registers
Bit
Name
Description
•
access to undefined address
•
Write operation to status register
•
DI stuck at '0' or '1'
•
CSN timeout
•
Parity failure
•
invalid or undefined setting
The SPI frame is ignored
Bit is latched until a “Read and clear” command
SPI clock counter
10
SPI SCK CNT
‘1’ indicates that an SPI frame with the wrong number of CLK cycles was detected
Bit is latched until a valid SPI frame
V1 overvoltage
9
V1_OV
‘1’ indicates the voltage at V1 has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
Prerelease product(s)
Thermal warning
8
TW
‘1’ indicates that the temperature has reached the thermal warning threshold
Bit is latched until a “Read and clear” command
V2 short circuit detection
7
V2SC
‘1’ indicates that a short circuit to GND condition of V2 at turn-on of the regulator
(V2 < V2_fail for t > tv2_short)
Bit is latched until a “Read and clear” command
V2 failure detection
6
V2FAIL
‘1’ indicates that a V2 fail event occurred since last readout
(V2 < V2_fail for t > tv2_fail)
Bit is latched until a “Read and clear” command
V1 failure detection
5
V1FAIL
‘1’ indicates that a V1 fail event occurred since last readout
(V1 < V1_fail for t > tv1_fail)
Bit is latched until a “Read and clear” command
4
RES
Reserved
VSREG overvoltage
3
VSREG_OV
‘1’ indicates that the voltage at VSREG has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
VSREG undervoltage
2
VSREG_UV
‘1’ indicates that the voltage at VSREG has reached the undervoltage threshold
Bit is latched until a “Read and clear” command
Vs overvoltage
1
VS_OV
‘1’ indicates that the voltage at Vs has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
Vs undervoltage
0
VS_UV
‘1’ indicates that the voltage at Vs has reached the undervoltage threshold
Bit is latched until a “Read and clear” command
DS14048 - Rev 1
page 118/135
SPSB081
Status registers
RES
RES
RES
RES
RES
RES
RES
RES
4
3
2
1
0
RES
RES
5
2
1
0
RES
OUT1_OC
6
RES
OUT2_OC
R&C
7
RES
OUT3_OC
R
8
RES
9
8
7
6
5
4
3
RES
10
RES
11
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
Access
22
OUT4_OC
Bit
name
RES
23
RES
Table 117. Status register SR3 (0x33)
R
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
OUT4_OC
20
OUT3_OC
19
OUT2_OC
18
OUT1_OC
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Description
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
Bit is latched until a “Read and clear” command
Access
R
DS14048 - Rev 1
21
20
19
18
17
16
15
14
13
12
11
10
9
OUT3_OL
OUT2_OL
OUT1_OL
RES
RES
RES
RES
RES
RES
RES
RES
RES
Bit
name
22
OUT4_OL
23
RES
Table 119. Status register SR4 (0x34)
RES
Prerelease product(s)
Table 118. SR3 description
R&C
R
page 119/135
SPSB081
Status registers
Bit
Name
Description
23
RES
Reserved
22
RES
Reserved
21
OUT4_OL
20
OUT3_OL
19
OUT2_OL
18
OUT1_OL
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Open-load
‘1’ indicates an open-load condition was detected at the output
Bit is latched until a “Read and clear” command
WU2_STATE
WU1_STATE
RES
RES
RES
RES
RES
RES
10
9
8
7
6
5
4
3
2
1
0
RES
RES
Access
11
RES
12
RES
13
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
WD_TIMER_STATE_0
Table 121. Status register SR5 (0x35)
WD_TIMER_STATE_1
Prerelease product(s)
Table 120. SR4 description
R
Table 122. SR5 description
Bit
23
22
Name
Description
WD_TIMER_STATE_ Watchdog timer status:
1
0 0: 0 - 33%
WD_TIMER_STATE_
0 1: 33 - 66%
0
DS14048 - Rev 1
page 120/135
SPSB081
Status registers
Bit
Name
Description
1 1: 66 - 100%
1 0: Invalid configuration
21
RES
Reserved
20
RES
Reserved
19
WU2_STATE
State of WUx input
0 input level is low
18
1 input level is high
WU1_STATE
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
RES
8
7
6
5
Bit
name
Access
R
4
3
2
1
0
RES
RES
9
RES
RES
10
RES
RES
11
CAN_SUP_LOW
RES
12
IP_SUP_LOW
RES
13
SGNDLOSS
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
23
RES
Table 123. Status register SR6 (0x36)
RES
Prerelease product(s)
The bit shows the momentary status of WUx and cannot be cleared (“Live bit”)
R&C
R
Table 124. SR6 description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
DS14048 - Rev 1
Description
page 121/135
SPSB081
Bit
Name
19
RES
Reserved
18
RES
Reserved
17
RES
Reserved
16
RES
Reserved
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
Description
Loss of ground status bit
5
SGNDLOSS
‘1’ indicates that ground at SGND pin has been lost
Bit is not latched
4
Internal IP voltage supply (analog and/or digital) is less than 3V
IP_SUP_LOW
Bit is latched until a “Read and clear” command
Voltage at the CAN supply pin reached the CAN supply low warning threshold
3
VCANSUP < VCANSUPlow
CAN_SUP_LOW
Bit is latched until a “Read and clear” command
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Access
13
12
11
10
9
8
TSD1_CL4
TSD1_CL3
TSD1_CL2
TSD1_CL1
RES
RES
RES
RES
RES
RES
RES
RES
R
R&C
7
6
5
4
3
2
1
0
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 125. Status register SR7 (0x37)
RES
Prerelease product(s)
Status registers
R
Table 126. SR7 description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
TSD1_CL4
Thermal shutdown of Cluster x
18
TSD1_CL3
‘1’ indicates Cluster x has reached the thermal shutdown threshold (TSD1) and the output cluster was shut
down
DS14048 - Rev 1
Description
page 122/135
SPSB081
Bit
Name
17
TSD1_CL2
16
TSD1_CL1
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Description
Bit is latched until a “Read and clear” command of this bit only
Access
13
12
11
10
9
8
TW_CL4
TW_CL3
TW_CL2
TW_CL1
RES
RES
RES
RES
RES
RES
RES
RES
R
R&C
7
6
5
4
3
2
1
0
RES
14
RES
15
RES
16
RES
17
RES
18
RES
19
RES
20
RES
21
RES
22
RES
Bit
name
23
RES
Table 127. Status register SR8 (0x38)
RES
Prerelease product(s)
Status registers
R
Table 128. SR8 description
Bit
Name
23
RES
Reserved
22
RES
Reserved
21
RES
Reserved
20
RES
Reserved
19
TW_CL4
18
TW_CL3
17
TW_CL2
16
TW_CL1
15
RES
Reserved
14
RES
Reserved
13
RES
Reserved
12
RES
Reserved
11
RES
Reserved
DS14048 - Rev 1
Description
Thermal warning for Cluster x
‘1’ indicates Cluster x has reached the thermal warning threshold
Bit is latched until a “Read and clear” command of this bit only
page 123/135
SPSB081
Status registers
Name
Description
10
RES
Reserved
9
RES
Reserved
8
RES
Reserved
7
RES
Reserved
6
RES
Reserved
5
RES
Reserved
4
RES
Reserved
3
RES
Reserved
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
Prerelease product(s)
Bit
DS14048 - Rev 1
page 124/135
SPSB081
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
8.1
QFN32L 5x5 package information
Prerelease product(s)
Figure 41. QFN32L 5x5 Package outline
DM00434112_rev2
DS14048 - Rev 1
page 125/135
SPSB081
QFN32L 5x5 package information
Table 129. QFN32L 5x5 mechanical data
Dimension
Millimeters
Ref.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
-
0.05
A2
0.2 REF
A3
0.1
D
5.00 BSC
D2
3.40
E
3.60
5.00 BSC
E2
3.40
e1
3.50
3.60
0.5 BSC
k
Prerelease product(s)
3.50
0.20
L1
-
-
.
0.05
La
0.40
0.50
0.50
bA
0.20
0.25
0.30
h
0.19 REF
h1
0.19 REF
LB
0.45
0.5
0.55
bB
0.20
0.25
0.30
N
32
R1
-
0.1
Table 130. Tolerance of form and position
DS14048 - Rev 1
Symbol
Tolerance
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
page 126/135
SPSB081
Revision history
Table 131. Document revision history
Revision
05-Oct-2022
1
Changes
Initial release.
Prerelease product(s)
Date
DS14048 - Rev 1
page 127/135
SPSB081
Contents
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
Prerelease product(s)
3
Supply voltage ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1
Supply Vs, Vsreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
3.4
3.2.1
Voltage regulator: V1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2
Voltage regulator: V2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3
Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.4
Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.5
Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2
SW-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3
V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.4
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.5
VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Wake-up from standby modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1
Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
Configurable window watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.1
3.7
Change watchdog timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.1
Temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.2
Non recoverable failures –Forced in VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8
Reset output (NRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9
DIAGN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10
V1 overvoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11
LIN bus interfaces (only for SPSB0815 and SPSB0813) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.1
DS14048 - Rev 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
page 128/135
SPSB081
Contents
3.12
Prerelease product(s)
3.13
4
3.11.2
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.3
Wake-up from standby modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CAN FD bus transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.12.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.12.2
CAN transceiver supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.12.3
CAN transceiver operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12.4
CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12.5
Wake-up by CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12.6
CAN receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12.7
CAN looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13.1
Vs supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13.2
Vsreg supply failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.14
Thermal state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15
Power outputs OUT1..4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.16
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.17
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.18
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.19
Constant current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.20
Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.21
Thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22
Functional safety management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1
ST SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1
4.2
4.3
4.4
DS14048 - Rev 1
Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.1
Clock and data characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.2
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.1
Information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.2
Device application registers (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.1
Clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.2
SCK polarity (CPOL) check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.3
SCK phase (CPHA) check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.4
CSN timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.5
SDI stuck at GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
page 129/135
SPSB081
Contents
Prerelease product(s)
5
4.4.6
SDI stuck at HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.7
SDO stuck @ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.1
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.4
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.5
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.6
DIAGN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.7
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.8
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.9
Outputs OUT1 – OUT4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.10
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.11
Output current threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.12
Wake-up inputs (WU1, DIR/WU2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.13
CAN FD transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.14
LIN transceiver (only for SPSB0815 & SPSB0813) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.15
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.16
Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.17
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.18
Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.19
SGND loss comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7
SPI registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
8
7.1
Global status byte (GSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.2
Control registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.3
Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.4
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.5
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.1
QFN32L 5x5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
DS14048 - Rev 1
page 130/135
SPSB081
List of tables
Prerelease product(s)
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient immunity ratings according to ISO 7637-2 . . . . . . . . . . . . . . . . . . . . .
Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage regulators configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temporary failures conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non recoverable failures conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Safety requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPSB081 information registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst read bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data consistency check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD Type/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical parameters numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage regulator V1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage regulator V2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIAGN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outputs OUT1–OUT4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power outputs switching times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN transmit data input: Pin TxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN receive data output: Pin RxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN transmitter dominant output characteristics . . . . . . . . . . . . . . . . . . . . . . .
CAN transmitter recessive output characteristics, CAN normal mode . . . . . . . . .
CAN receiver input characteristics during CAN normal mode . . . . . . . . . . . . . . .
CAN receiver input characteristics during CAN low power mode, biasing inactive .
CAN receiver input resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN transceiver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN receiver input resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Biasing control timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN transmit data input: Pin TxD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN receive data output: Pin RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN transmitter and receiver: Pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS14048 - Rev 1
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page 131/135
SPSB081
Prerelease product(s)
List of tables
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
LIN transceiver timing. . . . . . . . . . . . . . . . . . .
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . .
Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . .
DI, CLK and CSN timing . . . . . . . . . . . . . . . . .
Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . .
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug input . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt output . . . . . . . . . . . . . . . . . . . . . . .
Timer1 and Timer2 values . . . . . . . . . . . . . . . .
SGND loss comparator . . . . . . . . . . . . . . . . . .
Global status byte (GSB) . . . . . . . . . . . . . . . .
Global status byte (GSB) description . . . . . . . .
Global control registers . . . . . . . . . . . . . . . . . .
Control registers overview. . . . . . . . . . . . . . . .
Global status registers . . . . . . . . . . . . . . . . . .
Status registers overview . . . . . . . . . . . . . . . .
Control register CR1 (0x01). . . . . . . . . . . . . . .
CR1 signals description . . . . . . . . . . . . . . . . .
Control register CR2 (0x02). . . . . . . . . . . . . . .
CR2 signals description . . . . . . . . . . . . . . . . .
Control register CR3 (0x03). . . . . . . . . . . . . . .
CR3 signals description . . . . . . . . . . . . . . . . .
Control register CR4 (0x04). . . . . . . . . . . . . . .
CR4 signals description . . . . . . . . . . . . . . . . .
Control register CR5 (0x05). . . . . . . . . . . . . . .
CR5 signals description . . . . . . . . . . . . . . . . .
Control register CR6 (0x06). . . . . . . . . . . . . . .
CR6 signals description . . . . . . . . . . . . . . . . .
Control register CR7 (0x07). . . . . . . . . . . . . . .
CR7 signals description . . . . . . . . . . . . . . . . .
Control register CR8 (0x08). . . . . . . . . . . . . . .
CR8 signals description . . . . . . . . . . . . . . . . .
Control register CR9 (0x09). . . . . . . . . . . . . . .
CR9 signals description . . . . . . . . . . . . . . . . .
Control register CR10 (0x0A). . . . . . . . . . . . . .
CR10 signals description . . . . . . . . . . . . . . . .
Control register CR11 (0x0B). . . . . . . . . . . . . .
CR11 signals description. . . . . . . . . . . . . . . . .
Control register CR12 (0x0C) . . . . . . . . . . . . .
CR12 signals description . . . . . . . . . . . . . . . .
Control register CR13 (0x0D) . . . . . . . . . . . . .
CR13 signals description . . . . . . . . . . . . . . . .
Control register CR14 (0x0E). . . . . . . . . . . . . .
CR14 signals description . . . . . . . . . . . . . . . .
Control register CR15 (0x0F). . . . . . . . . . . . . .
CR15 signals description . . . . . . . . . . . . . . . .
Control register CR16 (0x10) . . . . . . . . . . . . . .
CR16 signals description . . . . . . . . . . . . . . . .
Control register CR19 (0x13) . . . . . . . . . . . . . .
CR17 to CR19 signals description . . . . . . . . . .
Control register CR20 (0x14) . . . . . . . . . . . . . .
CR20 signals description . . . . . . . . . . . . . . . .
CR21(0x15) to CR24 (0x18) . . . . . . . . . . . . . .
CR21(0x15) to CR24 (0x18) signals description .
DS14048 - Rev 1
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. 73
. 75
. 75
. 76
. 76
. 76
. 77
. 81
. 81
. 81
. 82
. 84
. 84
. 87
. 87
. 91
. 91
. 93
. 93
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109
.110
.110
.111
.112
page 132/135
SPSB081
Prerelease product(s)
List of tables
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Control register CR34 (0x22) . . . . . . . . .
CR34 signals description . . . . . . . . . . .
Configuration register (0x3F) . . . . . . . . .
Configuration register signals description
Status register SR1 (0x31) . . . . . . . . . .
SR1 description . . . . . . . . . . . . . . . . . .
Status register SR2 (0x32) . . . . . . . . . .
SR2 description . . . . . . . . . . . . . . . . . .
Status register SR3 (0x33) . . . . . . . . . .
SR3 description . . . . . . . . . . . . . . . . . .
Status register SR4 (0x34) . . . . . . . . . .
SR4 description . . . . . . . . . . . . . . . . . .
Status register SR5 (0x35) . . . . . . . . . .
SR5 description . . . . . . . . . . . . . . . . . .
Status register SR6 (0x36) . . . . . . . . . .
SR6 description . . . . . . . . . . . . . . . . . .
Status register SR7 (0x37) . . . . . . . . . .
SR7 description . . . . . . . . . . . . . . . . . .
Status register SR8 (0x38) . . . . . . . . . .
SR8 description . . . . . . . . . . . . . . . . . .
QFN32L 5x5 mechanical data . . . . . . . .
Tolerance of form and position . . . . . . . .
Document revision history . . . . . . . . . . .
DS14048 - Rev 1
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.112
.112
.113
.113
.115
.115
.117
.117
.119
.119
.119
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page 133/135
SPSB081
List of figures
Prerelease product(s)
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
DS14048 - Rev 1
Functional block diagram of SPSB0815 and SPSB0813. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional block diagram of SPSB081C5 and SPSB081C3 . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connection SPSB0815 and SPSB0813 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connection SPSB081C5 and SPSB081C3 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QFN32L 5x5 4-layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage regulator behavior and diagnosis during supply voltage ramp-up / ramp-down conditions
Interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static monitoring: wake-up occurs if threshold is greater than the filter time . . . . . . . . . . . . . . .
Cyclic monitoring: the external contacts are supplied periodically by the internal timer . . . . . . . .
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NReset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIAGN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage protection on V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage detection V1 = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up behavior according to LIN 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CANFD transceiver supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal shutdown protection and diagnosis related to thermal cluster 1. . . . . . . . . . . . . . . . . .
Thermal shutdown protection and diagnosis related to thermal cluster 2, 3 and 4 . . . . . . . . . . .
Constant current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal clusters identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDO frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slew-rate of the drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI CSN - output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI–CSN low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QFN32L 5x5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.. 3
.. 4
.. 5
.. 5
. 11
. 14
. 16
. 17
. 18
. 20
. 21
. 21
. 22
. 24
. 25
. 26
. 27
. 28
. 30
. 31
. 33
. 35
. 36
. 38
. 39
. 42
. 43
. 44
. 45
. 50
. 59
. 60
. 62
. 75
. 77
. 78
. 79
. 80
. 80
. 83
125
page 134/135
SPSB081
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
Prerelease product(s)
© 2022 STMicroelectronics – All rights reserved
DS14048 - Rev 1
page 135/135
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