STMicroelectronics STM32F446RE Datasheet

Table 76.

ADC static accuracy at f

Table 77.

ADC static accuracy at f

ADC dynamic accuracy at f

= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 78.

ADC dynamic accuracy at f

Table 79.

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

= 18 MHz - Limited test conditions . . . . . . . . . . . . . . . . . 141

= 36 MHz - Limited test conditions . . . . . . . . . . . . . . . . . 141

Table 80.

Table 81.

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 82.

BAT

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 83.

internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 84.

Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 85.

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 86.

Asynchronous non-multiplexed SRAM/PSRAM/NOR Read timings. . . . . . . . . . . . . . . . . 150

Table 87.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read 

NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 88.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 151

Table 89.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write 

NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 90.

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 91.

Asynchronous multiplexed PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . 153

Table 92.

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 155

DS10693 Rev 10 7/198

List of tables STM32F446xC/E

Table 93.

Asynchronous multiplexed PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . 155

Table 94.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 95.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 96.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 97.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 98.

Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 99.

Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 100. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 101. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 102. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 103. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 104. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 105. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 106. Dynamic characteristics: eMMC characteristics V

= 1.7 V to 1.9 V . . . . . . . . . . . . . . . 171

Table 107. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 108. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 109. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 110. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 111. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 112. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 183

Table 113. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 114. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 186

Table 115. WLCSP81 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 116. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 189

Table 117. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 118. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

8/198 DS10693 Rev 10

STM32F446xC/E

List of figures

List of figures

Figure 1.

Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2.

Compatible board for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3.

STM32F446xC/E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4.

STM32F446xC/E and Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5.

VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.

Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24

Figure 7.

Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8.

Startup in regulator OFF: slow V

slope  power-down reset risen after V

CAP_1

/ V

Figure 9.

Startup in regulator OFF mode: fast V

power-down reset risen before V

CAP_1

CAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27

slope

/ V



CAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10.

STM32F446xC/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11.

STM32F446xC/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12.

STM32F446xC LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13.

STM32F446xC/xE WLCSP81 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14.

STM32F446xC/xE UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 16.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 17.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 18.

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 19.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

current consumption 

(RTC ON/backup RAM OFF and LSE in low power mode) . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 22.

Typical V

BAT

current consumption 

(RTC ON/backup RAM OFF and LSE in high drive mode). . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 23.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 24.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 25.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 26.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 29.

PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 30.

PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 31.

FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 32.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 33.

Figure 34.

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 35.

FMPI

C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 36.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 37.

SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 38.

SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 39.

S slave timing diagram (Philips protocol)

(1)

Figure 40.

S master timing diagram (Philips protocol)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 41.

SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 42.

SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 43.

USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 136

Figure 44.

ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

DS10693 Rev 10 9/198

List of figures STM32F446xC/E

Figure 45.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 46.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 47.

Power supply and reference decoupling (V

REF+

Figure 48.

Power supply and reference decoupling (V

REF+ not connected to V

DDA connected to V

DDA

). . . . . . . . . . . . . 143

). . . . . . . . . . . . . . . . 144

Figure 49.

12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 50.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 149

Figure 51.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 151

Figure 52.

Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 53.

Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 54.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 55.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 56.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 57.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 58.

NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 59.

NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 60.

NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 164

Figure 61.

NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 164

Figure 62.

SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 63.

SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 64.

DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 65.

SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 66.

SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 67.

LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 68.

Figure 69.

LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 70.

LQFP100 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 71.

Figure 72.

LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 73.

LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 178

Figure 74.

Figure 75.

LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 76.

UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 77.

Figure 78.

UFBGA144 7 x 7 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . 184

Figure 79.

UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 80.

Figure 81.

UFBGA144 10 x 10 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . 187

Figure 82.

WLCSP81 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 83.

Figure 84.

WLCSP81 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 85.

USB controller configured as peripheral-only and used in full speed mode . . . . . . . . . . . 193

Figure 86.

USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 193

Figure 87.

USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 194

Figure 88.

USB controller configured as peripheral, host, or dual-mode  and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

10/198 DS10693 Rev 10

STM32F446xC/E

1 Introduction

Introduction

This document provides the description of the STM32F446xC/E products, based on an

Arm ®(a) core. It must be read in conjunction with the RM0390 reference manual, available on www.st.com

For information on the Cortex ® -M4 core refer to the Cortex ® -M4 programming manual

(PM0214), available on www.st.com

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS10693 Rev 10 11/198

Description

2 Description

STM32F446xC/E

The STM32F446xC/E devices are based on the high-performance Arm ® Cortex ® -M4 32-bit

RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a floating point unit (FPU) single precision supporting all Arm ® single-precision  data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.

The STM32F446xC/E devices incorporate high-speed embedded memories (Flash memory up to 512 Kbytes, up to 128 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose

16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.

They also feature standard and advanced communication interfaces.

 Up to four I

 Four SPIs, three I 2 Ss full simplex: to achieve audio class accuracy, the I 2 S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization

 Four USARTs plus two UARTs

 An USB OTG full-speed and an USB OTG high-speed with full-speed capability (with the ULPI), both with dedicated power rails allowing to use them throughout the whole power range

 Two CANs

 Two SAIs serial audio interfaces: to achieve audio class accuracy, the SAIs can be clocked via a dedicated internal audio PLL

 SDIO/MMC interface

 Camera interface

 HDMI-CEC

 SPDIF receiver (SPDIFRx)

 QuadSPI

Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors. Refer to

Table 2

for the list of peripherals available on each part number.

The STM32F446xC/E devices operate in the –40 to +105 °C temperature range from a 

1.7 to 3.6 V power supply.

The supply voltage can drop down to 1.7 V with the use of an external power supply supervisor (refer to

Section 3.16.2: Internal reset OFF ). A comprehensive set of

 power-saving modes enables the design of low-power applications.

The STM32F446xC/E devices offer devices in six packages, ranging from 64 to 144 pins.

The set of included peripherals changes with the chosen device.

These features make the STM32F446xC/E microcontrollers suitable for a wide range of applications, namely motor drive and control, medical equipment, industrial (PLC, inverters, circuit breakers), printers, and scanners, alarm systems, video intercom and HVAC, and home audio appliances.

12/198 DS10693 Rev 10

STM32F446xC/E Description

Packages

Peripherals

Table 2. STM32F446xC/E features and peripheral counts

STM32

F446MC

STM32

F446ME

STM32

F446RC

STM32

F446RE

STM32

F446VC

STM32

F446VE

256 512 256 512 Flash memory in Kbytes

SRAM in

Kbytes

System

Backup

FMC memory controller

Generalpurpose

Timers Advancedcontrol

Basic

SPI / I

USART/ 

UART

USB 

OTG FS

Communication interfaces

USB 

OTG HS

CAN

SAI

SDIO

SPDIF-Rx

HDMI-CEC

Quad SPI

(3)

Camera interface

GPIOs

12-bit ADC

Number of channels

12-bit DAC 

Number of channels

Maximum CPU frequency

Operating voltage

Operating temperatures

512 256

128 (112+16)

4/3 (simplex)

(2)

4/1 FMP +

4/2

Yes (6-Endpoints)

Yes (8-Endpoints)

STM32

F446ZC

256

Yes

(1)

STM32

F446ZE

512

Yes

63 50 81 114

14 16 16 24

Yes

180 MHz

1.8 to 3.6 V

(4)

WLCSP81

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to + 125 °C

LQFP64 LQFP100

LQFP144

UFBGA144

DS10693 Rev 10 13/198

Description STM32F446xC/E

1. For the LQFP100 package only FMC Bank1 is available, it can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. The interrupt line cannot be used as Port G is not available on this package.

2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either SPI mode or I2S audio mode.

3. For the LQFP64 package the Quad SPI is available with limited features.

4. V

DDA

minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and

with the use of an external power supply supervisor (refer to Section 3.16.2: Internal reset OFF

2.1 Compatibility with STM32F4 family

The STM32F446xC/xV is software and feature compatible with the STM32F4 family.

The STM32F446xC/xV can be used as drop-in replacement of the other STM32F4 products but some small changes have to be done on the PCB board.

Figure 1. Compatible board design for LQFP100 package

STM32F446xx

STM32F405/STM32F415 line

STM32F407/STM32F417 line

STM32F427/STM32F437 line

STM32F429/STM32F439 line

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PB11 not available anymore

Replaced by V

CAP1

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

MS33846V2

14/198 DS10693 Rev 10

STM32F446xC/E

Figure 2. Compatible board for LQFP64 package

STM32F405/STM32F415 line STM32F446xx

Description

53 52 51 50 49

28 29 30 31 32

VDD

VCAP2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

53 52 51 50 49

PB11 not available anymore

Replaced by V

CAP1 35

28 29 30 31 32

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

ESR 1 Ω or below

MS33845V2

Figure 3 shows the STM32F446xx block diagram.

DS10693 Rev 10 15/198

Description STM32F446xC/E

114 AF

D(7:0)

CMD, CK as AF

4 PWM, 4 PWM,

ETR, BKIN as AF

4 PWM, 4 PWM,

ETR, BKIN as AF

2 CH as AF

1 CH as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK,

CTS, RTS as AF

MOSI, MISO

SCK, NSS as AF

MOSI, MISO

SCK, NSS as AF

SD, SCK, FS

MCLK as AF

SD, SCK, FS

MCLK as AF

DDREF_ADC

8 AIN common to the 3 ADCs

8 AIN common to the ADC1 & 2

8 AIN to ADC3

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED(3:0)

DDUSB

= 3.3 TO 3.6 V

D+, D-

ULPI : CLK, D(7:0),

DIR, STP, NXT

ID, VBUS

PA(15:0)

PB(15:0)

PC(15:0)

PD(15:0)

PE(15:0)

PF(15:0)

PG(15:0)

PH(1 :0)

@VDDA

ADC1

ADC2

ADC 3

Figure 3. STM32F446xC/E block diagram

JTAG & SW

ETM

ARM

CORTEX M4

180MHz

MPU FPU

NVIC

I-BUS

D-BUS

S-BUS

USB

OTG HS

DMA/

FIFO

GP-DMA2

GP-DMA1

8 Streams

FIFO

8 Streams

FIFO

SDIO / MMC

16b

USART 2MBps

16b

USART 2MBps

16b smcard irDA smcard

USART 2MBps

SRAM,PSRAM,NOR-FLASH

NAND-FLASH, SDRAM

QuadSPI

FLASH 512kB

GPDMA2

SRAM1 112KB

SRAM2 16KB

AHB1 180MHz

@VDDA

RC HS

RC LS

PLL1+PLL2+PLL3

RESET&

CRC

AHB/APB2 AHB/APB1

GPDMA1

WinWATCHDOG

TIMER6

16b

TIMER7

16b

CAMERA

ITF

USB

OTG FS

POR

Reset

Int

SUPPLY

SUPERVISION

POR/PDR/

BOR

PVD

@VDDA

POWER MNGT

VOLT. REG.

3.3V TO 1.2V

@VDD

XTAL OSC

4-16MHz

WDG32K

Standby interface

BAT

XTAL 32kHz

RTC

AWU

BKP REG

4KB BKPRAM

TIMER2

32b

TIMER3

16b

TIMER4

16b

TIMER5

32b

TIMER12

16b

TIMER13

16b

TIMER14

16b

USART2

USART3 smcard irDA smcard irDA

UART4

UART5

SPDIF

HDMI-CEC

SPI2/I2S

SPI3/I2S

@VDDA

DAC1

DAC2

ITF

DAC1 as AF DAC2 as AF

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS

FMPI2C1 bxCAN1 bxCAN2

CLK, NE[3:0], A[23:0], D[31:0]

NOEN, NWEN, NBL[1:0]

SDCLKE[1:0], SDNE[1:0]

NRAS, NCAS, NADV

NWAIT, INTN

CLK, CSa, CSb, D[7:0]

HSYNC, VSYNC

PIXCK, D(13:0)

DDUSB

D+, D-

= 3.3 TO 3.6 V

ID, VBUS

DDA

, V

SSA

NRESET

=1.8 to 3.6V

CAP

OSCIN

OSCOUT

BAT

=1.8 to 3.6V

OSC32_IN

OSC32_OUT

ALARM_OUT

STAMP1

STAMP2

4 CH, ETR as AF

4 CH a s AF

2 CH as AF

1 CH as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK

CTS, RTS as AF

RX, TX as AF

SPDIF_RX[3:0] as AF

HDMI_CEC a s AF

MOSI, MISO, SCK

NSS/WS, MCK as AF

MOSI, MISO, SCK

NSS/WS, MCK as AF

SCL, SDA, SMBAL as AF

SCL, SDA, SM BAL as AF

TX, RX

MS33840V3

16/198 DS10693 Rev 10

STM32F446xC/E Functional overview

3.1 Arm

®

Cortex

®

-M4 with FPU and embedded Flash and SRAM

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

Note:

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

The STM32F446xC/E family is compatible with all Arm tools and software.

Figure 3 shows the general block diagram of the STM32F446xC/E family.

Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm ®

Cortex ®

Arm ®

-M4 with FPU processors. It balances the inherent performance advantage of the

Cortex ® -M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark ® benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole

4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS10693 Rev 10 17/198

Functional overview

3.4 Embedded Flash memory

STM32F446xC/E

The devices embed a Flash memory of 512KB available for storing programs and data.

3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

All devices embed:

 Up to 128 Kbytes of system SRAM

RAM is accessed (read/write) at CPU clock speed with 0 wait states.

 4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT modes.

3.7 Multi-AHB matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves Flash memory, RAM, QuadSPI , FMC, AHB and APB peripherals and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

18/198 DS10693 Rev 10

STM32F446xC/E

ARM

Cortex-M4

Functional overview

Figure 4. STM32F446xC/E and Multi-AHB matrix

DMA1

DMA2

USB OTG

S0 S1 S2

Bus matrix-S

S3 S4 S5 S6

ICODE

DCODE

Flash memory

SRAM1

112 Kbyte

SRAM2

16 Kbyte

AHB2 peripherals

AHB1 peripherals

FMC external

MemCtl/QuadSPI

APB1

APB2

MS33842V1

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

DS10693 Rev 10 19/198

Functional overview

The DMA can be used with the main peripherals:

 SPI and I

 I 2 C

 USART

 General-purpose, basic and advanced-control timers TIMx

 DAC

 SDIO

 Camera interface (DCMI)

 ADC

 SAI1/SAI2

 SPDIF Receiver (SPDIFRx)

 QuadSPI

3.9

STM32F446xC/E

Flexible memory controller (FMC)

All devices embed an FMC. It has seven Chip Select outputs supporting the following modes: SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. With the possibility to remap FMC bank 1 (NOR/PSRAM 1 and 2) and FMC SDRAM bank 1/2 in the

Cortex-M4 code area.

Functionality overview:

 8-,16-bit data bus width

 Read FIFO for SDRAM controller

 Write FIFO

 Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

All devices embed a Quad SPI memory interface, which is a specialized communication interface targeting Single, Dual or Quad SPI Flash memories. It can work in direct mode through registers, external Flash status register polling mode and memory mapped mode.

Up to 256 Mbytes external Flash are memory mapped, supporting 8, 16 and 32-bit access.

Code execution is supported. The opcode and the frame format are fully programmable.

Communication can be either in Single Data Rate or Dual Data Rate.

20/198 DS10693 Rev 10

STM32F446xC/E Functional overview

3.11 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M4 with FPU core.

 Closely coupled NVIC gives low-latency interrupt processing

 Interrupt entry vector table address passed directly to the core

 Early processing of interrupts

 Processing of late arriving, higher-priority interrupts

 Supports tail chaining

 Processor state automatically saved

 Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines.

3.13 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16

MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is

90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI, which makes it possible to achieve audio class performance. In this case, the I 2 S master clock can generate all standard sampling frequencies from 8 to 192 kHz.

DS10693 Rev 10 21/198

Functional overview STM32F446xC/E

At startup, boot pins are used to select one out of three boot options:

 Boot from user Flash

 Boot from system memory

 Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial (UART, I 2 C, CAN, SPI and USB) communication interface. Refer to application note AN2606 for details.

Note:

 V

= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V

pins.

 V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

DDA minimum value of 1.7 V is obtained with the use of an external power supply

supervisor (refer to Section 3.16.2

). Refer to Table 3

to identify the packages supporting this option.

 V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

 V

DDUSB

can be connected either to V

or an external independent power supply (3.0 to 3.6 V) for USB transceivers. 

For example, when device is powered at 1.8 V, an independent power supply 3.3 V can be connected to V

DDUSB it is independent from V

. When the V

DDUSB

or V

DDA

is connected to a separated power supply,

but it must be the last supply to be provided and the first to disappear. The following conditions must be respected:

– During power-on phase (V

< V

DD_MIN

), V

DDUSB

must be always lower than V

– During power-down phase (V

< V

DD_MIN

), V

DDUSB

must be always lower than

– V

DDUSB

rising and falling time rate specifications must be respected.

– In operating mode phase, V

DDUSB

can be lower or higher than V

– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

DDUSB

are operating between V

DDUSB_MIN and V

DDUSB_MAX

.The V supplies both USB transceivers (USB OTG_HS and USB OTG_FS).

DDUSB

– If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by V

DDUSB

– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by V

DDUSB

are operating between V

DD_MIN

and V

DD_MAX

22/198 DS10693 Rev 10

STM32F446xC/E Functional overview

Figure 5. V

DDUSB

connected to an external independent power supply

DDUSB_MAX

USB functional area

DDUSB

DDUSB_MIN

USB non functional area

DD_MIN

= V

DDA

USB non functional area

Power-on Operating mode Power-down time

MS37590V1

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V

POR/PDR

or V

BOR

is below a specified threshold,

, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DDA

power supply and compares it to the V

PVD generated when V

DDA higher than the V

PVD

drops below the V

PVD

threshold. An interrupt can be

threshold and/or when V

DDA message and/or put the MCU into a safe state. The PVD is enabled by software.

threshold. The interrupt service routine can then generate a warning

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor V

DD mode as long as V

and maintain the device in reset

is below a specified threshold. PDR_ON must be connected to V

, to let the device operate down to 1.7 V. Refer to

Figure 6 .

DS10693 Rev 10 23/198

Functional overview STM32F446xC/E

Figure 6. Power supply supervisor interconnection with internal reset OFF

STM32F446x

Application reset signal (optional)

VBAT

PDR_ON

PDR not active: 1.7 V < V

< 3.6 V

MS33844V2

The V

1.7 V.

specified threshold, below which the device must be maintained under reset, is

A comprehensive set of power-saving mode enables the design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

 The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

 The brownout reset (BOR) circuitry must be disabled

 The embedded programmable voltage detector (PVD) is disabled

 V

BAT

functionality is no more available and V

BAT

pin should be connected to V

All packages, except for the LQFP100/LQFP64, allow to disable the internal reset through the PDR_ON signal.

The regulator has four operating modes:

 Regulator ON

– Main regulator mode (MR)

– Low power regulator (LPR)

– Power-down

 Regulator OFF

24/198

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

There are three power modes configured by software when the regulator is ON:

 MR mode used in Run/sleep modes or in Stop modes

– In Run/Sleep mode

The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.

DS10693 Rev 10

STM32F446xC/E Functional overview

The over-drive mode makes possible operating at a frequency higher than the normal mode for a given voltage scaling.

– In Stop modes

The MR can be configured in two ways during stop mode:

MR operates in normal mode (default mode of MR in stop mode)

MR operates in under-drive mode (reduced leakage mode).

 LPR is used in the Stop modes:

The LP regulator mode is configured by software when entering Stop mode.

Like the MR mode, the LPR can be configured in two ways during stop mode:

– LPR operates in normal mode (default mode when LPR is ON)

– LPR operates in under-drive mode (reduced leakage mode).

 Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost.

Refer to Table 3

for a summary of voltage regulator modes versus device operating modes.

Two external ceramic capacitors should be connected on V

CAP_1

and V

CAP_2

pin.

All packages have the regulator ON feature.

Table 3. Voltage regulator configuration mode versus device operating mode

(1)

Voltage regulator configuration

Run mode Sleep mode Stop mode Standby mode

MR or LPR Normal mode

Over-drive mode

(2)

Under-drive mode

Power-down mode

1. ‘-’ means that the corresponding configuration is not available.

2. The over-drive mode is not available when V

= 1.7 to 2.1 V.

MR or LPR

Yes

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode enables to supply externally a V

voltage source through V

CAP_1

and V

CAP_2

pins.

Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors.

When the regulator is OFF, there is no more internal monitoring on V

12 supply supervisor should be used to monitor the V

. An external power

of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V

power domain.

DS10693 Rev 10 25/198

Functional overview STM32F446xC/E

In regulator OFF mode, the following features are no more supported:

 PA0 cannot be used as a GPIO pin since it resets a part of the V

12 not reset by the NRST pin.

logic power domain

 As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.

 The over-drive and under-drive modes are not available.

Figure 7. Regulator OFF

V12

External V

CAP_1/2

power supply supervisor

Ext. reset controller active when V

CAP_1/2

< Min V

Application reset signal (optional)

Note:

PA0

NRST

BYPASS_REG

V12

CAP_1

CAP_2 ai18498V3

The following conditions must be respected:

 V

should always be higher than V between power domains.

CAP_1

and V

CAP_2 to avoid current injection

 If the time for V

CAP_1

and V and V

CAP_2 reach V

CAP_2 to reach V

12 minimum value is faster than the time for

to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V

CAP_1 minimum value and until V

reaches 1.7 V (see Figure 8

 Otherwise, if the time for V

CAP_1 than the time for V

Figure 9 ).

and V

CAP_2 to reach V

12 minimum value is slower

to reach 1.7 V, then PA0 could be asserted low externally (see

 If V

CAP_1

and V

CAP_2

go below V

12 minimum value and V reset must be asserted on PA0 pin.

is higher than 1.7 V, then a

The minimum value of V

12 depends on the maximum frequency targeted in the application.

26/198 DS10693 Rev 10

STM32F446xC/E Functional overview

Figure 8. Startup in regulator OFF: slow V power-down reset risen after V

CAP_1

/ V

slope

CAP_2 stabilization

PDR = 1.7 V or 1.8 V

Min V

CAP_1

/ V

CAP_2 time

NRST

1. This figure is valid whatever the internal reset mode (ON or OFF).

Figure 9. Startup in regulator OFF mode: fast V

DD power-down reset risen before V

CAP_1

/ V

CAP_2

slope stabilization

DD time ai18491f

PDR = 1.7 V or 1.8 V

Min V

CAP_1

/ V

CAP_2 time

NRST

PA0 asserted externally time ai18492e

1. This figure is valid whatever the internal reset mode (ON or OFF).

3.17.3 Regulator ON/OFF and internal reset ON/OFF availability

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF

Yes No LQFP64 / LQFP100

LQFP144

UFBGA144

WLCSP81

Yes

BYPASS_REG set to Vss

Yes

BYPASS_REG set to V

Yes

PDR_ON set to V

Yes

PDR_ON set to Vss

DS10693 Rev 10 27/198

Functional overview STM32F446xC/E

3.18 Real-time clock (RTC), backup SRAM and backup registers

The backup domain includes:

 The real-time clock (RTC)

 4 Kbytes of backup SRAM

 20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power

RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and enables automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see

Section 3.19

). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data when V

power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see

Section 3.19

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the V

supply when present or from the V

BAT

pin.

28/198 DS10693 Rev 10

STM32F446xC/E Functional overview

The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

 Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

 Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled.

The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see

Table 5

– Normal mode (default mode when MR or LPR is enabled)

– Under-drive mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup).

Table 5. Voltage regulator modes in stop mode

Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR)

Normal mode

Under-drive mode

MR ON

MR in under-drive mode

LPR ON

LPR in under-drive mode

 Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

3.20 V

BAT

operation

The V

BAT

pin makes it possible to power the device V an external supercapacitor, or from V

DD supercapacitor are present.

BAT

domain from an external battery, when no external battery and an external

BAT

operation is activated when V

is not present.

The V

BAT

pin supplies the RTC, the backup registers and the backup SRAM.

DS10693 Rev 10 29/198

Functional overview

Note:

STM32F446xC/E

When the microcontroller is supplied from V

BAT do not exit it from V

BAT operation.

, external interrupts and RTC alarm/events

When PDR_ON pin is not connected to V

DD no more available and V

BAT

(Internal Reset OFF), the V pin has to be connected to V DD .

BAT functionality is

3.21 Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 6 compares the features of the advanced-control, general-purpose and basic timers.

Timer type

Timer

Counter resolution

Table 6. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max interface clock

(MHz)

Max timer clock

(MHz) (1)

Advancedcontrol

General purpose

Basic

TIM1,

TIM8

TIM2,

TIM5

TIM3,

TIM4

TIM9

TIM10,

TIM11

TIM12

TIM13,

TIM14

TIM6,

TIM7

16-bit

32-bit

16-bit

Up,

Down,

Up/down

Up,

Down,

Up/down

Up,

Down,

Up/down

Any integer between 1 and 65536

Yes

180

90/180

180

90/180

1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

30/198 DS10693 Rev 10

STM32F446xC/E Functional overview

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

 Input capture

 Output compare

 PWM generation (edge- or center-aligned modes)

 One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose

TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-

100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

There are ten synchronized general-purpose timers embedded in the STM32F446xC/E

devices (see Table 6 for differences).

 TIM2, TIM3, TIM4, TIM5

The STM32F446xC/E include four full-featured general-purpose timers: TIM2, TIM5,

TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the

Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from one to four Hall-effect sensors.

 TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

DS10693 Rev 10 31/198

Functional overview STM32F446xC/E

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

 A 24-bit downcounter

 Autoreload capability

 Maskable system interrupt generation when the counter reaches 0

 Programmable clock source.

circuit interface (I

2

C)

Four I²C bus interfaces can operate in multimaster and slave modes. Three I²C can support the standard (up to 100 KHz) and fast (up to 400 KHz) modes.

One I²C can support the standard (up to 100 KHz), fast (up to 400 KHz) and fast mode plus

(up to 1MHz) modes.

They (all I²C) support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave).

A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0 / PMBus.

The devices also include programmable analog and digital noise filters (see

Table 7 ).

Table 7. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of suppressed spikes  50 ns Programmable length from 1 to 15 I2C peripheral clocks

32/198

(USART)

The devices embed four universal synchronous/asynchronous receiver transmitters

(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, and UART5).

DS10693 Rev 10

STM32F446xC/E Functional overview

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s.

USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

Table 8. USART feature comparison (1)

USART name

Standard features

Modem

(RTS/CTS)

LIN

SPI master irDA

Max. baud rate in Mbit/s

Smartcard

(ISO 7816) Oversampling by 16

Oversampling by 8

APB mapping

USART1 X X X X X X 5.62

11.25

APB2 (max.

90 MHz)

USART2

USART3

UART4

UART5

2.81

5.62

APB1 (max.

45 MHz)

USART6 X X X X X X 5.62

11.25

APB2 (max.

90 MHz)

1. X = feature supported.

3.24 Serial peripheral interface (SPI)

The devices feature up to four SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, and SPI4 can communicate at up to 45 Mbits/s, SPI2 and

SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives eight master mode frequencies and the frame is configurable to 8- or 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the

DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.

3.25 HDMI (high-definition multimedia interface) consumer



electronics control (CEC)

The devices embed a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead.

DS10693 Rev 10 33/198

Functional overview STM32F446xC/E

3.26 Inter-integrated sound (I

2

S)

Three standard I

S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio

I sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the

S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I2Sx can be served by the DMA controller.

The SPDIF-RX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1).

The main features of the SPDIF-RX are the following:

 Up to 4 inputs available

 Automatic symbol rate detection

 Maximum symbol rate: 12.288 MHz

 Stereo stream from 32 to 192 kHz supported

 Supports Audio IEC-60958 and IEC-61937, consumer applications

 Parity bit management

 Communication using DMA for audio samples

 Communication using DMA for control and user channel information

 Interrupt capabilities

The SPDIF-RX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream.

The user can select the wanted SPDIF input, and when a valid signal is available the

SPDIF-RX re-samples the incoming signal, decodes the Manchester stream, recognizes frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags.

The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF sub-frame rate used to compute the exact sample rate for clock drift algorithms.

3.28 Serial audio interface (SAI)

The devices feature two serial audio interfaces (SAI1 and SAI2). Each serial audio interfaces based on two independent audio sub blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards,

LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub blocks can be configured in master or in slave mode. The SAIs use a PLL to achieve audio class accuracy.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency.

34/198 DS10693 Rev 10

STM32F446xC/E Functional overview

The two sub blocks can be configured in synchronous mode when full-duplex mode is required.

SAI1 and SA2 can be served by the DMA controller.

2

S)

The devices feature an additional dedicated PLL for audio I

S and SAI applications, to achieve error-free I

S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I

S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

S/SAI flow with an external PLL (or Codec output).

3.30 Serial audio interface PLL (PLLSAI)

An additional PLL dedicated to audio and USB is used for SAI1 and SAI2 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the 48 MHz clock for USB FS and SDIO in case the system PLL is programmed with factors not multiple of 48 MHz.

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface enables data transfer at up to 48 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

3.32 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated for each CAN.

DS10693 Rev 10 35/198

Functional overview STM32F446xC/E

3.33 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power rails allowing its use throughout the entire power range. The major features are:

 Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

 Supports the session request protocol (SRP) and host negotiation protocol (HNP)

 6 bidirectional endpoints

 12 host channels with periodic OUT support

 HNP/SNP/IP inside (no need for any external resistor)

 For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

3.34 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.

The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power rails allowing its use throughout the entire power range.

The major features are:

 Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing

 Supports the session request protocol (SRP) and host negotiation protocol (HNP)

 8 bidirectional endpoints

 16 host channels with periodic OUT support

 Internal FS OTG PHY support

 External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.

 Internal USB DMA

 HNP/SNP/IP inside (no need for any external resistor)

 for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

36/198 DS10693 Rev 10

STM32F446xC/E Functional overview

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 94.5 Mbyte/s (in 14-bit mode) at 54 MHz.

Its features:

 Programmable polarity for the input pixel clock and synchronization signals

 Parallel data communication can be 8-, 10-, 12- or 14-bit

 Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)

 Supports continuous mode or snapshot (a single frame) mode

 Capability to automatically crop the image black and white.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 90 MHz.

3.37 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

 Simultaneous sample and hold

 Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature makes possible a very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as V

BAT

, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and V

BAT conversion are enabled at the same time, only V

BAT

conversion is performed.

DS10693 Rev 10 37/198

Functional overview STM32F446xC/E

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.

This dual digital Interface supports the following features:

 two DAC converters: one for each output channel

 8-bit or 10-bit monotonic output

 left or right data alignment in 12-bit mode

 synchronized update capability

 noise-wave generation

 triangular-wave generation

 dual DAC channel independent or simultaneous conversions

 DMA capability for each channel

 external triggers for conversion

 input voltage reference V

REF+

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

3.40 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.41 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F446xx through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

38/198 DS10693 Rev 10

STM32F446xC/E

4 Pinout and pin description

Pinout and pin description

Figure 10. STM32F446xC/xE LQFP64 pinout

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

4 45

8 41

LQFP64

12 37

13 36

14 35

15 34

17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

MS31149V3

1. The above figure shows the package top view.

DS10693 Rev 10 39/198

Pinout and pin description

Figure 11. STM32F446xC/xE LQFP100 pinout

STM32F446xC/E

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VDD

VSSA/VREF-

VREF+

VDDA

PA0

PA1

PA2

LQFP100

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

VCAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

MS31151V4

1. The above figure shows the package top view.

40/198 DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Figure 12. STM32F446xC LQFP144 pinout

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PE 2

PE 3

PE 4

PE 5

PE 6

VBAT

PC13

PC14

PC15

PF9

PF10

PH0

PH1

NR ST

PC0

PC1

PC2

PC3

VDD

VSSA

VREF+

VDDA

PA 0

PA 1

PA 2

LQFP144

1. The above figure shows the package top view.

103

102

101

100

108

107

106

105

104

PD12

PD11

PD10

PD9

PD8

PB 15

PB 14

PB 13

PB 12

VDD

VSS

VCAP_2

PA 13

PA 12

PA 11

PA 10

PA 9

PA 8

PC9

PC8

PG 4

PG 3

PG 2

PD15

PD14

VDD

VSS

PD13

PC7

PC6

VDDUSB

VSS

PG 8

PG 7

PG 6

PG 5 ai18496c

DS10693 Rev 10 41/198

Pinout and pin description

VDD

PC12

STM32F446xC/E

Figure 13. STM32F446xC/xE WLCSP81 ballout

3 4 5 6 7 8 9

PD4 PD7 PB3 PB5 BOOT0 VDD PE4

VSS PA15 PD0 PD6 PB4 PB7 VSS

PDR_

VBAT

C PA11 VCAP_2 PA14 PD1 PB6 PB8 PB9 PC13 PC14

PC9 PA13 PC10 PC11 PD2 PE3

VDD

USB

PA8 PA10 PA12 PA7 PA3

PE2 NRESET PC15

PA2 PC2 PH0

PC6 PC7 PC8 PA9 PB0 PA5 VSSA PC3 PH1

PD13 PD12 PB15 PB12 PE9 PA6 PA1 VSS PC0

H PD11

PB13 VSS PB10 PE8 PB1 PA4 VDDA VDD

J PB14 VDD VCAP_1 PE10 PE7 PB2 PC4

BYPASS_

REG

PA0

1. The above figure shows the package top view.

MSv33518V2

42/198 DS10693 Rev 10

STM32F446xC/E

A PC13

PE3

PE2

Pinout and pin description

Figure 14. STM32F446xC/xE UFBGA144 ballout

4 5 6 7 8 9 10

PE1 PE0 PB4 PB3 PD6 PD7 PA15

PA14

PA13

B PC14 PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PAI2

C PC15 VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12

VDD

USB

PA11

D PH0 VSS VDD PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9

E PH1 PF3 PF4 PF5

PDR_

VSS VSS PG9 PD2 PD0 PC9 PA8

F NRST PF7 PF6 VDD VDD VDD VDD VDD VDD VDD PC8 PC7

G PF10 PF9 PF8 VSS VDD VDD VDD VSS VCAP_2 VSS PG8 PC6

PC0

PC1 PC2 PC3

BYPASS

_REG

VSS VCAP_1 PE11 PD11 PG7 PG6 PG5

VSSA PA0 PA4 PC4 PB2 PG1 PE10 PE12 PD10 PG4 PG3 PG2

VREFPA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15

L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15

M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13

MSv36519V2

1. The above picture shows the package top view.

DS10693 Rev 10 43/198

Pinout and pin description STM32F446xC/E

Name

Pin name

Pin type

I/O structure

Notes

Alternate functions

Additional functions

Table 9. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

FTf

TTa

RST

Input / output pin

5 V tolerant I/O

5V tolerant IO, I2C FM+ option

3.3 V tolerant I/O directly connected to ADC

Dedicated BOOT0 pin

Bidirectional reset pin with weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Pin number

Table 10. STM32F446xx pin and ball descriptions

Pin name (function after reset)

Alternate functions

Additional functions

1 D7 A3 1

2 D6 A2 2

3 A9 B2 3

4 B3 4

PE2

PE3

PE4

PE5

I/O FT -

TRACECLK, SPI4_SCK,

SAI1_MCLK_A,

QUADSPI_BK1_IO2,

FMC_A23, EVENTOUT

TRACED0, SAI1_SD_B,

FMC_A19, EVENTOUT

TRACED1, SPI4_NSS,

SAI1_FS_A, FMC_A20,

DCMI_D4, EVENTOUT

TRACED2, TIM9_CH1,

SPI4_MISO, SAI1_SCK_A,

FMC_A21, DCMI_D6,

EVENTOUT

44/198 DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

Pin name (function after reset)

Alternate functions

Additional functions

PE6 I/O FT

VBAT

PC13

PC14-

OSC32_IN(PC14)

PC15-

OSC32_OUT(PC15)

S -

I/O FT -

TRACED3, TIM9_CH2,

SPI4_MOSI, SAI1_SD_A,

FMC_A22, DCMI_D7,

EVENTOUT

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

I/O FT -

S -

I/O FT -

G1 22 PF10 I/O FT -

5 12 E9 D1 23 PH0-OSC_IN(PH0) I/O FT -

I2C2_SDA, FMC_A0,

EVENTOUT

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA, FMC_A2,

EVENTOUT

FMC_A3, EVENTOUT

FMC_A4, EVENTOUT

FMC_A5, EVENTOUT

TIM10_CH1, SAI1_SD_B,

QUADSPI_BK1_IO3,

EVENTOUT

TIM11_CH1,

SAI1_MCLK_B,

QUADSPI_BK1_IO2,

EVENTOUT

SAI1_SCK_B, TIM13_CH1,

QUADSPI_BK1_IO0,

EVENTOUT

SAI1_FS_B, TIM14_CH1,

QUADSPI_BK1_IO1,

EVENTOUT

DCMI_D11, EVENTOUT

EVENTOUT

ADC3_IN9

ADC3_IN14

ADC3_IN15

TAMP_1/WKUP1

OSC32_IN

OSC32_OUT

ADC3_IN4

ADC3_IN5

ADC3_IN6

ADC3_IN7

ADC3_IN8

OSC_IN

DS10693 Rev 10 45/198

Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

STM32F446xC/E

Pin name (function after reset)

Alternate functions

Additional functions

8 15 G9 H1 26

10 17 E8 H3 28

11 18 F8 H4 29

19 H9

G8 -

12 20 F7 J1 31

K1 -

21 L1 32

13 22 H8 M1 33

14 23 J9 J2 34

15 24 G7 K2 35

16 25 E7 L2 36

PH1-

OSC_OUT(PH1)

NRST

PC0

PC1

PC2

PC3

VDD

VSS

VSSA

VREF-

VREF+

VDDA

PA1

PA2

I/O

I/O RST -

I/O FT -

PA0-WKUP(PA0) I/O FT -

I/O FT -

EVENTOUT OSC_OUT

SAI1_MCLK_B,

OTG_HS_ULPI_STP,

FMC_SDNWE,

EVENTOUT

SPI3_MOSI/I2S3_SD,

SAI1_SD_A,

SPI2_MOSI/I2S2_SD,

EVENTOUT

SPI2_MISO,

OTG_HS_ULPI_DIR,

FMC_SDNE0, EVENTOUT

SPI2_MOSI/I2S2_SD,

OTG_HS_ULPI_NXT,

FMC_SDCKE0,

EVENTOUT

TIM2_CH1/TIM2_ETR,

TIM5_CH1, TIM8_ETR,

USART2_CTS,

UART4_TX, EVENTOUT

TIM2_CH2, TIM5_CH2,

USART2_RTS,

UART4_RX,

QUADSPI_BK1_IO3,

SAI2_MCLK_B,

EVENTOUT

TIM2_CH3, TIM5_CH3,

TIM9_CH1, USART2_TX,

SAI2_SCK_B, EVENTOUT

ADC123_IN10

ADC123_IN11

ADC123_IN12

ADC123_IN13

ADC123_IN0,

WKUP0/TAMP_2

ADC123_IN1

ADC123_IN2

46/198 DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

Pin name (function after reset)

Alternate functions

Additional functions

17 26 E6 M2 37

18 27 G4 38

J8 H5

19 28 F4

20 29 H7 J3 40

21 30 F6 K3 41

22 31 G6 L3 42

23 32 E5 M3 43

24 33 J7 J4 44

25 34 K4 45

PA3

VSS

BYPASS_REG

VDD

PA4

PA5

PA6

PA7

PC4

PC5

I/O FT -

S -

I FT -

S -

I/O TTa -

I/O FT -

TIM2_CH4, TIM5_CH4,

TIM9_CH2, SAI1_FS_A,

USART2_RX,

OTG_HS_ULPI_D0,

EVENTOUT

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART2_CK,

OTG_HS_SOF,

DCMI_HSYNC,

EVENTOUT

TIM2_CH1/TIM2_ETR,

TIM8_CH1N,

SPI1_SCK/I2S1_CK,

OTG_HS_ULPI_CK,

EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SPI1_MISO,

I2S2_MCK, TIM13_CH1,

DCMI_PIXCLK,

EVENTOUT

TIM1_CH1N, TIM3_CH2,

TIM8_CH1N,

SPI1_MOSI/I2S1_SD,

TIM14_CH1,

FMC_SDNWE,

EVENTOUT

I2S1_MCK, SPDIFRX_IN2,

FMC_SDNE0, EVENTOUT

USART3_RX,

SPDIFRX_IN3,

FMC_SDCKE0,

EVENTOUT

ADC123_IN3

ADC12_IN4,

DAC_OUT1

ADC12_IN5,

DAC_OUT2

ADC12_IN6

ADC12_IN7

ADC12_IN14

ADC12_IN15

DS10693 Rev 10 47/198

Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

STM32F446xC/E

Pin name (function after reset)

Alternate functions

Additional functions

26 35 F5 L4 46

27 36 H6 M4 47

28 37 J6 J5 48

M5 49

L5 50

G5 52

K5 53

M6 54

L6 55

K6 56

J6 57

38 J5 M7 58

39 H5 L7 59

40 G5 K7 60

PF15

PG0

PG1

PE7

PF11

PF12

VSS

VDD

PF13

PF14

PB0

PB1

PB2-BOOT1

(PB2)

PE8

PE9

I/O FT -

S -

I/O

I/O FTf -

I/O FTf

I/O FT -

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N,

SPI3_MOSI/I2S3_SD,

UART4_CTS,

OTG_HS_ULPI_D1,

SDIO_D1, EVENTOUT

TIM1_CH3N, TIM3_CH4,

TIM8_CH3N,

OTG_HS_ULPI_D2,

SDIO_D2, EVENTOUT

TIM2_CH4, SAI1_SD_A,

SPI3_MOSI/I2S3_SD,

QUADSPI_CLK,

OTG_HS_ULPI_D4,

SDIO_CK, EVENTOUT

SAI2_SD_B,

FMC_SDNRAS,

DCMI_D12, EVENTOUT

FMC_A6, EVENTOUT

FMPI2C1_SMBA,

FMC_A7, EVENTOUT

FMPI2C1_SCL, FMC_A8,

EVENTOUT

FMPI2C1_SDA, FMC_A9,

EVENTOUT

FMC_A10, EVENTOUT

FMC_A11, EVENTOUT

TIM1_ETR, UART5_RX,

QUADSPI_BK2_IO0,

FMC_D4, EVENTOUT

TIM1_CH1N, UART5_TX,

QUADSPI_BK2_IO1,

FMC_D5, EVENTOUT

TIM1_CH1,

QUADSPI_BK2_IO2,

FMC_D6, EVENTOUT

ADC12_IN8

ADC12_IN9

48/198 DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

Pin name (function after reset)

Alternate functions

Additional functions

29 47 H4 M9 69

41 J4 J7 63

42 H8 64

43 J8 65

44 K8 66

45 L8 67

46 M8 68

M10 70

30 48 J3 H7 71

31 49 H3 -

32 50 J2 G7 72

33 51 G4 M11 73

VSS

VDD

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VCAP_1

VSS

VDD

PB12

I/O FT -

TIM1_CH2N,

QUADSPI_BK2_IO3,

FMC_D7, EVENTOUT

TIM1_CH2, SPI4_NSS,

SAI2_SD_B, FMC_D8,

EVENTOUT

TIM1_CH3N, SPI4_SCK,

SAI2_SCK_B, FMC_D9,

EVENTOUT

TIM1_CH3, SPI4_MISO,

SAI2_FS_B, FMC_D10,

EVENTOUT

TIM1_CH4, SPI4_MOSI,

SAI2_MCLK_B, FMC_D11,

EVENTOUT

TIM1_BKIN, FMC_D12,

EVENTOUT

TIM2_CH3, I2C2_SCL,

SPI2_SCK/I2S2_CK,

SAI1_SCK_A,

USART3_TX,

OTG_HS_ULPI_D3,

EVENTOUT

TIM2_CH4, I2C2_SDA,

USART3_RX, SAI2_SD_A,

EVENTOUT

TIM1_BKIN, I2C2_SMBA,

SPI2_NSS/I2S2_WS,

SAI1_SCK_B,

USART3_CK, CAN2_RX,

OTG_HS_ULPI_D5,

OTG_HS_ID, EVENTOUT

DS10693 Rev 10 49/198

Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

STM32F446xC/E

Pin name (function after reset)

Alternate functions

Additional functions

34 52 H2 M12 74

35 53 J1 L11 75

36 54 G3 L12 76

55 -

56 K9 78

57 J9 79

58 H1

L9 77

H9 80

59 G2 L10 81

50/198

G1 K10 82

G8 83

F8 84

PB13

PB14

(1)

PB15

PD8

PD9

PD10

PD11

PD12

PD13

VSS

VDD

I/O FT -

I/O FTf -

TIM1_CH1N,

SPI2_SCK/I2S2_CK,

USART3_CTS, CAN2_TX,

OTG_HS_ULPI_D6,

EVENTOUT

TIM1_CH2N, TIM8_CH2N,

SPI2_MISO,

USART3_RTS,

TIM12_CH1,

OTG_HS_DM, EVENTOUT

RTC_REFIN, TIM1_CH3N,

TIM8_CH3N,

SPI2_MOSI/I2S2_SD,

TIM12_CH2, OTG_HS_DP,

EVENTOUT

USART3_TX,

SPDIFRX_IN1, FMC_D13,

EVENTOUT

USART3_RX, FMC_D14,

EVENTOUT

USART3_CK, FMC_D15,

EVENTOUT

FMPI2C1_SMBA,

USART3_CTS,

QUADSPI_BK1_IO0,

SAI2_SD_A, FMC_A16,

EVENTOUT

TIM4_CH1,

FMPI2C1_SCL,

USART3_RTS,

QUADSPI_BK1_IO1,

SAI2_FS_A, FMC_A17,

EVENTOUT

TIM4_CH2,

FMPI2C1_SDA,

QUADSPI_BK1_IO3,

SAI2_SCK_A, FMC_A18,

EVENTOUT

OTG_HS_VBUS

DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

Pin name (function after reset)

Alternate functions

Additional functions

61 K11 85

62 K12 86

J12

J11

J10

H12

H11

H10

G11 93

F10

E1 C11 95

37 63 F1 G12 96

38 64 F2 F12 97

39 65 F3 F11 98

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PG8

VSS

VDD

VDDUSB

PC6

PC7

PC8

I/O FTf -

I/O FT -

I/O FTf -

I/O FT -

TIM4_CH3,

FMPI2C1_SCL,

SAI2_SCK_A, FMC_D0,

EVENTOUT

TIM4_CH4,

FMPI2C1_SDA, FMC_D1,

EVENTOUT

FMC_A12, EVENTOUT

FMC_A13, EVENTOUT

FMC_A14/FMC_BA0,

EVENTOUT

FMC_A15/FMC_BA1,

EVENTOUT

QUADSPI_BK1_NCS,

DCMI_D12, EVENTOUT

USART6_CK, FMC_INT,

DCMI_D13, EVENTOUT

SPDIFRX_IN2,

USART6_RTS,

FMC_SDCLK, EVENTOUT

TIM3_CH1, TIM8_CH1,

FMPI2C1_SCL,

I2S2_MCK, USART6_TX,

SDIO_D6, DCMI_D0,

EVENTOUT

TIM3_CH2, TIM8_CH2,

FMPI2C1_SDA,

SPI2_SCK/I2S2_CK,

I2S3_MCK, SPDIFRX_IN1,

USART6_RX, SDIO_D7,

DCMI_D1, EVENTOUT

TRACED0, TIM3_CH3,

TIM8_CH3, UART5_RTS,

USART6_CK, SDIO_D0,

DCMI_D2, EVENTOUT

DS10693 Rev 10

51/198

Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

STM32F446xC/E

Pin name (function after reset)

Alternate functions

Additional functions

E11

E12 100

D12 101

D11 102

C12 103

B12 104

PC9

PA8

PA9

PA10

PA11

PA12

Table 14 , and Table 15

I/O FT -

46 72 D2 A12 105 PA13(JTMS-SWDIO) I/O FT -

73 C2 106

47 74 B1 G10 107

48 75 A1 F9 108

50 77 B2 A10 110

VCAP_2

VSS

VDD

PA15(JTDI)

S -

49 76 C3 A11 109 PA14(JTCK-SWCLK) I/O FT -

I/O FT -

MCO2, TIM3_CH4,

TIM8_CH4, I2C3_SDA,

I2S_CKIN, UART5_CTS,

QUADSPI_BK1_IO0,

SDIO_D1, DCMI_D3,

EVENTOUT

MCO1, TIM1_CH1,

I2C3_SCL, USART1_CK,

OTG_FS_SOF,

EVENTOUT

TIM1_CH2, I2C3_SMBA,

SPI2_SCK/I2S2_CK,

SAI1_SD_B, USART1_TX,

DCMI_D0, EVENTOUT

TIM1_CH3, USART1_RX,

OTG_FS_ID, DCMI_D1,

EVENTOUT

TIM1_CH4, USART1_CTS,

CAN1_RX, OTG_FS_DM,

EVENTOUT

TIM1_ETR, USART1_RTS,

SAI2_FS_B, CAN1_TX,

OTG_FS_DP, EVENTOUT

JTMS-SWDIO,

EVENTOUT

JTCK-SWCLK,

EVENTOUT

JTDI,

TIM2_CH1/TIM2_ETR,

HDMI_CEC,

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

UART4_RTS, EVENTOUT

OTG_FS_VBUS

52/198 DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

Pin name (function after reset)

Alternate functions

Additional functions

81 B3 E10 114

82 C4 D10 115

54 83 D5 E9 116

B11

B10 112

C10 113

111

117

85 A3 C9 118

86 -

B9 119

E7 120

F7 121

PD4

PD5

VSS

VDD

PD0

PD1

PD2

PC10

PC11

PC12

PD3

I/O FT -

SPI3_SCK/I2S3_CK,

USART3_TX, UART4_TX,

QUADSPI_BK1_IO1,

SDIO_D2, DCMI_D8,

EVENTOUT

SPI3_MISO, USART3_RX,

UART4_RX,

QUADSPI_BK2_NCS,

SDIO_D3, DCMI_D4,

EVENTOUT

I2C2_SDA,

SPI3_MOSI/I2S3_SD,

USART3_CK, UART5_TX,

SDIO_CK, DCMI_D9,

EVENTOUT

SPI4_MISO,

SPI3_MOSI/I2S3_SD,

CAN1_RX, FMC_D2,

EVENTOUT

SPI2_NSS/I2S2_WS,

CAN1_TX, FMC_D3,

EVENTOUT

TIM3_ETR, UART5_RX,

SDIO_CMD, DCMI_D11,

EVENTOUT

TRACED1,

SPI2_SCK/I2S2_CK,

USART2_CTS,

QUADSPI_CLK,

FMC_CLK, DCMI_D5,

EVENTOUT

USART2_RTS, FMC_NOE,

EVENTOUT

USART2_TX, FMC_NWE,

EVENTOUT

DS10693 Rev 10 53/198

Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

STM32F446xC/E

Pin name (function after reset)

Alternate functions

Additional functions

122

123

124

125

126

127

128

129

130

131

132

55 89 A5 A7 133

PD6

PD7

PG9

PG10

PG11

PG12

PG13

PG14

VSS

VDD

PG15

PB3(JTDO/TRACES

WO)

I/O FT -

I/O

FT -

SPI3_MOSI/I2S3_SD,

SAI1_SD_A, USART2_RX,

FMC_NWAIT, DCMI_D10,

EVENTOUT

USART2_CK,

SPDIFRX_IN0, FMC_NE1,

EVENTOUT

SPDIFRX_IN3,

USART6_RX,

QUADSPI_BK2_IO2,

SAI2_FS_B,

FMC_NE2/FMC_NCE3,

DCMI_VSYNC,

EVENTOUT

SAI2_SD_B, FMC_NE3,

DCMI_D2, EVENTOUT

SPI4_SCK, SPDIFRX_IN0,

DCMI_D3, EVENTOUT

SPI4_MISO,

SPDIFRX_IN1,

USART6_RTS, FMC_NE4,

EVENTOUT

TRACED2, SPI4_MOSI,

USART6_CTS, FMC_A24,

EVENTOUT

TRACED3, SPI4_NSS,

USART6_TX,

QUADSPI_BK2_IO3,

FMC_A25, EVENTOUT

USART6_CTS,

FMC_SDNCAS,

DCMI_D13, EVENTOUT

JTDO/TRACESWO,

TIM2_CH2, I2C2_SDA,

SPI1_SCK/I2S1_CK,

SPI3_SCK/I2S3_CK,

EVENTOUT

54/198 DS10693 Rev 10

STM32F446xC/E Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

Pin name (function after reset)

Alternate functions

Additional functions

56 90 B5 A6 134 PB4(NJTRST)

135

136

137

138

139

140

141

142

PB5

PB6

PB7

BOOT0

PB8

PB9

PE0

PE1

I/O FT -

I B -

I/O FT -

NJTRST, TIM3_CH1,

I2C3_SDA, SPI1_MISO,

SPI3_MISO,

SPI2_NSS/I2S2_WS,

EVENTOUT

TIM3_CH2, I2C1_SMBA,

SPI1_MOSI/I2S1_SD,

SPI3_MOSI/I2S3_SD,

CAN2_RX,

OTG_HS_ULPI_D7,

FMC_SDCKE1,

DCMI_D10, EVENTOUT

TIM4_CH1, HDMI_CEC,

I2C1_SCL, USART1_TX,

CAN2_TX,

QUADSPI_BK1_NCS,

FMC_SDNE1, DCMI_D5,

EVENTOUT

TIM4_CH2, I2C1_SDA,

USART1_RX,

SPDIFRX_IN0, FMC_NL,

DCMI_VSYNC,

EVENTOUT

TIM2_CH1/TIM2_ETR,

TIM4_CH3, TIM10_CH1,

I2C1_SCL, CAN1_RX,

SDIO_D4, DCMI_D6,

EVENTOUT

TIM2_CH2, TIM4_CH4,

TIM11_CH1, I2C1_SDA,

SPI2_NSS/I2S2_WS,

SAI1_FS_B, CAN1_TX,

SDIO_D5, DCMI_D7,

EVENTOUT

TIM4_ETR,

SAI2_MCLK_A,

FMC_NBL0, DCMI_D2,

EVENTOUT

FMC_NBL1, DCMI_D3,

EVENTOUT

DS10693 Rev 10

VPP

55/198

Pinout and pin description

Pin number

Table 10. STM32F446xx pin and ball descriptions (continued)

STM32F446xC/E

Pin name (function after reset)

Alternate functions

Additional functions

63 99 B7 E6

B8 E5

143

64 100 A8 F5 144

VSS

PDR_ON

VDD

1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB

56/198 DS10693 Rev 10

AF5

Table 11. Alternate function

AF6 AF7 AF8 AF9 AF0 AF1 AF2 AF3 AF4 AF10 AF11 AF12 AF13

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

SYS

MCO1

PA12 -

PA13

PA14

JTMS-

SWDIO

JTCK-

SWCLK

TIM1/2 TIM3/4/5

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

TIM2_CH1/

TIM2_ETR

TIM5_CH1

TIM2_CH2 TIM5_CH2

TIM2_CH3 TIM5_CH3

TIM2_CH4 TIM5_CH4

TIM8_ETR

TIM9_CH1

TIM9_CH2 -

USART2_

CTS

USART2_

RTS

USART2_

UART4_

SAI2_

SCK_B

QUADSPI_

BK1_IO3

SAI2_

MCLK_B

OTG_HS_

ULPI_D0

TIM2_CH1/

TIM2_ETR

TIM1_

BKIN

TIM3_CH1

TIM1_

CH1N

TIM3_CH2

TIM8_

CH1N

TIM8_

BKIN

TIM8_

CH1N

SAI1_

FS_A

SPI1_NSS/I

2S1_WS

SPI3_NSS

I2S3_WS

SPI1_SCK/I

2S1_CK

SPI1_MISO

I2S2_

MCK

SPI1_MOSI

I2S1_SD

USART2_

TIM13_CH1

TIM14_CH1

OTG_HS_

ULPI_CK

OTG_HS_

SOF

FMC_

SDNWE

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR -

I2C3_

SCL

I2C3_

SMBA

SPI2_SCK

/I2S2_CK

SAI1_

SD_B

USART1_

CTS

USART1_

RTS

SAI2_

FS_B

CAN1_RX

CAN1_TX

OTG_FS_

SOF

OTG_FS_

DCMI

DCMI_

HSYNC

DCMI_

PIXCLK

DCMI_D0

DCMI_D1

PA15 JTDI

TIM2_CH1/

TIM2_ETR

HDMI_

CEC

SPI1_NSS/

I2S1_WS

SPI3_

NSS/

I2S3_WS

UART4_RT

AF14

AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF0 AF1 AF2 AF3 AF4 AF10 AF11 AF12 AF13

Port

PB0

PB1

PB2

PB5

SYS

TIM1/2 TIM3/4/5

TIM1_CH2N TIM3_CH3

TIM1_CH3N TIM3_CH4

TIM2_CH4 -

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

TIM8_

CH2N

TIM8_

CH3N

SPI3_MOSI/

I2S3_SD

SPI3_MOSI/

I2S3_SD

UART4_

CTS

QUADSPI_

CLK

OTG_HS_

ULPI_D1

OTG_HS_

ULPI_D2

OTG_HS_

ULPI_D4

SDIO_D1

SDIO_D2

SDIO_CK

PB3

PB4

JTDO/

TRACE

SWO

NJTRS

TIM2_CH2

TIM3_CH1

TIM3_CH2 -

I2C2_

SDA

I2C3_

SDA

I2C1_

SMBA

SPI1_SCK

/I2S1_CK

SPI1_MISO

SAI1_

SD_A

SPI3_SCK

I2S3_CK

SPI3_

MISO

SPI1_MOSI

/I2S1_SD

SPI3_

MOSI/

I2S3_SD

SPI2_NSS/

I2S2_WS

CAN2_RX

OTG_HS_

ULPI_D7

FMC_

SDCKE1

PB6

PB7

PB8

PB9

PB10

PB11 -

TIM4_CH1

TIM4_CH2

TIM2_CH1/

TIM2_ETR

TIM4_CH3

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM4_CH4

HDMI_

CEC

TIM10_

CH1

TIM11_

CH1

I2C1_

SCL

I2C1_

SDA

I2C1_

SCL

I2C1_

SDA

I2C2_

SCL

I2C2_

SDA

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

SAI1_

FS_B

SAI1_

SCK_A

USART1_

USART3_

SPDIF_

RX0

SAI2_

SD_A

CAN2_TX

CAN1_RX

CAN1_TX

QUADSPI_

BK1_NCS

OTG_HS_

ULPI_D3

FMC_

SDNE1

FMC_NL

SDIO_D4

SDIO_D5

DCMI

DCMI_

D10

DCMI_

VSYNC

DCMI_D5

DCMI_D6

DCMI_D7

PB12

PB13

PB14 -

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

PB15

RTC_

REFIN

TIM1_CH3N -

TIM8_

CH2N

TIM8_

CH3N

I2C2_

SMBA

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

SPI2_MISO

SPI2_MOSI

/I2S2_SD

SAI1_

SCK_B

USART3_

CTS

USART3_

RTS

CAN2_RX

CAN2_TX

TIM12_CH1

TIM12_CH2

OTG_HS_

ULPI_D5

OTG_HS_

ULPI_D6

OTG_

HS_ID

OTG_

HS_DM

OTG_

HS_DP

AF14

AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

PC0

PC1

PC2

PC3

PC4

PC5

PC11

PC12

PC13

PC14

PC15

AF0

SYS

PC6 -

PC7 -

PC8

TRACE

PC9 MCO2

PC10 -

AF1

TIM1/2

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF2 AF3 AF4 AF10 AF11 AF12 AF13

TIM3/4/5

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

SPI3_MOSI

/I2S3_SD

SAI1_

MCLK_B

SAI1_

SD_A

SPI2_MOSI

/I2S2_SD

OTG_HS_

ULPI_STP

FMC_

SDNWE

SPI2_MISO

SPI2_MOS

II2S2_SD

OTG_HS_

ULPI_DIR

OTG_HS_

ULPI_NXT

FMC_

SDNE0

FMC_

SDCKE0

FMC_

SDNE0

FMC_

SDCKE0

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

I2S1_MCK -

SPDIF_

RX2

USART3_RX

SPDIF_

RX3

FMPI2C1

_SCL

FMPI2C1

_SDA

I2C3_

SDA

I2C2_

SDA

I2S2_MCK

I2S_CKIN

SPI2_SCK/

I2S2_CK

I2S3_MCK

SPDIF_RX1

UART5_RTS

USART6

_TX

USART6

_RX

USART6

_CK

SPI3_SCK

/I2S3_CK

SPI3_

MISO

SPI3_

MOSI/

I2S3_SD

USART3_CK UART5_TX -

UART5_CTS -

QUADSPI_

BK1_IO0

USART3_TX UART4_TX

QUADSPI_

BK1_IO1

USART3_RX UART4_RX

QUADSPI_

BK2_NCS

DCMI

SDIO_D7 DCMI_D1

SDIO_D0 DCMI_D2

SDIO_D1 DCMI_D3

SDIO_D2 DCMI_D8

SDIO_D3 DCMI_D4

SDIO_CK DCMI_D9

SDIO_D6 DCMI_D0

AF14

AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

PD0

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

AF0

SYS

PD1 -

PD2

PD3

TRACE

PD4 -

PD5 -

AF1

TIM1/2

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF2 AF3 AF4 AF10 AF11 AF12 AF13

TIM3/4/5

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

SPI4_MISO

SPI3_

MOSI/

I2S3_SD

CAN1_RX FMC_D2

SPI2_NSS/

I2S2_WS

CAN1_TX FMC_D3

TIM3_ETR

SPI2_SCK/

I2S2_CK

USART2_

CTS

USART2_

RTS

USART2_

UART5_RX

QUADSPI_

CLK

SDIO_CMD

FMC_CLK

FMC_NOE

FMC_NWE

DCMI

DCMI_

D11

DCMI_

SPI3_

MOSI/

I2S3_SD

SAI1_

SD_A

FMC_

NWAIT

DCMI_

D10

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4 -

FMPI2C1

_SMBA

FMPI2C1

_SCL

FMPI2C1

_SDA

FMPI2C1

_SCL

FMPI2C1

_SDA

USART2_

USART3_

CTS

USART3_

RTS

SPDIF_

RX0

SPDIF_

RX1

SAI2_

SCK_A

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

SAI2_SD_A

SAI2_FS_A

QUADSPI_

BK1_IO3

SAI2_SCK_A

FMC_NE1

FMC_D13

FMC_D14

FMC_D15

FMC_A16

FMC_A17

FMC_A18

FMC_D0

FMC_D1 -

AF14 AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF0 AF1 AF2 AF3 AF4 AF10 AF11 AF12 AF13

Port

PE0

PE1

PE7

PE8

PE9

PE10

PE11

SYS

PE2

PE3

PE4

PE5

PE6

TRACE

CLK

TRACE

TIM1/2

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM3/4/5

TIM4_ETR

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

SAI2_

MCLK_A

FMC_

NBL0

FMC_

NBL1

TIM9_CH1

TIM9_CH2 -

SPI4_SCK

SPI4_NSS

SPI4_MISO

SPI4_MOSI

SAI1_

MCLK_A

SAI1_

SD_B

SAI1_

FS_A

SAI1_

SCK_A

SAI1_

SD_A

QUADSPI_

BK1_IO2

FMC_A23

FMC_A19

DCMI

DCMI_D2

DCMI_D3

FMC_A20 DCMI_D4

FMC_A21 DCMI_D6

FMC_A22 DCMI_D7

SPI4_NSS -

UART5_RX

UART5_TX

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

QUADSPI_

BK2_IO2

QUADSPI_

BK2_IO3

SAI2_

SD_B -

FMC_D4

FMC_D5

FMC_D6

FMC_D7

FMC_D8 -

AF14

PE12

PE13

PE14

PE15 -

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN -

SPI4_SCK

SPI4_MISO

SPI4_MOSI

SAI2_

SCK_B

SAI2_

FS_B

SAI2_

MCLK_B

FMC_D9

FMC_D10

FMC_D11

FMC_D12 -

AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

PF4

PF5

PF6

PF7

PF8

PF9

PF0

PF1

PF2

PF3

PF10

PF11

PF12

PF13

PF14

PF15

AF0

SYS

AF1

TIM1/2

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF2 AF3 AF4 AF10 AF11 AF12

TIM3/4/5

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

I2C2_

SDA

I2C2_

SCL

I2C2_

SMBA

FMC_A0

FMC_A1

FMC_A2

FMC_A3

AF13

DCMI

FMC_A4

FMC_A5 -

TIM10_

CH1

TIM11_

CH1

SAI1_

SD_B

SAI1_

MCLK_B

SAI1_

SCK_B

SAI1_

FS_B

QUADSPI_

BK1_IO3

QUADSPI_

BK1_IO2

TIM13_CH1

TIM14_CH1

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

SAI2_SD_B

FMC_

SDNRAS

FMC_A6

DCMI_

D11

DCMI_

D12

FMPI2C1

_SMBA

FMPI2C1

_SCL

FMPI2C1

_SDA

FMC_A7

FMC_A8

FMC_A9 -

AF14 AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

PG4

PG5

PG6

PG7

PG8

PG9

PG10

PG0

PG1

PG2

PG3

Port

PG11

AF0

SYS

PG12 -

PG13

TRACE

PG14

TRACE

PG15 -

AF1

TIM1/2

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF2 AF3 AF4 AF10 AF11 AF12

TIM3/4/5

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

AF13

DCMI

FMC_A10 -

FMC_A11 -

SPI4_

SCK

SPI4_

MISO

SPI4_

MOSI

SPI4_

NSS

SPDIFRX_

IN2

SPDIFRX_

IN3

QUADSPI_

BK1_NCS

USART6_C

USART6_R

QUADSPI_

BK2_IO2

SAI2_FS_B

SAI2_SD_B

SPDIFRX_

IN0

SPDIFRX_

IN1

USART6_R

USART6_C

USART6_T

QUADSPI_

BK2_IO3

USART6_C

FMC_A24 -

FMC_A25

FMC_

SDNCAS

DCMI_

D13

FMC_A12 -

FMC_A13 -

FMC_A14/

FMC_BA0

FMC_A15/

FMC_BA1

FMC_INT

DCMI_

D12

DCMI_

D13

FMC_

SDCLK

FMC_NE2/

FMC_NCE3

DCMI_

VSYNC

(1)

FMC_NE3 DCMI_D2

DCMI_D3

FMC_NE4 -

AF14 AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

AF0

SYS

AF1

TIM1/2

Table 11. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF2 AF3 AF4 AF10 AF11 AF12

TIM3/4/5

TIM8/9/10/11

CEC

I2C1/2/3

/4/CEC

SPI1/2/3/4

SPI2/3/4/

SAI1

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

SAI/

USART6/

UART4/5/

SPDIFRX

CAN1/2

TIM12/13/

14/

QUADSPI

SAI2/

QUADSPI/

OTG2_HS/

OTG1_FS

FMC/

SDIO/

OTG2_FS

AF13

DCMI

PH0 -

PH1 -

The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.

AF14 AF15

SYS

EVENT

OUT

EVENT

OUT

STM32F446xC/E Memory mapping

The memory map is shown in

Figure 15

Figure 15. Memory map

0xFFFF FFFF 512-Mbyte

Block 7

Cortex-M4

Internal peripherals

0xE000 0000

0xDFFF FFFF

512-Mbyte

Block 6

FMC

0xD000 0000

0xCFFF FFFF

512-Mbyte

Block 5

FMC/QuadSPI

0xA000 0000

0x9FFF FFFF

512-Mbyte

Block 4

FMC bank 3 and QuadSPI

0x8000 0000

0x7FFF FFFF

512-Mbyte

Block 3

FMC bank 1

0x6000 0000

0x5FFF FFFF

512-Mbyte

Block 2

Peripherals

0x4000 0000

0x3FFF FFFF

512-Mbyte

Block 1

SRAM

0x2000 0000

0x1FFF FFFF

512-Mbyte

Block 0

SRAM

0x0000 0000

Reserved

SRAM (16 KB aliased

By bit-banding

SRAM (112 KB aliased

By bit-banding

Reserved

Option Bytes

Reserved

System memory

Reserved

Option bytes

Reserved

Flash memory

Reserved

Aliased to Flash, system memory or SRAM depending on the BOOT pins

0x2003 0000 - 0x3FFF FFFF

0x2002 0000 - 0x2002 FFFF

0x2001 C000 - 0x2001 FFFF

0x2000 0000 - 0x2001 BFFF

0x1FFF C008 - 0x1FFF FFFF

0x1FFF C000 - 0x1FFF C00F

0x1FFF 7A10 - 0x1FFF 7FFF

0x1FFF 0000 - 0x1FFF 7A0F

0x1FFE C008 - 0x1FFE FFFF

0x1FFE C000 - 0x1FFE C00F

0x1001 0000 - 0x1FFE BFFF

0x1000 0000 - 0x1000 FFFF

0x0820 0000 - 0x0FFF FFFF

0x0800 0000 - 0x081F FFFF

0x0020 0000 - 0x07FF FFFF

0x0000 0000 - 0x001F FFFF

Reserved

Cortex-M4 internal peripherals

AHB3

Reserved

AHB2

0xE010 0000 - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0x6000 0000 - 0xDFFF FFFF

0x5006 0C00 - 0x5FFF FFFF

0x5006 0BFF

Reserved

0x5000 0000

0x4008 0000 - 0x4FFF FFFF

0x4007 FFFF

AHB1

Reserved

APB2

Reserved

APB1

0x4002 0000

0x4001 6C00 - 0x4001 FFFF

0x4001 6BFF

0x4001 0000

0x4000 8000 - 0x4000 FFFF

0x4000 7FFF

0x4000 0000

MS33841V1

DS10693 Rev 10 65/198

Memory mapping STM32F446xC/E

Bus

Table 12. STM32F446xC/E register boundary addresses (1)

Boundary address Peripheral

Cortex-M4

AHB3

AHB2

0xE00F FFFF - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0xD000 0000 - 0xDFFF FFFF

0xC000 0000 - 0xCFFF FFFF

Reserved

Cortex-M4 internal peripherals

FMC bank 6

FMC bank 5

0xA000 2000 - 0x0xBFFF FFFF Reserved

0xA000 1000 - 0x0xA000 1FFF QuadSPI control register

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

FMC control register

QuadSPI

0x8000 0000 - 0x8FFF FFFF FMC bank 3

0x7000 0000 - 0x0x7FFF FFFF Reserved

0x6000 0000 - 0x6FFF FFFF FMC bank 1

0x5006 0C00- 0x5FFF FFFF

0x5006 0800- 0x500F 07FF

0x5005 0400 - 0x5006 07FF

Reserved

0x5005 0000 - 0x5005 03FF

0x5004 0000- 0x5004 FFFF

0x5000 0000 - 0X5003 FFFF

DCMI

Reserved

USB OTG FS

66/198 DS10693 Rev 10

STM32F446xC/E Memory mapping

Table 12. STM32F446xC/E register boundary addresses (1) (continued)

Bus Boundary address Peripheral

AHB1

0x4008 0000- 0x4FFF FFFF

0x4004 0000 - 0x4007 FFFF

0x4002 BC00- 0x4003 FFFF

0x4002 B000 - 0x4002 BBFF

0x4002 9400 - 0x4002 AFFF

0x4002 9000 - 0x4002 93FF

0x4002 8C00 - 0x4002 8FFF

0x4002 8800 - 0x4002 8BFF

0x4002 8400 - 0x4002 87FF

0x4002 8000 - 0x4002 83FF

0x4002 6800 - 0x4002 7FFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0X4002 5000 - 0X4002 5FFF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0X4002 3400 - 0X4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2C00 - 0x4002 2FFF

0x4002 2800 - 0x4002 2BFF

0x4002 2400 - 0x4002 27FF

0x4002 2000 - 0x4002 23FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0X4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

Reserved

USB OTG HS

Reserved

GPIOH

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

DMA2

DMA1

Reserved

BKPSRAM

Flash interface register

RCC

Reserved

CRC

Reserved

DS10693 Rev 10 67/198

Memory mapping STM32F446xC/E

Table 12. STM32F446xC/E register boundary addresses (1) (continued)

Bus Boundary address Peripheral

APB2

0x4001 6C00- 0x4001 FFFF

0x4001 6800 - 0x4001 6BFF

0x4001 5C00 - 0x4001 5FFF

0x4001 6000 - 0x4001 67FF

0x4001 5800 - 0x4001 5BFF

0x4001 5400 - 0x4001 57FF

0x4001 5000 - 0x4001 53FF

0x4001 4C00 - 0x4001 4FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0800 - 0x4001 0FFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

Reserved

SAI2

Reserved

SAI1

Reserved

TIM11

TIM10

TIM9

EXTI

SYSCFG

SPI4

SPI1

SDIO

Reserved

ADC1 - ADC2 - ADC3

Reserved

USART6

USART1

Reserved

TIM8

TIM1

68/198 DS10693 Rev 10

STM32F446xC/E Memory mapping

Table 12. STM32F446xC/E register boundary addresses (1) (continued)

Bus Boundary address Peripheral

APB1

0x4000 8000- 0x4000 FFFF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

1. The grey color is used for reserved boundary addresses.

Reserved

DAC

PWR

HDMI-CEC

CAN2

CAN1

FMPI2C1

I2C3

I2C2

I2C1

UART5

UART4

USART3

USART2

SPDIFRX

SPI3 / I2S3

TIM14

TIM13

TIM12

TIM7

TIM6

TIM5

SPI2 / I2S2

Reserved

IWDG

WWDG

RTC & BKP Registers

Reserved

TIM4

TIM3

TIM2

DS10693 Rev 10 69/198

Electrical characteristics STM32F446xC/E

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.7 V  tested.

= 3.3 V (for the

 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 16

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 17 .

Figure 16. Pin loading conditions Figure 17. Pin input voltage

MCU pin

C = 50 pF VIN

70/198

MS19011V2

DS10693 Rev 10

MS19010V2

STM32F446xC/E

6.1.6 Power supply scheme

BAT

1.65 to 3.6V

BAT

Figure 18. Power supply scheme

Power switch

Electrical characteristics

Backup circuitry

(OSC32K,RTC,

Wakeup logic

Backup registers, backup RAM)

OUT

GPIOs

12 × 100 nF

+ 1 × 4.7 μF

2 × 2.2 μF

CAP_1

CAP_2

1/2/...11/12

Voltage regulator

Logic

Kernel logic

(CPU, digital

& RAM)

DDUSB

(2)

100 nF

+ 1 μF

BYPASS_REG

DDUSB

(2)

Flash memory

OTG

PHY

Reset controller

REF

PDR_ON

DDA

REF+

100 nF

+ 1 μF

100 nF

+ 1 μF

REF-

ADC

Analog:

RCs,

PLL,..

SSA

MSv33072V1

1. V

DDA and V

SSA

must be connected to V

DD and V

, respectively.

2. V

DDUSB

is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and associated DP/DM GPIOs. Its value is independent from the V

and V

DDA

values, but must be the last supply to be provided and the first to disappear. If V

is different from V

PHY is used, the second OTG PHY GPIOs (DP/DM) are still supplied at

DDUSB

and only one on-chip OTG

VDDUSB

(3.3V).

3. V

DDUSB

is available only on WLCSP81, UFBGA144 and LQFP144 packages. For packages where V pin is not available, it is internally connected to V

DDUSB

4. V

CAP_2

pad is not available on LQFP64.

Caution: Each power supply pair (e.g. V

, V

DDA

SSA

) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

DS10693 Rev 10 71/198

171

Electrical characteristics STM32F446xC/E

Figure 19. Current consumption measurement scheme

IDD_VBAT

VBAT

6.2

IDD

VDD

VDDA

VDDUSB

MSv36557V1

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 13 ,

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47

Qualification Standard, extended mission profiles are available on demand.

Symbol

Table 13. Voltage characteristics

Ratings Min Max Unit

–V

External main supply voltage (including V

DDA

, V

DD,

DDUSB and V

BAT

)

(1)

Input voltage on FT & FTf pins

(2)

–0.3

4.0

Input voltage on TTa pins

–0.3

+4.0

–0.3

4.0

Input voltage on any other pin

Input voltage on BOOT0 pin

–0.3

4.0

9.0

|  V

DDx

| Variations between different V

power pins

SSX

 V

| Variations between all the different ground pins

ESD(HBM)

Electrostatic discharge voltage (human body model)

see Section 6.3.15

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed

injected current.

V mV

72/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 14. Current characteristics

Ratings Max.

Unit

 I

VDD

 I

VSS

 IV

DDUSB

VDD

VSS

Total current into sum of all V

DD power lines (source)

(1)

Total current out of sum of all V

SS ground lines (sink)

Total current into V

DDUSB power line (source)

Maximum current into each V

DD power pin (source)

Maximum current out of each V

ground pin (sink)

Total output current sourced by sum of all I/Os and control pins

Output current sunk by any I/O and control pin

240

- 240

100

- 100

Output current sourced by any I/Os and control pin

Total output current sunk by sum of all I/Os and control pins

(2)

- 25

120 mA

 I

INJ(PIN)

Total output current sunk by sum of all USB I/Os

Injected current on FT, FTf, RST and B pins

never be exceeded. Refer to

-120

–5/+0

(3)

±5

(4)

 I

INJ(PIN)

Injected current on TTa pins

Total injected current (sum of all I/O and control pins)

(5)

±25

1. All main power (V permitted range.

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A positive injection is induced by V

Table 13

DDA

while a negative injection is induced by V

for the maximum allowed input voltage value.

. IINJ(PIN) must

5. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the positive and

Symbol

STG

Table 15. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

125

Unit

°C

DS10693 Rev 10 73/198

171

Electrical characteristics STM32F446xC/E

6.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Parameter

Table 16. General operating conditions

Conditions

(1)

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Power Scale 3 (VOS[1:0] bits in

PWR_CR register = 0x01),

Regulator ON, over-drive OFF

Power Scale 2 (VOS[1:0] bits in PWR_CR register = 0x10),

Regulator ON

Overdrive

OFF

Overdrive

Power Scale 1 (VOS[1:0] bits in PWR_CR register= 0x11),

Regulator ON

Overdrive

OFF

Overdrive

Over-drive OFF

Over-drive ON

Over-drive OFF

Over-drive ON

Min Typ

Max Unit

120

144

168

MHz

180

74/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 16. General operating conditions (continued)

Parameter Conditions (1) Min Typ Max

DDA

(3)(4)

Standard operating voltage

Analog operating voltage

(ADC limited to 1.2 M samples)

Analog operating voltage

(ADC limited to 2.4 M samples)

Backup operating voltage V

BAT

VDDUSB

USB supply voltage (supply voltage for PA11,PA12, PB14 and PB15 pins)

Must be the same potential as V

USB not used

USB used

(5)

Regulator ON: 1.2 V internal voltage on V

CAP_1

FT pins

(7)

CAP_1

CAP_2

/V pins

CAP_2 pins

Regulator OFF: 1.2 V external voltage must be supplied from external regulator on

(6)

Input voltage on RST, FTf and

Input voltage on TTa pins

Input voltage on BOOT0 pin

Power Scale 3 ((VOS[1:0] bits in

PWR_CR register = 0x01), 120 MHz

HCLK max frequency

Power Scale 2 ((VOS[1:0] bits in

PWR_CR register = 0x10), 144 MHz

HCLK max frequency with over-drive

OFF or 168 MHz with over-drive ON

Power Scale 1 ((VOS[1:0] bits in

PWR_CR register = 0x11), 168 MHz

HCLK max frequency with over-drive

OFF or 180 MHz with over-drive ON

Max frequency 120 MHz

Max frequency 144 MHz

Max frequency 168 MHz

2 V  V

 3.6 V

1.7

 V  V

 2 V

LQFP64

Power dissipation at T

A for suffix 6 or T

A suffix 7

(8)

= 85 °C

= 105 °C for

WLCSP81

LQFP100

LQFP 144

UFBGA144 (7x7)

UFBGA144(10x10)

Ambient temperature for 6 suffix version

Maximum power dissipation

Low power dissipation

(9)

Ambient temperature for 7 suffix version

Maximum power dissipation

Low power dissipation

(9)

Junction temperature range

6 suffix version

7 suffix version

1.7

(2)

1.7

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:

2.4

1.65

1.7

1.08 1.14

1.20 1.26

1.26 1.32

3.6

2.4

3.6

1.20

1.32

1.40

1.10 1.14

1.20 1.26

1.26 1.32

–0.3

1.20

1.32

1.38

5.5

5.2

DDA

+0.3

345

–40 -

417

476

606

392

417

–40 -

105

125

105

125

Unit

V mW

°C

DS10693 Rev 10 75/198

171

Electrical characteristics STM32F446xC/E

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.

2. V

DDA

Internal reset OFF ).

3. When the ADC is used, refer to

Table 74: ADC characteristics .

4. If V

REF+

pin is present, it must respect the following condition: V

DDA

-V

REF+

< 1.2 V.

5. It is recommended to power V

DDA

DD and V from the same source. A maximum difference of 300 mV between V

DD and

6. The over-drive mode is not supported when the internal regulator is OFF.

7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

8. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

9. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

Jmax

Operating power supply range

Table 17. Limitations depending on the operating power supply range

ADC operation

Maximum Flash memory access frequency with no wait states

Flashmax

)

Maximum HCLK frequency vs Flash memory wait states

(1)(2)

I/O operation

Possible Flash memory operations

=1.7 to

2.1 V

(3)

= 2.1 to

2.4 V

= 2.4 to

2.7 V

= 2.7 to

3.6 V

(5)

Conversion time up to 1.2 Msps

Conversion time up to 2.4 Msps

20 MHz

(4)

22 MHz

24 MHz

30 MHz

168 MHz with 8 wait states and over-drive

OFF

– No I/O compensation

180 MHz with 8 wait states and over-drive

– No I/O compensation

180 MHz with 7 wait states and over-drive

– I/O compensation works

180 MHz with 5 wait states and over-drive

– I/O compensation works

8-bit erase and program operations only

16-bit erase and program operations

32-bit erase and program operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator enables to achieve a performance equivalent to 0 wait state program execution.

3. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

Section 3.16.2:

Internal reset OFF

4. Prefetch is not available.

5. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins are degraded between 2.7 and 3 V.

6.3.2 VCAP_1 / VCAP_2 external capacitor

Stabilization for the main regulator is achieved by connecting external capacitor C

EXT

VCAP_1 and VCAP_2 pins. For packages supporting only 1 V capacitors are replaced by a single capacitor. C

EXT

CAP

pin, the two C

is specified in

Table 18 .

EXT

to the

76/198 DS10693 Rev 10

STM32F446xC/E

Figure 20. External capacitor C

EXT

Electrical characteristics

ESR

Leak

MS19044V2

1. Legend: ESR is the equivalent series resistance.

Symbol

Table 18. VCAP_1 / VCAP_2 operating conditions

(1)

Parameter Conditions

EXT

ESR

Capacitance of external capacitor

ESR of external capacitor

2.2 µF

< 2 Ω

EXT

ESR

Capacitance of external capacitor with a single V

CAP

pin available

ESR of external capacitor with a single V

CAP

pin available

4.7 µF

< 1

1. When bypassing the voltage regulator, the two 2.2 µF V replaced by two 100 nF decoupling capacitors.

CAP

capacitors are not required and can be

Ω

Subject to general operating conditions for T

Table 19. Operating conditions at power-up/power-down (regulator ON)

Symbol Parameter Min Max t

VDD

rise time rate

fall time rate



Subject to general operating conditions for T

Table 20. Operating conditions at power-up / power-down (regulator OFF) (1)

Symbol Parameter Conditions Min Max Unit t t

VDD

VCAP

rise time rate

fall time rate

Power-up

Power-down

CAP_1

and V

CAP_2 rise time rate Power-up

CAP_1

and V

CAP_2

fall time rate Power-down

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V

1.08 V.

drops below



µs/V

DS10693 Rev 10 77/198

171

Electrical characteristics

6.3.5 Reset and power control block characteristics

STM32F446xC/E

The parameters given in

Table 21 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Symbol

Table 21. reset and power control block characteristics

Parameter Conditions

PVD

PVDhyst

POR/PDR

PDRhyst

BOR1

BOR2

BOR3

Programmable voltage detector level selection

PVD hysteresis

Power-on/power-down reset threshold

PDR hysteresis

Brownout level 1 threshold

Brownout level 2 threshold

Brownout level 3 threshold

BORhyst

BOR hysteresis

POR reset temporization -

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Min

2.09

2.14

2.19

1.98

2.04

2.08

2.23

2.30

2.37

2.13

2.19

2.25

2.39

2.45

2.51

2.29

2.35

2.39

2.54

2.60

2.65

2.44

2.51

2.56

2.70

2.76

2.82

2.59

2.66

2.71

2.86

2.93

2.99

2.65

2.84

3.02

2.96

3.03

3.10

2.85

2.93

2.99

3.07

3.14

3.21

2.95

3.03

3.09

100 -

1.60

1.68

1.76

1.64

1.72

1.80

40 -

2.13

2.19

2.24

2.23

2.29

2.33

2.44

2.50

2.56

2.53

2.59

2.63

2.75

2.83

2.88

2.85

2.92

2.97

100 -

0.5

Typ

1.5

Max Unit

3.0

V mV

V ms

78/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 21. reset and power control block characteristics (continued)

Parameter Conditions Min Typ Max Unit

RUSH

RUSH

The over-drive switching characteristics are given in Table 22

InRush current on voltage regulator poweron (POR or wakeup from

Standby)

InRush energy on voltage regulator poweron (POR or wakeup from

Standby)

= 1.7 V, T

RUSH

= 105 °C,

= 171 mA for 31 µs

160

200

5.4

1. Guaranteed based on test during characterization.

2. The reset temporization is measured from the power-on (POR reset or wakeup from V when first instruction is read by the user application code.

BAT

) to the instant mA

µC

6.3.7

When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up.

. They are sbject to general operating conditions for T

Symbol

Table 22. Over-drive switching characteristics

(1)

Parameter Conditions

Tod_swen

Tod_swdis

Over_drive switch enable time

HSI

HSE max for 4 MHz and min for 26 MHz

External HSE

50 MHz

HSI

Over_drive switch disable time

HSE max for 4 MHz and min for 26 MHz.

External HSE

50 MHz

1. Guaranteed based on test during characterization.

Min

Typ

Max

100

Unit

µs

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 19

All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

DS10693 Rev 10 79/198

171

Electrical characteristics STM32F446xC/E

Typical and maximum current consumption

The MCU is placed under the following conditions:

 All I/O pins are in input mode with a static value at V

or V

(no load).

 All peripherals are disabled except if it is explicitly mentioned.

 The Flash memory access time is adjusted both to f

HCLK

(see Table 17

frequency and V

DD range

 Regulator ON

 The voltage scaling and over-drive mode are adjusted to f

HCLK

frequency as follows:

– Scale 3 for f

HCLK

 

120 MHz

– Scale 2 for 120 MHz < f

HCLK

 144 MHz

– Scale 1 for 144 MHz < f

HCLK

 180 MHz. The over-drive is only ON at 180 MHz.

 The system clock is HCLK, f

PCLK1

= f

HCLK

/4, and f

PCLK2

= f

HCLK

/2.

 External clock frequency is 8 MHz and PLL is ON when f

HCLK

is higher than 16 MHz.

 Flash is enabled except if explicitly mentioned as disable.

 The maximum values are obtained for V

= 3.6 V and a maximum ambient temperature (T

), and the typical values for T otherwise specified.

= 25 °C and V

= 3.3 V unless

80/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 23. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM (1)

Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz) Typ

25 °C

85 °C

105 °C

Unit

Supply current in

RUN mode

External clock,

PLL ON,  all peripherals enabled enabled

(3)(4)

HSI, PLL OFF, all peripherals



180

168

150

144

(6)

120

2.3

1.8

83.0

(5)

71.0

63.6

58.4

44.9

35.3

25.5

16.2

14.41

11.4

9.5

8.3

7.7

42.0

35.5

31.5

100.0

95.3

85.4

78.8

62.1

50.7

39.2

28.1

26.17

23.1

20.3

18.9

18.1

59.0

51.4

47.8

110.0

100.8

91.2

73.2

60.0

46.8

36.0

32.4

25.2

101.0

22.5

21.1

20.5

75.0

55.7

51.9

External clock,

PLL ON,  all peripherals

180

168

150

144

(6)

120

29.2

23.3

19.0

44.7

36.8

31.8

48.6

40.4

35.1

14.7

10.7

9.96

8.7

8.1

26.9

22.1

21.24

18.9

17.8

29.9

24.9

24.02

21.9

20.9

HSI, PLL OFF,  all peripherals

1.7

1.4

7.64

7.4

17.23

16.94

20.32

20.03

1. Code and data processing running from SRAM1 using boot pins.

2. Guaranteed based on test during characterization.

3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

5. Tested in production.

6. Overdrive OFF

DS10693 Rev 10 81/198

171

Electrical characteristics STM32F446xC/E

Table 24. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled with prefetch) or RAM (1)

Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz) Typ

25 °C

85 °C

105 °C

Unit

External clock,

PLL ON, enabled

 all peripherals

(3)(4)

180

168

(5)

150

144

120

93.0

85.1

79.6

73.5

59.3

47.23

33.7

20.8

115.0

111.2

104.8

97.3

79.7

65.50

49.5

34.0

125.0

117.7

111.2

103.3

84.7

70.10

53.4

37.4

HSI, PLL OFF, all peripherals

enabled

(3)(4)



3.0

2.1

18.4

13.8

10.8

9.1

8.1

31.2

25.0

21.1

18.9

17.8

34.5

28.3

24.2

22.0

20.9

Supply current in

Run mode 46

55.0

49.6

48.2

75.0

67.5

65.8

86.0

72.6

70.8

External clock,

PLL ON,  all peripherals disabled

180

168

150

144

120

43.6

37.3

30.7

61.9

53.7

46.0

66.8

58.0

50.0

22.8

14.9

13.55

11.1

9.5

36.4

27.1

25.40

21.8

19.4

40.1

30.2

28.54

25.0

22.5

HSI, PLL OFF,  all peripherals disabled

2.4

1.8

8.34

7.77

18.10

17.39

21.17

20.50

1. Code and data processing running from SRAM1 using boot pins.

2. Guaranteed based on test during characterization.

3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

5. Overdrive OFF

82/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ

25 °C

85 °C

105 °C

Unit

External clock,

PLL ON, enabled

 all peripherals

(2)(3)

180

168

(4)

150

144

120

89.0

80.2

74.9

69.3

56.3

45.32

33.1

20.8

110.0

105.7

99.5

92.4

76.1

63.19

48.7

34.0

120.0

112.0

105.6

98.1

81.1

67.63

52.6

37.4

3.0

2.1

18.4

13.8

10.8

9.1

8.1

31.2

25.0

21.1

19.0

17.9

34.5

28.2

24.2

22.0

20.9

Supply current in

RUN mode

External clock,

PLL ON,  all peripherals

(2)(3)

47.0

43.2

41.8

69.0

61.9

60.3

79.0

67.1

65.4

180

168

150

144

120

39.3

34.3

28.8

56.9

50.2

43.6

61.6

54.4

47.5

HSI, PLL OFF, all peripherals



22.0

14.8

13.51

11.1

9.5

35.6

27.0

25.36

21.8

19.4

39.2

30.1

28.47

24.9

22.5

HSI, PLL OFF,  all peripherals

2.3

1.8

8.35

7.78

18.12

17.42

21.17

20.51

1. Guaranteed based on test during characterization unless otherwise specified.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

4. Overdrive OFF

DS10693 Rev 10 83/198

171

Electrical characteristics STM32F446xC/E

Table 26. Typical and maximum current consumption in Sleep mode (1)

Max

Symbol Parameter Conditions fHCLK

(MHz)

Typ

25 °C

85 °C

105 °C

IDD

Supply  current in 

Sleep mode

All peripherals enabled

External clock, 

PLL ON,

Flash memory on

HSI, PLL off, Flash memory on

180

168

(2)

150

144

120

59.00

53.94

49.26

45.37

35.70

29.17

22.41

16.03

14.92

13.10

12.31

11.63

11.23

29.3

22.8

16.3

10.1

51.2

46.8

42.2

38.6

9.0

6.5

5.2

4.5

4.1

77.25

66.48

60.84

55.47

42.49

34.78

27.12

19.72

18.41

15.1

13.5

12.5

12.0

102.00

79.40

73.41

66.96

51.46

43.12

34.83

26.86

25.38

22.3

20.4

19.3

18.8

Unit mA

84/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 26. Typical and maximum current consumption in Sleep mode (1) (continued)

Max

Symbol Parameter Conditions fHCLK

(MHz)

Typ

25 °C

85 °C

105 °C

Unit

IDD

Supply  current in 

Sleep mode

Flash memory on

External clock, 

PLL on,  all peripherals disabled

Flash in

Deep power down mode

Flash in

Stop mode

180

168

150

144

120

180

168

150

144

120

180

168

150

144

120

3.8

2.8

2.0

1.8

6.7

6.1

4.7

3.8

2.8

2.0

1.8

8.3

7.3

4.23

8.3

7.3

6.7

6.1

4.7

11.36

10.20

9.53

8.90

7.35

6.39

5.28

4.43

11.60

11.08

9.64

8.80

7.74

6.89

6.70

8.80

7.74

6.89

6.70

13.44

12.25

10.12

13.44

12.25

11.60

11.08

9.64

17.59

16.19

15.59

14.87

13.24

12.40

11.17

10.31

24.27

23.25

20.95

19.77

18.69

17.66

17.43

19.77

18.69

17.66

17.43

30.72

25.16

12.85

30.72

25.16

24.27

23.25

20.95

16.5

15.3

14.1

13.1

28.2

22.0

21.1

19.7

27.84

26.28

23.72

22.57

21.32

20.40

20.17

22.57

21.32

20.40

20.17

37.20

28.80

19.30

37.20

28.80

27.84

26.28

23.72

23.3

21.9

20.7

19.6

51.6

31.8

30.9

28.4

DS10693 Rev 10 85/198

171

Electrical characteristics STM32F446xC/E

Table 26. Typical and maximum current consumption in Sleep mode (1) (continued)

Max

Symbol Parameter Conditions fHCLK

(MHz)

Typ

25 °C

85 °C

105 °C

Unit

IDD

Supply  current in 

Sleep mode

Flash memory on

HSI, 

PLL off,  all  peripherals  disabled

Flash memory in Deep power down mode

3.89

2.45

1.69

1.28

1.0

0.9

Flash in

Stop mode

1.0

0.9

1. Guaranteed based on test during characterization unless otherwise specified.

2. Overdrive OFF

4.93

3.29

2.56

2.22

6.65

6.93

6.90

6.88

6.7

6.9

11.72

11.66

11.60

11.57

16.54

16.48

16.43

16.41

16.5

16.4

18.54

18.46

18.40

18.37

19.50

19.45

19.39

19.37

19.5

19.4

86/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 27. Typical and maximum current consumptions in Stop mode

Max

Typ

Parameter Conditions

= 3.6 V

25 °C

(1)

85 °C

105 °C

(1)

Unit

Supply current in

Stop mode with voltage regulator in main regulator mode

DD_STOP_NM

(normal mode)

Supply current in

Stop mode with voltage regulator in

Low power regulator mode

Flash memory in Stop mode, all oscillators OFF, no independent watchdog

Flash memory in Deep power down mode, all oscillators OFF, no independent watchdog

Flash memory in Stop mode, all oscillators OFF, no independent watchdog

Flash memory in Deep power down mode, all oscillators OFF, no independent watchdog

DD_STOP_UD

(underdrive mode)

Supply current in

Stop mode with voltage regulator in main regulator and under-drive mode

Supply current in

Stop mode with voltage regulator in

Low power regulator and under-drive mode

Flash memory in Deep power down mode, main regulator in under-drive mode, all oscillators

OFF, no independent watchdog

Flash memory in Deep power down mode, Low power regulator in under-drive mode, all oscillators OFF, no independent watchdog

1. Data based on characterization, tested in production.

0.234

0.205

0.15

0.121

0.119

0.055

1.2

0.95

0.9

0.4

0.35

9.5

8.5

5 mA

DS10693 Rev 10 87/198

171

Electrical characteristics STM32F446xC/E

Table 28. Typical and maximum current consumptions in Standby mode

Typ

(1)

Max

(2)

Symbol Parameter Conditions

= 25 °C

25 °C

85 °C

105 °C

1.7 V

2.4 V

3.3 V

Backup SRAM ON, and LSE oscillator in low power mode

Backup SRAM OFF, RTC ON and LSE oscillator in low power mode

DD_STBY

Supply current in

Standby mode

Backup SRAM ON, RTC ON and LSE oscillator in high drive mode

Backup SRAM OFF, RTC ON and LSE oscillator in high drive mode

Backup SRAM ON, RTC and

LSE OFF

Backup SRAM OFF, RTC and LSE OFF

2.43

1.81

3.32

2.57

2.03

1.28

3.44

2.81

4.33

3.59

2.73

1.97

4.12

3.33

4.95

4.16

3.5

2.03

(3)

1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.

2. Guaranteed based on test during characterization unless otherwise specified.

3. Tested in production.

= 3.3 V

When the regulator is OFF, V12 is provided externally as described in Table 16:

Unit

µA

88/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 29. Typical and maximum current consumptions in V

BAT

mode

Typ Max

(2)

85 °C

105 °C

= 25 °C

Symbol Parameter Conditions

(1)

BAT

1.7 V

BAT

2.4 V

BAT

3.3 V

DD_VBAT

Backup domain supply current

Backup SRAM ON, RTC ON and LSE oscillator in low power mode

Backup SRAM OFF, RTC ON and LSE oscillator in low power mode

Backup SRAM ON, RTC ON and LSE oscillator in high drive mode

Backup SRAM OFF, RTC ON and LSE oscillator in high drive mode

Backup SRAM ON, RTC and

LSE OFF

Backup SRAM OFF, RTC and

LSE OFF

1.46

0.72

2.24

1.50

0.74

0.05

1.62

0.85

2.40

1.64

0.75

0.05

1.83

1.00

2.64

1.86

0.78

0.05

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C

of 6 pF for typical values.

2. Guaranteed based on test during characterization.

BAT

= 3.6 V

Unit

µA

Figure 21. Typical V

BAT

current consumption

(RTC ON/backup RAM OFF and LSE in low power mode)

DS10693 Rev 10 89/198

171

Electrical characteristics STM32F446xC/E

Figure 22. Typical V

BAT

current consumption

(RTC ON/backup RAM OFF and LSE in high drive mode)

Additional current consumption

The MCU is placed under the following conditions:

 All I/O pins are configured in analog mode.

 The Flash memory access time is adjusted to fHCLK frequency.

 The voltage scaling is adjusted to fHCLK frequency as follows:

– Scale 3 for f

HCLK

≤ 120 MHz,

– Scale 2 for 120 MHz < f

HCLK

≤ 144 MHz

– Scale 1 for 144 MHz < f

HCLK

≤ 180 MHz. The over-drive is only ON at 180 MHz.

 The system clock is HCLK, f

PCLK1

= f

 HSE crystal clock frequency is 8 MHz.

HCLK

/4, and f

PCLK2

= f

HCLK

/2.

 Flash is enabled except if explicitly mentioned as disable.



General operating conditions

 T

= 25 °C.

90/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 30. Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON

(ART accelerator enabled except prefetch), V

= 1.7 V (1)

Max

Symbol Parameter Conditions f

HCLK

(MHz) Typ

25 °C

85 °C

105 °C

Unit

Supply current in

Run mode from

supply

All peripherals enabled

All peripherals disabled

144

120

168

150

144

120

168

150

65.11

58.31

53.14

39.58

29.99

20.37

11.37

9.65

29.74

25.81

24.57

17.69

13.58

9.41

5.44

4.73

70.0

62.8

57.1

47.2

34.70

25.2

12.9

10.9

32.43

29.12

26.61

22.09

15.92

11.05

6.64

5.72

79.7

73.4

69.9

60.7

45.23

35.2

28.4

17.8

42.4

39.4

36.0

32.9

30.0

24.4

15.0

12.57

1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.

41.9

40.8

36.5

30.2

22.0

19.06

90.0

79.9

75.3

71.4

49.34

38.2

33.2

24.3

48.5

43.8

DS10693 Rev 10 91/198

171

Electrical characteristics STM32F446xC/E

Table 31. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch) (1)

Symbol Parameter Conditions f

HCLK

(MHz)

= 3.3 V V

= 1.7 V

Unit

168

DD12

61.72

1.6

DD12

60.15

1.5

DD12

/ I

Supply current in

Run mode from

and V

DD supply

All peripherals enabled

All peripherals disabled

27.38

23.37

21.73

14.74

10.30

5.64

4.80

55.46

50.94

40.66

28.18

20.05

11.26

9.56

30.06

1.5

1.3

1.2

1.0

0.9

0.8

1.0

0.9

0.8

1.6

1.5

1.3

1.1

28.67

25.51

19.06

14.83

10.16

5.41

4.599

51.69

51.45

38.94

29.48

19.23

10.41

8.83

31.44

150

144

120

168

150

144

120

90 mA

1.4

1.3

1.2

1.0

0.8

0.7

0.6

0.8

0.7

0.6

1.5

1.4

1.3

1.2

1.0

1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.

92/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 32. Typical current consumption in Sleep mode, regulator ON, V

= 1.7 V (1)

Max

Symbol Parameter Conditions f

HCLK

(MHz) Typ

25 °C

85 °C

105 °C

Unit

Supply current in

Sleep mode from

supply

All peripherals enabled, Flash memory on

All peripherals disabled, Flash memory on

168

150

144

120

168

150

144

120

43.7

39.2

35.7

26.5

20.0

13.6

7.4

6.3

7.3

6.6

6.0

4.6

3.6

2.6

1.8

1.6

47.5

42.7

38.8

28.6

21.91

15.2

8.5

7.5

8.6

7.94

7.3

5.5

4.6

3.4

2.7

2.49

66.5

60.7

55.3

41.8

33.85

25.8

18.4

16.9

21.2

20.4

18.6

14.9

13.6

12.5

11.3

11.09

1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.

31.9

31.0

28.5

23.4

22.1

20.8

19.7

19.42

79.3

73.3

66.9

51.6

43.20

34.9

27.0

25.5

DS10693 Rev 10 93/198

171

Electrical characteristics STM32F446xC/E

Symbol

DD12

Table 33. Typical current consumption in Sleep mode, regulator OFF (1)

= 3.3 V V

= 1.7 V

Parameter Conditions f

HCLK

(MHz)

180

DD12

47.605

1.2

DD12

Supply current in Sleep mode from V

and

supply

All peripherals enabled

All peripherals disabled

0.8

0.7

1.2

0.9

0.8

0.7

1.0

0.9

3.78

2.66

1.65

1.45

8.71

7.00

6.88

6.29

4.87

44.35

40.58

35.68

27.30

20.69

13.88

7.66

6.49

180

168

150

144

120

168

150

144

120

3.96

2.80

1.74

1.52

8.42

7.61

6.99

5.95

41.53

39.96

34.60

29.11

19.78

13.36

7.85

6.66

0.6

0.5

0.8

0.7

0.6

0.5

0.8

0.7

Unit

1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 56: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

94/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 35

), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

= V

 f

 C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

Symbol

DDIO

Table 34. Switching output I/O current consumption (1)

Parameter Conditions

I/O toggling frequency (fsw)

Typ Unit

I/O switching current

= 3.3 V

C= C

INT

(2)

= 3.3 V

EXT

= 0 pF

C = C

INT

+ C

EXT

+ C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz mA

0.1

0.4

1.23

2.43

2.93

3.86

4.07

1.1

1.3

1.8

1.9

0.0

0.2

0.6

DS10693 Rev 10 95/198

171

Electrical characteristics STM32F446xC/E

Symbol

Table 34. Switching output I/O current consumption (1) (continued)

Parameter Conditions

I/O toggling frequency (fsw)

Typ Unit

DDIO

I/O switching current

= 3.3 V

EXT

C = C

= 10 pF

C = C

INT

+ C

EXT

= 3.3 V

= 22 pF

INT

+ C

= 3.3 V

EXT

C = C

= 33 pF

INT

EXT

+ C

+ Cext + C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

2 MHz

8 MHz

25 MHz

50 MHz

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

1. C

is the PCB board capacitance including the pad pin. C

= 7 pF (estimated value).

2. This test is performed by cutting the LQFP144 package pin (pad removal).

0.26

1.01

3.14

6.39

10.68

0.33

1.29

4.23

11.02

0.18

0.67

2.09

3.6

4.5

7.8

9.8

On-chip peripheral current consumption

The MCU is placed under the following conditions:

 At startup, all I/O pins are in analog input configuration.

 All peripherals are disabled unless otherwise mentioned.

 HCLK is the system clock. f

PCLK1

= f

HCLK

/ 4, and f

PCLK2

= f

HCLK

/ 2.

The given value is calculated by measuring the difference of current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

– f

HCLK f

HCLK

= 180 MHz (Scale1 + over-drive ON), f

= 120 MHz (Scale 3)"

HCLK

= 144 MHz (Scale 2),

 Ambient operating temperature is 25 °C and V

= 3.3 V.

96/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

AHB1

AHB2

AHB3

Peripheral

Table 35. Peripheral current consumption

(typ.)

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

CRC

BKPSRAM

DMA1

(1)

DMA2 (1)

OTG_HS+ULPI

DCMI

OTGFS

FMC

QSPI

Scale 1 +

OverDrive

0.53

0.76

2.39N + 4.13

2.39N + 4.45

45.45

3.74

30.04

16.15

16.78

2.39

2.31

2.36

2.13

2.29

2.33

2.34

Scale 2

0.51

0.72

2.23N+3.56

2.19N+3.72

42.08

3.42

27.88

15.01

15.60

2.19

2.14

2.19

1.98

2.14

2.13

2.17

2.19

Scale 3

0.46

0.65

1.97N+3.51

2.00N+3.66

37.28

3.01

24.69

13.33

13.84

1.93

1.91

1.94

1.75

1.89

1.93

1.94

Unit

µA/MHz

DS10693 Rev 10 97/198

171

Electrical characteristics

APB1

Table 35. Peripheral current consumption (continued)

(typ.)

Peripheral

Scale 1 +

OverDrive

Scale 2 Scale 3

5.51

6.58

5.91

0.71

2.96

4.22

4.13

4.04

3.98

3.91

3.76

5.09

1.07

1.89

1.93

6.91

4.20

18.18

14.49

15.18

16.91

2.69

2.56

7.07

4.96

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

WWDG

SPI2

(2)

SPI3

The wakeup times given in Table 36

SPDIFRX

USART2

USART3

UART4

UART5

I2C1

I2C2

I2C3

FMPI2C1

CAN1

CAN2

CEC

DAC

5.19

6.14

5.56

0.69

2.72

3.94

3.89

3.78

3.69

3.61

3.53

4.72

1.00

1.78

1.81

6.44

3.83

16.92

13.47

14.11

15.69

2.47

2.44

6.56

4.64

4.57

5.43

4.90

0.60

2.40

3.50

3.40

3.33

3.17

3.13

4.27

0.93

1.57

1.67

5.80

3.40

15.07

12.00

12.50

14.07

2.20

2.17

5.83

4.07

STM32F446xC/E

Unit

µA/MHz

98/198 DS10693 Rev 10

STM32F446xC/E

6.3.8

Electrical characteristics

Table 35. Peripheral current consumption (continued)

(typ.)

Peripheral

Scale 1 +

OverDrive

Scale 2 Scale 3

Unit

APB2

TIM1

TIM8

USART1

USART6

ADC1

ADC2

ADC3

SDIO

SPI1

SPI4

SYSCFG

TIM9

TIM10

TIM11

SAI1

SAI2

Bus Matrix

17.51

18.40

4.53

4.69

4.70

4.66

9.06

1.97

1.88

1.51

8.17

5.07

5.37

3.89

3.74

8.15

16.28

17.10

4.21

4.35

4.31

8.38

1.89

1.75

1.40

7.64

4.75

5.06

3.64

3.49

8.10

14.43

15.22

3.72

3.85

3.87

3.82

7.47

1.67

1.57

1.23

6.77

4.22

4.50

3.17

3.10

7.13

µA/MHz

1. N = Number of strean enable (1..8)

2. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.

Wakeup time from low-power modes

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

 For Stop or Sleep modes: the wakeup event is WFE.

 WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V

= 3.3 V.

DS10693 Rev 10 99/198

171

Electrical characteristics STM32F446xC/E

Symbol

Table 36. Low-power mode wakeup timings

Parameter Conditions t

WUSLEEP

(2)

Wakeup from Sleep -

WUSLEEPFDSM

Wakeup from Sleep with Flash memory in

Deep power down mode

Main regulator is ON

Typ

(1)

33.5

12.8

Max

(1)

Unit

CPU clock cycle

Main regulator is ON and Flash memory in Deep power down mode

104.9

115 t

WUSTOP

external clock signal has to respect the Table 56: I/O static characteristics . However, the

Wakeup from Stop mode with MR/LP regulator in normal mode

Low power regulator is ON 20.6

Low power regulator is ON and

Flash memory in Deep power down mode

112.8

120 t t

Wakeup from Stop mode with MR/LP regulator in Under-drive mode

Main regulator in under-drive mode

(Flash memory in Deep powerdown mode)

Low power regulator in under-drive mode

(Flash memory in Deep powerdown mode)

Wakeup from Standby mode

110

114.4

325

140

128

400

1. Guaranteed based on test during characterization.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

3. t

WUSTDBY maximum value is given at –40 °C.

µ s

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

The characteristics given in

Table 37 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

external clock signal has to respect the Table 56: I/O static characteristics . However, the

100/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 37. High-speed external user clock characteristics

Parameter f

HSE_ext

External user clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

(1)

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

Conditions

 V



Min

0.7V

Typ

1. Guaranteed by design.

Max Unit

0.3V

±1

MHz

V ns pF

µA

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

The characteristics given in

Table 38 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

the requirements of the crystal or resonator (see Figure 25

Symbol

Table 38. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current

1. Guaranteed by design.

Conditions

 V

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

200

±1

Unit kHz

V ns pF

µA

DS10693 Rev 10 101/198

171

Electrical characteristics STM32F446xC/E

Figure 23. High-speed external clock source AC timing diagram

VHSEH

90 %

VHSEL

10 % tr(HSE)

THSE tf(HSE)

External clock source fHSE_ext

OSC_IN tW(HSE)

STM32F tW(HSE) t ai17528

Figure 24. Low-speed external clock source AC timing diagram

VLSEH

VLSEL

90%

10 % tr(LSE)

TLSE tf(LSE) tW(LSE) tW(LSE) t

External clock source fLSE_ext

OSC32_IN

STM32F ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 39 . In

the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

102/198 DS10693 Rev 10

STM32F446xC/E

Note:

Electrical characteristics

Symbol

Table 39. HSE 4-26 MHz oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor -

200

MHz k 

HSE current consumption

=3.3 V,

ESR= 30 Ω ,

=5 pF@25 MHz

=3.3 V,

ESR= 30 Ω ,

=10 pF@25 MHz

450

530 -

µA

ACC

HSE

(2)

HSE accuracy

G m

_crit_max Maximum critical crystal g m t

SU(HSE

(3)

Startup time

Startup

is stabilized

-500

500

ppm mA/V ms

1. Guaranteed by design.

2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications.

3. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is Guaranteed based on test during characterization. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 25. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

CL1

8 MHz resonator

OSC_IN

OSC_OU T

Bias controlled gain fHSE

CL2

REXT(1) STM32F ai17530

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 40 . In

the application, the resonator and the load capacitors have to be placed as close as

DS10693 Rev 10 103/198

171

Electrical characteristics

Note:

STM32F446xC/E possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 40. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

ACC

LSE

(2)

Feedback resistor

LSE current consumption

LSE accuracy -

-500

18.4

500

M 

µA ppm

G m

_crit_max

Maximum critical crystal g m

Startup low-power mode

Startup high-drive mode

0.56

1.5

SU(LSE)

(3) startup time V

is stabilized 2 -

1. Guaranteed by design.

2. This parameter depends on the crystal used in the application. Refer to application note AN2867.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is guaranteed based on test during characterization. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

µA/V s

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 26. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

CL1

32.768 kH z resonator

OSC32_IN

Bias controlled gain

OSC32_OU T

CL2 fLSE

STM32F ai17531

104/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

6.3.10 Internal clock source characteristics

The parameters given in

Table 41 and

Table 42

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in Table 16

High-speed internal (HSI) RC oscillator

Symbol

Table 41. HSI oscillator characteristics (1)

Parameter Conditions

I t f

HSI

ACC

HSI su(HSI)

DD(HSI)

Frequency -

Accuracy of the HSI oscillator

User-trimmed with the RCC_CR register

(2)

= - 40 to 105 °C (3)

= - 10 to 85 °C

= 25 °C

(4)

HSI oscillator startup time

HSI oscillator power consumption

1. V

= 3.3 V, PLL off, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed based on test during characterization.

4. Factory calibrated, parts not soldered.

Min Typ Max Unit

- 8

- 4

- 1

2.2

4.5

MHz

µs

µA

Figure 27. LACC

HSI

versus temperature

0.06

0.04

0.02

-0.02

-0.04

-0.06

-0.08

-40 0 25 5 8 105 125 TA (°C)

Min

Max

Typical

MS30492V1

1. Guaranteed based on test during characterization.

DS10693 Rev 10 105/198

171

Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 42. LSI oscillator characteristics

(1)

Symbol Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed based on test during characterization..

3. Guaranteed by design.

Min

Typ

0.4

Figure 28. ACC

LSI

versus temperature

STM32F446xC/E

Max

0.6

Unit kHz

µs

µA

-10

-20

-30

-40

-45 -35 -25 -15 -5 5 15 25 35

Temperat ure (°C)

45 55 65 75 85 95 105 max avg min

MS19013V1

Symbol f

PLL_IN f

PLL_OUT f

PLL48_OUT f

VCO_OUT

The parameters given in

Table 43 and

Table 44

are derived from tests performed under temperature and V

supply voltage conditions summarized in

Parameter

Table 43. Main PLL characteristics

Conditions Min

PLL input clock

(1)

PLL multiplier output clock

48 MHz PLL multiplier output clock

PLL VCO output -

0.95

(2)

12.5

100

Typ

Max

2.10

180

432

Unit

MHz

106/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 43. Main PLL characteristics (continued)

Parameter Conditions Min Typ Max t

LOCK

PLL lock time

Cycle-to-cycle jitter

VCO frequency = 100 MHz

VCO frequency = 432 MHz

System clock

120 MHz

RMS

Peak to peak

RMS

100



150

200

300

Jitter

(3)

15 -

Period Jitter

Bit Time CAN jitter

Peak to peak

Cycle to cycle at 1 MHz on

1000 samples

 200

330 -

DD(PLL)

(4)

DDA(PLL)

PLL power consumption on V

VCO frequency = 100 MHz

VCO frequency = 432 MHz

PLL power consumption on V

DDA

VCO frequency = 100 MHz

VCO frequency = 432 MHz

0.15

0.45

0.30

0.55

0.40

0.75

0.40

0.85

1. Use the appropriate division factor M (each PLL has its own) to obtain the specified PLL input clock values.

2. Guaranteed by design.

3. The use of PLLs in parallel can degrade the jitter up to +30%.

4. Guaranteed based on test during characterization.

Unit

µs ps mA mA

Symbol f

PLLI2S_IN f

PLLI2S_OUT f

VCO_OUT t

LOCK

Jitter

(3)

Table 44. PLLI2S (audio PLL) characteristics

Parameter

PLLI2S input clock

(1)

PLLI2S multiplier output clock

PLLI2S VCO output

PLLI2S lock time

Master I2S clock jitter

WS I2S clock jitter

Conditions

VCO frequency = 100 MHz

VCO frequency = 432 MHz

Cycle to cycle at

12.288 MHz on

48 KHz period,

N = 432, R = 5

RMS

Peak to peak

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

Cycle to cycle at 48 KHz on 1000 samples

Min

0.95

(2)

100

 280

400

Typ

Max

2.10

216

432

200

300

Unit

MHz

µs

ps ps

DS10693 Rev 10 107/198

171

Electrical characteristics

Symbol

Table 44. PLLI2S (audio PLL) characteristics (continued)

Parameter Conditions Min

DD(PLLI2S)

(4)

DDA(PLLI2S)

PLLI2S power consumption on

DDA

VCO frequency = 100 MHz

VCO frequency = 432 MHz

VCO frequency = 100 MHz

VCO frequency = 432 MHz

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

Guaranteed based on test during characterization.

Typ

STM32F446xC/E

Max

0.40

0.75

0.40

0.85

Unit mA mA f f t

Symbol f

PLLSAI_IN

PLLSAI_OUT

VCO_OUT

LOCK

Parameter

PLLSAI input clock

PLLSAI lock time

(1)

PLLSAI VCO output

Table 45. PLLSAI characteristics

PLLSAI multiplier output clock

Conditions

VCO frequency = 100 MHz

VCO frequency = 432 MHz

Min

0.95

100

(2)

Jitter

(3)

Main SAI clock jitter

FS clock jitter

Cycle to cycle at

12.288 MHz on

48 KHz period,

N = 432, R = 5

RMS

Peak to peak

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

Cycle to cycle at 48 KHz on 1000 samples

DD(PLLSAI)

(4)

DDA(PLLSAI)

interferences (see Table 52: EMI characteristics

PLLSAI power consumption on V

DDA

VCO frequency = 100 MHz

VCO frequency = 432 MHz

VCO frequency = 100 MHz

VCO frequency = 432 MHz

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed based on test during characterization.

Typ

 280

400

0.40

0.75

0.40

0.85

6.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature reduces electromagnetic

). It is available only on the main PLL.

Max

2.10

216

432

200

300

µs

Unit

MHz

MHz ps ps mA mA

108/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol f

Mod md

MODEPER * INCSTEP

1. Guaranteed by design.

Table 46. SSCG parameters constraint

Parameter Min Typ

Modulation frequency

Peak modulation depth

0.25

Max

(1)

15  1

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round f

PLL_IN

 

Mod

  f

PLL_IN and f

Mod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER = 

  

  = 250

Unit

KHz

Equation 2

The increment step (INCSTEP) can be calculated with Equation 2:

INCSTEP = round    2

– 1   md PLLN    100 5  MODEPER   f

VCO_OUT must be expressed in MHz.

With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP = round    2

– 1   2 240    100 5  250   = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

% =   100  5     2

– 1   PLLN 

As a result: md quantized

% =   100  5     2

– 1   240  = 2.002%(peak)

Figure 29

and

Figure 30 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

DS10693 Rev 10 109/198

171

Electrical characteristics STM32F446xC/E

Figure 29. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT) md

F0 md tmode 2xtmode

Time ai17291

Figure 30. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT)

2xmd tmode 2xtmode

Time ai17292b

Flash memory

The characteristics are given at T

= - 40 to 105 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Symbol

Parameter

Table 47. Flash memory characteristics

Conditions Min

Supply current

Write / Erase 8-bit mode, V

= 1.7 V

Write / Erase 16-bit mode, V

= 2.1 V

Write / Erase 32-bit mode, V

= 3.3 V -

Typ

Max Unit

110/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 48. Flash memory programming

Parameter Conditions t t prog

ERASE16KB

Word programming time

Sector (16 KB) erase time

Program/erase parallelism

(PSIZE) = x 8/16/32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32 t

ERASE64KB

Sector (64 KB) erase time

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8 t

ERASE128KB

Sector (128 KB) erase time

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

V t

ME prog

Mass erase time

Programming voltage

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

32-bit program operation

16-bit program operation

8-bit program operation

1. Guaranteed based on test during characterization.

Min

(1)

2.7

2.1

1.7

Typ Max

(1)

Unit

400

300

250

1.3

5.5

100

800

600

500

1200 2400

700 1400

550 1100

2.6

3.6

µs ms ms s s

Symbol

Table 49. Flash memory programming with V

Parameter t prog t

ERASE16KB t

ERASE64KB t

ERASE128KB t

V prog

Double word programming

Sector (16 KB) erase time

Sector (64 KB) erase time

Sector (128 KB) erase time

Mass erase time

Programming voltage

Conditions

 0 to +40 °C

= 3.3 V

= 8.5 V

Min

(1)

2.7

Typ Max

(1)

230

490

875

3.5

100

3.6

Unit

µs ms s

DS10693 Rev 10 111/198

171

Electrical characteristics STM32F446xC/E

Symbol

Table 49. Flash memory programming with V

(continued)

Parameter Conditions t

VPP

(2)

voltage range

Minimum current sunk on the V

Cumulative time during which V

PP is applied

1. Guaranteed by design.

2. V

should only be connected during programming/erasing.

Min (1)

Typ Max (1)

Unit

V mA hour

Symbol

Table 50. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (suffix versions 6)

= –40 to +105 °C (suffix versions 7)

1 kcycle

(2)

at T

= 85 °C

1 kcycle

at T

= 105 °C

10 kcycles

The test results are given in Table 51

at T

= 55 °C

1. Guaranteed based on test during characterization.

2. Cycling performed over the whole temperature range.

Unit

Kcycles

Year

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs.

 Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

 FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset enables resuming normal operation.

. They are based on the EMS levels and classes defined in AN1709 EMC design guide for STM8, STM32 and Legacy MCUs , available on www.st.com

112/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

FESD

EFTB

Table 51. EMS characteristics

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

 3.3 V, LQFP144, 

= +25 °C, f

HCLK

= 168 MHz, conforms to IEC 61000-4-2

 3.3 V, LQFP144, 

= +25 °C, f

HCLK

= 168 MHz, conforms to IEC 61000-4-2

Level/Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. Good EMC performance is highly dependent on the user application and the software in particular. It is therefore recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for the application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

 Corrupted program counter

 Unexpected reset

 Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see AN1015 Software techniques for improving microcontrollers EMC performance , available on www.st.com

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

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Electrical characteristics STM32F446xC/E

EMI

Symbol Parameter

Peak level

Table 52. EMI characteristics

Conditions

= 3.3 V, T

= 25 °C, LQFP144 package, conforming to SAE J1752/3

EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled.

 3.3 V, T

 25 °C, LQFP144 package, conforming to SAE J1752/3

EEMBC, ART ON, all peripheral clocks enabled, clock dithering enabled

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI level

Max vs.

HSE

CPU

]

8/180 MHz

Unit dBµV

dBµV

6.3.15 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol Ratings

Table 53. ESD absolute maximum ratings

Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage

(human body model)

 + 25 °C conforming to ANSI/JEDEC JS-001

ESD(CDM)

Electrostatic discharge voltage

(charge device model)

 + 25 °C conforming to ANSI/ESD STM5.3.1,

LQFP64, LQFP100, WLCSP81 packages

 + 25 °C conforming to ANSI/ESD STM5.3.1,

LQFP144, UFBGA144 (7 x 7), UFBGA144 (10 x 10) packages

1. Guaranteed based on test during characterization.

2000

500

250

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

 A supply overvoltage is applied to each power supply pin

 A current injection is applied to each input, output and configurable I/O pin

114/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

These tests are compliant with EIA/JESD 78A IC latchup standard.

Parameter

Static latch-up class

Table 54. Electrical sensitivities

Conditions

 +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –

5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in Table 55

Symbol

Table 55. I/O current injection susceptibility (1)

Functional susceptibility

Description

Negative injection

Positive injection

–0

INJ

Injected current on BOOT0 pin

Injected current on NRST pin

Injected current on PE2, PE3,PE4, PE5, PE6, PC13, PC14,

PF10, PH0, PH1, NRST, PC0, PC1, PC2, PC3, PG15, PB3,

PB4, PB5, PB6, PB7, PB8, PB9, PE0, PE1

Injected current on any other FT and FTf pins

Injected current on any other pins

1. NA = not applicable .

–0

-5

–5

Unit mA

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

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Electrical characteristics STM32F446xC/E

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 56 are derived from tests

performed under the conditions summarized in Table 16

All I/Os are CMOS and TTL compliant.

Symbol

HYS

I lkg

Parameter

Table 56. I/O static characteristics

FT, FTf, TTa and NRST I/O input low level voltage

Conditions

1.7 V  V

 3.6 V

Min

BOOT0 I/O input low level voltage



1.75 V  V

3.6 V, 



– 40 °C  T



105 °C

1.7 V  V



 3.6 V, 0 °C  T



105 °C

FT, FTf, TTa and NRST I/O input high level voltage

(4)

1.7 V  V

 3.6 V

0.45V

+0.3

(1)

0.7V

(2)

BOOT0 I/O input high level voltage

1.75 V  V

3.6 V, 



– 40 °C  T



105 °C

1.7 V

0 °C



 T



3.6 V,

105 °C

FT, FTf, TTa and NRST I/O input hysteresis

1.7 V  V

 3.6 V

1.75 V  V



3.6 V, –40 °C  T



105 °C

BOOT0 I/O input hysteresis

I/O input leakage current

(3)

1.7 V

0 °C



 T



3.6 V,

105 °C

 V

I/O FT input leakage current

(4)

 5 V

0.17V

+0.7

(1)

Typ Max

10%V

100m

0.35V

–0.04

(1)

0.3V

(2)

0.1V



+0.1

(1)

Unit

µA

116/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol Parameter

Table 56. I/O static characteristics (continued)

Conditions Min Typ Max Unit

Weak pull-up equivalent resistor

(5)

All pins except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

 V

14 k 

Weak pulldown equivalent resistor

(6)

All pins except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

 V

30 40 50

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

7 10 14

(7)

I/O pin capacitance 5 -

1. Guaranteed by design.

2. Tested in production.

3. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to

Table 55: I/O current injection susceptibility

4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to

Table 55: I/O current injection susceptibility

5. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order).

6. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).

7. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed based on test during characterization.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in

Figure 31

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Electrical characteristics STM32F446xC/E

2.52

Figure 31. FT I/O input characteristics

VIL/VIH (V)

2.00

1.92

TTL requirement

VIHmin = 2V

+0.3

1.22

1.19

1.065

Tested in production - CMOS requirement VIHmin = 0.7V

Area not

0.80

0.55

0.51

Tested in production -

CMOS requirement

VILmax = 0.3V

VILmax = 0.8V

-0.04

(V)

1.7

2.0

2.4

2.7

3.3

3.6

MS33746V3

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to  8 mA, and sink or source up to  20 mA (with a relaxed V

) except PC13, PC14 and PC15 which can sink or source up to  3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

. In particular:

 The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

DD,

 I

VDD

(see

Table 14 ).

plus the maximum Run cannot exceed the absolute maximum rating

 The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

 I

VSS

(see Table 14

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in

Table 57 are derived from tests

performed under ambient temperature and V

Table 16 . All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized in

118/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 57. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V  V

 3.6 V

TTL port

(2)

=+ 8mA

2.7 V  V

 3.6 V

–0.4

2.4

0.4

(1)

(3)

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

1.8 V  V

= +20 mA

2.7 V  V

1.7 V  V



3.6 V

= +6 mA

3.6 V

= +4 mA

3.6V

–1.3

(4)

–0.4

(4)

–0.4

(5)

1.3

0.4

(4)

(5)

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 14

. and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 14

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Based on characterization data.

5. Guaranteed by design.

OSPEEDR y[1:0] bit value

(1)

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 32

and

Table 58 , respectively.

Unless otherwise specified, the parameters given in

Table 58 are derived from tests

performed under the ambient temperature and V

DD in

3. The maximum frequency is defined in Figure 32 .

supply voltage conditions summarized

Table 58. I/O AC characteristics

(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

00 f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

≥ 2.7 V -

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 50 to 3.6 V pF, V

= 1.7 V

100

MHz ns

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Electrical characteristics STM32F446xC/E

Table 58. I/O AC characteristics (1)(2) (continued)

OSPEEDR y[1:0] bit value

(1)

Symbol

Parameter Conditions f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out t

EXTIpw

Output high to low level fall time and output low to high level rise time

Pulse width of external signals detected by the EXTI controller

= 50 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.8 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.7 V

= 30 pF, V

≥ 1.8 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.7 V

= 30 pF, V

≥ 1.8 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

Min Typ Max Unit

10 ns

42.5

42.5

100

(4)

100 (4)

12.5

72.5

2.5

3.5

MHz ns

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STM32F446xC/E Electrical characteristics

1. Guaranteed by design.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.

4. For maximum frequencies above 50 MHz and V

> 2.4 V, the compensation cell should be used.

Figure 32. I/O AC characteristics definition

90% 10%

50%

10%

50%

90%

EXTERNAL

OUTPUT

ON CL tr(IO)out tf(IO)out

Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by C L specified in the table “

I/O AC characteristics

”. ai14131d

6.3.18 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 56 ).

Unless otherwise specified, the parameters given in

Table 59 are derived from tests

performed under the ambient temperature and V

DD in

supply voltage conditions summarized

Symbol

Table 59. NRST pin characteristics

Parameter Conditions Min Typ Max

F(NRST)

(2)

NF(NRST)

Table 59 . Otherwise the reset is not taken into account by the device.

NRST_OUT

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse

NRST Input not filtered pulse

Generated reset pulse duration

 V

> 2.7 V

Internal Reset source

300

100

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution resistance must be minimum (~10% order)

to the series

2. Guaranteed by design.

Unit k  ns ns

µs

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171

Electrical characteristics STM32F446xC/E

Figure 33. Recommended NRST pin protection

External reset circuit (1)

NRST(2)

VDD

RPU

0.1 μF

Filter

Internal Reset

STM32F ai14132c

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

3. The external capacitor on NRST must be placed as close as possible to the device.

The parameters given in

Table 60 are guaranteed by design.

for more details on the input/output alternate function

for details on the input/output alternate function characteristics

(output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 60. TIMx characteristics (1)(2)

Conditions

(3)

Min Max Unit t t res(TIM) f

EXT

Res

TIM

MAX_COUNT

Timer resolution time

AHB/APBx prescaler=1 or

2 or 4, f

TIMxCLK

= 180 MHz f

AHB/APBx prescaler>4,

TIMxCLK

= 90 MHz

Timer external clock frequency on CH1 to CH4

Timer resolution

Maximum possible count with

32-bit counter

TIMxCLK

= 180 MHz

TIMxCLK

16/32

65536 × 65536 t t t

TIMxCLK

MHz

TIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK = 4x PCLKx.

bit

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I

C interface characteristics

The I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and SCL too are mapped as not “true”  open-drain. When configured as open-drain, the PMOS connected between the I/O pin and

DD is disabled, but is still present.

DS10693 Rev 10

STM32F446xC/E Electrical characteristics

The I

C characteristics are described in

Table 61

. Refer also to

Section 6.3.17

for more details on the input/output alternate function characteristics (SDA and SCL).

Symbol Parameter

Table 61. I 2 C characteristics

Standard mode

(1)(2)

Min Max

Fast mode I

(1)(2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t v(SDA, ACK) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

Data, ACK valid time

SDA and SCL rise time

SDA and SCL fall time t t t su(STA) su(STO) w(STO:STA) t

C b

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode

Capacitive load for each bus line

4.7

4.0

250

4.0

4.7

4.0

4.7

3450 (3)

3.45

1000

300

400

1.3

0.6

100

0.6

900 (4)

0.9

0.6 -

0.6

1.3

0.05

300

0.09

400

(5)

µs ns

µs

µs pF

1. Guaranteed based on test during characterization.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I 2 achieve fast mode I clock.

C frequencies. It must be at least 4 MHz to

C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I 2 C fast mode

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

5. The minimum width of the spikes filtered by the analog filter is above t

(max).

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171

Electrical characteristics STM32F446xC/E

Figure 34. I 2 C bus AC waveforms and measurement circuit

VDD_I2C VDD_I2C

I²C bus

SDA

SCL

STM32

START REPEATED

START

SDA tf(SDA)

SCL tw(SCLH) th(STA) tr(SDA) tw(SCLL) tsu(SDA) th(SDA) tr(SCL) tf(SCL) tsu(STA)

S TOP tsu(STO)

START tw(STO:STA) ai14979d

1. R

= series protection resistor.

2. R

= external pull-up resistor.

3. V

DD_I2C

is the I2C bus power supply.

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STM32F446xC/E Electrical characteristics

FMPI

C characteristics

The FMPI2C characteristics are described in

Table 62 .

Refer also to

Section 6.3.17

characteristics (SDA and SCL).

Table 62. FMPI 2 C characteristics (1)

Standard mode Fast mode Fast+ mode

Parameter

Min Max Min Max Min

FMPI2CC

MPI2CCLK

frequency 2 8 t w(SCLL) t w(SCLH) t su(SDA) t

H(SDA) t v(SDA,ACK) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

Data, ACK valid time

SDA and SCL rise time

SDA and SCL fall time

Start condition hold time t su(STA)

Repeated Start condition setup time

Stop condition setup time t su(STO) t w(STO:STA)

Stop to Start condition time

(bus free) t

C b

Pulse width of the spikes suppressed by the analog filter for standard and fast mode

Capacitive load for each bus line

4.7

4.0

0.25

4.7

3.45

0.100

0.30

400

1.3

0.6

0.10

0.6

1.3

0.05

0.9

0.30

0.09

400

1. Guaranteed based on test during characterization.

2. When tr(SDA,SCL)<=110ns.

3. Can be limited. Maximum supported value can be retrieved by referring to the following formulas:  t r(SDA/SCL)

= 0.8473 x R p

x C load 

R p(min)

= (V

-V

OL(max)

) / I

OL(max)

0.26

0.5

0.05

(2)

0.5

0.26

0.05

Max

0.45

0.12

0.09

550

(3)

Unit us pF

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171

Electrical characteristics STM32F446xC/E

Figure 35. FMPI 2 C timing diagram and measurement circuit

DD_I2C

I²C bus

SDA

SCL

STM32Fxx

START

SDA tf(SDA)

SCL tw(SCLL) th(STA) tr(SDA) tw(SCLH) tsu(SDA) th(SDA) tr(SCL) tf(SCL) tsu(STA)

STOP

START REPEATED tsu(STO)

START tw(STO:STA) ai14979c

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STM32F446xC/E Electrical characteristics

SPI interface characteristics

Symbol f

SCK

1/t c(SCK)

Unless otherwise specified, the parameters given in

Table 63

for SPI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

, with the following configuration:

supply voltage

 Output speed is set to OSPEEDRy[1:0] = 10

 Capacitive load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V

Table 64 for QSPI are derived from

for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO for SPI).

Table 63. SPI dynamic characteristics

(1)

Parameter Conditions Min Typ Max Unit

SPI clock frequency

Master full duplex/receiver mode, 

2.7 V ≤ V

SPI1/4

≤ 3.6 V 

Master transmitter 

1.71V <V

< 3.6V



SPI1/4

Master 

1.71V <V

SPI1/2/3/4

< 3.6V



Slave transmitter/  full duplex mode 

SPI1/4 

2.7V <V

< 3.6V

Slave receiver mode 

SPI1/4 

1.71V <V

< 3.6V

Slave mode 

PI1/2/3/4 

1.71V <V

< 3.6V

22.5

(2)

MHz

Duty(SCK)

Duty cycle of SPI clock frequency

Slave mode 30 50 70 %

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171

Electrical characteristics STM32F446xC/E

Symbol

Table 63. SPI dynamic characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit t w(SCKH) t w(SCKL) t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO

) t dis(SO)

SCK high and low time

NSS setup time

NSS hold time

Data input setup time

Data input hold time

Master mode, SPI presc = 2

Slave mode, SPI presc = 2

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode

Data output disable time Slave mode

PCLK

4 T

PCLK

2 T

PCLK

- 1.5

PCLK

+ 1.5

12 t v(SO)

Data output valid/hold time

Slave mode (after enable edge), 

2.7V ≤ V

≤ 3.6V

Slave mode (after enable edge), 

1.7 V ≤ V

≤ 3.6 V

7.5

10.5

t h(SO)

Data output valid/hold time

Slave mode (after enable edge) 5 t v(MO) t h(MO)

Data output valid time

Data output hold time

Master mode (after enable edge)

1.5

1. Guaranteed based on test during characterization.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having t su(MI)

= 0 while Duty(SCK) = 50%.

Figure 36. SPI timing diagram - slave mode and CPHA = 0

NSS input

128/198

SCK input

MISO

OUTPUT

MOSI

INPUT

(SI)

MSB OUT

MSB IN

(SI)

BIT6 OUT

BIT1 IN

DS10693 Rev 10

LSB OUT

LSB IN

STM32F446xC/E

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI)

Electrical characteristics

Figure 37. SPI timing diagram - slave mode and CPHA = 1 t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN ai14135b

Figure 38. SPI timing diagram - master mode

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

DS10693 Rev 10 129/198

171

Electrical characteristics STM32F446xC/E

QSPI interface characteristics

Unless otherwise specified, the parameters given in

tests performed under the ambient temperature, f

AHB

frequency and V

, with the following configuration:

supply voltage

 Output speed is set to OSPEEDRy[1:0] = 11

 Capacitive load C = 20 pF

 Measurement points are done at CMOS levels: 0.5 V

supply voltage conditions summarized in Table 16

for more details on the input/output alternate function characteristics.

Symbol

Table 64. QSPI dynamic characteristics in SDR mode

(1)

Parameter Conditions

1/t f

SCK c(SCK)

QSPI clock frequency

Write mode 

1.71 V ≤ V

≤ 3.6 V 

Cload = 15 pF

Read mode 

2.7 V < V

< 3.6 V 

Cload = 15 pF

1.71 V ≤ V

≤ 3.6 V t w(CKH) t w(CKL) t s(IN) t h(IN) t v(OUT) t h(OUT)

QSPI clock high and low

Data input setup time

Data input hold time

Data output valid time

Data output hold time

1. Guaranteed based on test during characterization.

Min

(CK)

/ 2) - 2

(CK)

/ 2

4.5

Typ

1.5

Max

(CK)

/ 2

(CK)

/ 2) +2

Unit

MHz ns

Symbol f

SCK

1/t c(SCK)

Table 65. QSPI dynamic characteristics in DDR mode

(1)

Parameter Conditions Min Typ

QSPI clock frequency

Write mode 

1.71 V ≤ V

≤ 3.6 V 

Cload = 15 pF

Read mode 

2.7 V < V

< 3.6 V

Cload = 15 pF



1.71 V ≤ V

≤ 3.6 V -

Max

Unit

MHz

130/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 65. QSPI dynamic characteristics in DDR mode (1) (continued)

Parameter Conditions t w(CKH) t w(CKL) t s(IN) t h(IN)

QSPI clock high and low

Data input setup time

Data input hold time -

t v(OUT)

Data output valid time

2.7 V < V

< 3.6 V

1.71 V < V

< 3.6 V t h(OUT)

Data output hold time

1. Guaranteed based on test during characterization.

Min

(CK)

/ 2) - 2

(CK)

/ 2

5.5

3.5

Typ

5.5

Max

(CK)

/ 2

(CK)

/ 2) +2

6.5

9.5

Unit ns

Symbol f

MCK f

I

S interface characteristics

Unless otherwise specified, the parameters given in

Table 66 for the I

2 S interface are derived from tests performed under the ambient temperature, f

PCLKx frequency and V

, with the following configuration:

 Output speed is set to OSPEEDRy[1:0] = 10

 Capacitive load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V

PCM short pulse Slave mode

for more details on the input/output alternate function characteristics

(CK, SD, WS).

Parameter

Table 66. I

S dynamic characteristics

(1)

Conditions

I2S Main clock output

I2S clock frequency

Master data

Slave data

I2S clock frequency duty cycle Slave receiver

Min Max

256 x 8K 256 x Fs (2)

64 x Fs

Unit

MHz

DS10693 Rev 10 131/198

171

Electrical characteristics

Symbol

Table 66. I 2 S dynamic characteristics (1) (continued)

Parameter Conditions t t t t v(WS) h(WS) su(WS)

h(WS)

WS valid time

WS hold time

WS setup time

WS hold time

Master mode

Slave mode

PCM short pulse Slave mode

(3)

Slave mode

t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed based on test during characterization.

2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).

3. Measurement done with respect to I2S_CK rising edge.

Min

1.5

2.5

Note:

STM32F446xC/E

Unit ns

Max

4.5

5.5

Refer to the I2S section of RM0390 reference manual for more details on the sampling frequency (F

). f

MCK

, f

, and D

values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. D

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of 

(I2SDIV / (2*I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2*I2SDIV + ODD).

maximum value is supported for each mode/condition.

132/198 DS10693 Rev 10

STM32F446xC/E

CPOL = 0

Electrical characteristics

Figure 39. I 2 S slave timing diagram (Philips protocol) (1) tc(CK)

CPOL = 1 tw(CKH) tw(CKL) th(WS)

WS input

SDtransmit tsu(WS)

LSB transmit

(2) tsu(SD_SR)

LSB receive

(2)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB transmit

LSB receive SDreceive ai14881b

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 40. I 2 S master timing diagram (Philips protocol) (1) tf(CK) tr(CK) tc(CK)

CPOL = 0 tw(CKH)

CPOL = 1 tv(WS) tw(CKL) th(WS)

WS output

SDtransmit

LSB transmit

(2) tsu(SD_MR)

LSB receive

(2)

MSB transmit

MSB receive tv(SD_MT)

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive SDreceive ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DS10693 Rev 10 133/198

171

Electrical characteristics STM32F446xC/E

SAI characteristics

Unless otherwise specified, the parameters given in

Table 67

for SAI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

, with the following configuration:

supply voltage

 Output speed is set to OSPEEDRy[1:0] = 10

 Capacitive load C = 30 pF

 Measurement points are performed at CMOS levels: 0.5 V

for more details on the input/output alternate

characteristics (SCK,SD,WS).

function

Table 67. SAI characteristics

(1)

Symbol Parameter Conditions f

MCK

SAI Main clock output f

SAI clock frequency

(2)

Master data: 32 bits

Slave data: 32 bits t v(FS)

FS valid time

Master mode 

2.7 V ≤ V

≤ 3.6 V

Master mode 

1.71 V ≤ V

≤ 3.6 V

Master mode t h(FS) t su(FS) t h(FS) t su(SD_A_MR) t su(SD_B_SR) t h(SD_A_MR) t h(SD_B_SR) t v(SD_B_ST)

FS hold time

FS setup time

FS hold time

Data input setup time

Slave mode

Master receiver

Slave receiver

Master receiver

Data input hold time

Data output valid time

Slave receiver

Slave transmitter (after enable edge 

2.7 V ≤ V

≤ 3.6 V

Slave transmitter (after enable edge 

1.71 V ≤ V

≤ 3.6 V

Slave transmitter (after enable edge t h(SD_B_ST)

Data output hold time t v(SD_B_ST)

Data output valid time

Master transmitter (after enable edge 

2.7 V ≤ V

≤ 3.6 V

Master transmitter (after enable edge 

1.71 V ≤ V

≤ 3.6 V

Master transmitter (after enable edge t h(SD_B_ST)

Data output hold time

1. Guaranteed based on test during characterization.

2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency)

3. With Fs = 192 KHz

256 x 8K 256 x Fs

128 x Fs

(3)

128 x Fs

Table 73 for ULPI are derived from

17.5

9.5

MHz

% ns

134/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Figure 41. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

Figure 42. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n

Slot n+2 th(SD_ST)

SAI_SD_X

(receive)

MS32772V1

USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Table 68. USB OTG full speed startup time

Symbol Parameter t

STARTUP

(1)

USB OTG full speed transceiver startup time

1. Guaranteed by design.

Max

Unit

µs

DS10693 Rev 10 135/198

171

Electrical characteristics

Note:

STM32F446xC/E

Symbol

Table 69. USB OTG full speed DC electrical characteristics

Parameter Conditions Min.

(1)

Typ. Max.

(1)

Unit

Input levels

Output levels

DDUSB

USB OTG full speed transceiver operating voltage

(3)

Differential input sensitivity

I(USB_FS_DP/DM,

USB_HS_DP/DM)

Differential common mode range

Includes V

DI range

Single ended receiver threshold

Static output level low

Static output level high

PA11, PA12, PB14, PB15

(USB_FS_DP/DM,

USB_HS_DP/DM)

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

of 1.5

k Ω to 3.6 V (4)

of 15 k Ω to V

(4)

= V

DDUSB

PA12, PB15

(USB_FS_DP,

USB_HS_DP)

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

= V

3.0

(2)

0.2

0.8

1.3

2.8

0.65

1.1

1.5

1.8

3.6

2.5

2.0

0.3

3.6

2.0

2.1

0.25

0.37

0.55

1. All the voltages are measured from the local ground potential.

2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7 to 3.0 V V

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB OTG full speed drivers.

V k 

When VBUS sensing feature is enabled, PA9 and PB13 must be left at their default state

(floating input), not as alternate function. A typical 200 µA current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled.

Figure 43. USB OTG full speed timings: definition of data signal rise and fall time

Cross over points

Differential data lines

CRS

SS t f t r ai14137b

136/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Table 70. USB OTG full speed electrical characteristics (1)

Driver characteristics

Symbol

Z t t f r t rfm

CRS

DRV

Rise time (2)

Fall time

(2)

Parameter

Rise/ fall time matching

Output signal crossover voltage

Output driver impedance

(3)

Conditions

= 50 pF

= 50 pF t r

/t f

Driving high or low

Min

1.3

Max

110

2.0

Unit ns ns



1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -

Chapter 7 (version 2.0).

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver.

USB high speed (HS) characteristics

Unless otherwise specified, the parameters given in

tests performed under the ambient temperature, f

HCLK and V

frequency summarized in

Table 72

supply voltage conditions summarized in

Table 71 , with the following configuration:

 Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified

 Capacitive load C = 30 pF, unless otherwise specified

 Measurement points are done at CMOS levels: 0.5 V

for more details on the input/output characteristics.

Symbol

Table 71. USB HS DC electrical characteristics

Parameter

Input level V

USB OTG HS operating voltage

1. All the voltages are measured from the local ground potential.

Min.

(1)

1.7

Max.

(1)

3.6

Unit

Symbol

START_8BIT

STEADY

START_8BIT

STEADY t

STEADY

Table 72. USB HS clock timing parameters

(1)

Parameter Min Typ f

HCLK

value to guarantee proper operation of

USB HS interface

Frequency (first transition) 8-bit ±10%

Frequency (steady state) ±500 ppm

Duty cycle (first transition) 8-bit ±10%

Duty cycle (steady state) ±500 ppm

Time to reach the steady state frequency and duty cycle after the first transition

59.97

49.975

Max Unit

MHz

66 MHz

60.03

MHz

60 %

50.025

1.4

DS10693 Rev 10 137/198

171

Electrical characteristics STM32F446xC/E

Symbol

Table 72. USB HS clock timing parameters (1)

(continued)

Parameter t t t

START_DEV

START_HOST

PREP

Clock startup time after the de-assertion of SuspendM

Peripheral

Host

PHY preparation time after the first transition of the input clock

1. Guaranteed by design.

Min

Typ

Max

5.6

Unit ms

µs

Figure 44. ULPI timing diagram

Clock tSC tSD tHC

Control In

(ULPI_DIR,

ULPI_NXT) data In

(8-bit) tHD tDC tDC

Control out

(ULPI_STP) data out

(8-bit) tDD ai17361c

Symbol t

SC t

HC t

SD t

HD t

Table 73. Dynamic characteristics: USB ULPI (1)

Parameter

Control in (ULPI_DIR, ULPI_NXT) setup time

Control in (ULPI_DIR, ULPI_NXT) hold time

Data in setup time

Data in hold time

Data/control output delay

Conditions

2.7 V < V

= 20 pF

< 3.6 V, 

1.71 V < V

< 3.6 V,

= 15 pF

Min.

Typ.

Max.

Unit

1.5

8.5

11.5

1. Guaranteed based on test during characterization.

CAN (controller area network) interface

Table 74 are derived from tests

for more details on the input/output alternate function characteristics

(CANx_TX and CANx_RX).

138/198 DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Unless otherwise specified, the parameters given in

performed under the ambient temperature, f

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:

PCLK2 frequency and V

DDA

supply voltage

Symbol

DDA

REF+

REFf

ADC f

TRIG

(2)

AIN

(2)

Parameter

Power supply

Positive reference voltage

Negative reference voltage

ADC clock frequency

External trigger frequency

Table 74. ADC characteristics

Conditions

DDA

 V

REF+

< 1.2 V

Min

1.7

(1)

DDA

to 2.4 V

DDA

= 2.4 to 3.6 V f

ADC

= 30 MHz, 

12-bit resolution

0.6

Conversion voltage range

(3)

0 (V

SSA or V

REFtied to ground)

External input impedance

See Equation 1 for details

ADC

(2)(4)

Sampling switch resistance

ADC

(2)

Internal sample and hold capacitor

t lat

(2) t latr

(2) t

STAB

(2) t

CONV

(2)

Typ

Max

3.6

DDA

1764

REF+

Injection trigger conversion latency f

ADC

= 30 MHz

ADC

= 30 MHz

ADC

= 30 MHz

Regular trigger conversion latency

Sampling time

0.100

Power-up time f

ADC

= 30 MHz

12-bit resolution f

ADC

= 30 MHz

10-bit resolution

Total conversion time (including sampling time) f

ADC

= 30 MHz

8-bit resolution

0.50

0.43

0.37

16.40

16.34

16.27

ADC

= 30 MHz

6-bit resolution

0.30

16.20

9 to 492 (t

for sampling +n-bit resolution for successive approximation)

0.100

3 (5)

0.067

(5)

480

Unit



 pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

MHz

MHz kHz

1/f

ADC

µs

1/f

ADC

DS10693 Rev 10 139/198

171

Electrical characteristics STM32F446xC/E

Symbol Parameter

Table 74. ADC characteristics (continued)

Conditions Min Typ Max Unit f

(2) t

Sampling rate

ADC

= 30 MHz, and 

= 3 ADC cycles)

12-bit resolution

Single ADC

12-bit resolution

Interleave Dual ADC mode

12-bit resolution

Interleave Triple ADC mode

3.75

Msps

VREF+

(2)

VDDA

(2)

ADC V

REF

DC current consumption in conversion mode

ADC V

DDA

DC current consumption in conversion mode

300

1.6

500

1.8

1. V

DDA

Internal reset OFF ).

2. Guaranteed based on test during characterization.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. R

ADC

maximum value is given for V

=1.7 V, and minimum value for V

=3.3 V.

5. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in

Table 74

µA mA

Equation 1: R

AIN

max formula

RAIN =

 k 0.5



RADC

 ln  2 

–

140/198

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

Symbol

Table 75. ADC static accuracy at f

ADC

= 18 MHz

(1)

Parameter Test conditions Typ Max

(2)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

=18 MHz

DDA

= 1.7 to 3.6 V

REF

= 1.7 to 3.6 V

DDA

 V

REF

< 1.2 V

±3

±2

±1

±2

1. Better performance can be achieved with restricted V

, frequency and temperature ranges.

2. Guaranteed based on test during characterization.

±4

±3

±2

±3

Unit

LSB

DS10693 Rev 10

STM32F446xC/E Electrical characteristics

Symbol

Table 76. ADC static accuracy at f

ADC

= 30 MHz (1)

Parameter Test conditions Typ Max

(2)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

AIN

= 30 MHz, 

< 10 k  , 

DDA

REF

= 2.4 to 3.6 V, 

= 1.7 to 3.6 V, 

DDA

 V

REF

< 1.2 V

±2

±1.5

±1

±1.5

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed based on test during characterization.

±5

±2.5

±3

±2

±3

Symbol

Table 77. ADC static accuracy at f

ADC

= 36 MHz

(1)

Parameter Test conditions Typ Max

(2)

ET Total unadjusted error ±4 ±7

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

=36 MHz,

DDA

= 2.4 to 3.6 V,

REF

= 1.7 to 3.6 V

DDA

 V

REF

< 1.2 V

±2

±3

±2

±3

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed based on test during characterization.

±3

±6

±3

±6

Unit

LSB

Unit

LSB

Symbol

Table 78. ADC dynamic accuracy at f

ADC

= 18 MHz - Limited test conditions (1)

Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits

SINAD Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion

1. Guaranteed based on test during characterization.

ADC

=18 MHz

DDA

= V

REF+

= 1.7 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.3

10.4

64 64.2

64 65

72 -

bits dB

Symbol

Table 79. ADC dynamic accuracy at f

ADC

= 36 MHz - Limited test conditions

(1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

Total harmonic distortion

1. Guaranteed based on test during characterization.

ADC

=36 MHz

DDA

= V

REF+

= 3.3 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.6

10.8

66 67

64 68

- 70 - 72

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion

DS10693 Rev 10 141/198

171

Electrical characteristics STM32F446xC/E being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 6.3.17

does not affect the ADC accuracy.

and  I

INJ(PIN)

Figure 45. ADC accuracy characteristics

[1LSB IDEAL =

V REF+

4096

V DDA

(or depending on package)]

4096

4095

4094

4093

(2)

(3)

EO EL

1L SBIDEAL

(1)

VSSA

1 2 3 456 7 4093 4094 4095 4096

VDDA ai14395c

1. See also Table 76 .

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E

= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.



= Offset error: deviation between the first actual transition and the first ideal one.



= Gain error: deviation between the last ideal transition and the last actual one.



= Differential linearity error: maximum deviation between actual steps and the ideal one.



= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

142/198 DS10693 Rev 10

STM32F446xC/E

VAIN

Electrical characteristics

Figure 46. Typical connection diagram using the ADC

RAIN(1)

AINx

Cparasitic

VDD

0.6 V

IL±1 μA

STM32F

Sample and hold ADC converter

RADC(1)

12-bit converter

CADC(1) ai17534

1. Refer to Table 74 for the values of R

AIN

, R

ADC

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (~ 5 has to be reduced.

pF). A high C parasitic

value downgrades conversion accuracy. To remedy this, f

ADC

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 47

Figure 48

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip.

Figure 47. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

STM32F

REF+

(1)

1 μF // 10 nF

DDA

1 μF // 10 nF

SSA

REF-

(1) ai17535b

1. V and V

REF– inputs are both available on UFBGA144. V

REF+

and V

REF–

REF+ is also available on LQFP100, LQFP144, are not available, they are internally connected to V

DDA and V

SSA

DS10693 Rev 10 143/198

171

Electrical characteristics STM32F446xC/E

Figure 48. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

STM32F

REF+

DDA

(1)

1 μF // 10 nF

REF-

SSA

(1) ai17536c

1. V and V

REF– inputs are both available on UFBGA144. V

REF+

and V

REF–

REF+ is also available on LQFP100, LQFP144, are not available, they are internally connected to V

DDA and V

SSA

6.3.22 Temperature sensor characteristics

Symbol

Table 80. Temperature sensor characteristics

Parameter Min Typ Max

(1)

Avg_Slope

(1)

(1) t

START

(2)

S_temp

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature (1 °C accuracy)

1. Guaranteed based on test during characterization.

2. Guaranteed by design.

 1

2.5

0.76

 2

Unit

°C mV/°C

µs

Symbol

Table 81. Temperature sensor calibration values

Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V

DDA

= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V

DDA

= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

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STM32F446xC/E

6.3.23 V

BAT

monitoring characteristics

Symbol

Table 82. V

BAT

monitoring characteristics

Parameter Min

(1)

S_vbat

(2)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT 

1 mV accuracy

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

- 1

Electrical characteristics

Typ

Max

+ 1

Unit

K 

µs

The parameters given in

Table 83 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Symbol

Table 83. internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

S_vrefint

(1)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

–40 °C < T

< +105 °C

RERINT_s

(2)

Internal reference voltage spread over the temperature range

= 3 V  10 mV

Coeff

(2) t

START

(2)

Temperature coefficient

Startup time -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.18

1.21

1.24

µs mV ppm/°C

µs

Symbol

REFIN_CAL

Table 84. Internal reference voltage calibration values

Parameter Memory address

Raw data acquired at temperature of 30 °C

VDDA

= 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B

Symbol

DDA

REF+

Parameter

Analog supply voltage

Reference supply voltage

Table 85. DAC characteristics

Conditions Min Typ Max Unit

1.7

(1)

1.7

(

3.6

Comments

V V

REF+

 V

DDA

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Electrical characteristics STM32F446xC/E

Symbol

SSA

LOAD

(2)

LOAD

(2)

Parameter

Ground

Resistive load

Impedance output with buffer OFF

Capacitive load

Table 85. DAC characteristics (continued)

Conditions Min Typ Max Unit

0 V

DAC output buffer ON

Connected to V

SSA

Connected to V

DDA

25 -

k Ω

Comments

k Ω pF

When the buffer is OFF, the

Minimum resistive load between DAC_OUT and V

SS to have a 1% accuracy is

1.5 M Ω

Maximum capacitive load at

DAC_OUT pin (when the buffer is ON).

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer

OFF

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer

OFF

0.2

0.5

DDA

– 0.2

REF

± 1

LSB

V mV

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

REF+

= 3.6 V and (0x1C7) to

(0xE38) at V

REF+

= 1.7 V

It gives the maximum output excursion of the DAC.

VREF+

DDA

DAC DC V

REF current consumption in quiescent mode

(Standby mode)

DAC DC V

DDA current consumption in quiescent mode

(3) -

170 240

50 75

µA

280 380 µA

475 625 µA

With no load, worst code

(0x800) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, middle code

(0x800) on the inputs

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

DNL

(4)

Differential non linearity difference between two consecutive code -

1 LSB)

±0.5 LSB

Given for the DAC in 10-bit configuration.

±2 LSB

Given for the DAC in 12-bit configuration.

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STM32F446xC/E Electrical characteristics

Symbol Parameter

Table 85. DAC characteristics (continued)

Conditions Min Typ Max Unit Comments

INL

Integral non linearity (difference between measured value at

Code i and the value at Code i on a line drawn between Code 0 and last Code

1023)

Offset

Offset error

(difference between measured value at

Code (0x800) and the ideal value =

REF+

/2)

Gain

Gain error t

Total harmonic distortion

Buffer ON

±1

±4

±10

LSB

±3 LSB

±12 LSB

±0.5

6 mV

µs

Given for the DAC in 10-bit configuration.

Given for the DAC in 12-bit configuration.

Given for the DAC in 12-bit configuration

Given for the DAC in 10-bit at

REF+

= 3.6 V

Given for the DAC in 12-bit at

REF+

= 3.6 V

Given for the DAC in 12-bit configuration

LOAD





50 pF,

5 k Ω



THD

LOAD

 50 pF, 

 5 k Ω t

Update rate

(2)

WAKEUP

PSRR+

(2)

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1 LSB)

Wakeup time from off state (Setting the ENx bit in the

DAC Control register)

Power supply rejection ratio (to

DDA

) (static DC measurement)

6.5

MS/ s

µs

LOAD

 50 pF, 

 5 k Ω

 50 pF, R

LOAD

 5 k Ω input code between lowest and highest possible ones.

- 67 - 40 dB No R

LOAD

, C

LOAD

= 50 pF

1. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

Section 3.16.2:

Internal reset OFF ).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.

4. Guaranteed based on test during characterization.

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171

Electrical characteristics

Figure 49. 12-bit buffered/non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

LOAD

12-bit digital to analog converter

DACx_OUT

LOAD

STM32F446xC/E ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Unless otherwise specified, the parameters given in

Table 86

to Table 93

for the FMC interface are derived from tests performed under the ambient temperature, f

HCLK and V

DD frequency

supply voltage conditions summarized in

Table 15

, with the following configuration:

 Output speed is set to OSPEEDRy[1:0] = 10

 Capacitance load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V

through Figure 53 represent asynchronous waveforms and

for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figure 50

Table 86 through

Table 93 provide the corresponding timings. The results shown in these tables are obtained

with the following FMC configuration:

 AddressSetupTime = 0x1

 AddressHoldTime = 0x1

 DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

 BusTurnAroundDuration = 0x0

In all timing tables, the T

HCLK

is the HCLK clock period.

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STM32F446xC/E Electrical characteristics

Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

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Electrical characteristics STM32F446xC/E

Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR Read timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

– 2 2 T

HCLK

+ 0.5

0 1

HCLK

- 1 2T

HCLK

+ 0.5

0 -

HCLK

- 2

HCLK

- 2

0.5

HCLK

+1 ns

Symbol

Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read

NWAIT timings (1)(2)

Parameter Min Max Unit t w(NE)

FMC_NE low time 7T

HCLK

+ 1 7T

HCLK t w(NOE) t w(NWAIT) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT low time

FMC_NWAIT valid before FMC_NEx high

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

– 1 5T

HCLK

+ 1

HCLK

– 0.5

HCLK

+ 1.5

FMC_NEx hold time after FMC_NWAIT invalid 4T

HCLK

+ 1 -

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STM32F446xC/E Electrical characteristics

Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)

Symbol Parameter

t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

Min Max

3 T

HCLK

- 2 3 T

HCLK

+0.5

HCLK

– 0.5

HCLK

+ 0.5

HCLK

+ 0.5

HCLK

+ 0.5

HCLK

- 0.5

HCLK

+ 0.5

HCLK

+ 2

HCLK

+ 0.5

HCLK

+ 0.5

Unit

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Electrical characteristics STM32F446xC/E

Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write

NWAIT timings (1)(2)

Symbol Parameter Min Max t w(NE)

FMC_NE low time t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

- 0.5

HCLK

+ 1

HCLK

- 0.5

HCLK

+ 1

HCLK

- 0.5

HCLK

+ 2 -

Unit ns

Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0]

NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

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STM32F446xC/E Electrical characteristics

Table 90. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t tw(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low t h(AD_NADV)

FMC_NADV low time

FMC_AD(address) valid hold time after

FMC_NADV high) t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FMC_NOE high

FMC_BL time after FMC_NOE high

FMC_NEx low to FMC_BL valid

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

– 2 3T

HCLK

+0.5

HCLK

– 0.5

HCLK

– 1 T

HCLK

+ 0.5

0 -

HCLK

– 0.5

HCLK

+ 0.5

HCLK

– 0.5

HCLK

+ 1.5

HCLK

+ 1

Unit ns

Table 91. Asynchronous multiplexed PSRAM/NOR read NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time 8T

HCLK

- 1 8T

HCLK

+ 2 t t t w(NOE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time 5T

HCLK

– 1

FMC_NWAIT valid before FMC_NEx high 5T

HCLK

+ 1.5

FMC_NEx hold time after FMC_NWAIT invalid

HCLK

+ 1

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

+ 1

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Electrical characteristics STM32F446xC/E

Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

FMC_NOE

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) t h(NE_NWE) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32756V1

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Table 92. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time t h(AD_NADV)

FMC_AD(adress) valid hold time after

FMC_NADV high) t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FMC_NWE high

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

- 2 4T

HCLK

+0.5

HCLK

+ 0.5

HCLK

+ 0.5

0.5

HCLK

– 0.5

HCLK

+ 0.5

HCLK

– 2 -

HCLK

–2

HCLK

+ 0.5

HCLK

+ 1.5

Unit ns

Table 93. Asynchronous multiplexed PSRAM/NOR write NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

+ 0.5

HCLK

+ 1.5

HCLK

– 1

HCLK

+ 2

Synchronous waveforms and timings

Figure 54

through Figure 57

represent synchronous waveforms and Table 94

through

Table 97 provide the corresponding timings. The results shown in these tables are obtained

with the following FMC configuration:

 BurstAccessMode = FMC_BurstAccessMode_Enable;

 MemoryType = FMC_MemoryType_CRAM;

 WriteBurst = FMC_WriteBurst_Enable;

 CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)

 DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

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Electrical characteristics STM32F446xC/E

In all timing tables, the T

HCLK

FMC_CLK = 90 MHz).

is the HCLK clock period (with maximum

Figure 54. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

MS32757V1

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Table 94. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid t su(ADV-CLKH)

FMC_A/D[15:0] valid data before FMC_CLK high t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

- 0.5

HCLK

– 0.5

3.5

2.5

0.5

Unit ns

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Electrical characteristics STM32F446xC/E

FMC_CLK

Figure 55. Synchronous multiplexed PSRAM write timings tw(CLK) tw(CLK) BUSTURN = 0

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) td(CLKL-Data)

AD[15:0] td(CLKL-Data)

D1 D2

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Symbol

Table 95. Synchronous multiplexed PSRAM write timings (1)(2)

Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t

(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period, VDD range= 2.7 to 3.6 V

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

- 1

HCLK

+ 0.5

HCLK

- 0.5

HCLK

- 0.5

2.5

Unit ns

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Electrical characteristics STM32F446xC/E

Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 96. Synchronous non-multiplexed NOR/PSRAM read timings

(1)(2)

Symbol Parameter Min Max t w(CLK) t

(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

HCLK

– 0.5

HCLK

– 0.5

3.5

2.5

Unit ns

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STM32F446xC/E Electrical characteristics

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

Figure 57. Synchronous non-multiplexed PSRAM write timings tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx tw(CLK)

Data latency = 0 td(CLKH-NExH) td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

FMC_D[15:0] td(CLKL-Data)

D1 td(CLKL-Data)

FMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH)

FMC_NBL td(CLKH-NBLH) th(CLKH-NWAITV)

MS32760V1

DS10693 Rev 10 161/198

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Electrical characteristics STM32F446xC/E

Table 97. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. C

= 30 pF.

2. Guaranteed based on test during characterization.

HCLK

– 1

HCLK

– 0.5

HCLK

+ 1

HCLK

+ 1.5

1.5

2.5

Unit ns

NAND controller waveforms and timings

Figure 58

through Figure 61 represent synchronous waveforms, and Table 98

and

Table 99

provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

 COM.FSMC_SetupTime = 0x01;

 COM.FMC_WaitSetupTime = 0x03;

 COM.FMC_HoldSetupTime = 0x02;

 COM.FMC_HiZSetupTime = 0x01;

 ATT.FMC_SetupTime = 0x01;

 ATT.FMC_WaitSetupTime = 0x03;

 ATT.FMC_HoldSetupTime = 0x02;

 ATT.FMC_HiZSetupTime = 0x01;

 Bank = FMC_Bank_NAND;

 MemoryDataWidth = FMC_MemoryDataWidth_16b;

 ECC = FMC_ECC_Enable;

 ECCPageSize = FMC_ECCPageSize_512Bytes;

 TCLRSetupTime = 0;

 TARSetupTime = 0.

In all timing tables, the T

HCLK

is the HCLK clock period.

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Figure 58. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NOE) th(NOE-ALE)

FMC_NOE (NRE)

FMC_D[15:0] tsu(D-NOE) th(NOE-D)

MS32767V1

Figure 59. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NWE) th(NWE-ALE)

FMC_NOE (NRE)

FMC_D[15:0] tv(NWE-D) th(NWE-D)

MS32768V1

DS10693 Rev 10 163/198

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Electrical characteristics STM32F446xC/E

Figure 60. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE) th(NOE-ALE)

FMC_NWE tw(NOE)

FMC_NOE tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

Figure 61. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE)

FMC_NWE tw(NWE) th(NOE-ALE)

FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Symbol

Table 98. Switching characteristics for NAND Flash read cycles (1)

Parameter Min Max t w(N0E) t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)

1. C

= 30 pF.

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_ALE valid before FMC_NOE low

FMC_NWE high to FMC_ALE invalid

HCLK

– 0.5 4T

HCLK

+ 0.5

9 -

2.5

HCLK

– 2

HCLK

0.5

Unit ns

164/198 DS10693 Rev 10

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Table 99. Switching characteristics for NAND Flash write cycles (1)

Symbol t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)

1. C

= 30 pF.

Parameter

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_ALE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

Min

HCLK

- 2

HCLK

– 1

HCLK

– 3

HCLK

– 2

Max Unit

HCLK

ns ns

HCLK

0.5

SDRAM waveforms and timings

Figure 62. SDRAM read access waveforms (CL = 1)

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0]

Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC)

Coln td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE

FMC_D[31:0] tsu(SDCLKH_Data)

Data1 th(SDCLKH_Data)

Data2 Datai Datan

MS32751V2

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Electrical characteristics STM32F446xC/E

Symbol

Table 100. SDRAM read timings (1)(2)

Parameter Min t w(SDCLK) t su(SDCLKH _Data)

FMC_SDCLK period

Data input setup time

2T t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL_ SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK .

2. Guaranteed based on test during characterization.

HCLK

0.5

Symbol

Table 101. LPSDR SDRAM read timings (1)(2)

Parameter Min t w(SDCLK) t su(SDCLKH _Data) t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL_ SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. CL = 10 pF .

2. Guaranteed based on test during characterization.

HCLK

- 0.5

Max

HCLK

+ 0.5

Max

HCLK

+0.5

1.5

0.5

Unit ns

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Figure 63. SDRAM write access waveforms

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0] Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC)

Coln td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE td(SDCLKL_Data)

FMC_D[31:0] td(SDCLKL_NBL)

FMC_NBL[3:0]

Data1 Data2 Datai th(SDCLKL_Data)

Datan

MS32752V2

Symbol

Table 102. SDRAM write timings (1)(2)

Parameter Min

(SDCLK) t w(SDCLK) t d(SDCLKL _Data) t h(SDCLKL _Data) t d(SDCLK _Add) t d(SDCLKL _SDNWE)) t h(SDCLKL_SDNWE)) t d(SDCLKL_SDNE)) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

Frequency of operation

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valie time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. C

= 10 pF on data and address line. C

=15 pF on FMC_SDCLK.

2. Guaranteed based on test during characterization.

HCLK

- 0.5

0.5

Max

HCLK

+ 0.5

1.5

Unit

MHz ns

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Electrical characteristics

Symbol

Table 103. LPSDR SDRAM write timings (1)(2)

Parameter Min

(SDCLK) t w(SDCLK) t d(SDCLKL _Data) t h(SDCLKL _Data) t d(SDCLK _Add) t d(SDCLKL _SDNWE)) t h(SDCLKL_SDNWE)) t d(SDCLKL_SDNE)) t h(SDCLKL_ SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_SDNCAS)

Frequency of operation

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. CL = 10 pF.

2. Guaranteed based on test during characterization.

HCLK

- 0.5

0.5

Max

HCLK

+ 0.5

2.5

STM32F446xC/E

Unit

MHz ns

Unless otherwise specified, the parameters given in Table 104

for DCMI are derived from tests performed under the ambient temperature, f

HCLK

frequency and V voltage summarized in

Table 16 , with the following configuration:

supply

 DCMI_PIXCLK polarity: falling

 DCMI_VSYNC and DCMI_HSYNC polarity: high

 Data formats: 14 bits

Symbol

Table 104. DCMI characteristics

Parameter

Frequency ratio DCMI_PIXCLK/f

HCLK

DCMI_PIXCLK Pixel clock input

Pixel t su(DATA) t h(DATA) t su(HSYNC) t su(VSYNC) t h(HSYNC) t h(VSYNC)

Pixel clock input duty cycle

Data input setup time

Data input hold time

DCMI_HSYNC/DCMI_VSYNC input setup time

DCMI_HSYNC/DCMI_VSYNC input hold time

Min

3.5

Max

0.4

Unit

MHz

% ns

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Figure 64. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK t su(HSYNC) t h(HSYNC)

DCMI_HSYNC t su(VSYNC) t h(HSYNC)

DCMI_VSYNC t su(DATA) t h(DATA)

DATA[0:13]

MS32414V2

6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in

Table 105 for the SDIO are derived

from tests performed under the ambient temperature, f

PCLK2 frequency and V voltage conditions summarized in

Table 16 , with the following configuration:

supply

 Output speed is set to OSPEEDRy[1:0] = 10

 Capacitive load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V