In the order code, the letter ‘F’ refers to product versions with data EEPROM and ‘H’ refers to product versions without data EEPROM. The identifiers ‘F’ and ‘H’ do not coexist in a given order code.

The datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information.

• For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

• For information on programming, erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual (PM0051).

• For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

• For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

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Description

2 Description

STM8AF6246/48/66/68

The STM8AF6246, STM8AF6248, STM8AF6266 and STM8AF6268 automotive 8-bit microcontrollers offer from 16 to 32 Kbyte of Flash program memory and integrated true data EEPROM. They are referred to as medium density STM8A devices in STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

All devices of the STM8A product line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset.

Device performance is ensured by a clock frequency of up to 16 MHz CPU and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.

Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8A family thanks to their advanced core which is made in a state-of-the art technology for automotive applications with 3.3 V to 5 V operating supply.

All STM8A and ST7 microcontrollers are supported by the same tools including

STVD/STVP development environment, the STice emulator and a low-cost, third party incircuit debugging tool.

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STM8AF6246/48/66/68 Product line-up

Order code

STM8AF/P6268

STM8AF/P6248

STM8AF/P6266

STM8AF/P6246

STM8AF/P6266

STM8AF/P6246

Table 1. STM8AF6246/48/66/68 product line-up

Package

Medium density

Flash program memory

(byte)

RAM

(byte)

Data EE

(byte)

10-bit

A/D ch.

Timers

(IC/OC/PWM)

32 K 1 K

LQFP48

(7x7)

LQFP32

(7x7)

VFQFPN32

16 K

32 K

16 K

32 K

16 K

2 K

0.5 K

1 K

0.5 K

1 K

0.5 K

Serial interfaces

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(8/8/8)

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(8/8/8)

LIN(UART),

SPI, I²C

LIN(UART),

SPI, I²C

LIN(UART),

SPI, I²C

I/0 wakeup pins

38/35

25/23

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Block diagram STM8AF6246/48/66/68

Figure 1. STM8AF6246/48/66/68 block diagram

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1. Legend:

ADC: Analog-to-digital converter beCAN: Controller area network

BOR: Brownout reset

I²C: Inter-integrated circuit multimaster interface

IWDG: Independent window watchdog

LINUART: Local interconnect network universal asynchronous receiver transmitter

POR: Power on reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

Window WDG: Window watchdog

Block diagram

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Product overview STM8AF6246/48/66/68

This section describes the family features that are implemented in the products covered by this datasheet.

For more detailed information on each feature please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

5.1 STM8A central processing unit (CPU)

The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency and performance. It contains 21 internal registers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

5.1.1 Architecture and registers

• Harvard architecture

• 3-stage pipeline

• 32-bit wide program memory bus with single cycle fetching for most instructions

• X and Y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

• 8-bit accumulator

• 24-bit program counter with 16-Mbyte linear memory space

• 16-bit stack pointer with access to a 64 Kbyte stack

• 8-bit condition code register with seven condition flags for the result of the last instruction.

5.1.2 Addressing

• 20 addressing modes

• Indexed indirect addressing mode for look-up tables located anywhere in the address space

• Stack pointer relative addressing mode for efficient implementation of local variables and parameter passing

• 80 instructions with 2-byte average instruction size

• Standard data movement and logic/arithmetic functions

• 8-bit by 8-bit multiplication

• 16-bit by 8-bit and 16-bit by 16-bit division

• Bit manipulation

• Data transfer between stack and accumulator (push/pop) with direct stack access

• Data transfer using the X and Y registers or direct memory-to-memory transfers

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5.2 Single wire interface module (SWIM) and debug module (DM)

5.2.1 SWIM

The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated in all device operation modes and can be connected to a running device

(hot plugging).The maximum data transmission speed is 145 bytes/ms.

The non-intrusive debugging module features a performance close to a full-flavored emulator. Besides memory and peripheral operation, CPU operation can also be monitored in real-time by means of shadow registers.

• R/W of RAM and peripheral registers in real-time

• R/W for all resources when the application is stopped

• Breakpoints on all program-memory instructions (software breakpoints), except the interrupt vector table

• Two advanced breakpoints and 23 predefined breakpoint configurations

• Nested interrupts with three software priority levels

• 21 interrupt vectors with hardware priority

• Five vectors for external interrupts (up to 34 depending on the package)

• Trap and reset interrupts

5.4 Flash program and data EEPROM

• 16 Kbyte to 32 Kbyte of medium density single voltage program Flash memory

• Up to 1 Kbyte true (not emulated) data EEPROM

• Read while write: writing in the data memory is possible while executing code in the

Flash program memory

The whole Flash program memory and data EEPROM are factory programmed with 0x00.

5.4.1 Architecture

• The memory is organized in blocks of 128 bytes each

• Read granularity: 1 word = 4 bytes

• Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel

• Writing, erasing, word and block management is handled automatically by the memory interface.

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Product overview

5.4.2 Write protection (WP)

STM8AF6246/48/66/68

Write protection in application mode is intended to avoid unintentional overwriting of the memory. The write protection can be removed temporarily by executing a specific sequence in the user software.

If the user chooses to update the Flash program memory using a specific boot code to perform in application programming (IAP), this boot code needs to be protected against unwanted modification.

In the STM8A a memory area of up to 32 Kbyte can be protected from overwriting at user option level. Other than the standard write protection, the UBC protection can exclusively be modified via the debug interface, the user software cannot modify the UBC protection status.

The UBC memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the UBC and NUBC option bytes

(see Section 9: Option bytes on page 44

Figure 2. Flash memory organization of STM8AF6246/48/66/68

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5.4.4 Read-out protection (ROP)

Product overview

The STM8A provides a read-out protection of the code and data memory which can be activated by an option byte setting (see the ROP option byte in section 10).

The read-out protection prevents reading and writing Flash program memory, data memory and option bytes via the debug module and SWIM interface. This protection is active in all device operation modes. Any attempt to remove the protection by overwriting the ROP option byte triggers a global erase of the program and data memory.

The ROP circuit may provide a temporary access for debugging or failure analysis. The temporary read access is protected by a user defined, 8-byte keyword stored in the option bytes area. This keyword must be entered via the SWIM interface to temporarily unlock the device.

If desired, the temporary unlock mechanism can be permanently disabled by the user through OPT6/NOPT6 option bytes.

The clock controller distributes the system clock coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.

5.5.1 Features

• Clock sources

– 16 MHz high-speed internal RC oscillator (HSI)

– 128 kHz low-speed internal RC (LSI)

– 1-16 MHz high-speed external crystal (HSE)

– Up to 16 MHz high-speed user-external clock (HSE user-ext)

• Reset : After reset the microcontroller restarts by default with an internal 2-MHz clock

(16 MHz/8). The clock source and speed can be changed by the application program as soon as the code execution starts.

• Safe clock switching : Clock sources can be changed safely on the fly in Run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

• Clock management : To reduce power consumption, the clock controller can stop the clock to the core or individual peripherals.

• Wakeup : In case the device wakes up from low-power modes, the internal RC oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device switches to the clock source that was selected before Halt mode was entered.

• Clock security system (CSS) : The CSS permits monitoring of external clock sources and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.

• Configurable main clock output (CCO) : This feature permits to output a clock signal for use by the application.

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Product overview

5.5.2 16 MHz high-speed internal RC oscillator (HSI)

• Default clock after reset 2 MHz (16 MHz/8)

• Fast wakeup time

STM8AF6246/48/66/68

User trimming

The register CLK_HSITRIMR with three trimming bits plus one additional bit for the sign permits frequency tuning by the application program. The adjustment range covers all possible frequency variations versus supply voltage and temperature. This trimming does not change the initial production setting.

For reason of compatibility with other devices from the STM8A family, a special mode with only two trimming bits plus sign can be selected. This selection is controlled with the HSITRIM0 bit in the option byte registers OPT3 and NOPT3.

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5.5.3

5.5.4

128 kHz low-speed internal RC oscillator (LSI)

Product overview

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the independent watchdog or the AWU wakeup timer.

In systems which do not need independent clock sources for the watchdog counters, the

128 kHz signal can be used as the system clock. This configuration has to be enabled by setting an option byte (OPT3/OPT3N, bit LSI_EN).

16 MHz high-speed external crystal oscillator (HSE)

The external high-speed crystal oscillator can be selected to deliver the main clock in normal Run mode. It operates with quartz crystals and ceramic resonators.

• Frequency range: 1 MHz to 16 MHz

• Crystal oscillation mode: preferred fundamental

• I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT

5.5.6

An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The frequency range is 0 to 16 MHz.

Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock failure.

In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is automatically selected with a frequency of 2 MHz (16 MHz/8).

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit

Periphera l clock

Bit

Peripheral clock

Bit

Peripheral clock

Bit

Peripheral clock

PCKEN17

PCKEN16

PCKEN15

PCKEN14

TIM1

TIM3

TIM2

TIM4

PCKEN13 LINUART PCKEN27 Reserved PCKEN23

PCKEN12 Reserved PCKEN26 Reserved PCKEN22

PCKEN11

PCKEN10

SPI

I 2 C

PCKEN25

PCKEN24

Reserved

PCKEN21

PCKEN20

ADC

AWU

Reserved

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Product overview

5.6 Low-power operating modes

STM8AF6246/48/66/68

For efficient power management, the application can be put in one of four different low power modes. Users can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

• Wait mode

In this mode, the CPU is stopped but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.

• Active-halt mode with regulator on

In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in Activehalt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

• Active-halt mode with regulator off

This mode is the same as Active-halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

• Halt mode

CPU and peripheral clocks are stopped, the main voltage regulator is powered off.

Wakeup is triggered by external event or reset.

In all modes the CPU and peripherals remain permanently powered on, the system clock is applied only to selected modules. The RAM content is preserved and the brown-out reset circuit remains activated.

5.7 Timers

The watchdog system is based on two independent timers providing maximum security to the applications. The watchdog timer activity is controlled by the application program or option bytes. Once the watchdog is activated, it cannot be disabled by the user program without going through reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application timing perfectly. The application software must refresh the counter before time-out and during a limited time window. If the counter is refreshed outside this time window, a reset is issued.

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Independent watchdog timer

The independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. If the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count.

5.7.3 Beeper

This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be output on a pin. This is useful when audible sounds without interference need to be generated for use in the application.

5.7.4

This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by the internal 128 kHz internal low-frequency RC oscillator or external clock.

LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.

Timer

TIM1

TIM2

TIM3

Advanced control and general purpose timers

STM8A devices described in this datasheet, contain up to three 16-bit advanced control and general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can be used either as input compare, output compare or PWM channel. These timers are named TIM1, TIM2 and TIM3.

Counter width

Table 3. Advanced control and general purpose timers

Counter type

Prescaler factor

Channels

Inverted outputs

Repetition counter trigger unit

16-bit Up/down 1 to 65536

16-bit Up

2 n n = 0 to 15

16-bit Up

2 n n = 0 to 15

None

Yes

External trigger

Yes

Break input

Yes

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Product overview STM8AF6246/48/66/68

TIM1: Advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and bridge driver.

• 16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.

• Four independent CAPCOM channels configurable as input capture, output compare,

PWM generation (edge and center aligned mode) and single pulse mode output

• Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In the present implementation it is possible to trigger the ADC upon a timer event.

• External trigger to change the timer behavior depending on external signals

• Break input to force the timer outputs into a defined state

• Three complementary outputs with adjustable dead time

• Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

TIM2 and TIM3: 16-bit general purpose timers

• 16-bit auto-reload up-counter

• 15-bit prescaler adjustable to fixed power of two ratios 1…32768

• Timers with three or two individually configurable CAPCOM channels

• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

Timer

TIM4

The typical usage of this timer (TIM4) is the generation of a clock tick.

Counter width

Counter type

8-bit Up

Table 4. TIM4

Prescaler factor

Channels

Inverted outputs

Repetition counter

2 n n = 0 to 7

0 None No trigger unit

External trigger

Break input

No No

• 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128

• Clock source: master clock

• Interrupt source: 1 x overflow/update

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5.8 Analog-to-digital converter (ADC)

Product overview

The STM8A products described in this datasheet contain a 10-bit successive approximation

ADC with up to 16 multiplexed input channels, depending on the package.

The ADC name differs between the datasheet and STM8S series and STM8AF series 8-bit microcontrollers reference manual (see

Table 5 ).

Table 5. ADC naming

Peripheral name in datasheet

Peripheral name in reference manual

(RM0016)

ADC ADC1

Note:

ADC features

• 10-bit resolution

• Single and continuous conversion modes

• Programmable prescaler: f

MASTER

divided by 2 to 18

• Conversion trigger on timer events and external events

• Interrupt generation at end of conversion

• Selectable alignment of 10-bit data in 2 x 8 bit result register

• Shadow registers for data consistency

• ADC input range: V

SSA

≤ V

DDA

• Analog watchdog

• Schmitt-trigger on analog inputs can be disabled to reduce power consumption

• Scan mode (single and continuous)

• Dedicated result register for each conversion channel

• Buffer mode for continuous conversion

An additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

The following sections give a brief overview of the communication peripheral. Some peripheral names differ between the datasheet and STM8S series and STM8AF series 8-bit microcontrollers reference manual (see

Table 6 ).

Table 6. Communication peripheral naming correspondence

Peripheral name in datasheet

Peripheral name in reference manual

(RM0016)

LINUART UART2

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Product overview

5.9.1

5.9.2

Serial peripheral interface (SPI)

STM8AF6246/48/66/68

The devices covered by this datasheet contain one SPI. The SPI is available on all the supported packages.

• Maximum speed: 10 Mbit/s or f

MASTER

/2 both for master and slave

• Full duplex synchronous transfers

• Simplex synchronous transfers on two lines with a possible bidirectional data line

• Master or slave operation - selectable by hardware or software

• CRC calculation

• 1 byte Tx and Rx buffer

• Slave mode/master mode management by hardware or software for both master and slave

• Programmable clock polarity and phase

• Programmable data order with MSB-first or LSB-first shifting

• Dedicated transmission and reception flags with interrupt capability

• SPI bus busy status flag

• Hardware CRC feature for reliable communication:

– CRC value can be transmitted as last byte in Tx mode

– CRC error checking for last received byte

Inter integrated circuit (I

C) interface

The devices covered by this datasheet contain one I 2 C interface. The interface is available on all the supported packages.

• I 2 C master features:

– Clock generation

– Start and stop generation

• I 2 C slave features:

– Programmable I 2 C address detection

– Stop bit detection

• Generation and detection of 7-bit/10-bit addressing and general call

• Supports different communication speeds:

– Standard speed (up to 100 kHz),

– Fast speed (up to 400 kHz)

• Status flags:

– Transmitter/receiver mode flag

– End-of-byte transmission flag

– I 2 C busy flag

• Error flags:

– Arbitration lost condition for master mode

– Acknowledgment failure after address/data transmission

– Detection of misplaced start or stop condition

– Overrun/underrun if clock stretching is disabled

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• Interrupt:

– Successful address/data communication

– Error condition

– Wakeup from Halt

• Wakeup from Halt on address detection in slave mode

5.9.3 Universal

(LINUART)

The devices covered by this datasheet contain one LINUART interface. The interface is available on all the supported packages. The LINUART is an asynchronous serial communication interface which supports extensive LIN functions tailored for LIN slave applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.2.

Detailed feature list:

LIN mode

Master mode:

• LIN break and delimiter generation

• LIN break and delimiter detection with separate flag and interrupt source for read back checking.

Slave mode:

• Autonomous header handling – one single interrupt per valid header

• Mute mode to filter responses

• Identifier parity error checking

• LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI) clock source

• Break detection at any time, even during a byte reception

• Header errors detection:

– Delimiter too short

– Synch field error

– Deviation error (if automatic resynchronization is enabled)

– Framing error in synch field or identifier field

– Header time-out

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Product overview STM8AF6246/48/66/68

UART mode

• Full duplex, asynchronous communications - NRZ standard format (mark/space)

• High-precision baud rate generator

– A common programmable transmit and receive baud rates up to f

MASTER

/16

• Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control

• Separate enable bits for transmitter and receiver

• Error detection flags

• Reduced power consumption mode

• Multi-processor communication - enter mute mode if address match does not occur

• Wakeup from mute mode (by idle line detection or address mark detection)

• Two receiver wakeup modes:

– Address bit (MSB)

– Idle line

The product features four different I/O types:

• Standard I/O 2 MHz

• Fast I/O up to 10 MHz

• High sink 8 mA, 2 MHz

• True open drain (I 2 C interface)

To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum slew rate. The rise and fall times are similar to those of standard I/Os.

The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitttrigger input stage on the analog I/Os can be disabled in order to reduce the device standby consumption.

STM8A I/Os are designed to withstand current injection. For a negative injection current of

4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to this feature, external protection diodes against current injection are no longer required.

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6 Pinouts and pin description

Pinouts and pin description

Figure 3. VFQFPN/LQFP 32-pin pinout

(HS) high sink capability.

NRST

OSCIN/PA1

OSCOUT/PA2

VCAP

DDIO

AIN12/PF4

32 31 30 29 28 27 26 25

9 10 11 12 13 14 1516

PC7/SPI_MISO

PC6/SPI_MOSI

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

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Pinouts and pin description

Figure 4. LQFP 48-pin pinout

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NRST

OSCIN/PA1

OSCOUT/PA2

SSIO_1

VCAP

DDIO_1

TIM2_CH3/PA3

PA4

PA5

PA6

48 47 46 45 44 43 42 41 40 39 38 37

7 30

8 29

9 28

10 27

13 14 15 16 17 18 19 20 21 22 23 24

PG1

PG0

PC7/SPI_MISO

PC6/SPI_MOSI

DDIO_2

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

C2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

(HS) high sink capability.

Type

Level

Output speed

Port and control configuration

Reset state

Table 7. Legend/abbreviation

I= input, O = output, S = power supply

Input CM = CMOS (standard for all I/Os)

Output HS = High sink (8 mA)

O1 = Standard (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

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STM8AF6246/48/66/68 Pinouts and pin description

Pin number

Table 8. STM8AF6246/48/66/68 (32 Kbyte) microcontroller pin description (1)(2)

Input Output

Pin name

Default alternate function

Alternate function after remap

[option bit]

2 2 PA1/OSCIN

1 NRST

3 PA2/OSCOUT

SSIO_1

5 4 V

6 5 VCAP

7 6 V

(3)

8 7 V

DDIO_1

8 PF4/AIN12

(4)(5)

PA3/TIM2_CH3

I/O X - Reset

I/O X X O1 X X Port A1 Resonator/crystal in

I/O X X X O1 X X Port A2 Resonator/crystal out -

S - I/O ground -

S -

I/O X X

O1 X

- Digital ground

- 1.8 V regulator capacitor

- Digital power supply

- I/O power supply

X Port F4 Analog input 12

I/O X X X O1 X X Port A3 Timer 2 - channel 3

TIM3_CH1

[AFR1]

10 PA4

11 PA5

12 PA6

13 9 V

DDA

14 10 V

SSA

15 PB7/AIN7

16 PB6/AIN6

11 PB5/AIN5

12 PB4/AIN4

13 PB3/AIN3

14 PB2/AIN2

15 PB1/AIN1

16 PB0/AIN0

PE7/AIN8

I/O X X X O3 X X Port A4

I/O X X X O3 X X Port A5

I/O X X X O3 X X Port A6

S - Analog power supply

S - Analog ground

I/O X X X O1 X X Port B7 Analog input 7

I/O X X X O1 X X Port B6 Analog input 6

I/O

O1 X

Port B5

Port B4

Port B3

Port B2

Port B1

Port B0

Port E7

Analog input 5

Analog input 4

Analog input 3

Analog input

Analog input 1

Analog input 0

Analog input 8

C_SDA

[AFR6]

C_SCL

[AFR6]

TIM1_ETR

[AFR5]

TIM1_NCC3

[AFR5]

TIM1_NCC2

[AFR5]

TIM1_NCC1

[AFR5]

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Pinouts and pin description STM8AF6246/48/66/68

Table 8. STM8AF6246/48/66/68 (32 Kbyte) microcontroller pin description (1)(2) (continued)

Pin number

Input Output

Pin name

Default alternate function

Alternate function after remap

[option bit]

24 PE6/AIN9

25 17 PE5/SPI_NSS

I/O X X X O1 X X Port E7 Analog input 9 -

I/O X X X O1 X X Port E5 SPI master/slave select -

26 18 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1 Timer 1 - channel 1 -

27 19 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2 Timer 1- channel 2

28 20 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3 Timer 1 - channel 3

29 21 PC4/TIM1_CH4 I/O X X X HS O3 X X Port C4 Timer 1 - channel 4

30 22 PC5/SPI_SCK I/O X X X O3 X X Port C5 SPI clock

31 V

32 V

SSIO_2

DDIO_2

23 PC6/SPI_MOSI

I/O

X -

- I/O ground

- I/O power supply

O3 X X Port C6

SPI master out/ slave in

34 24 PC7/SPI_MISO I/O X X X O3 X X Port C7 SPI master in/ slave out -

35 PG0 I/O X X O1 X X Port G0 -

36 PG1 I/O X X O1 X X Port G1 -

37 PE3/TIM1_BKIN I/O X X X O1 X X Port E3 Timer 1 - break input -

38 PE2/I

C_SDA

39 PE1/I

C_SCL

I/O X X O1 T

(6)

Port E2

Port E1 I

C data

C clock

40 PE0/CLK_CCO I/O X X X O3 X X Port E0

Configurable clock output

25 PD0/TIM3_CH2

26 PD1/SWIM

(7)

27 PD2/TIM3_CH1

28 PD3/TIM2_CH2

46 30

PD4/TIM2_CH1/

BEEP

PD5/

LINUART_TX

I/O X

I/O X

I/O

X HS O3 X

X HS O4 X

X HS O3 X

X O1 X

Port D0

Port D1

Port D2

Port D3

Port D4

Port D5

Timer 3 - channel 2

SWIM data interface

Timer 3 - channel 1

Timer 2 - channel 2

Timer 2 - channel 1

LINUART data transmit -

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

TIM2_CH3

[AFR1]

ADC_ETR

[AFR0]

BEEP output

[AFR7]

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STM8AF6246/48/66/68 Pinouts and pin description

Table 8. STM8AF6246/48/66/68 (32 Kbyte) microcontroller pin description (1)(2) (continued)

Pin number

Input Output

Pin name

Default alternate function

Alternate function after remap

[option bit]

47 31

PD6/

LINUART_RX

48 32 PD7/TLI

(8)

I/O X X X O1 X X Port D6 LINUART data receive -

I/O X X X O1 X X Port D7 Top level interrupt -

1. Refer to Table 7

for the definition of the abbreviations.

2. Reset state is shown in bold.

3. In Halt/Active-halt mode this pad behaves in the following way:

- the input/output path is disabled

- if the HSE clock is used for wakeup, the internal weak pull up is disabled

- if the HSE clock is off, internal weak pull up setting from corresponding OR bit is used

By managing the OR bit correctly, it must be ensured that the pad is not left floating during Halt/Active-halt.

4. On this pin, a pull-up resistor as specified in

Table 35

. I/O static characteristics is enabled during the reset phase of the product.

5. AIN12 is not selectable in ADC scan mode or with analog watchdog.

6. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up, and protection diode to V not implemented)

are

7. The PD1 pin is in input pull-up during the reset phase and after reset release.

8. If this pin is configured as interrupt pin, it will trigger the TLI.

As shown in the rightmost column of Table 8

, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits.

Refer to Section 9: Option bytes on page 44

. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the

GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual,

RM0016).

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Memory and register map

7 Memory and register map

STM8AF6246/48/66/68

Figure 5. Register and memory map of STM8A products

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STM8AF6246/48/66/68 Memory and register map

Table 9. Memory model for the devices covered in this datasheet

Flash program memory size

Flash program memory end address

RAM size

RAM end address

Stack roll-over address

32K

16K

0x00 0FFFF

0x00 0BFFF

2K 0x00 07FF 0x00 0600

In this section the memory and register map of the devices covered by this datasheet is described. For a detailed description of the functionality of the registers, refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual, RM0016.

Address Block

Table 10. I/O port hardware register map

Register label Register name

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

Port A

Port B

Port C

Port D

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Reset status

0x00

0xXX

(1)

0x00

0xXX (1)

0x00

0xXX

(1)

0x00

0xXX

(1)

0x00

0x02

0x00

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Memory and register map STM8AF6246/48/66/68

Table 10. I/O port hardware register map (continued)

Block Register label Register name Address

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5018

0x00 5019

0x00 501A

Port E

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

0x00 501B

0x00 501C

0x00 501D

0x00 501E

Port F PF_DDR

PF_CR1

PF_CR2

PG_ODR

0x00 501F

0x00 5020

0x00 5021

0x00 5022

Port G

1. Depends on the external circuitry.

PG_IDR

PG_DDR

PG_CR1

PG_CR2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

Port G data output latch register

Port G input pin value register

Port G data direction register

Port G control register 1

Port G control register 2

Reset status

0x00

0xXX

(1)

0x00

0xXX

(1)

0x00

0xXX (1)

Address

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

0x00 505F

0x00 5060 to

0x00 5061

0x00 5062

0x00 5063

0x00 5064

0x00 5065 to

0x00 509F

Block

Table 11. General hardware register map

Register label Register name

Flash

FLASH_CR1

FLASH_CR2

FLASH_NFPR

Flash control register 1

Flash control register 2

FLASH_NCR2 Flash complementary control register 2

FLASH_FPR Flash protection register

Flash complementary protection register

FLASH_IAPSR

Flash in-application programming status register

Reserved area (2 bytes)

FLASH_PUKR

Flash Program memory unprotection register

Reserved area (1 byte)

FLASH_DUKR Data EEPROM unprotection register

Reserved area (59 bytes)

Reset status

0x00

0xFF

0x00

0xFF

0x40

0x00

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STM8AF6246/48/66/68 Memory and register map

Address

0x00 50CD

0x00 50CE to 0x00 50D0

0x00 50D1

0x00 50D2

0x00 50D3 to

0x00 50DF

0x00 50E0

0x00 50E1

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50A0

0x00 50A1

0x00 50A2 to

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

0x00 50F1

0x00 50F2

Table 11. General hardware register map (continued)

Block

ITC

RST

CLK

WWDG

IWDG

AWU

Register label Register name

EXTI_CR1

EXTI_CR2

External interrupt control register 1

External interrupt control register 2

RST_SR

Reserved area (17 bytes)

Reset status register

Reserved area (12 bytes)

AWU_CSR1

AWU_APR

AWU_TBR

Reserved area (13 bytes)

AWU control/status register 1

AWU asynchronous prescaler buffer register

AWU timebase selection register

Reset status

0x00

0xXX

(1)

CLK_ICKR

CLK_ECKR

Internal clock control register

External clock control register

Reserved area (1 byte)

0x01

0x00

CLK_SWR

CLK_SWCR

CLK_CKDIVR

CLK_PCKENR1

CLK_CSSR

CLK_CCOR

Clock master switch register

Clock switch control register

Clock divider register

Peripheral clock gating register 1

Clock security system register

Configurable clock control register

CLK_PCKENR2 Peripheral clock gating register 2

Reserved area (1 byte)

CLK_HSITRIMR HSI clock calibration trimming register

CLK_SWIMCCR SWIM clock control register

0x00

0bXXXX

XXX0

0xE1

0xXX

0x18

0xFF

0x00

0xFF

Reserved area (3 bytes)

0x7F

0x7F WWDG_WR WWDR window register

IWDG_KR

IWDG_PR

IWDG_RLR

Reserved area (13 bytes)

IWDG key register

IWDG prescaler register

IWDG reload register

0xXX

(2)

0x00

0xFF

0x00

0x3F

0x00

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Memory and register map STM8AF6246/48/66/68

Address

0x00 50F3

0x00 50F4 to

0x00 50FF

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 521E to

0x00 523F

Table 11. General hardware register map (continued)

Block Register label Register name

BEEP

SPI

I2C

BEEP_CSR BEEP control/status register

Reserved area (12 bytes)

SPI_CR1

SPI_CR2

SPI_ICR

SPI_SR

SPI_DR

SPI_CRCPR

SPI_RXCRCR

SPI_TXCRCR

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

SPI data register

SPI CRC polynomial register

SPI Rx CRC register

SPI Tx CRC register

Reserved area (8 bytes)

I2C_CR1

I2C_CR2

I2C_FREQR

I2C_OARL

I2C_OARH

I2C_DR

I2C_SR1

I2C_SR2

I2C_SR3

I2C_ITR

I2C_CCRL

I2C_CCRH

I2C_TRISER

I2C control register 1

I2C control register 2

I2C frequency register

I2C own address register low

I2C own address register high

Reserved area (1 byte)

I2C data register

I2C status register 1

I2C status register 2

I2C status register 3

I2C interrupt control register

I2C clock control register low

I2C clock control register high

I2C TRISE register

Reserved area (24 bytes)

Reset status

0x1F

0x00

0x02

0x00

0x07

0xFF

0x00

0x02

0x00

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STM8AF6246/48/66/68 Memory and register map

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

Table 11. General hardware register map (continued)

Block Register label Register name Address

0x00 5240

0x00 5241

0x00 5242

0x00 5243

0x00 5244

0x00 5245

0x00 5246

0x00 5247

0x00 5248

0x00 5249

0x00 524A to

0x00 524F

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

LINUART

TIM1

0x00 525C

UART2_SR

UART2_DR

UART2_BRR1

UART2_BRR2

UART2_CR1

UART2_CR2

UART2_CR3

UART2_CR4

UART2_CR6

LINUART status register

LINUART data register

LINUART baud rate register 1

LINUART baud rate register 2

LINUART control register 1

LINUART control register 2

LINUART control register 3

LINUART control register 4

Reserved

LINUART control register 6

Reserved area (6 bytes)

TIM1_CR1

TIM1_CR2

TIM1_SMCR

TIM1_ETR

TIM1_IER

TIM1 control register 1

TIM1 control register 2

TIM1 slave mode control register

TIM1 external trigger register

TIM1 Interrupt enable register

TIM1_SR1

TIM1_SR2

TIM1_EGR

TIM1 status register 1

TIM1 status register 2

TIM1 event generation register

TIM1_CCMR1 TIM1 capture/compare mode register 1

TIM1_CCMR2 TIM1 capture/compare mode register 2

TIM1_CCMR3 TIM1 capture/compare mode register 3

TIM1_CCMR4 TIM1 capture/compare mode register 4

TIM1_CCER1

TIM1 capture/compare enable register

TIM1_CCER2

TIM1 capture/compare enable register

TIM1 counter high TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1_PSCRL

TIM1 counter low

TIM1 prescaler register high

TIM1 prescaler register low

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1 auto-reload register high

TIM1 auto-reload register low

TIM1 repetition counter register

Reset status

0xC0

0xXX

0x00

0xFF

0x00

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Memory and register map STM8AF6246/48/66/68

Address

0x00 5265

0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C

0x00 526D

0x00 526E

0x00 526F

0x00 5270 to

0x00 52FF

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307

0x00 5308

0x00 5309

0x00 530A

0x00 530B

00 530C0x

0x00 530D

0x00 530E

0x00 530F

0x00 5310

0x00 5311

0x00 5312

0x00 5313

Table 11. General hardware register map (continued)

Block

TIM1

TIM2

Register label Register name

TIM1_CCR1L TIM1 capture/compare register 1 low

TIM1_CCR2H TIM1 capture/compare register 2 high

TIM1_CCR2L TIM1 capture/compare register 2 low

TIM1_CCR3H TIM1 capture/compare register 3 high

TIM1_CCR3L TIM1 capture/compare register 3 low

TIM1_CCR4H TIM1 capture/compare register 4 high

TIM1_CCR4L

TIM1_BKR

TIM1 capture/compare register 4 low

TIM1 break register

TIM1_DTR

TIM1_OISR

TIM1 dead-time register

TIM1 output idle state register

Reserved area (147 bytes)

TIM2_CR1

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2 control register 1

TIM2 interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2_EGR TIM2 event generation register

TIM2_CCMR1 TIM2 capture/compare mode register 1

TIM2_CCMR2 TIM2 capture/compare mode register 2

TIM2_CCMR3 TIM2 capture/compare mode register 3

TIM2_CCER1

TIM2 capture/compare enable register

TIM2_CCER2

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2 capture/compare enable register

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2_ARRL TIM2 auto-reload register low

TIM2_CCR1H TIM2 capture/compare register 1 high

TIM2_CCR1L TIM2 capture/compare register 1 low

TIM2_CCR2H

TIM2_CCR2L

TIM2 capture/compare reg. 2 high

TIM2 capture/compare register 2 low

TIM2_CCR3H TIM2 capture/compare register 3 high

0x00

0xFF

0x00

Reset status

0x00

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Address

0x00 5314

0x00 5315 to

0x00 531F

0x00 5320

0x00 5321

0x00 5322

0x00 5323

0x00 5324

0x00 5325

0x00 5326

0x00 5327

0x00 5328

0x00 5329

0x00 532A

0x00 532B

0x00 532C

0x00 532D

0x00 532E

0x00 532F

0x00 5330

0x00 5331 to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347 to

0x00 53DF

Table 11. General hardware register map (continued)

Block Register label Register name

TIM2

TIM3

TIM4

TIM2_CCR3L TIM2 capture/compare register 3 low

Reserved area (11 bytes)

TIM3_CR1

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3 control register 1

TIM3 interrupt enable register

TIM3 status register 1

TIM3 status register 2

TIM3_EGR TIM3 event generation register

TIM3_CCMR1 TIM3 capture/compare mode register 1

TIM3_CCMR2 TIM3 capture/compare mode register 2

TIM3_CCER1

TIM3_CNTRH

TIM3 capture/compare enable register

TIM3 counter high

TIM3_CNTRL TIM3 counter low

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3 prescaler register

TIM3 auto-reload register high

TIM3 auto-reload register low

TIM3_CCR1H TIM3 capture/compare register 1 high

TIM3_CCR1L TIM3 capture/compare register 1 low

TIM3_CCR2H TIM3 capture/compare register 2 high

TIM3_CCR2L TIM3 capture/compare register 2 low

Reserved area (15 bytes)

TIM4_CR1

TIM4_IER

TIM4_SR

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 control register 1

TIM4 interrupt enable register

TIM4 status register

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register

Reserved area (185 bytes)

Reset status

0x00

0xFF

0x00

0xFF

0x00

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Memory and register map STM8AF6246/48/66/68

Address

0x00 53F1

0x00 53F2

0x00 53F3

0x00 53F4 to

0x00 53FF

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 53E0

0x00 53E1

0x00 53E2

0x00 53E3

0x00 53E4

0x00 53E5

0x00 53E6

0x00 53E7

0x00 53E8

0x00 53E9

0x00 53EA

0x00 53EB

0x00 53EC

0x00 53ED

0x00 53EE

0x00 53EF

0x00 53F0

0x00 5406

0x00 5407

0x00 5408

0x00 5409

0x00 540A

Table 11. General hardware register map (continued)

Block Register label Register name

ADC

ADC _DB0RH

ADC _DB0RL

ADC _DB1RH

ADC _DB1RL

ADC _DB2RH

ADC _DB2RL

ADC _DB3RH

ADC _DB3RL

ADC _DB4RH

ADC _DB4RL

ADC _DB5RH

ADC _DB5RL

ADC _DB6RH

ADC _DB6RL

ADC _DB7RH

ADC _DB7RL

ADC _DB8RH

ADC _DB8RL

ADC _DB9RH

ADC _DB9RL

ADC data buffer register 0 high

ADC data buffer register 0 low

ADC data buffer register 1 high

ADC data buffer register 1 low

ADC data buffer register 2 high

ADC data buffer register 2 low

ADC data buffer register 3 high

ADC data buffer register 3 low

ADC data buffer register 4 high

ADC data buffer register 4 low

ADC data buffer register 5 high

ADC data buffer register 5 low

ADC data buffer register 6 high

ADC data buffer register 6 low

ADC data buffer register 7 high

ADC data buffer register 7 low

ADC data buffer register 8 high

ADC data buffer register 8 low

ADC data buffer register 9 high

ADC data buffer register 9 low

ADC _CSR

ADC_CR1

ADC_CR2

ADC_CR3

ADC_DRH

ADC_DRL

ADC_TDRH

ADC_TDRL

ADC _HTRH

ADC_HTRL

ADC _LTRH

Reserved area (12 bytes)

ADC control/status register

ADC configuration register 1

ADC configuration register 2

ADC configuration register 3

ADC data register high

ADC data register low

ADC Schmitt trigger disable register high

ADC Schmitt trigger disable register low

ADC high threshold register high

ADC high threshold register low

ADC low threshold register high

Reset status

0x00

0xXX

0x00

0xFF

0x03

0x00

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Table 11. General hardware register map (continued)

Block Register label Register name Address

0x00 540B

0x00 540C

0x00 540D

0x00 540E

0x00 540F

0x00 5410 to

0x00 541F

ADC

ADC_LTRL

ADC _AWSRH

ADC_AWSRL

ADC _AWCRH

ADC _AWCRL

1. Depends on the previous reset source.

2. Write only register.

ADC low threshold register low

ADC watchdog status register high

ADC watchdog status register low

ADC watchdog control register high

ADC watchdog control register low

Reserved area (16 bytes)

Reset status

0x00

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76 to

0x00 7F79

0x00 7F80

CPU

(1)

CPU

ITC

SWIM

Address

Table 12. CPU/SWIM/debug module/interrupt controller registers

Block Register label Register name

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

PCE

PCH

PCL

SPH

SPL

SWIM_CSR

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 bytes)

Global configuration register

Interrupt software priority register 1

Interrupt software priority register 2

Interrupt software priority register 3

Interrupt software priority register 4

Interrupt software priority register 5

Interrupt software priority register 6

Reserved area (4 bytes)

SWIM control status register

0x00

0xFF

0x00

Reset status

0x00

0x80

0x00

0x17 (2)

0xFF

0x28

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Memory and register map STM8AF6246/48/66/68

Address

Table 12. CPU/SWIM/debug module/interrupt controller registers (continued)

Block Register label Register name

Reset status

0x00 7F81 to

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

Reserved area (15 bytes)

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM debug module control register 1

DM debug module control register 2

DM debug module control/status register 1

DM debug module control/status register 2

DM enable function register

0x00 7F9B to

0x00 7F9F

Reserved area (5 bytes)

1. Accessible by debug module only

2. Product dependent value, see Figure 5: Register and memory map of STM8A products .

0xFF

0x00

0x10

0x00

0xFF

Address

0x00 5800

0x00 5801

0x00 5802

0x00 5803

0x00 5804

0x00 5805

0x00 5806

0x00 5807

0x00 5808

Block

TMU

Table 13. Temporary memory unprotection registers

Register label Register name

TMU_K1

TMU_K2

TMU_K3

TMU_K4

TMU_K5

TMU_K6

TMU_K7

TMU_K8

TMU_CSR

Temporary memory unprotection key register 1

Temporary memory unprotection key register 2

Temporary memory unprotection key register 3

Temporary memory unprotection key register 4

Temporary memory unprotection key register 5

Temporary memory unprotection key register 6

Temporary memory unprotection key register 7

Temporary memory unprotection key register 8

Temporary memory unprotection control and status register

Reset status

0x00

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STM8AF6246/48/66/68 Interrupt table

Priority

Source block

Table 14. STM8A interrupt table

Description

Interrupt vector address

Wakeup from Halt

Comments

AWU

Clock controller

MISC

Main clock controller

Ext interrupt E0

Ext interrupt E1

MISC

10 SPI

Ext interrupt E2

Ext interrupt E3

MISC

Reserved

(1)

Ext interrupt E4

Reserved (1) -

Timer 1

End of transfer

Update/overflow/ trigger/break

Capture/compare

Reset

TRAP

TLI

Timer 2

Timer 3

Reset 0x00 8000

SW interrupt 0x00 8004

External top level interrupt 0x00 8008

Auto-wakeup from Halt 0x00 800C

Update/overflow

Capture/compare

Update/overflow

0x00 8010

0x00 8014

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

16 Timer 3

17 Reserved

(1)

18 Reserved

(1)

19 I

LINUART

22 ADC

23 Timer 4

EEPROM

Capture/compare

C interrupts

Tx complete/error

Receive data full reg.

End of conversion

Update/overflow

End of Programming/

Write in not allowed area

0x00 8048

0x00 8054

0x00 8058

0x00 805C

0x00 8060

0x00 8064

0x00 8068

Yes

User RESET vector

Port A interrupts

Port B interrupts

Port C interrupts

Port D interrupts

Port E interrupts

1. All reserved and unused interrupts must be initialized with ‘IRET’ for robust programming.

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Option bytes STM8AF6246/48/66/68

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in Table 15: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the

ROP and UBC options that can only be toggled in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Table 15. Option bytes

Option bits

Addr.

Option name

Option byte no.

7 6 5 4 3 2 1 0

0x00

4800

Read-out protection

(ROP)

OPT0

ROP[7:0]

0x00

4808

0x00

4809

0x00

480A

0x00

4805

0x00

4806

0x00

4807

0x00

4801

0x00

4802

0x00

4803

0x00

4804

User boot code

(UBC)

OPT1

NOPT1

Reserved

Alternate function remapping

(AFR)

OPT2

NOPT2

AFR7

NAFR

AFR6

NAFR

AFR5

NAFR

AFR4

NAFR

Watchdog option

OPT3

NOPT3

Reserved

16MHZ

TRIM0

N16MHZ

TRIM0

Clock option

HSE clock startup

OPT4

NOPT4

OPT5

NOPT5

Reserved

NAFR

LSI

_EN

NLSI

_EN

EXT

CLK

BC[5:0

AFR3

HSECNT[7:0]

BC[5:0

NHSECNT[7:0]

]

AFR2 AFR1 AFR0

NAFR

IWDG

_HW

NIWDG

_HW

CKAWU

SEL

WWDG

_HW

WWDG

_HALT

NWWD

G_HW

PRS

NWWG

_HALT

PRS

NCKAW

USEL

NPR

SC1

NPR

SC0

Factory default setting

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

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STM8AF6246/48/66/68 Option bytes

Addr.

Option name

Option byte no.

Table 15. Option bytes (continued)

6 5 4

Option bits

3 2 1 0

Factory default setting

0x00

4817

0x00

4818

0x00

4819 to

487D

0x00

487E

0x00

487F

0x00

4814

0x00

4815

0x00

4816

0x00

480F

0x00

4810

0x00

4811

0x00

4812

0x00

4813

0x00

480B

0x00

480C

TMU

0x00

480D Flash wait

0x00

480E states

TMU

Bootloader

(1)

OPT6

NOPT6

OPT7

NOPT7

OPT8

OPT9

OPT10

OPT11

OPT12

OPT13

OPT14

OPT15

OPT16

OPT17

NOPT17

TMU[3:0]

NTMU[3:0]

Reserved

TMU_KEY 1 [7:0]

TMU_KEY 2 [7:0]

TMU_KEY 3 [7:0]

TMU_KEY 4 [7:0]

TMU_KEY 5 [7:0]

TMU_KEY 6 [7:0]

TMU_KEY 7 [7:0]

TMU_KEY 8 [7:0]

TMU_MAXATT [7:0]

Reserved

BL [7:0]

NBL[7:0]

WAIT

STATE

NWAIT

STATE

0x00

0xFF

0x00

0xFF

0x00

0xC7

0x00

0xFF

1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no effect on EMC reset.

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Option bytes STM8AF6246/48/66/68

Option byte no.

OPT0

OPT1

OPT2

Table 16. Option byte description

Description

ROP[7:0]: Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.

UBC[5:0]: User boot code area

0x00: No UBC, no write-protection

0x01: Page 0 to 1 defined as UBC, memory write-protected

0x02: Page 0 to 3 defined as UBC, memory write-protected

0x03 to 0x3F: Pages 4 to 63 defined as UBC, memory write-protected

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM write protection for more details.

AFR7: Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CH1

1: Port D4 alternate function = BEEP

AFR6: Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I

C_SDA, port B4 alternate function =

I 2 C_SCL.

AFR5: Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0.

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N.

AFR4: Alternate function remapping option 4

Reserved, bit must be kept at “0”

AFR3: Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = TIM1_BKIN

AFR2: Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1: Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CH3, port D2 alternate function

TIM3_CH1.

1: Port A3 alternate function = TIM3_CH1, port D2 alternate function

TIM2_CH3.

AFR0: Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CH2

1: Port D3 alternate function = ADC_ETR

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STM8AF6246/48/66/68 Option bytes

Option byte no.

OPT3

OPT4

OPT5

OPT6

OPT7

OPT8

OPT9

OPT10

OPT11

Table 16. Option byte description (continued)

Description

HSITRIM: Trimming option for 16 MHz internal RC oscillator

0: 3-bit on-the-fly trimming (compatible with devices based on the 128K silicon)

1: 4-bit on-the-fly trimming

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG independent watchdog activated by software

1: IWDG independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on Halt

0: No reset generated on Halt if WWDG active

1: Reset generated on Halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto-wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for AWU

PRSC[1:0]: AWU clock prescaler

00: Reserved

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilization time to 0.5, 8, 128, and 2048 HSE cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and 0x00.

TMU [3:0]: Enable temporary memory unprotection

0101: TMU disabled (permanent ROP).

Any other value: TMU enabled.

Reserved

TMU_KEY 1 [7:0]: Temporary unprotection key 0

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 2 [7:0]: Temporary unprotection key 1

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 3 [7:0]: Temporary unprotection key 2

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 4 [7:0]: Temporary unprotection key 3

Temporary unprotection key: Must be different from 0x00 or 0xFF

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Option bytes STM8AF6246/48/66/68

Option byte no.

OPT12

OPT13

OPT14

OPT15

OPT16

OPT17

Table 16. Option byte description (continued)

Description

TMU_KEY 5 [7:0]: Temporary unprotection key 4

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 6 [7:0]: Temporary unprotection key 5

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 7 [7:0]: Temporary unprotection key 6

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 8 [7:0]: Temporary unprotection key 7

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_MAXATT [7:0]: TMU access failure counter

TMU_MAXATT can be initialized with the desired value only if TMU is disabled (TMU[3:0]=0101 in OPT6 option byte).

When TMU is enabled, any attempt to temporary remove the readout protection by using wrong key values increments the counter.

When the option byte value reaches 0x08, the Flash memory and data

EEPROM are erased.

BL [7:0]: Bootloader enable

If this option byte is set to 0x55 (complementary value 0xAA) the bootloader program is activated also in case of a programmed code memory

(for more details, see the bootloader user manual, UM0560).

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Unless otherwise specified, all voltages are referred to V

10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

Amax

(given by the selected temperature range).

= -40 °C, T

= 25 °C, and T

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production.

Unless otherwise specified, typical data are based on T

A given only as design guidelines and are not tested.

= 25 °C, V

= 5.0 V. They are

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 6 .

Figure 6. Pin loading conditions

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Electrical characteristics STM8AF6246/48/66/68

10.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7

Figure 7. Pin input voltage

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10.2 Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

DDx

- V

Table 17. Voltage characteristics

Ratings

Supply voltage (including V

DDA and

DDIO

)

(1)

Input voltage on true open drain pins (PE1, PE2)

(2)

Input voltage on any other pin

(2)

DDx

- V

| Variations between different power pins

SSx

- V

| Variations between all the different ground pins

Min

-0.3

Max

6.5

- 0.3

6.5

- 0.3

+ 0.3

ESD

Electrostatic discharge voltage

Unit

V mV see Absolute maximum ratings

(electrical sensitivity) on page 76

1. All power (V , V external power supply

, V

DDA

) and ground (V

, V

SSIO

, V

SSA

) pins must always be connected to the

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V injection is induced by V

> V

maximum is respected. If V

while a negative injection is induced by V

< V

maximum

value. A positive

. For true open-drain

maximum must always be respected

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Symbol

Table 18. Current characteristics

Ratings Max.

Unit

VDDIO

VSSIO

Total current into V

DDIO power lines (source)

(1)(2)(3)

Total current out of V

SS IO ground lines (sink)

(1)(2)(3)

Output current sunk by any I/O and control pin

100

IO mA

Output current source by any I/Os and control pin -20

INJ(PIN)

(4)

INJ(TOT)

Injected current on any pin

Sum of injected currents

±10

1. All power (V external supply.

, V

DDIO

, V

DDA

) and ground (V

, V

SSIO

, V

SSA

) pins must always be connected to the

2. The total limit applies to the sum of operation and injected currents.

3. V includes the sum of the positive injection currents. V currents.

SSIO

includes the sum of the negative injection

4. This condition is implicitly insured if V maximum is respected. If V injection current must be limited externally to the I while a negative injection is induced by V current allowed and the corresponding V

INJ(PIN)

maximum cannot be respected, the

value. A positive injection is induced by V

> V

< V

. For true open-drain pads, there is no positive injection

maximum must always be respected.

Table 19. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range

Maximum junction temperature

-65 to 150

160

Symbol

Table 20. Operating lifetime (1)

Ratings Value

OLF Conforming to AEC-Q100 rev G

-40 to 125 °C

-40 to 150 °C

1. For detailed mission profile analysis, please contact the nearest local ST Sales Office.

°C

Unit

Grade 1

Grade 0

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Electrical characteristics STM8AF6246/48/66/68

Symbol

Table 21. General operating conditions

Parameter Conditions Min Max Unit f

CPU

DD/

DDIO

CAP

(1)

Internal CPU clock frequency T

= -40 °C to 150 °C

Standard operating voltage -

EXT

: capacitance of external capacitor

ESR of external capacitor

ESL of external capacitor at 1 MHz

(2)

Power dissipation (all temperature ranges)

Ambient temperature

Junction temperature range

LQFP32

VFQFPN32

LQFP48

Suffix A

Suffix C

Suffix D

Suffix A

Suffix C

Suffix D

3.0

470

-40

5.5

3300

125

150

0.3

200

130

155

MHz

V nF

Ω nH mW

°C

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

2. This frequency of 1 MHz as a condition for V

CAP

parameters is given by design of internal regulator.

Figure 8. f

CPUmax

versus V

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Symbol

Table 22. Operating conditions at power-up/power-down

Parameter Conditions Min Typ Max Unit

V t t

VDD

TEMP

IT+

IT-

HYS(BOR)

rise time rate

fall time rate

Reset release delay

Reset generation delay

Power-on reset threshold

(2) (3)

Brown-out reset threshold

Brown-out reset hysteresis

rising

falling

(1)

2.65

2.58

2.8

2.73

(1)

∞

1.7

2.95

2.88

µs/V ms

µs

V mV

1. Guaranteed by design, not tested in production

2. If V is below 3 V, the code execution is guaranteed above the V kept. The EEPROM programming sequence must not be initiated.

IT-

and V

IT+

thresholds. RAM content is

3. There is inrush current into V depends from C

present after device power on to charge C

EXT

EXT capacitor value. For example, a C

EXT capacitor. This inrush energy

of 1 μ F requires Q=1 μ F x 1.8V = 1.8 μ C.

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Electrical characteristics STM8AF6246/48/66/68

10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C

CAP

pin. C

EXT to less than 15 nH.

EXT

to the

is specified in

Table 21 . Care should be taken to limit the series inductance

Figure 9. External capacitor C

EXT

(6/

(65

5/HDN

06Y9

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

10.3.2 Supply current characteristics

The current consumption is measured as described in Figure 6 on page 49

and Figure 7 on page 50 .

If not explicitly stated, general conditions of temperature and voltage apply.

Symbol

Table 23. Total current consumption in Run, Wait and Slow mode.

General conditions for V

apply, T

= − 40 to 150 °C

Parameter Conditions Typ Max Unit

DD(RUN)

(1)

DD(RUN)

(1)

Supply current in

Run mode

Supply current in

Run mode

All peripherals clocked, code executed from Flash program memory,

HSE external clock

(without resonator)

All peripherals clocked, code executed from RAM and EEPROM, HSE external clock

(without resonator) f f

CPU

= 16 MHz

= 8 MHz f

CPU

= 4 MHz f

CPU

= 2 MHz f

CPU

= 16 MHz f

CPU

= 8 MHz f

CPU

= 4 MHz f

CPU

= 2 MHz f

CPU

= 16 MHz f

CPU

= 8 MHz

DD(WFI)

(1)

Supply current in

Wait mode

CPU stopped, all peripherals off, HSE external clock f

CPU

= 4 MHz

DD(SLOW)

(1)

Supply current in

Slow mode f

CPU

scaled down, all peripherals off, code executed from

RAM f

CPU

= 2 MHz

Ext. clock 16 MHz f

CPU

= 125 kHz

LSI internal RC f

CPU

= 128 kHz

1. The current due to I/O utilization is not taken into account in these values.

2. Values not tested in production. Design guidelines only.

7.4

4.0

1.4

1.0

1.65

1.15

2.4

1.5

3.7

2.2

0.90

0.80

1.50

7.4

(2)

4.1

(2)

2.5

5.0

3.0

(2)

2.0

(2)

1.5

2.5

1.9

(2)

1.6

(2)

1.5

1.95

1.80

(2) mA

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Table 24. Total current consumption in Halt and Active-halt modes.

General conditions for V

apply, T

= − 40 to 55 °C

Conditions

Symbol

DD(H)

DD(AH)

Parameter

Supply current in Halt mode

Supply current in Active-halt mode with regulator on

Supply current in Active-halt mode with regulator off

Main voltage regulator

(MVR)

(1)

Off

Flash mode

(2)

Powerdown

Clock source and specific temperature condition

Clocks stopped

Clocks stopped,

= 25 °C

Ext. clock 16 MHz f

MASTER

= 125 kHz

LSI clock 128 kHz

LSI clock 128 kHz,

= 25 °C t

WU(AH)

Wakeup time from Activehalt mode with regulator on

Wakeup time from Activehalt mode with regulator off

Off

Operating mode

1. Configured by the REGAH bit in the CLK_ICKR register.

2. Configured by the AHALT bit in the FLASH_CR1 register.

3. Data based on characterization results. Not tested in production.

= -40 to 150 °C

Current consumption for on-chip peripherals

Typ

770 900

(3)

150 230

(3)

25 42

(3)

Max Unit

(3)

µA

µs

Table 25. Oscillator current consumption

Symbol Parameter Conditions Typ Max

(1) Unit

DD(OSC)

HSE oscillator current consumption

(2)

Quartz or ceramic resonator,

CL = 33 pF

= 5 V

Quartz or ceramic resonator,

CL = 33 pF

= 3.3 V f f f f f f

OSC

= 24 MHz

= 16 MHz

= 8 MHz

= 24 MHz

= 16 MHz

= 8 MHz

0.6

0.57

0.5

0.25

0.18

2.0

1.0

(3)

(3) mA

1. During startup, the oscillator current consumption may reach 6 mA.

2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small

R m

value. Refer to crystal manufacturer for more details

3. Informative data.

DocID14952 Rev 11

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Electrical characteristics STM8AF6246/48/66/68

Symbol

Table 26. Programming current consumption

Parameter Conditions Typ

DD(PROG)

Programming current

= 5 V, -40 °C to 150 °C, erasing and programming data or Flash program memory

1.0

Max

1.7

Unit mA

Symbol

Table 27. Typical peripheral current consumption V

= 5.0 V

(1)

Parameter

Typ. f master

2 MHz

Typ. f master

16 MHz

DD(TIM1)

DD(TIM2)

DD(TIM3)

DD(TIM4)

DD(LINUART)

DD(SPI)

DD(I 2 C)

DD(AWU)

DD(TOT_DIG)

TIM1 supply current

(2)

TIM2 supply current

(2)

TIM3 supply current

(2)

TIM4 supply current

(2)

LINUART supply current

(2)

SPI supply current

(2)

C supply current

(2)

AWU supply current

(2)

All digital peripherals on

0.03

0.02

0.01

0.004

0.03

0.01

0.02

0.003

0.22

0.23

0.12

0.1

0.03

0.11

0.04

0.06

0.02

DD(ADC)

ADC supply current when converting

(3)

0.93

0.95

1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital supply voltage, the values are similar in the full supply voltage range.

2. Data based on a differential I

measurement between no peripheral clocked and a single active peripheral. This measurement does not include the pad toggling consumption.

3. Data based on a differential I conversions.

measurement between reset configuration and continuous A/D

Current consumption curves

Unit mA

Figure 10

to Figure 15

show typical current consumption measured with code executing in

RAM.

Figure 10. Typ. I

CPU

DD(RUN)HSE

vs. V

= 16 MHz, peripheral = on

2.5

3 3.5

25°C

85°C

125°C

5.5

6 4 4.5

[V]

Figure 11. Typ. I

@ V

DD(RUN)HSE

vs. f

CPU

= 5.0 V, peripheral = on

0 5 25

25°C

85°C

125°C

30 10 15 fcpu [MHz]

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STM8AF6246/48/66/68

Figure 12. Typ. I

@ f

CPU

DD(RUN)HSI

vs. V

= 16 MHz, peripheral = off

2.5

3.5

4.5

VDD [V]

5.5

25°C

85°C

125°C

6.5

Figure 14. Typ. I

@ V

DD(WFI)HSE

vs. f

CPU

= 5.0 V, peripheral = on

0 5 10 15 fcpu [MHz]

20 25

25°C

85°C

125°C

Electrical characteristics

Figure 13. Typ. I

@ f

CPU

DD(WFI)HSE

vs. V

= 16 MHz, peripheral = on

2.5

3.5

4.5

VDD [V]

5.5

25°C

85°C

125°C

6.5

Figure 15. Typ. I

DD(WFI)HSI

@ f

CPU

vs. V

= 16 MHz, peripheral = off

2.5

1.5

0.5

2.5

3 3.5

5 5.5

25°C

85°C

125°C

6 4 4.5

[V]

HSE user external clock

Subject to general operating conditions for V

and T

Symbol

Table 28. HSE user external clock characteristics

Parameter Conditions Min f

HSE_ext

HSEdHL

HSEH

HSEL

User external clock source frequency

Comparator hysteresis

OSCIN input pin high level voltage

OSCIN input pin low level voltage

LEAK_HSE

OSCIN input leakage current

is -40 to

150 °C

< V

(1)

0.1 x V

0.7 x V

-1

1. In CSS is used, the external clock must have a frequency above 500 kHz.

Typ

Max

0.3 x V

Unit

MHz

µA

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Electrical characteristics

Figure 16. HSE external clock source

STM8AF6246/48/66/68

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HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 16 MHz.

All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Symbol

Table 29. HSE oscillator characteristics

Parameter Conditions Min Typ Max t

R g

(1) m

SU(HSE)

(2)

Feedback resistor

Recommended load capacitance

Oscillator transconductance

Startup time

is stabilized

220

2.8

1. The oscillator needs two load capacitors, C

* C

)/(C

+ C

). If C

= C

, C load

= C

and C

, to act as load for the crystal. The total load capacitance (C load

) is

/ 2. Some oscillators have built-in load capacitors, C

and C

2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 16 MHz oscillation is reached. It can vary with the crystal type that is used.

Unit k Ω pF mA/V

58/99

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STM8AF6246/48/66/68 Electrical characteristics

Figure 17. HSE oscillator circuit diagram

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HSE oscillator critical g

formula

The crystal characteristics have to be checked with the following formula: g m

» g mcrit where g mcrit

can be calculated with the crystal parameters as follows: g mcrit

= ( 2 × Π × f

HSE )

× R m

(

C m m m

: Notional resistance (see crystal specification)

: Notional inductance (see crystal specification)

: Notional capacitance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

= C

= C: Grounded external capacitance

10.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for V

and T

High speed internal RC oscillator (HSI)

)

Symbol f

HSI

Table 30. HSI oscillator characteristics

Parameter Conditions

Frequency -

Min

Typ

Max

Unit

MHz

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Electrical characteristics STM8AF6246/48/66/68

Symbol

ACC

HS t su(HSI)

Table 30. HSI oscillator characteristics

Parameter Conditions Min

HSI oscillator user trimming accuracy

HSI oscillator accuracy

(factory calibrated)

Trimmed by the application for any V

DD conditions

and T

3.0 V ≤

-40 °C ≤

≤

5.5 V,

150 °C

3.0V

≤

-40°C ≤

≤

5.5V,

125 °C

-1

(1)

-0.5

(1)

-5

-2.5

(2)

HSI oscillator wakeup time

1. Depending on option byte setting (OPT3 and NOPT3)

2. These values are guaranteed for STM8AF62x6ITx order codes only.

3. Guaranteed by characterization, not tested in production

Figure 18. Typical HSI frequency vs V

Typ

2.5

(2)

(3)

Max

(1)

0.5

(1)

Unit

µs

-1%

-2%

-3%

2.5

-40°C

25°C

85°C

125°C

3 3.5

[V]

4.5

5 5.5

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for V

and T

Symbol

Table 31. LSI oscillator characteristics

Parameter Conditions f

LSI t su(LSI)

Frequency -

LSI oscillator wakeup time -

1. Data based on characterization results, not tested in production.

Min

112

Typ

128

Max

144

7 (1)

Unit kHz

µs

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STM8AF6246/48/66/68 Electrical characteristics

Figure 19. Typical LSI frequency vs V

-1%

-2%

-3%

2.5

3 3.5

[V]

4.5

25°C

5 5.5

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Electrical characteristics STM8AF6246/48/66/68

Flash program memory/data EEPROM memory

General conditions: T

= -40 to 150 °C.

Symbol

DD t prog t erase

Table 32. Flash program memory/data EEPROM memory

Parameter Conditions Min Typ Max Unit

Operating voltage

(all modes, execution/write/erase)

Operating voltage

(code execution)

Standard programming time (including erase) for byte/word/block

(1 byte/4 bytes/128 bytes)

Fast programming time for 1 block

(128 bytes)

Erase time for 1 block (128 bytes) f

CPU

is 0 to 16 MHz with 0 ws f

CPU

is 0 to 16 MHz with 0 ws

3.0

2.6

5.5

6.6

3.3

V ms

Unit

Temperature for writing and erasing -40 150 °C

Flash program memory endurance

(erase/write cycles)

(1)

= 25 °C 1000 cycles t

RET

Data retention time

= 25 °C

= 55 °C

20 -

years

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte.

Symbol

Table 33. Flash program memory

Parameter

Condition

Table 34. Data memory

Condition

Min

Max

Max Unit

Temperature for writing and erasing -40 150 °C

N t

RET

Data memory endurance

(erase/write cycles)

Data retention time

(1) T

= 25 °C

= 55 °C

300 k

= -40°C to 125 °C 100 k

(2)

= 25 °C 40 (2)(3)

(2)(3)

cycles years

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte.

2. More information on the relationship between data retention time and number of write/erase cycles is available in a separate technical document.

3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.

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STM8AF6246/48/66/68 Electrical characteristics

10.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

and T

unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Symbol Parameter

Table 35. I/O static characteristics

Conditions Min Typ Max Unit

V hys

Input low level voltage

Input high level voltage

Hysteresis

(1)

-0.3 V

0.7 x V

0.1 x

0.3 x V

+ 0.3 V

Output high level voltage

Standard I/0, V

I = 3 mA

= 5 V,

Standard I/0, V

I = 1.5 mA

= 3 V,

High sink and true open drain I/0, V

= 5 V

I = 8 mA

- 0.5 V

- 0.4 V

0.5

R pu

Output low level voltage

Pull-up resistor

Standard I/0, V

I = 3 mA

= 5 V

Standard I/0, V

I = 1.5 mA

= 3 V

= 5 V, V

= V

Fast I/Os

Load = 50 pF

Standard and high sink I/Os

Load = 50 pF

50 65

0.6

0.4

(2)

125

(2) k Ω t

, t

Rise and fall time

(10% - 90%)

(2)

(2) ns

Fast I/Os

Load = 20 pF

Standard and high sink I/Os

Load = 20 pF

I lkg

Digital input pad leakage current

≤ V

±1 µA

I lkg ana

Analog input pad leakage current

≤ V

-40 °C < T

≤ V

< 125 °C

≤ V

-40 °C < T

≤ V

< 150 °C

±250

±500 nA

I lkg(inj)

Leakage current in adjacent I/O

(3)

Injection current ±4 mA ±1

(3)

µA

DDIO

Total current on either

DDIO

or V

SSIO

Including injection currents 60

1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

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Electrical characteristics STM8AF6246/48/66/68

2. Guaranteed by design.

3. Data based on characterization results, not tested in production.

Figure 20. Typical V

and V

vs V

@ four temperatures

-40°C

25°C

85°C

125°C

2.5

3 3.5

[V]

4.5

5 5.5

Figure 21. Typical pull-up resistance R

vs V

@ four temperatures

2.5

3 3.5

[V]

4.5

5 5.5

-40°C

25°C

85°C

125°C

64/99

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STM8AF6246/48/66/68 Electrical characteristics

Figure 22. Typical pull-up current I pu

vs V

@ four temperatures

140

120

100

0 1 2

Note: The pull-up is a pure resistor (slope goes through 0).

[V]

4 5

-40°C

25°C

85°C

125°C

Typical output level curves

Figure 23

to Figure 32

show typical output level curves measured with output on a single pin.

Figure 23. Typ. V

@ V

DD ports)

= 3.3 V (standard

1.5

1.25

-40°C

25°C

85°C

125°C

0.75

0.5

0.25

0 1 2 3

[mA]

4 5 6 7

Figure 24. Typ. V

@ V

= 5.0 V (standard ports)

1.5

1.25

-40°C

25°C

85°C

125°C

0.75

0.5

0.25

0 2 4 6

[mA]

8 10 12

Figure 25. Typ. V

@ V

= 3.3 V (true open drain ports)

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

0.75

0.5

0.25

0 2 4 6

[mA]

8 10 12 14

Figure 26. Typ. V

@ V

= 5.0 V (true open drain ports)

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

0.75

0.5

0.25

0 5 10

[mA]

15 20 25

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Electrical characteristics STM8AF6246/48/66/68

Figure 27. Typ. V

@ V

DD ports)

= 3.3 V (high sink

1.5

1.25

-40°C

25°C

85°C

125°C

0.75

0.5

0.25

0 2 4 6

[mA]

8 10 12 14

Figure 29. Typ. V

DD -

@ V

= 3.3 V

(standard ports)

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

0.75

0.5

0.25

0 1 2 3

[mA]

4 5 6 7

Figure 31. Typ. V

DD -

@ V sink ports)

= 3.3 V (high

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

0.75

0.5

0.25

0 2 4 6

[mA]

8 10 12 14

Figure 28. Typ. V

@ V

DD ports)

= 5.0 V (high sink

1.5

1.25

-40°C

25°C

85°C

125°C

0.75

0.5

0.25

0 5 10

[mA]

15 20 25

Figure 30. Typ. V

DD -

@ V

(standard ports)

= 5.0 V

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

0.75

0.5

0.25

0 2 4 6

[mA]

8 10 12

Figure 32. Typ. V

DD -

@ V

= 5.0 V (high sink ports)

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

0.75

0.5

0.25

0 5 10 15 20 25

[mA]

66/99

DocID14952 Rev 11

STM8AF6246/48/66/68 Electrical characteristics

Subject to general operating conditions for V

and T

unless otherwise specified.

Symbol

Table 36. NRST pin characteristics

Parameter Conditions t

IL(NRST)

IH(NRST)

OL(NRST)

PU(NRST) t

IFP

INFP(NRST)

NRST input low level voltage

(1)

NRST input high level voltage

(1)

NRST output low level voltage

(1)

NRST pull-up resistor

NRST input filtered pulse

(1)

NRST Input not filtered pulse duration

(2)

= 3 mA

1. Data based on characterization results, not tested in production.

2. Data guaranteed by design, not tested in production.

Min

0.7 x V

500

Typ

Figure 33. Typical NRST V

and V

vs V

@ four temperatures

-40°C

25°C

85°C

125°C

Max

0.3 x V

0.6

315

Unit k

Ω ns

2.5

3 3.5

[V]

4.5

5 5.5

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Electrical characteristics STM8AF6246/48/66/68

Figure 34. Typical NRST pull-up resistance R

vs V

-40°C

25°C

85°C

125°C

2.5

3 3.5

[V]

4.5

5 5.5

140

Figure 35. Typical NRST pull-up current I pu

vs V

120

100

-40°C

25°C

85°C

125°C

0 1 2 3

[V]

4 5 6

The reset network shown in Figure 36 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below V

IL(NRST)

max (see Table 36:

NRST pin characteristics ), otherwise the reset is not taken into account internally.

Figure 36. Recommended reset pin protection

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DocID14952 Rev 11

STM8AF6246/48/66/68 Electrical characteristics

10.3.8 TIM 1, 2, 3, and 4 timer specifications

Subject to general operating conditions for V

DD specified.

, f

MASTER

, and T

unless otherwise

Table 37. TIM 1, 2, 3, and 4 electrical specifications

Symbol Parameter Conditions Min Typ Max f

EXT

Timer external clock frequency

(1)

1. Not tested in production. On 64 Kbyte devices, the frequency is limited to 16 MHz.

Unit

MHz

10.3.9 SPI serial peripheral interface

Unless otherwise specified, the parameters given in Table 38

are derived from tests performed under ambient temperature, f

MASTER conditions. t

MASTER

= 1/f

MASTER

frequency and V

DD supply voltage

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 38. SPI characteristics

Conditions Min Max Unit

Master mode

1/t f

SCK c(SCK)

SPI clock frequency

Slave mode

< 4.5 V

= 4.5 V to 5.5 V t r(SCK

) t f(SCK) t su(NSS)

(3) t h(NSS)

(3) t t w(SCKH)

(3) w(SCKL)

(3) t t su(MI)

(3) su(SI)

(3)

SPI clock rise and fall time Capacitive load: C = 30 pF

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Slave mode

Master mode

Slave mode t

SCK

4 * t

MASTER

/2 - 15 t

SCK

(1)

(2)

/2 + 15

MHz t t h(MI)

(3)

(3) h(SI) t a(SO)

(3)(4) t dis(SO)

(3)(5)

Data input hold time

Master mode

Slave mode

Data output access time Slave mode

Data output disable time Slave mode t v(SO)

(3)

Data output valid time

Slave mode

(after enable edge)

< 4.5 V

= 4.5 V to 5.5 V

Master mode (after enable edge) t v(MO)

(3) t h(SO)

(3) t h(MO)

(3)

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

1. f

SCK

< f

MASTER

/2.

2. The pad has to be configured accordingly (fast mode).

3* t

MASTER

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Electrical characteristics STM8AF6246/48/66/68

3. Values based on design simulation and/or characterization results, and not tested in production.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Figure 37. SPI timing diagram where slave mode and CPHA = 0

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and 0.7 V

Figure 38. SPI timing diagram where slave mode and CPHA = 1

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70/99

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STM8AF6246/48/66/68

Figure 39. SPI timing diagram - master mode

Electrical characteristics

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Electrical characteristics STM8AF6246/48/66/68

10.3.10 I

C interface characteristics

Symbol

Table 39. I 2 C characteristics

Standard mode I

C Fast mode I

(1)

Parameter

Min

(2)

Max

(2)

Min

(2)

Max

(2)

Unit t w(SCLL) t w(SCLH) t su(SDA)

SCL clock low time

SCL clock high time

SDA setup time t h(SDA)

SDA data hold time t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA) t su(STA) t su(STO)

SDA and SCL rise time

= 3 to 5.5 V)

SDA and SCL fall time

= 3 to 5.5 V)

START condition hold time

Repeated START condition setup time

STOP condition setup time t w(STO:STA)

STOP to START condition time

(bus free)

4.7

4.0

250

(3)

4.0

4.7

4.0

4.7

1000

300

1.3

0.6

100

(4)

0.6

1.3

900

(3)

300

µs ns

µs

C b

Capacitive load for each bus line 400 400

1. f

MASTER

, must be at least 8 MHz to achieve max fast I 2 C speed (400 kHz)

2. Data based on standard I

C protocol requirement, not tested in production

3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time pF

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL

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STM8AF6246/48/66/68 Electrical characteristics

Subject to general operating conditions for V

DDA specified.

, f

MASTER

, and T

unless otherwise

Symbol Parameter

Table 40. ADC characteristics

Conditions Min Typ Max Unit f

ADC

DDA

REF+

ADC clock frequency

Analog supply

Positive reference voltage -

111 kHz

2.75

4 MHz kHz/MHz

5.5

DDA

REF-

Negative reference voltage V

SSA

0.5

SSA

DDA

AIN

Conversion voltage range

(1) Devices with external V

REF+

REF-

pins

REF-

REF+

C samp

Internal sample and hold capacitor 3 pF t t

(1)

STAB

Sampling time

(3 x 1/f

ADC

)

Wakeup time from standby f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz

1.5

0.75

3.5

µs t

CONV

Total conversion time including sampling time

(14 x 1/f

ADC

)

Equivalent switch resistance f

ADC

= 4 MHz -

3.5

R switch

30 k Ω

1. During the sample time, the sampling capacitance, C voltage level within t effect on the conversion result.

samp

After the end of the sample time t

(3 pF typ), can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final

, changes of the analog input voltage have no

Figure 40. Typical application with ADC s

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FRQYHUVLRQ

VDPS

1. Legend: R

AIN

= external resistance, C

AIN

= capacitors, C samp

= internal sample and hold capacitor.

06Y9

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Electrical characteristics STM8AF6246/48/66/68

Symbol

Table 41. ADC accuracy for V

DDA

= 5 V

Parameter Conditions Typ Max

(1) Unit

Total unadjusted error

(2)

Offset error

(2)

Gain error

(2)

Differential linearity error

(2)

Integral linearity error

(2)

Total unadjusted error

(2)

Offset error

(2)

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2) f f

ADC

= 2 MHz

= 4 MHz

1.4

0.8

0.1

0.9

0.7

1.9

(4)

1.3

0.6

1.5

1.2

(4)

(3)

1.5

(4)

1.5

(4)

LSB

1. Max value is based on characterization, not tested in production.

2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for

INJ(PIN)

and Σ I

INJ(PIN)

in Section 10.3.6

does not affect the ADC accuracy.

3. TUE 2LSB can be reached on specific sales types on the whole temperature range.

4. Target values.

Figure 41. ADC accuracy characteristics

1023

1022

1021

1LSBIDEAL =

1024

1 LSB

IDEAL

SSA

1 2 3 4 5 6 7

(2)

(3)

(1)

1021102210231024

DDA

1. Example of an actual transfer curve

2. The ideal transfer curve

3. End point correlation line

= Differential linearity error: Maximum deviation between actual steps and the ideal one.

= Integral linearity error: Maximum deviation between any actual transition and the end point correlation line.

= Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.

= Offset error: Deviation between the first actual transition and the first ideal one.

= Gain error: Deviation between the last ideal transition and the last actual one.

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STM8AF6246/48/66/68 Electrical characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Symbol

FESD

EFTB

Table 42. EMS data

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V

SS pins to induce a functional disturbance f

= 3.3 V, T

MASTER

= 25 °C,

= 16 MHz (HSI clock),

Conforms to IEC 1000-4-2

= 3.3 V, T

= 25 °C, f

MASTER

= 16 MHz (HSI clock),

Conforms to IEC 1000-4-4

Level/class

3/B

4/A

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Electrical characteristics STM8AF6246/48/66/68

Electromagnetic interference (EMI)

Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading.

Table 43. EMI data

Conditions

Symbol Parameter

General conditions

Monitored frequency band

Max f

CPU

(1)

MHz

Unit

EMI

Peak level

= 5 V,

25 °C,

LQFP80 package conforming to IEC

61967-2

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

-1

2.5

dBµV

EMI level

1. Data based on characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.

Symbol

Table 44. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

ESD(MM)

Electrostatic discharge voltage

(Human body model)

Electrostatic discharge voltage

(Charge device model)

Electrostatic discharge voltage

(Machine model)

= 25°C, conforming to

JESD22-A114

= 25°C, conforming to

JESD22-C101

= 25°C, conforming to

JESD22-A115

1. Data based on characterization results, not tested in production

4000

500

200

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STM8AF6246/48/66/68 Electrical characteristics

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance.

• A supply overvoltage (applied to each power supply pin) and

• A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter

Table 45. Electrical sensitivities

Conditions Class

(1)

LU Static latch-up class

= 25 °C

= 85 °C

= 125 °C

= 150 °C

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

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Package information STM8AF6246/48/66/68

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 42. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package outline

6HDWLQJSODQH

GGG &

$ $

( E

3LQ,'

1. Drawing is not to scale.

%RWWRPYLHZ

(

?-%?!-+/2?6

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STM8AF6246/48/66/68 Package information

Table 46. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max b

E2 e

L ddd

0.800

0.000

0.180

4.850

3.500

4.850

3.500

0.300

0.900

0.020

0.200

0.250

5.000

3.600

5.000

3.600

0.500

0.400

1.000

0.050

0.300

5.150

3.700

5.150

3.700

0.500

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0315

0.0000

0.0071

0.1909

0.1378

0.1909

0.1378

0.0118

0.0354

0.0008

0.0079

0.0098

0.1969

0.1417

0.1969

0.1417

0.0197

0.0157

0.0394

0.0020

0.0118

0.2028

0.1457

0.2028

0.1457

0.0197

0.0020

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Package information STM8AF6246/48/66/68

Figure 43. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package recommended footprint

9DU$

9DU%

9DU$

9DU%

1. Dimensions are expressed in millimeters.

?&0?!-+/2?6

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STM8AF6246/48/66/68 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 44. VFQFPN32 marking example (package top view)

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999999

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: 88

6WDQGDUG67ORJR

3LQLGHQWLILHU

5HYLVLRQFRGH

069

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Package information STM8AF6246/48/66/68

11.2 LQFP48 package information

Figure 45. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

"?-%?6

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STM8AF6246/48/66/68 Package information

Symbol

Table 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

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Package information STM8AF6246/48/66/68

Figure 46. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

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AID

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 47. LQFP48 marking example (package top view)

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LGHQWLILFDWLRQ

999999

6WDQGDUG67ORJR

3LQLGHQWLILHU

'DWHFRGH

: 88

5HYLVLRQFRGH

069

DocID14952 Rev 11

STM8AF6246/48/66/68 Package information

11.3 LQFP32 package information

Figure 48. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

7@.&@7

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Package information STM8AF6246/48/66/68

Symbol

Table 48. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.300

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.370

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

1.600

0.150

1.450

0.450

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

0.0551

0.0146

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0039

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

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Figure 49. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint

6?&0?6

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 50. LQFP32 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ

999999

6WDQGDUG67ORJR

3LQLGHQWLILHU

'DWHFRGH

: 88

5HYLVLRQFRGH

069

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Package information STM8AF6246/48/66/68

In case the maximum chip junction temperature (T

Jmax

) specified in

Table 21: General operating conditions on page 52

is exceeded, the functionality of the device cannot be guaranteed.

Jmax

, in degrees Celsius, may be calculated using the following equation:

Jmax

= T

Amax

+ (P

Dmax

x Θ

)

Where:

– T

Amax

is the maximum ambient temperature in ° C

– Θ

is the package junction-to-ambient thermal resistance in ° C/W

– P

Dmax

is the sum of P

INTmax

and P

I/Omax

Dmax

= P

INTmax

+ P

I/Omax

)

– P

INTmax

is the product of I

DD and chip internal power.

, expressed in Watts. This is the maximum

– P

I/Omax

Where:

represents the maximum power dissipation on output pins

I/Omax

= Σ (V

*I taking into account the actual V in the application.

) + Σ ((V

-V

)*I

OH and

of the I/Os at low and high level

Symbol

Table 49. Thermal characteristics (1)

Parameter Value

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm

Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

Thermal resistance junction-ambient

VFQFPN32

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

Unit

°C/W

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.

11.4.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Section 12: Ordering information ).

The following example shows how to calculate the temperature range needed for a given application.

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STM8AF6246/48/66/68 Package information

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 14 mA, V

= 82 °C (measured according to JESD51-2),

= 5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V

INTmax

= 14 mA x 5 V= 70 mW

IOmax

= 20 x 8 mA x 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

64 mW:

Dmax

= 70 mW + 64 mW

Thus: P

Dmax

= 134 mW.

Using the values obtained in Table 49: Thermal characteristics T

Jmax follows:

is calculated as

For LQFP64 46 °C/W

Jmax

= 82 °C + (46 °C/W x 134 mW) = 82 °C + 6 °C = 88 °C

This is within the range of the suffix C version parts (-40 < T

< 125 °C).

Parts must be ordered at least with the temperature range suffix C.

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Ordering information STM8AF6246/48/66/68

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Figure 51. STM8AF6246/48/66/68 ordering information scheme

(1) (2)

STM8A F 62 6 6 I T D xxx

(3)

Y Example:

Product class

8-bit automotive microcontroller

Program memory type

F = Flash + EEPROM

P = FASTROM

Device family

62 = Silicon rev X and rev W, LIN only

Program memory size

4 = 16 Kbyte

6 = 32 Kbyte

Pin count

6 = 32 pins

8 = 48 pins

HSI accuracy

Blank = ± 5 %

I = ± 2.5 %

Package type

T = LQFP

U = VFQFPN

Temperature range

A = -40 to 85 °C

C = -40 to 125 °C

D = -40 to 150 °C

Packing

Y = Tray

U = Tube

X = Tape and reel compliant with EIA 481-C

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com

or contact the nearest ST Sales Office.

2. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

Samples to run qualification activity.

3. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed to be replaced later by the target silicon.

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13 STM8 development tools

STM8 development tools

Development tools for the STM8A microcontrollers include the

• STice emulation system offering tracing and code profiling

• STVD high-level language debugger including assembler and visual development environment - seamless integration of third party C compilers.

• STVP Flash programming software

In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

The STM8 tool line includes the STice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code.

In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.

13.1.1 STice key features

• Program and data trace recording up to 128 K records

• Advanced breakpoints with up to 4 levels of conditions

• Data breakpoints

• Real-time read/write of all device resources during emulation

• Occurrence and time profiling and code coverage analysis (new features)

• In-circuit debugging/programming via SWIM protocol

• 8-bit probe analyzer

• 1 input and 2 output triggers

• USB 2.0 high speed interface to host PC

• Power supply follower managing application voltages between 1.62 to 5.5 V

• Modularity that allows users to specify the components they need to meet their development requirements and adapt to future requirements.

• Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

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STM8 development tools STM8AF6246/48/66/68

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8.

The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes:

ST visual develop

Full-featured integrated development environment from STMicroelectronics, featuring:

• Seamless integration of C and ASM toolsets

• Full-featured debugger

• Project management

• Syntax highlighting editor

• Integrated programming interface

• Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A microcontroller Flash memory. STVP also offers project mode for saving programming configurations and automating programming sequences.

13.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of the application directly from an easy-to-use graphical interface.

Available toolchains include:

C compiler for STM8

All compilers are available in free version with a limited code size depending on the compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com, and www.iar.com.

STM8 assembler linker

Free assembly toolchain included in the STM8 toolset, which allows users to assemble and link the application source code.

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During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on the user application board via the SWIM protocol. Additional tools are used to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8A.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

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Revision history STM8AF6246/48/66/68

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Date

22-Aug-2008

10-Aug-2009

22-Oct-2009

08-Jul-2010

Revision

Table 50. Document revision history

Changes

Initial release

Document revised as the following:

Updated Features ;

Updated Table: Device summary;

Updated Section: Product line-up;

Changed Section: Product overview ;

Updated Section: Pinouts and pin description;

Changed Section: Register map;

Updated Section: Interrupt table;

Updated Section: Option bytes;

Updated Section: Electrical characteristics;

Updated Section: Package information;

Updated Section: Ordering information;

Added Section: STM8 development tools.

Adapted Table: STM8AF61xx/62xx (32 Kbyte) microcontroller pin description.

Added Section: LIN header error when automatic resynchronization is enabled.

Updated title on cover page.

Added VFQFPN32 5x 5 mm package.

Added STM8AF62xx devices, and modified cover page header to clarify the part numbers covered by the datasheets. Updated Note 1 below Table: Device summary.

Updated D temperature range to -40 to 150°C.

Content of Section: Product overview reorganized.

Renamed Section: Memory and register map , and content merged with Register map section.

Renamed BL_EN and NBL_EN, BL and NBL, respectively, in Table:

Option bytes.

Added Table: Operating lifetime.

Added CEXT and P

(power dissipation) in Table: General operating conditions , and Section: VCAP external capacitor.

Suffix D maximum junction temperature (T

General operating conditions.

) updated in Table:

Update t

VDD in Table: Operating conditions at power-up/power-down .

Moved Table: Typical peripheral current consumption VDD = 5.0 V to

Section: Current consumption for on-chip peripherals and removed

DD(CAN)

Updated Section: Ordering information for the devices supported by the datasheet.

Updated Section: STM8 development tools.

DocID14952 Rev 11

STM8AF6246/48/66/68 Revision history

Date

31-Jan-2011

Table 50. Document revision history (continued)

Revision Changes

Modified references to reference manual, and Flash programming manual in the whole document.

Added reference to AEC Q100 standard on cover page.

Renamed timer types as follows:

– Auto-reload timer to general purpose timer

– Multipurpose timer to advanced control timer

– System timer to basic timer

Introduced concept of medium density Flash program memory.

Updated timer names in Figure: STM8A block diagram.

Added TMU brief description in Section: Flash program and data

EEPROM , and updated TMU_MAXATT description in Table: Option byte description .

Updated clock sources in clock controller features. Changed

16MHZTRIM0 to HSITRIM bit in Section: User trimming.

Added Table: Peripheral clock gating bits.

Updated Section: Low-power operating modes.

Added calibration using TIM3 in Section: Auto-wakeup counter.

Added Table: ADC naming and Table: Communication peripheral naming correspondence.

Added Note 1 related AIN12 pin in Section: Analog-to-digital converter (ADC) and Table: STM8AF61xx/62xx (32 Kbyte) microcontroller pin description.

Updated SPI data rate to 10 Mbit/s or f

MASTER peripheral interface (SPI).

/2 in Section: Serial

Added reset state in Table: Legend/abbreviation.

Table: STM8AF61xx/62xx (32 Kbyte) microcontroller pin description: added Note 7 related to PD1/SWIM, modified Note 6, corrected wpu input for PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to

TIMn_CHx and TIMn_CHxN, respectively.

Section: Register map:

Replaced tables describing register maps and reset values for nonvolatile memory, global configuration, reset status, clock controller, interrupt controller, timers, communication interfaces, and ADC, by

Table: General hardware register map .

Added Note 1 for Px_IDR registers in Table: I/O port hardware register map. Updated register reset values for Px_IDR registers.

Added SWIM and debug module register map.

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Revision history STM8AF6246/48/66/68

Date

31-Jan-2011

18-Jul-2012

Table 50. Document revision history (continued)

Revision Changes

(continued)

Renamed Fast Active Halt mode to Active-halt mode with regulator on, and Slow Active Halt mode to Active-halt mode with regulator off.

Updated Table: Total current consumption in Halt and Active-halt modes. General conditions for VDD apply, TA = -40 to 55 °C , in t particular I

DD(FAH)

WU(SAH) and I

DD(SAH) renamed t

WU(AH) renamed I

DD(AH)

; t

WU(FAH) and

, and temperature condition added.

Removed I

DD(USART) from Table: Typical peripheral current consumption VDD = 5.0 V.

Updated general conditions in Section: Memory characteristics.

Modified T

maximum value in Table: Flash program memory and

Table: Data memory.

Update I lkg ana maximum value for T

ranging from − 40 to 150 °C in

Table: I/O static characteristics .

Added t

IFP(NRST) and renamed V

F(NRST) t

IFP in Table: NRST pin characteristics.

Added recommendations concerning NRST pin level above Figure: Recommended reset pin protection, and updated external capacitor value.

Added Raisonance compiler in Section: Software tools.

Moved know limitations to separate errata sheet.

Updated wildcards of document part numbers.

Table: Device summary: u pdated the footnotes to all STM8AF61xx part numbers.

Section: Introduction: small text change in first paragraph.

Table: STM8AF62xx product line-up : added “P” version for all order codes; updated RAM.

Table: STM8AF/H61xx product line-up : added “P” version for all order codes.

Figure: STM8A block diagram : updated POR, BOR and WDG; updated LINUART input; added legend.

Section: Flash program and data EEPROM: removed non relevant bullet points and added a sentence about the factory programmer.

Table: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers: updated

ADC features: updated ADC input range.

Table: Memory model for the devices covered in this datasheet: updated 16 Kbyte and 8 Kbyte information.

Table: Option bytes : updated factory default setting for NOPT17; added footnote 1 .

Section: Minimum and maximum values: T

40 °C).

= -40 °C (not

Table: General operating conditions: updated V

CAP

Table: Total current consumption in Run, Wait and Slow mode

General conditions for VDD apply, TA = -40 to 150 °C : updated conditions for I

DD(RUN)

Table: I/O static characteristics : added new condition and new max values for rise and fall time; updated the footnote.

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STM8AF6246/48/66/68 Revision history

Date

18-Jul-2012

04-Apr-2014

24-Jun-2014

12-Nov-2014

Table 50. Document revision history (continued)

Revision Changes

(continued)

Section: Reset pin characteristics: updated text below Figure: Typical

NRST pull-up current Ipu vs VDD .

Figure: Recommended reset pin protection : updated unit of capacitor.

Table: SPI characteristics: updated SCK high and low time conditions and values.

Figure: SPI timing diagram - master mode : replaced ‘SCK input’ signals with ‘SCK output’ signals.

Updated Table: VFQFPN 32-lead very thin fine pitch quad flat nolead package mechanical data, T able: LQFP 48-pin low profile quad flat package mechanical data , and Table: LQFP 32-pin low profile quad flat package mechanical data.

Replaced Figure: LQFP 48-pin low profile quad flat package (7 x 7) and Figure: LQFP 32-pin low profile quad flat package (7 x 7) .

Added Figure: LQFP 48-pin recommended footprint and Figure:

LQFP 32-pin recommended footprint.

Figure: Ordering information scheme(1): added footnote 1 , added

“xxx” and footnote 2 , updated example and device family; added

FASTROM.

Section: C and assembly toolchains: added www.iar.com

Updated:

– Table: Device summary,

– Table: STM8AF62xx product line-up,

– Table: STM8AF/H61xx product line-up.

– SPI description in Features.

– The typical and maximum values for t

TEMP

reset release delay in

Table: Operating conditions at power-up/power-down.

– The symbol for NRST Input not filtered pulse duration in Table:

NRST pin characteristics

– The address and comment of Reset interrupt in Table: STM8A interrupt table.

Added the three footnotes to Figure VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5) .

Updated Table: HSI oscillator characteristics.

Added HSI accuracy and removed temperature range B in Figure:

Ordering information scheme(1).

Updates in Table: HSI oscillator characteristics (HSI oscillator accuracy (factory calibrated) values) and F igure: Ordering information scheme(1) (changed the value for I).

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Revision history STM8AF6246/48/66/68

Date

09-Jun-2015

14-Jun-2016

Table 50. Document revision history (continued)

Revision Changes

Updated:

– the product naming in the document headers and captions,

– LIN version in

Features

and Section 5.9.3: Universal asynchronous receiver/transmitter with LIN support (LINUART)

Added:

– the third table footnote to Table 22: Operating conditions at powerup/power-down ,

–

Figure 44: VFQFPN32 marking example (package top view) ,

–

Figure 47: LQFP48 marking example (package top view)

–

Figure 50: LQFP32 marking example (package top view)

– the note about the parts marked “E” and “ES” below

Figure 51:

STM8AF6246/48/66/68 ordering information scheme(1) (2)

– the standard for EMI characteristics in

Table 43: EMI data

Removed the references to STM8AF61xx and STM8AH61xx obsolete products.

Moved Section 11.4: Thermal characteristics

Section 11: Package information .

Update Table 46: VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data

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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

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Inhoudsopgave

Advertentie

Automotive 8-bit MCU, with up to 32 Kbyte Flash, data EEPROM,

10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V

Features

Contents

List of tables

List of figures

1 Introduction

2 Description

5.1 STM8A central processing unit (CPU)

5.2 Single wire interface module (SWIM) and debug module (DM)

5.4 Flash program and data EEPROM

User trimming

5.6 Low-power operating modes

5.7 Timers

Window watchdog timer

Independent watchdog timer

TIM1: Advanced control timer

TIM2 and TIM3: 16-bit general purpose timers

5.8 Analog-to-digital converter (ADC)

ADC features

LIN mode

UART mode

6 Pinouts and pin description

7 Memory and register map

10.2 Absolute maximum ratings

Current consumption for on-chip peripherals

Current consumption curves

HSE user external clock

HSE crystal/ceramic resonator oscillator

HSE oscillator critical g

formula

High speed internal RC oscillator (HSI)

Low speed internal RC oscillator (LSI)

Flash program memory/data EEPROM memory

General characteristics

Typical output level curves

Functional EMS (electromagnetic susceptibility)

Designing hardened software to avoid noise problems

Electromagnetic interference (EMI)

Absolute maximum ratings (electrical sensitivity)

Electrostatic discharge (ESD)

Static latch-up

Device marking

11.2 LQFP48 package information

Device marking

11.3 LQFP32 package information

Device marking

13 STM8 development tools

ST visual develop

ST visual programmer (STVP)

C compiler for STM8

STM8 assembler linker

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