STMicroelectronics TDA7492PE Datasheet
विज्ञापन
विज्ञापन
TDA7492PE
Datasheet
45 W + 45 W dual BTL class-D audio amplifier
PowerSSO36 with exposed pad down
Product status
TDA7492PE
Product summary
Order code
Temperature range
Package
Packing
TDA7492PETR
-40 to +85 °C
PowerSSO-36 EPD
Tape and reel
Features
• Wide-range single-supply operation
(7 - 26 V)
• Possible output configurations:
– 2 x PBTL
– 1 x Parallel BTL
• BTL output capabilities (V
CC
= 22 V):
– 44 W + 44 W, 4 Ω, THD 1%
– 57 W + 57 W, 4 Ω, THD 10%
– 32 W + 32 W, 6 Ω, THD 1%
– 41 W + 41 W, 6 Ω, THD 10%
– 25 W + 25 W, 8 Ω, THD 1%
– 32 W + 32 W, 8 Ω, THD 10%
• Parallel BTL output capabilities (V
CC
= 22 V):
– 70 W, 3 Ω, THD 1%
– 90 W, 3 Ω, THD 10%
• High efficiency
• Four selectable, fixed-gain settings of nominally 20.8 dB, 26.8 dB, 30 dB and
32.8 dB
• Differential inputs minimize common-mode noise
• Standby, mute and play operating modes
• Short-circuit protection
• Output power limited by P
LIMIT
function
• Detection of shorted output pins during startup
• Thermal overload protection
• ECOPACK ® environmentally friendly package
Description
The TDA7492PE is a dual BTL class-D audio amplifier with single power supply designed for home audio applications.
The device is housed in a 36-pin PowerSSO package with exposed pad down (EPD) to facilitate power dissipation through a properly designed PCB area underneath the
TDA7492PE .
DS10652 - Rev 3 - September 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
TDA7492PE
Device block diagram
Device block diagram
channels of the TDA7492PE.
Figure 1. Internal block diagram (showing one channel only)
GAIN
PLMT
Gain Settings
Power Limit
INP
INN -
+
-
+
VREF
-
+
+
-
+
-
+
-
Gate
Driver
Gate
Driver
ROSC
SYNCLK
Oscillator
Standby Mute/Play
STANDBY MUTE
Thermal,Undervoltage
Overcurrent protections
DIAG
VDD,VSS Regulators
VDDS VSS
OUTP
OUTN
DS10652 - Rev 3 page 2/19
2
2.1
Pin description
Pinout
S UB_GND 1
OUTP B
OUTP B
2
P GNDB
3
4
P GNDB 5
P VC CB 6
P VC CB 7
OUTNB
OUTNB
8
9
OUTNA 10
OUTNA 11
P VC CA 12
P VC CA 13
P GNDA 14
P GNDA 15
OUTP A 16
OUTP A 17
P GND 18
Figure 2. Pin connections (top view)
EP
Exposed pad down
(Connected to ground )
27 S GND
26 VDDS
25 S YNCLK
24 ROS C
23 INNA
22 INP A
21 MUTE
20 S TBY
19 VDDP W
36 VS S
35 S VCC
34 VRE F
33 INNB
32 INP B
31 GAIN
30 P LIMIT
29 S VR
28 DIAG
TDA7492PE
Pin description
DS10652 - Rev 3 page 3/19
2.2
TDA7492PE
Pin list
Pin list
OUTPA
PGND
VDDPW
STBY
MUTE
INPA
INNA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
PLIMIT
GAIN
INPB
INNB
VREF
SVCC
VSS
EP
Name
SUB_GND
OUTPB
PGNDB
PVCCB
OUTNB
OUTNA
PVCCA
PGNDA
22
23
24
25
26
12, 13
14, 15
16, 17
18
19
20
21
30
31
32
33
34
35
27
28
29
-
36
Number
1
2, 3
4, 5
6, 7
8, 9
10, 11
I
I
O
I/O
O
I
I
O
PWR
O
-
O
PWR
O
O
I
I
I
I
O
PWR
Type
PWR
O
PWR
PWR
O
O
PWR
PWR
Table 1. Pin description list
Description
Connect to the frame
Positive PWM for right channel
Power stage ground for right channel
Power supply for right channel
Negative PWM output for right channel
Negative PWM output for left channel
Power supply for left channel
Power stage ground for left channel
Positive PWM output for left channel
Power stage ground
3.3 V (nominal) regulator output referred to ground for power stage
Standby mode control
Mute mode control
Positive differential input of left channel
Negative differential input of left channel
Master oscillator frequency-setting pin
Clock in/out for external oscillator
3.3 V (nominal) regulator output referred to ground for signal blocks
Signal ground
Open-drain diagnostic output
Supply voltage rejection
Output voltage level setting
Gain setting input
Positive differential input of right channel
Negative differential input of right channel
Half VDDS (nominal) referred to ground
Signal power supply
3.3 V (nominal) regulator output referred to power supply
Exposed pad for heatsink, to be connected to GND
DS10652 - Rev 3 page 4/19
3
3.1
3.2
TDA7492PE
Electrical specifications
Electrical specifications
Absolute maximum ratings
Symbol
V
CC
VI
T j
T op
T stg
Thermal data
Table 2. Absolute maximum ratings
Parameter
DC supply voltage for pins PVCCA, PVCCB, SVCC
Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN,
MODE
Operating junction temperature
Operating ambient temperature
Storage temperature
Symbol
R th j-case
R th j-amb
Table 3. Thermal data
Parameter
Thermal resistance, junction-to-case
Thermal resistance, junction-to-ambient
Min.
-
Value
30
-0.3 to +4.6
-40 to +150
-40 to +85
-40 to +150
Typ.
2.98
24
Max.
Unit
°C/W
°C/W
Unit
V
V
°C
°C
°C
DS10652 - Rev 3 page 5/19
3.3
TDA7492PE
Electrical specifications
Electrical specifications
Unless otherwise stated, the results in Table 1 below are given for the conditions: V
CC
= 22 V, R
L
= 6 Ω, R
OSC
=
R3 = 33 kΩ, f = 1 kHz, G
V
= 20.8 dB and Tamb = 25 °C.
Table 4. Electrical specifications
Symbol
V
CC
Parameter
Supply voltage for pins PVCCA,
PVCCB, SVCC
Condition
-
Min.
7
Typ.
-
Max.
26
Unit
V
I q
I qSTBY
V
OS
Total quiescent current
Quiescent current in standby
Output offset voltage
No LC filter, no load
-
Vi = 0, no load
-
-
40
1
20
mA
µA mV
I
OCP
T j
Overcurrent protection threshold to switch off the device
Junction temperature at thermal shutdown
-
9
140
10
150
13
160
A
°C
R i
Input resistance Differential input 60 kΩ
R dsON
G
V
Power transistor on-resistance
Closed-loop gain
High side
Low side
GAIN < 0.25*Vdd
0.25*Vdd < GAIN < 0.5*Vdd
0.5*Vdd < GAIN < 0.75*Vdd
GAIN1 > 0.75*Vdd
-
-
-
-
-
0.2
0.2
20.8
26.8
30
32.8
-
-
-
-
-
-
Ω dB
ΔG
CT
V
SVRR
T r
, T f f
SW
Gain matching
Cross talk
Supply voltage rejection ratio
Rise and fall times
Switching frequency
f = 1 kHz, P
O
= 1 W fr = 100 Hz, Vr = 0.5 Vpp,
C
SVR
= 10 µF
-
Internal oscillator
-
-
-
70
60
24
500
±1
-
-
40 dB dB dB ns kHz f
SWR
Output switching frequency range
Digital input high (H)
With internal oscillator by changing
Rosc
450 550
V inH
V inL
Digital input low (L)
-
2.0
-
-
0.8
Function mode
A
MUTE
Standby, Mute, Play
Mute attenuation
STBY < 0.5 V Mute = X
STBY > 2.5 V Mute < 0.8 V
STBY > 2.5 V Mute > 2.5 V
V
MUTE
= 1 V 60
Standby
80
Mute
Play
-
1. f
SW
= 10 6 / [( R
OSC
* 12 + 110) * 4] kHz, f
SYNCLK
= 2 * f
SW
(where R
OSC is in kΩ. and f
SW
in kHz) with Rosc = 33 kΩ.
kHz
V dB
DS10652 - Rev 3 page 6/19
3.4
3.5
TDA7492PE
Stereo BTL application
Stereo BTL application
All specifications are for V
CC
= 22 V, Rosc = 33 kΩ, f = 1 kHz, Tamb = 25 °C, unless otherwise specified.
Symbol
P o
THD
VN
Parameter
Output power
Total harmonic distortion
Total output noise
Table 5. Stereo BTL application
Condition
R
L
= 6 Ω, THD = 10%
R
L
= 6 Ω, THD = 1%
R
L
= 6 Ω, THD = 10%,
V
CC
= 18 V
R
L
= 6 Ω, THD = 1%,
V
CC
= 18 V
P o
= 1 W, fin = 1 kHz
Inputs shorted and connected to
GND,
A Curve, G
V
= 20.8 dB
Min.
-
-
-
-
-
-
Typ.
41
32
27
21
0.04
150
Max.
-
-
-
-
-
-
Unit
W
%
µV
Parallel BTL (mono) application
All specifications are for V
CC unless otherwise specified.
= 22 V, Rosc = 33 kΩ, f = 1 kHz, Tamb = 25 °C, INPB, INNB connected to VDDS,
P o
Symbol
THD
VN
Parameter
Output power
Total harmonic distortion
Total output noise
Table 6. Stereo BTL (mono) application
Condition
R
L
= 3 Ω, THD = 10%
R
L
= 3 Ω, THD = 1%
R
L
= 3 Ω, THD = 10%,
Vcc = 18 V
R
L
= 3 Ω, THD = 1%,
Vcc = 18 V
P o
= 1 W, fin = 1 kHz
Inputs shorted and connected to
GND,
A Curve, G
V
= 20.8 dB
Min.
-
-
-
-
-
-
41
0.04
150
Typ.
90
70
53
Max.
-
-
-
Unit
W
-
-
-
%
µV
DS10652 - Rev 3 page 7/19
TDA7492PE
Application information
4
Application information
4.1
4.2
4.3
4.3.1
Gain setting
The four gain settings of the TDA7492PE are set by GAIN (pin 31). Internally, gain is set by changing the feedback resistors of the amplifier. The gain setting pins can be controlled by standard logic drivers.
Voltage on GAIN pin
V
GAIN
< 0.25*VDDS
0.25*VDDS < V
GAIN
< 0.5*VDDS
0.5*VDDS < V
GAIN
< 0.75*VDDS
V
GAIN
> 0.75*VDDS
Table 7. Gain settings
Total gain
20.8 dB
26.8 dB
30 dB
32.8 dB
Application recommendations
GAIN pin connected to SGND
External resistor divider < 100 k
External resistor divider < 100 k
GAIN pin connected to VDDS
Stereo and mono applications
The TDA7492PE can be used in stereo BTL or in mono BTL configuration. When the input pins, INPB and INNB of the right channel are directly shorted to VDDS (without input capacitors) the device is in mono configuration as shown in
.
Figure 3. Mono BTL settings
INPA
INNA
INPB
INNB
IC
OUTPB
OUTPA
OUTNA
OUTNB
LC
Filter
Smart protections
Overcurrent protection (OCP)
If the overcurrent protection threshold is reached, the power stage will be shut down immediately. The device will recover automatically when the fault is removed.
Table 8. Overcurrent protection
High-side (A)
Low-side (A)
I (shutdown)
11.2
10.0
The thresholds in mute mode are reduced to about 1/2 and two typical thresholds are as follows.
DS10652 - Rev 3 page 8/19
TDA7492PE
Smart protections
4.3.2
4.3.3
High-side (A)
Low-side (A)
Table 9. Overcurrent protection (mute mode)
I (shutdown)
6.2
5.9
Thermal protection
When internal die temperature exceeds 140 °C, the device enters into Mute by pulling the MUTE pin low first.
When internal die temperature exceeds 150 °C, the device directly shuts down the power stage. The TDA7492PE automatically recovers when the temperature become lower than the threshold.
Power limit
A built-in power limit is used to limit the output voltage level below the supply rail by limiting the duty cycle. The limit level is set through the voltage at PLIMIT (pin 30). The pin voltage is set by the following equation:
VPLIMIT = VDD
Rdn//400k
Rdn//400k + Rup
(1)
Figure 4. Recommended power limit pin connections
VDDS
Rup
PLIMIT
Rdn
Power
Limiter
It is recommended that external resistors are less than 40 kΩ if a voltage divider is used as shown in
Figure 5. Recommended power limit pin connections
. The relationship of the maximum duty cycle (Dmax) and the voltage at P
LIMIT
is:
Dmax =
8.8 ×
Vcc −
VPLIMIT
2 × Vcc × Rs
Rload × 2 × Rs
2
+ 1
Where V
CC
is the power supply voltage, VPLIMIT is the voltage applied at the P
LIMIT
pin, Rs is the series resistance including Rdson of the power transistor, output filter resistance and bonding wire resistance. Rload is the load resistance.
(2)
An example of maximum effective control voltage at P
LIMIT
vs. power supply and load resistance is shown in
Table 10. Max. effective voltage of P
pin vs. power supply and load .
R load
4 Ω
6 Ω
8 Ω
Table 10. Max. effective voltage of P
LIMIT
pin vs. power supply and load
7 V
0.71 V
0.74 V
0.75 V
Power supply
13 V
1.32 V
1.37 V
1.39 V
24 V
2.44 V
2.53 V
2.57 V
DS10652 - Rev 3 page 9/19
4.4
TDA7492PE
Mode selection
Mode selection
The three operating modes of the TDA7492PE are set by two inputs: STBY (pin 20) and MUTE (pin 21).
• Standby mode: all circuits are turned off, very low current consumption.
•
•
Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle
Play mode: the amplifiers are active.
The protection functions of the TDA7492PE are implemented by pulling down the voltages of the STBY and
MUTE inputs shown in
Figure 6. Standby and mute circuits . The input current of the corresponding pins must be
limited to 200 µA.
Table 11. Mode settings
Mode
Standby
Mute
Play
1. Drive levels defined in
Table 4. Electrical specifications
.
STBY
H
H
Figure 5. Standby and mute circuits
0 V
0 V
Standby
3.3 V
R 2
33 kΩ
C7
Mute R4
3.3 V
33 kΩ
C15
20
STBY
2.2 µF
TDA7492PE
21
MUTE
2.2 µF
MUTE
X (do not care)
L
H
DS10652 - Rev 3 page 10/19
Figure 6. Turn-on/off sequence for minimizing speaker “pop”
TDA7492PE
Mode selection
DS10652 - Rev 3 page 11/19
5
TDA7492PE
Schematic diagram
Schematic diagram
Figure 7. Application circuit
VCC
C1
1uF
C2
1uF
C3
1nF
C4
1nF
R6
22R
INPUT
J1
2
L+
1
4
3
MONO
INPUT
L+, L- Only
L-
R+
R-
C5
100nF
J7
For
Single-Ended
Input
FREQUENCY SHIFT
PS
Q1
KTC3875(S)
R9
180K
R13
1
47k
R14
100k
2
3
C8
100nF
R3
39K
R7
22R
C6
100nF
R1
47k
R21
R20
J12
J9
3V3
J4
C29
PS
R19
4.7k
OUT
2.2uF
1
R10 R11
J8
100k
For
Single-Ended
R12
100k
Input
S2 MUTE
1
3
2
S1
IC2
3
L4931CZ33
IN
3
2
2 GND C9
100nF
C11
1uF
C12
1uF
R4
33k
R2
33k
R8
VCC
1.2k
J11
J10
J3
J15
+ C15
2.2uF
16V
+ C7
2.2uF
16V
J6
J5
C10
100nF
C13
1nF
C14
1nF
3V3 POWER SUPPLY
C25
100nF
C17
4.7uF
10V
C16
10uF
10V
C30
1uF
C27
330pF
VCC
R5
22R
C19
100nF
C31
1uF
C21
330pF
VCC
TDA7492PE CLASS-D AMPLIFIER
MONO
OUT
MONO
OUT
C28
220nF
C26
*220nF
C24
220nF
C23
2200uF
35V
+
C18
220nF
C20
*220nF
C22
220nF
Optional components or circuitry
R15
8R
C40
220nF
C41
220nF
R16
8R
1
2
VCC
GND
J2
R17
8R
C42
220nF
C43
220nF
R18
8R
L-OUTPUT
Load=6 ohm
L+
2
1
L-
J13
R-OUTPUT
Load=6 ohm
R+ J14
1
R2
Load impedance
4 Ω
6 Ω
8 Ω
L4, L3, L2, L1
15 µh
22 µh
22 µh
Table 12. BTL configuration
C26, C20
1 µF
680 nF
470 nF
C28, C24, C22,
C18
220 nF
220 nF
220 nF
R15, R16, R17,
R18
8 Ω
8 Ω
8 Ω
C40, C41, C42,
C43
220 nF
220 nF
220 nF
DS10652 - Rev 3 page 12/19
6
TDA7492PE
Characterization curves
Characterization curves
Unless otherwise stated, measurements were made under the following conditions:
V
CC
= 22 V, RI = 6 Ω, f = 1 kHz, Gv = 20.8 dB, R
OSC
= 33 kΩ, Gain = 20.8 dB and T amb
= 25 °C.
Note: Maximum output power must be derated according to case temperature.
Figure 8. Output power vs. supply voltage
Figure 9. Efficiency vs. output power
90
80
70
60
50
40
30
Vs = 20 V
Rl = 6 ohm f = 1 kHz
20
10
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Pout per channel (W)
Figure 10. THD vs. output power (f = 1 kHz)
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10 m 20 m
Vs = 20 V, Rl = 6 Ω , f = 1 kHz
50 m 100m 200m 500m
Pout (W)
1 2 5 10 20 50
Figure 11. THD vs. output power (100 Hz)
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10m 20m
Vs = 20 V, Rl = 6 Ω , f = 100 Hz
50m 100 m 200 m 500 m
Pout (W)
1 2 5 10 20 50
DS10652 - Rev 3 page 13/19
DS10652 - Rev 3
TDA7492PE
Characterization curves
Figure 12. THD vs. frequency
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
Vs = 20 V, Rl = 6 Ω , f = 1 kHz, Pout = 1 W
50 100 200 500 freq (Hz)
1k 2k 5k 10k 20k
Figure 13. Frequency response
+2
+1.5
+1
+0.5
-0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
-6
20
Vs = 20 V, Rl = 6 Ω, Pout = 1 W
50 100 200 500 freq (Hz)
1k 2k 5k 10k 20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
Figure 14. FFT (0 dB)
Vs = 20 V, Rl = 6 Ω,
Pout = 1 W, f = 1 kHz
50 100 200 500 1 k freq (Hz)
2 k 5 k 10 k 20 k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
Figure 15. FFT (-60 dB)
Vs = 20 V, Rl= 6 Ω,
Pout = 1 W, f = 1 kHz
50 100 200 500 freq (Hz)
1k 2 k 5 k 10 k 20 k
Figure 16. PSRR parameter page 14/19
7
TDA7492PE
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS10652 - Rev 3 page 15/19
7.1
TDA7492PE
PowerSSO-36 EPD package information
PowerSSO36 EPD package information
Figure 17. PowerSSO-36 EPD package outline
DS10652 - Rev 3
7587131_I page 16/19
DS10652 - Rev 3
Symbol
E3
E4
G1
G2
G3
D3 e
E
E1
E2 b b1 c c1
D
D1
D2
θ
θ1
θ2
A
A1
A2 h
L
L1
L2
N
R
R1
S
TDA7492PE
PowerSSO-36 EPD package information
-
-
0.30
0.55
4.10
-
-
-
Min.
0º
5°
0°
2.15
0.00
2.15
0.18
0.13
0.23
0.20
6.50
-
-
0.30
0.20
0.25
Table 13. PowerSSO-36 EPD package mechanical data
Dimensions in mm
Typ.
-
-
-
-
-
-
-
0.25
-
0.20
10.30 BSC
-
3.65
4.30
0.50 BSC
10.30 BSC
7.50 BSC
-
2.30
2.90
1.20
1.00
0.80
-
0.70
1.40 REF
0.25 BSC
Max.
8°
10°
-
2.45
0.10
2.35
0.32
0.30
0.32
0.30
7.10
-
-
-
-
0.40
0.85
4.70
-
-
-
Min.
0º
5°
0°
0.085
0.00
0.085
0.007
0.005
0.009
0.008
0.256
-
-
0.161
-
-
-
-
-
0.012
0.022
Dimensions in inches
Typ.
-
-
-
-
-
-
-
0.010
-
0.008
0.406 BSC
-
0.144
0.169
0.020 BSC
0.406 BSC
0.295 BSC
-
0.091
0.114
0.047
0.039
0.032
-
0.028
0.055 REF
0.010 BSC
36
-
-
-
-
-
0.012
0.008
0.010
-
-
-
0.280
-
-
0.185
-
-
-
-
-
0.016
0.033
Max.
8°
10°
-
0.096
0.004
0.093
0.013
0.012
0.013
0.012
-
-
page 17/19
Revision history
Date
14-Nov-2014
24-Feb-2017
21-Sep-2020
Revision
1
2
3
Table 14. Document revision history
Changes
Initial release
Updated minimum voltage to 7 V throughout datasheet
Updated V
OS
and T r
, T f
in
Table 4. Electrical specifications
.
Updated Section 7.1 PowerSSO-36 EPD package information
.
Updated order code table.
TDA7492PE
DS10652 - Rev 3 page 18/19
TDA7492PE
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DS10652 - Rev 3 page 19/19
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