PowerSSO-36 with exposed pad down
Features
50 W continuous output power: R
L
THD = 10% at V
CC
= 25 V
= 6 ,
40 W continuous output power: R
L
THD = 10% at V
CC
= 25 V
= 8 ,
Wide range single supply operation (10 - 26 V)
High efficiency ( = 90%)
Four selectable, fixed gain settings of nominally 21.6 dB, 27.6 dB, 31.1 dB and
33.6 dB
Differential inputs minimize common-mode noise
Standby and mute features
Short-circuit protection
Thermal-overload protection
Externally synchronizable
TDA7492MV
50 W mono BTL class-D audio amplifier
Datasheet
-
production data
Description
The TDA7492MV is a mono BTL class-D audio amplifier with single power supply designed for home systems and docking stations.
Thanks to the high efficiency and an exposed-pad-down (EPD) package no heatsink is required.
Order code
TDA7492MV13TR
Table 1. Device summary
Operating temp. range Package
0 to 70 °C PowerSSO-36 EPD
May 2020
This is information on a product in full production.
DocID16264 Rev 3
Packaging
Tape and reel
1/28 www.st.com
1
2
Contents
Contents
3
4
5
6
7
TDA7492MV
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
For 6
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
For 8
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3
Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4
Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5
Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5.1
5.5.2
Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6
Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.7
Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
PowerSSO-36 EPD package mechanical data . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28 DocID16264 Rev 3
TDA7492MV
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9.
PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10.
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID16264 Rev 3 3/28
28
List of figures
List of figures
TDA7492MV
Figure 1.
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.
Pin connection (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3.
Output power vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4.
THD vs output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5.
THD vs output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6.
THD vs frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7.
THD vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8.
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9.
FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10.
FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.
Output power vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.
THD vs output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13.
THD vs output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14.
THD vs frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15.
THD vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16.
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17.
FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18.
FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19.
Test board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20.
Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21.
Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22.
Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23.
Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 24.
Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25.
Typical LC filter for a 8
speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26.
Typical LC filter for a 4
speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27.
Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28.
PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/28 DocID16264 Rev 3
TDA7492MV
1 Device block diagram
Figure 1 shows the block diagram of the TDA7492MV.
Figure 1. Internal block diagram
Device block diagram
DocID16264 Rev 3 5/28
28
Pin description
2 Pin description
2.1 Pin out
Figure 2. Pin connection (top view, PCB view)
SUB_GND
NC
NC
NC
NC
NC
NC
NC
NC
OUTN
OUTN
PVCC
PVCC
PGND
PGND
OUTP
OUTP
PGND
8
9
10
11
6
7
4
5
12
13
14
15
1
2
3
16
17
18
EP, exposed pad down
Connect to ground
29
28
27
26
33
32
31
30
25
24
36
35
34
23
22
21
20
19
TDA7492MV
DIAG
SGND
VDDS
SYNCLK
ROSC
INN
INP
MUTE
STBY
VDDPW
VSS
SVCC
VREF
SGND2
VDDS2
GAIN1
GAIN0
SVR
6/28 DocID16264 Rev 3
TDA7492MV
2.2 Pin list
-
19
23
24
25
20
21
22
26
31
32
33
34
35
36
27
28
29
30
Pin n°
1
2,3
4,5
6,7
8,9
10,11
12,13
14,15
16,17
18
Name
SUB_GND
NC
NC
NC
NC
OUTN
PVCC
PGND
OUTP
PGND
VDDS
SGND
DIAG
SVR
GAIN0
GAIN1
VDDS2
SGND2
VREF
SVCC
VSS
VDDPW
STBY
MUTE
INP
INN
ROSC
SYNCLCK
EP
Pin description
POWER
OUT
OUT
INPUT
INPUT
INPUT
INPUT
OUT
POWER
OUT
-
Table 2. Pin description list
Type Description
-
-
POWER
-
-
OUT
POWER
POWER
OUT
POWER
OUT
INPUT
INPUT
INPUT
INPUT
OUT
IN/OUT
OUT
Connect to the frame
No internal connection
No internal connection
No internal connection
No internal connection
Negative PWM output
Power supply for output channel
Power ground for output channel
Positive PWM output
Power supply ground
3.3-V (nominal) regulator output referred to ground for power stage
Standby mode control
Mute mode control
Positive differential input
Negative differential input
Master oscillator frequency-setting pin
Clock in/out for external oscillator
3.3-V (nominal) regulator output referred to ground for signal blocks
Signal ground
Open-drain diagnostic output
Supply voltage rejection
Gain setting input 1
Gain setting input 2
To be connected to VDDS (pin 26)
To be connected to SGND (pin 27)
Half VDDS (nominal) referred to ground
Signal power supply
3.3-V (nominal) regulator output referred to power supply
Exposed pad for ground-plane heatsink, to be connected to ground
DocID16264 Rev 3 7/28
28
Electrical specifications
3 Electrical specifications
3.1 Absolute maximum ratings
Symbol
V
CC
V
T
T
T
I op j stg
Table 3. Absolute maximum ratings
Parameter
DC supply voltage for pins PVCC, SVCC
Voltage limits for input pins
STBY, MUTE, INN, INP, GAIN0, GAIN1
Operating temperature
Junction temperature
Storage temperature
30
Value
-0.3 - 3.6
0 to 70
-40 to 150
-40 to 150
TDA7492MV
Unit
V
V
°C
°C
°C
3.2 Thermal data
Symbol
R th j-case
Table 4. Thermal data
Parameter
Thermal resistance, junction to case -
Min Typ Max Unit
2 3 °C/W
3.3
8/28
Electrical specifications
Unless otherwise stated, the results in
Table 5
below are given for the conditions:
V
CC
= 25 V, R
Tamb = 25 °C.
L
(load) = 8 , R
OSC
= R3 = 39 k , C8 = 100 nF, f = 1 kHz, G
V
= 21.6 dB and
Symbol
V
CC
I q
I qSTBY
V
OS
I
OCP
T j
R i
V
OVP
V
UVP
Table 5. Electrical specifications
Parameter Condition
Supply voltage for pins PVCCA, PVCCB, SVCC
Total quiescent current
Quiescent current in standby
-
-
Without LC
Play mode
Output offset voltage
Mute mode
Overcurrent protection threshold R
L
= 0
Junction temperature at thermal shutdown
-
Input resistance Differential input
Overvoltage protection threshold -
Undervoltage protection threshold
-
-
Min Typ Max Unit
10
-
48
28
-
-
26
2.5
-100 -
-60 -
4.8
6.0
150 -
-
60
29
26
-
-
7
V
35 mA
5.0
µA
-
100
60 mV
A
°C k
V
V
DocID16264 Rev 3
TDA7492MV Electrical specifications
Symbol
Table 5. Electrical specifications (continued)
Parameter Condition Min Typ Max Unit
R dsON
Power transistor on resistance
High side
Low side -
0.2
0.2
-
-
P
P
P
o o
D
THD
Output power
Output power
Dissipated power
Efficiency
Total harmonic distortion
THD = 10%
THD = 1%
R
L
= 6 , THD = 10%,
V
CC
= 25V
R
L
= 6 , THD = 1%
V
CC
= 25V
P o
=40W, THD = 10%
P o
= 40 W
P o
= 1 W
GAIN0 = L, GAIN1 = L
GAIN0 = L, GAIN1 = H
-
-
-
-
-
-
80
40
32
50
40
4.0
90
0.1
-
-
-
-
-
-
0.4
W
W
W
%
%
G
V
Closed-loop gain
20.6
21.6
22.6
26.6
27.6
28.6
30.1
31.1
32.1
dB
GAIN0 = H, GAIN1 = L
G
V
Gain matching -
GAIN0 = H, GAIN1 = H 32.6
33.6
34.6
-1 1 dB eN
SVRR
Total input noise
Supply voltage rejection ratio
A Curve, G
V
= 20 dB f = 22 Hz to 22 kHz
fr = 100 Hz, Vr = 0.5 V,
C
SVR
= 10 µF
-
-
40
20
25
50 -
-
35
µV dB f f
T r
, T
SW
SWR f
Rise and fall times
Switching frequency
Output switching frequency range
50 ns
Internal oscillator
With internal oscillator
(1)
With external oscillator
(2)
290 310 330 kHz
250 -
250 -
400
400 kHz
V inH
V inL
Digital input high (H)
Digital input low (L)
-
-
2.3
-
-
A
MUTE
Mute attenuation V
MUTE
= 1 V 60 80
1. f
SW
= 10 6 / ((16 * R
OSC
+ 182) * 4) kHz, f
SYNCLK
= 2 * f
SW
with R3 = 39 k (see
Figure 20.
).
2. f
SW
= f
SYNCLK
/ 2 with the frequency of the external oscillator.
-
-
-
0.8
V dB
DocID16264 Rev 3 9/28
28
Characterization curves
4 Characterization curves
4.1
TDA7492MV
The following characterization curves were made using the TDA7492MV exposed-paddown test board with V
CC
= 25 V, a signal frequency of 1 kHz and an output power of 1 W unless otherwise specified.
The LC filter for the 8 load uses components of 33 µH and 220 nF and for the 6 load
22 µH and 220 nF.
For 6 load
Figure 3. Output power vs supply voltage
THD = 10%
THD = 1%
15 16 17 18 19 20 21 22 23 24 25
Figure 4. THD vs output power (1 kHz)
10/28 DocID16264 Rev 3
TDA7492MV Characterization curves
Figure 5. THD vs output power (100 Hz)
Figure 6. THD vs frequency (100 mW)
0.01
20
Figure 7. THD vs frequency
0.01
20
DocID16264 Rev 3 11/28
28
Characterization curves
Figure 8. Frequency response
TDA7492MV
-5
10
Figure 9. FFT (0 dB)
-150
20
Figure 10. FFT (-60 dB)
12/28
-150
20
DocID16264 Rev 3
TDA7492MV
4.2 For 8 load
Characterization curves
Figure 11. Output power vs supply voltage
42
38
34
30
THD = 10%
26
22
THD = 1%
18
14
10
15 16 17 18 19 20 21 22 23 24 25
Supply Voltage (V)
Figure 12. THD vs output power (1 kHz)
DocID16264 Rev 3 13/28
28
Characterization curves
Figure 13. THD vs output power (100 Hz)
TDA7492MV
Figure 14. THD vs frequency (100 mW)
0.01
20
Figure 15. THD vs frequency
14/28
0.01
20
DocID16264 Rev 3
TDA7492MV
Figure 16. Frequency response
Characterization curves r r
-5
10
Figure 17. FFT (0 dB)
+10
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20 50 100 200 500 1k 2k 5k 10k 20k
Figure 18. FFT (-60 dB)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20 50 100 200 500 1k 2k 5k 10k 20k
DocID16264 Rev 3 15/28
28
Characterization curves
4.3 Test board
Figure 19. Test board layout
TDA7492MV
16/28 DocID16264 Rev 3
TDA7492MV
5 Applications information
5.1
Applications information
Applications circuit
Figure 20. Applications circuit for class-D amplifier
TDA7492MV
DocID16264 Rev 3 17/28
28
Applications information
5.2 Mode selection
TDA7492MV
The three operating modes of the TDA7492MV are set by the two inputs STBY (pin 20) and
MUTE (pin 21).
Standby mode: all circuits are turned off, very low current consumption.
Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle.
Play mode: the amplifiers are active.
The protection functions of the TDA7492MV are realized by pulling down the voltages of the
STBY and MUTE inputs shown in
Figure 21
. The input current of the corresponding pins must be limited to 200 µA.
Mode Selection
L
(1)
H
(1)
H
Table 6. Mode settings
STBY
Standby
Mute
Play
1. Drive levels defined in
Table 5: Electrical specifications on page 8
0 V
0 V
X (don’t care)
L
H
MUTE
Figure 21. Standby and mute circuits
Standby
3.3 V
Mute
3.3 V
R2
30 k
R4
30 k
C7
2.2 µF
C15
2.2 µF
STBY
TDA7492MV
MUTE
Figure 22. Turn-on/off sequence for minimizing speaker “pop”
18/28 DocID16264 Rev 3
TDA7492MV
5.3
Applications information
Gain setting
The gain of the TDA7492MV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31).
Internally, the gain is set by changing the feedback resistors of the amplifier.
GAIN0
L
L
H
H
Table 7. Gain settings
GAIN1
L
H
L
H
Nominal gain, G v
(dB)
21.6
27.6
31.1
33.6
5.4 Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 60 k (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 23 . For Ci = 470 nF the high-pass filter cut-off frequency is below 20 Hz:
fc = 1 / (2 * * Ri * Ci)
Figure 23. Device input circuit and frequency response
Rf
Input signal
Ci
Input pin
Ri
DocID16264 Rev 3 19/28
28
Applications information
5.5
5.5.1
5.5.2
Internal and external clocks
TDA7492MV
The clock of the class-D amplifier can be generated internally or can be driven by an external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one
TDA7492MV as master clock, while the other devices are in slave mode (that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
Master mode (internal clock)
Using the internal oscillator, the output switching frequency, f
SW resistor, R
OSC
, connected to pin ROSC:
, is controlled by the f
SW
= 10 6 / ((16 * R
OSC
+ 182) * 4) kHz where R
OSC
is in k .
In master mode, pin SYNCLK is used as a clock output pin, whose frequency is: f
SYNCLK
= 2 * f
SW
For master mode to operate correctly then resistor R
OSC below in
Table 8
.
must be less than 60 k as given
Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in
Table 8
.
The output switching frequency of the slave devices is: f
SW
= f
SYNCLK
/ 2
Master
Slave
Mode
Table 8. How to set up SYNCLK
ROSC
R
OSC
< 60 k
Floating (not connected)
Output
Input
SYNCLK
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TDA7492MV Applications information
Cosc
100 nF
Figure 24. Master and slave connection
Master Slave
TDA7492xy TDA7492M
ROSC ROSC SYNCLK
Output
SYNCLK
Input
Rosc
39 k
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Applications information
5.6 Output low-pass filter
TDA7492MV
To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L-C component values depending on the loud speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are shown in
Figure 25
and
Figure 26 below.
Figure 25. Typical LC filter for a 8 speaker
Figure 26. Typical LC filter for a 4 speaker
5.7
22/28
Protection function
The TDA7492MV is fully protected against overvoltage, undervoltage, overcurrent and thermal overloads as explained here.
Overvoltage protection (OVP)
If the supply voltage exceeds the value for V
OVP
given in
Table 5: Electrical specifications on page 8
the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range the device restarts.
Undervoltage protection (UVP)
If the supply voltage drops below the value for V
UVP
given in Table 5: Electrical specifications on page 8
the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers to within the operating range the device restarts.
DocID16264 Rev 3
TDA7492MV Applications information
Overcurrent protection (OCP)
If the output current exceeds the value for I
OCP
given in Table 5: Electrical specifications on page 8
the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, T
OC by the R-C components connected to pin STBY.
, is determined
Thermal protection (OTP)
If the junction temperature, T j
, reaches 145 °C (nominal), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature exceeds the value for T j
given in Table 5: Electrical specifications on page 8 the
device shuts down and the output is forced to the high impedance state. When the device cools sufficiently the device restarts.
5.8 Diagnostic output
The output pin DIAG is an open drain transistor. When the protection is activated it is in the high-impedance state. The pin can be connected to a power supply (< 26 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin.
Figure 27. Behavior of pin DIAG for various protection conditions
VDD
TDA7492MV
R1
DIAG
Protection logic
VDD
Overcurrent protection
Restart
OV, UV, OT protection
Restart
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Package information
6 Package information
TDA7492MV
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
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TDA7492MV
6.1
Package information
PowerSSO-36 EPD package mechanical data
The TDA7492MV comes in a 36-pin PowerSSO package with exposed pad down.
Figure 28
below shows the package outline and Table 9 gives the dimensions.
Figure 28. PowerSSO-36 EPD outline drawing
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Package information TDA7492MV
Symbol
U
X
Y
Q
S
T h k
L
M
N
O
E e e3
F
G
H
A
A2 a1 b c
D
Min.
-
4.10
6.50
-
-
-
-
0
0.60
-
-
-
7.40
-
-
-
-
10.10
2.15
2.15
0.00
0.18
0.23
10.10
Max.
0.40
8 degrees
1.00
-
10 degrees
-
-
4.70
7.10
-
-
-
7.60
-
-
-
0.10
10.50
2.47
2.40
0.10
0.36
0.32
10.50
Table 9. PowerSSO-36 EPD dimensions
Dimensions in mm Dimensions in inches
Typ.
0.80
2.90
3.65
1.00
-
-
-
-
-
4.30
-
1.20
-
0.5
8.5
2.3
-
-
-
-
-
-
-
-
Min.
-
-
-
-
0.161
0.256
-
-
-
-
0
0.024
0.291
-
-
-
-
0.398
0.085
0.085
0.000
0.007
0.009
0.398
Typ.
0.031
0.114
0.144
0.039
-
-
-
-
-
0.169
-
0.047
-
0.020
0.335
0.091
-
-
-
-
-
-
-
-
Max.
0.016
8 degrees
0.039
-
10 degrees
-
-
-
-
-
0.185
0.280
0.299
-
-
-
0.004
0.413
0.097
0.094
0.004
0.014
0.013
0.413
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TDA7492MV
7 Revision history
Date
20-Oct-2009
20-Feb-2014
11-May-2020
Table 10. Document revision history
Revision Changes
1
2
3
Initial release
Updated order code Table 1 on page 1
Updated Y dimensions in
Table 9
Revision history
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TDA7492MV
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