STMicroelectronics VND7012AY Datasheet

VND7012AY
Double channel high-side driver with MultiSense analog
feedback for automotive applications
Datasheet - production data




Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
Loss of ground and loss of VCC
Reverse battery through self turn-on
Electrostatic discharge protection
Applications

Features
Max transient supply voltage
VCC
41 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch)
RON
12 mΩ
Current limitation (typ)
ILIMH
75 A
Standby current (max)
ISTBY
0.5 µA




AEC-Q100 qualified
General

Double channel smart high side driver
with MultiSense analog feedback

Very low standby current

Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions

Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature

Overload and short to ground (power
limitation) indication

Thermal shutdown indication

Off-state open-load detection

Output short to VCC detection

Sense enable/ disable
Protections

Undervoltage shutdown

Overvoltage clamp

Load current limitation

Self limiting of fast thermal transients
July 2016

All types of Automotive resistive, inductive
and capacitive loads
Specially intended for Automotive Turn
Indicators (up to 3 x P27W or SAE1156 and
2 x R5W paralleled or Automotive
Headlamps)
Description
The device is a double channel high-side driver
manufactured using ST proprietary VIPower®
M0-7 technology and housed in PowerSSO-36
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
DocID027407 Rev 4
This is information on a product in full production.
1/45
www.st.com
Contents
VND7012AY
Contents
1
Block diagram and pin description ................................................ 5
2
Electrical specification .................................................................... 7
3
4
5
6
2.1
Absolute maximum ratings ................................................................ 7
2.2
Thermal data ..................................................................................... 8
2.3
Main electrical characteristics ........................................................... 8
2.4
Electrical characteristics curves ...................................................... 21
Protections..................................................................................... 25
3.1
Power limitation ............................................................................... 25
3.2
Thermal shutdown ........................................................................... 25
3.3
Current limitation ............................................................................. 25
3.4
Negative voltage clamp ................................................................... 25
Application information ................................................................ 26
4.1
GND protection network against reverse battery............................. 26
4.2
Immunity against transient electrical disturbances .......................... 27
4.3
MCU I/Os protection ........................................................................ 27
4.4
Multisense - analog current sense .................................................. 28
Principle of Multisense signal generation ......................................... 29
4.4.2
TCASE and VCC monitor ................................................................. 31
4.4.3
Short to VCC and OFF-state open-load detection ........................... 32
Maximum demagnetization energy (VCC = 16 V) ........................ 33
Package and PCB thermal data .................................................... 34
6.1
7
4.4.1
PowerSSO-36 thermal data ............................................................ 34
Package information ..................................................................... 38
7.1
PowerSSO-36 package information ................................................ 38
7.2
PowerSSO-36 packing information ................................................. 40
7.3
PowerSSO-36 marking information ................................................. 42
8
Order codes ................................................................................... 43
9
Revision history ............................................................................ 44
2/45
DocID027407 Rev 4
VND7012AY
List of tables
List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Power section ............................................................................................................................... 8
Table 6: Switching (VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified) ................................. 9
Table 7: Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) ................................................................ 10
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C) ................................................................. 11
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) ................................................................. 11
Table 10: Truth table ................................................................................................................................. 19
Table 11: MultiSense multiplexer addressing ........................................................................................... 20
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 27
Table 13: MultiSense pin levels in off-state .............................................................................................. 31
Table 14: PCB properties ......................................................................................................................... 35
Table 15: Thermal parameters ................................................................................................................. 36
Table 16: PowerSSO-36 mechanical data................................................................................................ 38
Table 17: Reel dimensions ....................................................................................................................... 40
Table 18: PowerSSO-36 carrier tape dimensions .................................................................................... 41
Table 19: Device summary ....................................................................................................................... 43
Table 20: Document revision history ........................................................................................................ 44
DocID027407 Rev 4
3/45
List of figures
VND7012AY
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE vs. IOUT ............................................................................................................. 17
Figure 5: Current sense precision vs. IOUT ............................................................................................. 17
Figure 6: Switching times and Pulse skew ............................................................................................... 18
Figure 7: MultiSense timings (current sense mode) ................................................................................. 18
Figure 8: MultiSense timings (chip temperature and VCC sense mode) ................................................. 19
Figure 9: TDSKON .................................................................................................................................... 19
Figure 10: OFF-state output current ......................................................................................................... 21
Figure 11: Standby current ....................................................................................................................... 21
Figure 12: IGND(ON) vs. Iout ................................................................................................................... 21
Figure 13: Logic Input high level voltage .................................................................................................. 21
Figure 14: Logic Input low level voltage.................................................................................................... 21
Figure 15: High level logic input current ................................................................................................... 21
Figure 16: Low level logic input current .................................................................................................... 22
Figure 17: Logic Input hysteresis voltage ................................................................................................. 22
Figure 18: FaultRST Input clamp voltage ................................................................................................. 22
Figure 19: Undervoltage shutdown ........................................................................................................... 22
Figure 20: On-state resistance vs. Tcase ................................................................................................. 22
Figure 21: On-state resistance vs. VCC ................................................................................................... 22
Figure 22: Turn-on voltage slope .............................................................................................................. 23
Figure 23: Turn-off voltage slope .............................................................................................................. 23
Figure 24: Won vs. Tcase ......................................................................................................................... 23
Figure 25: Woff vs. Tcase ......................................................................................................................... 23
Figure 26: ILIMH vs. Tcase ....................................................................................................................... 23
Figure 27: OFF-state open-load voltage detection threshold ................................................................... 23
Figure 28: Vsense clamp vs. Tcase.......................................................................................................... 24
Figure 29: Vsenseh vs. Tcase .................................................................................................................. 24
Figure 30: Application diagram ................................................................................................................. 26
Figure 31: Simplified internal structure ..................................................................................................... 26
Figure 32: MultiSense and diagnostic – block diagram ............................................................................ 28
Figure 33: MultiSense block diagram ....................................................................................................... 29
Figure 34: Analogue HSD – open-load detection in off-state ................................................................... 30
Figure 35: Open-load / short to VCC condition ......................................................................................... 31
Figure 36: GND voltage shift .................................................................................................................... 32
Figure 37: Maximum turn off current versus inductance .......................................................................... 33
Figure 38: PowerSSO-36 PCB board ....................................................................................................... 34
Figure 39: Rthj-amb vs PCB copper area in open box free air condition (one channel on) ..................... 35
Figure 40: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .............. 36
Figure 41: Thermal fitting model of a double-channel HSD in PowerSSO-16.......................................... 36
Figure 42: PowerSSO-36 package outline ............................................................................................... 38
Figure 43: PowerSSO-36 reel 13" ............................................................................................................ 40
Figure 44: PowerSSO-36 carrier tape ...................................................................................................... 41
Figure 45: PowerSSO-36 schematic drawing of leader and trailer tape .................................................. 42
Figure 46: PowerSSO-36 marking information ......................................................................................... 42
4/45
DocID027407 Rev 4
VND7012AY
1
Block diagram and pin description
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Name
VCC
OUTPUT0,1
GND
INPUT0,1
MultiSense
SEn
Function
Battery connection.
Power output.
Ground connection.
Voltage controlled input pin with hysteresis, compatible with 3V and 5V CMOS
outputs. They control output switch state.
Multiplexed analog sense output pin; delivers a current proportional to the selected
diagnostic: load current, supply voltage or chip temperature.
Active high compatible with 3V and 5V CMOS outputs; it enables the MultiSense
diagnostic pin.
SEL0,1
Active high compatible with 3V and 5V CMOS outputs; they address the MultiSense
multiplexer.
FaultRST
Active low compatible with 3V and 5V CMOS outputs; unlatches the output in case of
fault; if kept low, sets the outputs in auto-restart mode.
DocID027407 Rev 4
5/45
Block diagram and pin description
VND7012AY
Figure 2: Configuration diagram (top view)
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SEn
N.C.
SEL1
SEL0
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TAB/Vcc
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT1
INPUT0
MultiSense
GND
FaultRST
PowerSSO-36 PACKAGE
GAPGCFT00640
Table 2: Suggested connections for unused and not connected pins
SEn, SELx,
Connection/pin
MultiSense
N.C.
Output
Input
Floating
Not allowed
X (1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not
allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
Notes:
(1)X:
6/45
do not care.
DocID027407 Rev 4
FaultRST
VND7012AY
2
Electrical specification
Electrical specification
Figure 3: Current and voltage conventions
IS
VCC
FaultRST
ISEn
IOUT
OUTPUT0,1
ISEL
MultiSense
VSEn
SEL0,1
VSEL
VOUT
ISENSE
SEn
VFR
VCC
VFn
IFR
VSENSE
IIN
VIN
INPUT0,1
IGND
GAPGCFT00315
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
16
VCCPK
Maximum transient supply voltage (ISO7637-2:2004 Pulse 5b level
IV clamped to 40 V; RL = 4 Ω)
40
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1 DC output current
Internally
limited
A
-IOUT
Reverse DC output current
IIN
INPUT0,1 DC input current
ISEn
SEn DC input current
ISEL
SEL0,1 DC input current
IFR
FaultRST DC input current
VFR
FaultRST DC input voltage
DocID027407 Rev 4
V
22
-1 to 10
mA
7.5
V
7/45
Electrical specification
VND7012AY
Symbol
Parameter
Unit
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V)
10
MultiSense pin DC output current in reverse (VCC < 0 V)
-20
EMAX
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150°C)
144
mJ
VESD
Electrostatic discharge (JDEC 22 A-114 F)

INPUT0,1

MultiSense

SEn, SEL0,1, FaultRST

OUTPUT0,1

VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
ISENSE
Tj
Tstg
2.2
Value
mA
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4: Thermal data
Symbol
Parameter
Typ. value
Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1)(2)
Rthj-board
Rthj-amb
Rthj-amb
Unit
4
Thermal resistance junction-ambient (JEDEC JESD
51-5)(1)(3)
50.6
Thermal resistance junction-ambient (JEDEC JESD
51-7)(1)(2)
16.6
°C/W
Notes:
(1)One
2.3
channel ON.
(2)Device
mounted on four-layers 2s2p PCB
(3)Device
mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Power section
Symbol
Test conditions
Min.
Typ.
Max.
4
13
28
VCC
Operating supply
voltage
VUSD
Undervoltage
shutdown
4
VUSDReset
Undervoltage
shutdown reset
5
VUSDhyst
Undervoltage
shutdown hysteresis
RON
8/45
Parameter
On-state resistance
(1)
Unit
V
0.3
IOUT = 7 A; Tj = 25°C
IOUT = 7 A; Tj = 150°C
DocID027407 Rev 4
12
24
mΩ
VND7012AY
Electrical specification
Symbol
Parameter
Test conditions
Min.
Typ.
IOUT = 7 A; VCC = 4 V; Tj = 25°C
RON_REV
Vclamp
On-state resistance
in reverse battery
Supply current in
standby at
VCC = 13 V (2)
ISTBY
41
IS = 20 mA; Tj = -40 °C
38
V
VCC = 13 V;
VIN0,1 = VOUT0,1 = VFR = VSEn 0 V;
VSEL0,1 = 0 V; Tj = 85°C(3)
0.5
µA
VCC = 13 V;
VIN0,1 = VOUT0,1 = VFR = VSEn 0 V;
VSEL0,1 = 0 V; Tj = 125°C
3
µA
300
550
µs
5
8
mA
10
mA
Supply current
VCC = 13 V;
VSEn = VFR = VSEL0,1 = 0 V;
VIN0,1 = 5 V; IOUT0 = 0 A; IOUT1 = 0 A
Control stage current
consumption in ON
state. All channels
active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN0,1 = 5 V;
IOUT0 = 7 A; IOUT1 = 7 A
Output - VCC diode
voltage(1)
V
µA
IS(ON)
VF
52
0.5
VCC = 13 V; VIN0,1 = VOUT0,1 = 0 V;
VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
IL(off)
46
VCC = 13 V;
VIN0,1 = VOUT0,1 = VFR = VSEn 0 V;
VSEL0,1 = 0 V; Tj = 25°C
Standby mode
blanking time
Off-state output
current at
VCC = 13 V (1)
mΩ
12
IS = 20 mA; 25°C < Tj < 150°C
tD_STBY
IGND(ON)
Unit
18
IOUT = -7 A; VCC = -13 V; Tj = 25°C
Clamp voltage
Max.
60
VIN0,1 = VOUT0,1 = 0 V; VCC = 13 V;
Tj = 25°C
0
VIN0,1 = VOUT0,1 = 0 V; VCC = 13 V;
Tj = 125°C
0
0.01
0.5
µA
3
IOUT = -7 A; Tj = 150 °C
0.7
V
Notes:
(1)For
each channel.
(2)PowerMOS
(3)Parameter
leakage included.
specified by design; not subjected to production test.
Table 6: Switching (VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified)
Symbol
Parameter
td(on)(1)
Turn-on delay time at Tj = 25 °C
td(off)(1)
Turn-off delay time at Tj = 25 °C
(dVOUT/dt)on(1)
Turn-on voltage slope at Tj = 25 °C
(1)
Turn-off voltage slope at Tj = 25 °C
(dVOUT/dt)off
Test
conditions
RL = 1.84 Ω
RL = 1.84 Ω
Min.
Typ.
Max.
10
50
120
10
45
100
0.1
0.45
0.7
0.2
0.5
0.8
WON
Switching energy losses at turn-on
(twon)
RL = 1.84 Ω
—
0.6
WOFF
Switching energy losses at turn-off
(twoff)
RL = 1.84 Ω
—
0.6
DocID027407 Rev 4
1.4
(2)
1.3
(2)
Unit
µs
V/µs
mJ
mJ
9/45
Electrical specification
VND7012AY
Symbol
tSKEW (1)
Test
conditions
Parameter
Differential pulse skew (tPHL - tPLH)
RL = 1.84 Ω
Min.
Typ.
Max.
Unit
-60
-10
40
µs
Max.
Unit
Notes:
(1)See
Figure 6: "Switching times and Pulse skew"
(2)Parameter
guaranteed by design and characterization, not subjected to production test.
Table 7: Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min.
Typ.
INPUT0,1 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
0.9
VIN = 0.9 V
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
1
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
FaultRST characteristics
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
µA
7.5
-0.7
V
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Input clamp voltage
0.9
VIN = 0.9 V
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
1
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
10/45
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
DocID027407 Rev 4
V
5.3
µA
V
7.2
V
VND7012AY
Electrical specification
Symbol
Parameter
Test conditions
Min.
IIN = -1 mA
Typ.
Max.
Unit
-0.7
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
VCC = 13 V
DC short circuit
current
ILIMH(1)
Min.
Typ.
Max.
60
75
96
4 V < VCC < 18 V (2)
ILIML
Short circuit current
during thermal cycling
TTSD
Shutdown
temperature
TR
Reset temperature(2)
TRS
Thermal reset of fault
diagnostic indication
96
VCC = 13 V; TR < Tj < TTSD
VFR = 0 V; VSEn = 5 V
150
175
TRS + 1
TRS + 5
°C
5
ΔTJ_SD
Dynamic temperature
60
VFR = 5 V to 0 V;
VSEn = 5 V; VIN0,1 = 5 V;
VSEL0,1 = 0 V
Turn-off output
voltage clamp
VDEMAG
Output voltage drop
limitation
VON
200
135
Thermal hysteresis
(TTSD - TR)(2)
Fault reset time for
output unlatch(2)
A
25
THYST
tLATCH_RST
Unit
3
10
IOUT = 2 A; L = 6 mH; Tj = 40 °C
VCC 38
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC 41
IOUT = 0.7 A
K
20
µs
V
VCC 46
VCC 52
20
mV
Notes:
(1)Parameter
guaranteed by an indirect test sequence.
(2)Parameter
guaranteed by design and characterization; not subjected to production test.
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
VSENSE_CL
MultiSense clamp
voltage
Test conditions
VSEn = 0 V;
ISENSE = 1 mA
Min.
Typ.
-17
VSEn = 0 V; ISENSE = 1 mA
Max.
Unit
-12
V
7
V
Current Sense characteristics
KOL
dKcal/Kcal(1)(2)
IOUT/ISENSE
IOUT = 10 mA;
VSENSE = 0.5 V;
VSEn = 5 V
1400
Current sense ratio
drift at calibration point
ICAL = 130 mA;
IOUT = 10 mA to
250 mA;
VSENSE = 0.5 V;
VSEn = 5 V
-35
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35
%
11/45
Electrical specification
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
KLED
IOUT/ISENSE
IOUT = 250 mA;
VSENSE = 0.5 V;
VSEn = 5 V
2490
5100
8000
K0
IOUT/ISENSE
IOUT = 0.7 A;
VSENSE = 0.5 V;
VSEn = 5 V
2560
5120
7680
Current sense ratio
drift
IOUT = 0.7 A;
VSENSE = 0.5 V;
VSEn = 5 V
-25
IOUT/ISENSE
IOUT = 1.4 A;
VSENSE = 4 V;
VSEn = 5 V
3480
Current sense ratio
drift
IOUT = 1.4 A;
VSENSE = 4 V;
VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 7 A;
VSENSE = 4 V;
VSEn = 5 V
3410
Current sense ratio
drift
IOUT = 7 A;
VSENSE = 4 V;
VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 21 A;
VSENSE = 4 V;
VSEn = 5 V
3810
Current sense ratio
drift
IOUT = 21 A;
VSENSE = 4 V;
VSEn = 5 V
-5
5
%
MultiSense disabled:
VSEn = 0 V;
0
0.5
µA
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
0.5
µA
MultiSense enabled:
VSEn = 5 V;
All channel ON;
IOUTX = 0 A;
ChX diagnostic
selected;

E.g. Ch0:
VIN0 = 5 V;
VIN1 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A;
IOUT1 = 7 A
0
2
µA
dK0/K0(1)(2)
K1
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
dK3/K3(1)(2)
ISENSE0
12/45
VND7012AY
MultiSense leakage
current
DocID027407 Rev 4
25
4900
6470
20
4280
%
5120
10
4300
%
%
4660
VND7012AY
Electrical specification
Symbol
Parameter
Test conditions
MultiSense enabled:
VSEn = 5 V;
ChX channel OFF;
ChX diagnostic
selected;

E.g. Ch0:
VIN0 = 0 V;
VIN1 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT1 = 7 A
VOUT_MSD(1)
VSENSE_SAT
ISENSE_SAT(1)
IOUT_SAT(1)
Min.
Typ.
0
Max.
Unit
2
µA
Output Voltage for
MultiSense shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩ

E.g. Ch0:
VIN0 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 7 A
Multisense saturation
voltage
VCC = 7 V;
RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0,1 = 0 V;
IOUT0 = 21 A; Tj = 150°C
5
V
CS saturation current
VCC = 7 V;
VSENSE = 4 V;
VSEn = 5 V; VIN0 = 5 V;
VSEL0,1 = 0 V;
Tj = 150°C
4
mA
Output saturation
current
VCC = 7 V;
VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1 = 0 V;
Tj = 150°C
23
A
Off-state open-load
voltage detection
threshold
VSEn = 5 V; ChX OFF;
ChX diagnostic selected

E.g: Ch0
VIN0 = 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V
2
OFF state output sink
current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
-100
Off-state diagnostic
delay time from falling
edge of INPUT (see
Figure 9: "TDSKON")
VSEn = 5 V; ChX ON to
OFF transition
ChX diagnostic selected

E.g: Ch0
VIN0 = 5 V to 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
100
5
V
Off-state diagnostic
VOL
IL(off2)
tDSTKON
DocID027407 Rev 4
3
350
4
V
-15
µA
700
µs
13/45
Electrical specification
VND7012AY
Symbol
tD_OL_V
tD_VOL
Parameter
Test conditions
Settling time for valid
OFF-state open load
diagnostic indication
from rising edge of
SEn
VIN0 = 0 V; VIN1 = 0 V;
VFR = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V;
VOUT0 = 4 V; VSEn = 0 V
to 5 V
Off-state diagnostic
delay time from rising
edge of VOUT
VSEn = 5 V; ChX OFF
ChX diagnostic selected

E.g: Ch0
VIN0 = 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
VOUT = 0 V to 4 V
Min.
Typ.
Max.
Unit
60
µs
5
30
µs
Chip temperature analog feedback
VSENSE_TC
dVSENSE_TC/dT(1)
MultiSense output
voltage proportional to
chip temperature
Temperature
coefficient
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V;
VIN0,1 = 0 V;
RSENSE = 1 KΩ; Tj = 40°C
2.325
2.41
2.495
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V;
VIN0,1 = 0 V;
RSENSE = 1 kΩ;
Tj = 25°C
1.985
2.07
2.155
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V;
VIN0,1 = 0 V;
RSENSE = 1 kΩ;
Tj = 125°C
1.435
1.52
1.605
V
Tj = -40°C to 150°C
Transfer function
-5.5
mV/K
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
VSENSE_VCC
MultiSense output
voltage proportional to
VCC supply voltage
Transfer function (3)
VCC = 13 V; VSEn = 5 V;
VSEL0 = 5 V;
VSEL1 = 5 V;
VIN0,1 = 0 V;
RSENSE = 1 kΩ
3.16
3.23
3.3
V
6.6
V
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10: "Truth table")
VSENSEH
14/45
MultiSense output
voltage in fault
condition
VCC = 13 V;
RSENSE = 1 kΩ;

E.g: Ch0 in open
load
VIN0 = 0 V;
VSEn = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
DocID027407 Rev 4
5
VND7012AY
Electrical specification
Symbol
ISENSEH
Parameter
MultiSense output
current in fault
condition
Test conditions
VCC = 13 V;
VSENSE = 5 V
Min.
Typ.
Max.
Unit
7
20
30
mA
MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense
mode)")(4)
tDSENSE1H
Current sense settling
time from rising edge
of SEn
VIN = 5 V;
VSEn = 0 V to 5 V;
RSENSE = 1 kΩ;
RL = 1.84 Ω
tDSENSE1L
Current sense disable
delay time from falling
edge of SEn
VIN = 5 V;
VSEn = 5 V to 0 V;
RSENSE = 1 kΩ;
RL = 1.84 Ω
tDSENSE2H
Current sense settling
time from rising edge
of INPUT
VIN = 0 V to 5 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 1.84 Ω
ΔtDSENSE2H
Current sense settling
time from rising edge
of IOUT (dynamic
response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 1.84 Ω
tDSENSE2L
Current sense turn-off
delay time from falling
edge of INPUT
VIN = 5 V to 0 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 1.84 Ω
60
µs
5
20
µs
100
250
µs
100
µs
250
µs
50
MultiSense timings (chip temperature sense mode - see Figure 8: "MultiSense timings (chip
temperature and VCC sense mode)")(4)
tDSENSE3H
VSENSE_TC settling time
from rising edge of
SEn
VSEn = 0 V to 5 V;
VSEL0 = 0 V;
VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE3L
VSENSE_TC disable delay
time from falling edge
of SEn
VSEn = 5 V to 0 V;
VSEL0 = 0 V;
VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (VCC voltage sense mode - see Figure 8: "MultiSense timings (chip
temperature and VCC sense mode)")(4)
tDSENSE4H
VSENSE_VCC settling time
from rising edge of
SEn
VSEn = 0 V to 5 V;
VSEL0 = 5 V;
VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE4L
VSENSE_VCC disable
delay time from falling
edge of SEn
VSEn = 5 V to 0 V;
VSEL0 = 5 V;
VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (Multiplexer transition times) (4)
DocID027407 Rev 4
15/45
Electrical specification
VND7012AY
Symbol
Max.
Unit
MultiSensetransition
delay from ChX to ChY
VIN0 = 5 V; VIN1 = 5 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 0 A; IOUT1 = 3 A;
RSENSE = 1 kΩ
20
µs
tD_CStoTC
MultiSensetransition
delay from current
sense to TC sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V to 5 V;
IOUT0 = 3.5 A;
RSENSE = 1 kΩ
60
µs
tD_TCtoCS
MultiSensetransition
delay from TC sense to
current sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V;
VSEL1 = 5 V to 0 V;
IOUT0 = 3.5 A;
RSENSE = 1 kΩ
20
µs
tD_CStoVCC
MultiSensetransition
delay from current
sense to VCC sense
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V;
VSEL1 = 0 V to 5 V;
IOUT1 = 3.5A;
RSENSE = 1 kΩ
60
µs
tD_VCCtoCS
MultiSensetransition
delay from VCC sense
to current sense
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V;
VSEL1 = 5 V to 0 V;
IOUT1 = 3.5 A;
RSENSE = 1 kΩ
20
µs
tD_TCtoVCC
MultiSensetransition
delay from TC sense to
VCC sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V;
VSEL0 = 0 V to 5 V;
VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
tD_VCCtoTC
MultiSensetransition
delay from VCC sense
to TC sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V;
VSEL0 = 5 V to 0 V;
VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
tD_CStoVSENSEH
MultiSensetransition
delay from stable
current sense on ChX
to VSENSEH on ChY
VIN0 = 5 V; VIN1 = 0 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 7 A;
VOUT1 = 4 V;
RSENSE = 1 kΩ
20
µs
tD_XtoY
Parameter
Test conditions
Notes:
(1)Parameter
(2)All
(3)V
CC
sensing and TC sensing are referred to GND potential.
(4)Transition
16/45
specified by design; not subjected to production test.
values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
delay are measured up to +/- 10% of final conditions.
DocID027407 Rev 4
Min.
Typ.
VND7012AY
Electrical specification
Figure 4: IOUT/ISENSE vs. IOUT
9000
8000
K-factor
Max
7000
Min
6000
Typ
5000
4000
3000
2000
1000
0
0
2
4
6
8
10
12
14
IOUT [A]
16
18
20
22
24
GAPG0907141021CFT
Figure 5: Current sense precision vs. IOUT
60.0
55.0
50.0
45.0
40.0
35.0
Current sense uncalibrated precision
% 30.0
Current sense calibrated precision
25.0
20.0
15.0
10.0
5.0
0.0
0
2
4
6
8
10
12
14
IOUT [A]
16
18
20
22
24
GAPG0907141026CFT
DocID027407 Rev 4
17/45
Electrical specification
VND7012AY
Figure 6: Switching times and Pulse skew
Figure 7: MultiSense timings (current sense mode)
18/45
DocID027407 Rev 4
VND7012AY
Electrical specification
Figure 8: MultiSense timings (chip temperature and VCC sense mode)
Figure 9: TDSKON
Table 10: Truth table
Mode
Conditions
INX
FR
SEn
SELX
OUTX
MultiSense
Standby
All logic inputs
low
L
L
L
L
L
Hi-Z
L
X
L
See (1)
Normal
Nominal load
connected;
Tj < 150°C
H
L
H
See (1)
See (1)
DocID027407 Rev 4
Comments
Low quiescent
current
consumption
Outputs
configured for
auto-restart
19/45
Electrical specification
VND7012AY
Mode
Overload
Conditions
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
INX
FR
H
OUTX
MultiSense
Comments
H
H
See (1)
Outputs
configured for
latch off
L
X
L
See (1)
H
L
H
See (1)
Output cycles
with temperature
hysteresis
H
H
L
See (1)
Output latches
off
L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
H
See (1)
H
See (1)
<0V
See (1)
Undervoltage
VCC < VUSD
(falling)
X
X
Off-state
diagnostics
Short to VCC
L
X
Open-load
L
X
Inductive loads
turn-off
L
X
Negative
output
voltage
SEn
SELX
See
(1)
X
X
See (1)
See (1)
External pull up
Notes:
(1)Refer
to Table 11: "MultiSense multiplexer addressing"
Table 11: MultiSense multiplexer addressing
MultiSense output
SEn
SEL1
SEL0
MUXchannel
Normal
mode
Overload
Off-state
diag. (1)
Negative
output
L
X
X
Hi-Z
H
L
L
Channel 0
diagnostic
ISENSE =
1/K * IOUT0
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
H
Channel 1
diagnostic
ISENSE =
1/K * IOUT1
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
H
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
H
VCC Sense
VSENSE = VSENSE_VCC
Notes:
(1)In
case the output channel corresponding to the selected MUX channel is latched off while the relevant input is
low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L
(latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN0 = 0; OUT0 = latched,
VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = V SENSEH
20/45
DocID027407 Rev 4
VND7012AY
2.4
Electrical specification
Electrical characteristics curves
Figure 10: OFF-state output current
Figure 11: Standby current
ISTBY [µA]
Iloff [nA]
6
3000
5
2500
Off State
Vcc = 13V
Vin = Vout = 0
2000
Vcc = 13V
4
1500
3
1000
2
500
1
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
GAPG0907141458CFT
GAPG0907141459CFT
Figure 13: Logic Input high level voltage
Figure 12: IGND(ON) vs. Iout
ViH, VFRH, VSELH, VSEnH [V]
IGND(ON) [mA]
9.0
2
8.0
1.8
7.0
1.6
6.0
1.4
Vcc = 13V
Iout0 = Iout1 = 7A
1.2
5.0
1
4.0
0.8
3.0
0.6
2.0
0.4
1.0
0.2
0
0.0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
GAPG0907141506CFT
GAPG0907141507CFT
Figure 14: Logic Input low level voltage
Figure 15: High level logic input current
IiH, IFRH, ISELH, ISEnH [µA]
VilL VFRL, VSELL, VSEnL [V]
2
4
1.8
3.5
1.6
3
1.4
2.5
1.2
1
2
0.8
1.5
0.6
1
0.4
0.5
0.2
0
0
-50
-25
0
25
50
75
100
125
150
175
T [°C]
-50
-25
0
25
50
75
100
125
150
175
T [°C]
GAPG0907141508CFT
DocID027407 Rev 4
GAPG0907141509CFT
21/45
Electrical specification
VND7012AY
Figure 16: Low level logic input current
Figure 17: Logic Input hysteresis voltage
IiL, IFRL, ISELL, ISEnL [µA]
Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V]
4
1
3.5
0.9
0.8
3
0.7
2.5
0.6
2
0.5
1.5
0.4
0.3
1
0.2
0.5
0.1
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
GAPG0907141511CFT
GAPG0907141512CFT
Figure 19: Undervoltage shutdown
Figure 18: FaultRST Input clamp voltage
VFRCL [V]
VUSD [V]
8
8
7
7
Iin = 1mA
6
6
5
5
4
4
3
3
2
2
1
Iin = -1mA
0
1
-1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
T [°C]
GAPG0907141513CFT
GAPG0907141514CFT
Figure 20: On-state resistance vs. Tcase
Ron [mOhm]
Figure 21: On-state resistance vs. VCC
Ron [mOhm]
25
50
45
T = 150 °C
20
40
T = 125 °C
35
Iout = 7A
Vcc = 13V
30
15
25
T = 25 °C
10
20
T = -40 °C
15
5
10
5
0
0
-50
-25
0
25
50
75
100
125
150
175
GAPG0907141515CFT
22/45
0
5
10
15
20
25
30
35
40
Vcc [V]
T [°C]
DocID027407 Rev 4
GAPG0907141517CFT
VND7012AY
Electrical specification
Figure 22: Turn-on voltage slope
Figure 23: Turn-off voltage slope
(dVout/dt)On [V/µs]
(dVout/dt)Off [V/µs]
1
1
0.9
0.9
0.8
0.8
Vcc = 13V
Rl = 1.84Ω
0.7
Vcc = 13V
Rl = 1.84Ω
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
T [°C]
GAPG0907141518CFT
GAPG0907141519CFT
Figure 25: Woff vs. Tcase
Figure 24: Won vs. Tcase
Won [mJ]
Woff [mJ]
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
-50
-25
0
25
50
75
100
125
150
0
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
T [°C]
GAPG0907141520CFT
GAPG0907141521CFT
Figure 27: OFF-state open-load voltage
detection threshold
Figure 26: ILIMH vs. Tcase
Ilimh [A]
VOL [V]
80
4
Vcc = 13V
75
3.5
3
70
2.5
65
2
60
1.5
1
55
0.5
50
-50
-25
0
25
50
75
100
125
150
175
0
-50
T [°C]
GAPG0907141524CFT
-25
0
25
50
75
100
125
150
175
T [°C]
GAPG0907141525CFT
DocID027407 Rev 4
23/45
Electrical specification
VND7012AY
Figure 29: Vsenseh vs. Tcase
Figure 28: Vsense clamp vs. Tcase
VSENSEH [V]
VSENSE_CL [V]
10
10
9
9
8
8
7
Iin = 1mA
7
6
6
5
5
4
4
3
3
2
2
1
Iin = -1mA
0
1
-1
-50
-25
0
25
50
75
100
125
150
175
0
-50
T [°C]
0
25
50
75
100
125
150
175
T [°C]
GAPG0907141526CFT
24/45
-25
DocID027407 Rev 4
GAPG0907141528CFT
VND7012AY
3
Protections
3.1
Power limitation
Protections
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔT j_SD. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to T R (FaultRST = Low) or remains off (FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
DocID027407 Rev 4
25/45
Application information
4
VND7012AY
Application information
Figure 30: Application diagram
4.1
GND protection network against reverse battery
Figure 31: Simplified internal structure
Vcc
5V
Rprot
INPUT
Rprot
SEn
Rprot
FaultRST
MCU
Dld
OUTPUT
Rprot
Multisense
GND
Rsense
GND
GAPG2603140904CFT
The device does not need any external components to protect the internal logic in case of a
reverse battery condition. The protection is provided by internal structures.
26/45
DocID027407 Rev 4
VND7012AY
Application information
In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,
thus providing the same low ohmic path as in regular operating conditions, no additional
power dissipation has to be considered.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional
performance status
Minimum
number of
pulses or test
time
Burst cycle /
pulse repetition
time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112V
500 pulses
0,5 s
2a
III
+55V
500 pulses
0,2 s
5s
50µs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1µs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1µs, 50Ω
IV
-7V
1 pulse
4
(2)
min
max
2ms, 10Ω
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B
(3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)U
S
4.3
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test
pulse from ISO 7637-2:2004(E).
(3)With
40 V external suppressor referred to ground (-40°C < Tj < 150°C).
MCU I/Os protection
If a ground protection network is used and negative transients are present on the V CC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R prot) in line both to
prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
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Application information
VND7012AY
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:



Current monitor: current mirror of channel output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
Figure 32: MultiSense and diagnostic – block diagram
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4.4.1
Application information
Principle of Multisense signal generation
Figure 33: MultiSense block diagram
Current monitor
When current mode is selected via MultiSense, this output is capable of providing:


Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to a known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage V SENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), V SENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:


VSENSE is the voltage measurable on RSENSE resistor
ISENSE is the current provided from MultiSense pin in current output mode
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Application information


VND7012AY
IOUT is the current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying the ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 34: Analogue HSD – open-load detection in off-state
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Application information
Figure 35: Open-load / short to VCC condition
Table 13: MultiSense pin levels in off-state
Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
MultiSense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because a
voltage shift is generated between the device GND and the microcontroller input GND
reference.
Figure 36: "GND voltage shift" shows the link between VMEASURED and the real VSENSE
signal.
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Application information
VND7012AY
Figure 36: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable of providing information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid
the overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
RPU <
32/45
VPU - 4
IL(off2)min @4V
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VND7012AY
Maximum demagnetization energy (VCC = 16 V)
Figure 37: Maximum turn off current versus inductance
VND7012AY - Maximum turn off curr ent ve rsus indu ctance
100
10
I (A)
5
Maximum demagnetization energy (VCC = 16 V)
1
VND7012AY - Sing le Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1
10
100
1000
L (mH)
GAPG1007140727CFT
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data
VND7012AY
6
Package and PCB thermal data
6.1
PowerSSO-36 thermal data
Figure 38: PowerSSO-36 PCB board
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Package and PCB thermal data
Table 14: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
129 mm x 86 mm
Board material
FR4
Cu thickness (outer layers)
0.070 mm
Cu thickness (inner layers)
0.035 mm
Thermal via separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Cu thickness on vias
0.025 mm
Footprint dimension
4.1 mm x 6.5 mm
Figure 39: Rthj-amb vs PCB copper area in open box free air condition (one channel on)
RTHj_amb(°C/W)
65
RTHjamb
60
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^ 2)
GAPG1007140802CFT
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Package and PCB thermal data
VND7012AY
Figure 40: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
10
Cu=foot print
4Layer
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
GAPG1007140805CFT
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
Figure 41: Thermal fitting model of a double-channel HSD in PowerSSO-16
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal parameters
Area/island
36/45
(cm2)
Footprint
R1 = R7 (°C/W)
0.3
R2 = R8 (°C/W)
0.9
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2
8
4L
VND7012AY
Package and PCB thermal data
Area/island
(cm2)
Footprint
2
8
4L
R3 (°C/W)
3.4
3.4
3.4
2.4
R4 (°C/W)
8
6
6
4
R5 (°C/W)
20
14
10
2
R6 (°C/W)
30
26
15
7
C1 = C7 (W.s/°C)
0.0014
C2 = C8 (W.s/°C)
0.01
C3 (W.s/°C)
0.1
0.1
0.1
0.1
C4 (W.s/°C)
0.5
0.8
0.8
0.8
C5 (W.s/°C)
1
2
3
10
C6 (W.s/°C)
3
5
9
18
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Package information
7
VND7012AY
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-36 package information
Figure 42: PowerSSO-36 package outline
BOTTOM VIEW
TOP VIEW
SECTION A-A
SECTION B-B
GAPG2508150825CF T
Table 16: PowerSSO-36 mechanical data
Dimensions
Ref.
Millimeters
Min.
38/45
Typ.
Max.
Θ
0°
8°
Θ1
5°
10°
Θ2
0°
A
2.15
2.45
A1
0.00
0.10
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VND7012AY
Package information
Dimensions
Ref.
Millimeters
Min.
A2
2.15
b
0.18
b1
0.13
c
0.23
c1
0.20
D
D1
Typ.
2.35
0.32
0.25
0.30
0.32
0.20
0.30
10.30 BSC
6.90
7.50
D2
3.65
D3
4.30
e
0.50 BSC
E
10.30 BSC
E1
7.50 BSC
E2
Max.
4.30
5.20
E3
2.30
E4
2.90
G1
1.20
G2
1.00
G3
0.80
h
0.30
L
0.55
0.40
0.70
L1
1.40 REF
L2
0.25 BSC
N
36
R
0.30
R1
0.20
S
0.25
0.85
Tolerance of form and position
aaa
0.20
bbb
0.20
ccc
0.10
ddd
0.20
eee
0.10
fff
0.20
ggg
0.15
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Package information
7.2
VND7012AY
PowerSSO-36 packing information
Figure 43: PowerSSO-36 reel 13"
Table 17: Reel dimensions
Description
Value(1)
Base quantity
1000
Bulk quantity
1000
A (max)
330
B (min)
1.5
C (± 0.2)
13
F
20.2
G (+2 / -0)
24.4
N (min)
100
T (max)
30.4
Notes:
(1)All
40/45
dimensions are in mm.
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VND7012AY
Package information
Figure 44: PowerSSO-36 carrier tape
Table 18: PowerSSO-36 carrier tape dimensions
Description
Value(1)
A0
10.90 ± 0.10
B0
10.80 ± 0.10
K0
2.75 ± 0.10
K1
2.45 ± 0.10
D0
1.50 (+0.10 / -0)
D1
1.60 ± 0.10
P0
4.00 ± 0.10
P1
12.00 ± 0.10
P2
2.00 ± 0.10
P10
40.00 ± 0.20
E
1.75 ± 0.10
F
11.50 ± 0.10
W
24.00 ± 0.30
T
0.30 ± 0.05
Notes:
(1)All
dimensions are in mm.
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Package information
VND7012AY
Figure 45: PowerSSO-36 schematic drawing of leader and trailer tape
7.3
PowerSSO-36 marking information
Figure 46: PowerSSO-36 marking information
Marking area
1
2
3
4
5
6
7
8
9
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-36 TOPVIEW
(not in scale)
GAPG1604151446CFT
Engineering Samples: Parts marked as & are not yet qualified and therefore not
approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of
these engineering samples in production. ST’s Quality department must be
contacted to run a qualification activity prior to any decision to use these
engineering samples.
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
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8
Order codes
Order codes
Table 19: Device summary
Order codes
Package
Tape and reel
PowerSSO-36
VND7012AYTR
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Revision history
9
VND7012AY
Revision history
Table 20: Document revision history
44/45
Date
Revision
Changes
06-Oct-2015
1
Initial release.
11-Apr-2016
2
Added AEC-Q101 qualified in Features section
Updated Figure 40: "PowerSSO-16 thermal impedance junction
ambient single pulse (one channel on)"
Updated Table 15: "Thermal parameters"
26-May-2016
3
Modified reference to qualification type in Features section
Updated Table 1: "Pin functions"
15-Jul-2016
4
Updated Figure 43: "PowerSSO-36 reel 13""and Table 17: "Reel
dimensions"
DocID027407 Rev 4
VND7012AY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
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