advertisement
VND9012AJ
Datasheet
Double channel high-side driver with current sense analog feedback for automotive applications
PowerSSO-16
Product status link
VND9012AJ
Product summary
Order code VND9012AJTR
Package
Packing
PowerSSO-16
Tape and reel
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per Ch)
Current limitation (typ)
Standby current (max)
V
CC
V
CC
R
ON
I
LIMH
I
STBY
36 V
4 to 28 V
12 mΩ
63 A
0.5 µA
• AEC-Q100 qualified
• Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013)
• General
– Double channel smart high-side driver with current sense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS outputs
• Current sense diagnostic functions
– Multiplexed analog feedback of load current with high precision proportional current mirror
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to V
CC
detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin
– Loss of ground and loss of V
CC
– Reverse battery through self turn-on
– Electrostatic discharge protection
Applications
• Automotive resistive, inductive and capacitive loads
• Protected supply for ADAS systems: radars and sensors
DS12727 - Rev 3 - July 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
VND9012AJ
Description
The device is a double channel high-side driver manufactured using ST proprietary VIPower M0-9 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics.
The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog output pin delivers diagnostic functions including high precision proportional load current sense, in addition to the detection of overload and short circuit to ground, short to V
CC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices.
DS12727 - Rev 3 page 2/40
1
VND9012AJ
Block diagram and pin description
Block diagram and pin description
Figure 1. Block diagram
VCC
IN0
IN1
SEn
SEL
FaultRST
CS
GND
VCC – GND clamp
Internal supply
Undervoltage shut-down
Channel 1
Channel 0 control & diagnostic
Gate driver
VCC-OUT clamp
CH 0
CH 1
Logic
Power limitation
Overtemperature
Open-Load in OFF
Reverse battery
Current limitation
Current
Sense
OUT1
OUT0
GADG0507181254PS
Table 1. Pin functions
Name Function
V
CC
OUTPUT
0,1
GND
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode / resistor network.
INPUT
CS
SEn
SEL
0,1
FaultRST
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state.
Multiplexed analog sense output pin; it delivers a current proportional to the selected load current.
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin.
Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer.
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode.
DS12727 - Rev 3 page 3/40
VND9012AJ
Block diagram and pin description
Figure 2. Configuration diagram (top view)
INPUT0
FaultRST
SEn
GND
SEL
N.C.
CS
INPUT1
1
2
3
4
5
6
7
8
PowerSSO-16
16
15
14
13
12
11
10
9
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = V
CC
GADG1605171045PS
Connection / pin
Floating
To ground
1. X: do not care.
Table 2. Suggested connections for unused and not connected pins
CS
Not allowed
Through 1 kΩ resistor
N.C.
X
X
Output
X
Not allowed
Input
X
Through 15 kΩ resistor
SEn, SELx, FaultRST
X
Through 15 kΩ resistor
DS12727 - Rev 3 page 4/40
2
Note:
2.1
VND9012AJ
Electrical specifications
Electrical specifications
Figure 3. Current and voltage conventions
V
FR
V
SEn
V
SEL
V
IN
I
IN
I
FR
I
SEn
I
SEL
FaultRST
SE n
SEL
INPUT
0,1
I
S
V
CC
OUTPUT
0,1
I
OUT
I
SENSE
CS
V
Fn
V
SENSE
V
OUT
V
CC
I
GND
GADG1605171029PS
V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table below for extended periods may affect the device reliability.
Symbol
V
CC
-V
CC
V
CCJS
-I
GND
I
OUT
-I
OUT
I
IN
I
SEn
I
SEL
I
FR
I
SENSE
E
MAX
Table 3. Absolute maximum ratings
Parameter
DC supply voltage
Reverse DC supply voltage
Maximum jump start voltage for single pulse short circuit protection
DC reverse ground pin current
OUTPUT
0,1
DC output current
Reverse DC output current
INPUT
0,1
DC input current
SEn DC input current
SEL DC input current
FaultRST DC input current
CS pin DC output current (V
GND
= V
CC
and V
SENSE
< 0 V)
CS pin DC output current in reverse (V
CC
< 0 V)
Maximum switching energy (single pulse) T jstart
= 150 °C)
Value
36
16
28
200
Internally limited
13
-1 to 10
-1 to 1
-1 to 10
Unit mA
V
V mA
A
10
-20
29.5
mA mJ
DS12727 - Rev 3 page 5/40
2.2
Symbol
V
V
T
ESD
ESD
T j stg
Parameter
•
•
•
•
•
Electrostatic discharge (JEDEC 22A-114F)
INPUT
0,1
CS
SEn, SEL, FaultRST
OUTPUT
0,1
V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
Thermal data
Table 4. Thermal data
Symbol
R thj-board
R thj-amb
R thj-amb
Parameter
Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)
Thermal resistance junction-ambient (JEDEC JESD 51-5)
Thermal resistance junction-ambient (JEDEC JESD 51-7)
1. One channel ON.
2. Device mounted on a four-layer 2s2p PCB
3. Device mounted on a two-layer 2s0p PCB with 2 cm 2 heatsink copper trace
VND9012AJ
Thermal data
Value
2000
2000
2000
4000
4000
750
-40 to 150
-55 to 150
Unit
V
V
V
V
V
V
°C
Typ. value
6.7
54.8
22.2
Unit
°C/W
DS12727 - Rev 3 page 6/40
2.3
VND9012AJ
Main electrical characteristics
Main electrical characteristics
7 V < V
CC
< 28 V; -40°C < T j
< 150°C, unless otherwise specified.
All typical values refer to V
CC
= 13 V; T j
= 25°C, unless otherwise specified.
Table 5. Power section
Symbol Parameter
V
CC
V
USD
Operating supply voltage
Undervoltage shutdown
V
USDReset
Undervoltage shutdown reset
V
USDhyst
Undervoltage shutdown hysteresis
I
R t
V
D_STBY
I
ON_REV
GND(ON)
I
I
R
ON clamp
STBY
S(ON)
L(off)
V
F
Test conditions
On-state resistance
I
OUT
= 4.75 A; T j
= 25°C
I
OUT
= 4.75 A; T j
= 150°C
I
OUT
= 4.75 A; V
CC
= 4 V; T j
= 25°C
I
OUT
= 1 A; V
CC
= 2.7 V; V
CC
decreasing
R
DSON
in reverse battery condition
V
CC
= -13 V; I
OUT
= -4.75 A; T
J
= 25°C
Clamp voltage
Supply current in standby at
V
CC
= 13 V
Standby mode blanking time
Supply current
Control stage current consumption in ON state. All channels active.
Off-state output current at
V
CC
= 13 V
I
S
= 20 mA; 25°C < T j
< 150°C
I
S
= 20 mA; T j
= -40°C
V
CC
= 13 V; V
IN0,1
= V
OUT0,1
= V
FR
= V
SEn
= 0 V;
V
SEL
= 0 V; T j
= 25°C
V
CC
= 13 V; V
IN0,1
= V
OUT0,1
= V
FR
= V
SEn
= 0 V;
V
SEL
= 0 V; T j
= 85°C
V
CC
= 13 V; V
IN0,1
= V
OUT0,1
= V
FR
= V
SEn
= 0 V;
V
SEL
= 0 V; T j
= 125°C
V
CC
= 13 V; V
IN
= V
OUT
= V
FR
= V
SEL0,1
V
SEn
= 5 V to 0 V
= 0 V;
V
CC
= 13 V; V
SEn
V
IN1
= 5 V;
= V
FR
= V
SEL0,1
= 0 V; V
IN0
= 5 V;
I
OUT0
= 0 A; I
OUT1
= 0 A
V
CC
= 13 V; V
SEn
= 5 V; V
FR
= V
SEL
= 0 V;
V
IN0
= 5 V; V
IN1
= 5 V; I
OUT0
= 4.75 A;
I
OUT1
= 4.75 A
V
IN0,1
= V
OUT0,1
= 0 V; V
CC
= 13 V; T j
= 25°C
V
IN0,1
= V
OUT0,1
= 0 V; V
CC
= 13 V; T j
= 125°C
Output - V
CC
diode voltage at T
J
=
150 °C
I
OUT
= -4.75 A; T j
= 150°C
1. For each channel
2. PowerMOS leakage included.
3. Parameter specified by design; not subject to production test.
Min. Typ. Max. Unit
4 13 28 V
2.1
2.7
V
4.5
V
36
36
60
0
0
0.15
12
12
38
260
2.9
0.01
26.4
20.4
72
45
0.5
0.5
3
550
4
4.5
0.5
3
0.7
V mΩ mΩ
V
V
µA
µs mA mA
µA
V
DS12727 - Rev 3 page 7/40
VND9012AJ
Main electrical characteristics
Table 6. Switching
Symbol
V
CC
= 13 V; -40°C < T j
< 150°C, unless otherwise specified
Parameter Test conditions Min.
Typ.
t t d(on) d(off)
(dV
OUT
/dt) on
W
W
ON
OFF t
SKEW
Turn-on delay time at T j
= 25 °C
Turn-off delay time at T j
= 25 °C
Turn-on voltage slope at T j
= 25 °C
(dV
OUT
/dt) off
Turn-off voltage slope at T j
= 25 °C
Switching energy losses at turn-on (t won
Switching energy losses at turn-off (t woff
Differential Pulse skew (t
PHL
- t
PLH
)
)
)
R
R
L
L
= 2.8 Ω
= 2.8 Ω
R
L
= 2.8 Ω
R
L
= 2.8 Ω
R
L
= 2.8 Ω
1. See
Figure 4. Switching time and Pulse skew
.
2. Parameter guaranteed by design and characterization; not subject to production test.
10
10
0.2
0.2
—
—
-85
58
26
0.44
0.53
0.4
0.34
-35
Max.
120
100
0.7
0.7
15
Unit
µs
V/µs mJ mJ
µs
DS12727 - Rev 3 page 8/40
DS12727 - Rev 3
VND9012AJ
Main electrical characteristics
Symbol
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
V
ICL
V
SELL
I
SELL
V
SELH
I
SELH
V
SEL(hyst)
V
SELCL
V
SEnL
I
SEnL
V
SEnH
I
SEnH
V
SEn(hyst)
V
SEnCL
V
FRL
I
FRL
V
FRH
I
FRH
V
FR(hyst)
V
FRCL
Table 7. Logic inputs
Parameter
7 V < V
CC
< 28 V; -40°C < T j
< 150°C
Test conditions
INPUT
0,1
characteristics
Input low level voltage
Low level input current V
IN
= 0.9 V
Input high level voltage
High level input current V
IN
= 2.1 V
Input hysteresis voltage
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
FaultRST characteristics
Input low level voltage
Low level input current
Input high level voltage
V
IN
= 0.9 V
High level input current V
IN
= 2.1 V
Input hysteresis voltage
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
SEL characteristics (7 V < V
CC
< 18 V)
Input low level voltage
Low level input current V
IN
= 0.9 V
Input high level voltage
High level input current
Input hysteresis voltage
V
IN
= 2.1 V
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
SEn characteristics (7 V < V
CC
< 18 V)
Input low level voltage
Low level input current V
IN
= 0.9 V
Input high level voltage
High level input current V
IN
= 2.1 V
Input hysteresis voltage
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
Min.
Typ.
Max.
Unit
1
2.1
0.2
6
1
2.1
0.2
6
1
2.1
0.2
6
1
2.1
0.2
9
-0.7
-0.7
-0.7
-0.7
0.9
10
8.5
0.9
10
8.5
0.9
10
8.5
0.9
10
12
V
µA
V
µA
V
V
V
µA
V
µA
V
V
V
µA
V
µA
V
V
V
µA
V
µA
V
V page 9/40
DS12727 - Rev 3
VND9012AJ
Main electrical characteristics
Table 8. Protections
Symbol Parameter
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Test conditions
I
I
LIMH
LIMH2
I
LIMH at 22 V t
T
T
T
HYST
ΔT
TSD
RS
J_SD
LATCH_RST t
D_Restart
V
DEMAG
DC short- circuit current
V
CC
= 16 V; T j
= -40°C
V
CC
= 16 V; T j
= 150°C
V
CC
= 19 V; T j
= -40°C
V
CC
= 19 V; T j
= 150°C
V
CC
= 22 V; T j
= 25°C
Shutdown temperature
Shutdown temperature (V
CC decreasing)
V
CC
= 2.7 V
Thermal reset of fault diagnostic indication
Thermal hysteresis
(T
TSD
- T
RS
)
V
FR
= 0 V; V
SEn
= 5 V
Dynamic temperature
V
CC
= 16 V;
V
CC
= 19 V;
Fault reset time for output unlatch
•
V
FR
= 5 V to 0 V; V
SEn
= 5 V;
E.g. Ch
0
:
V
IN0
= 5 V; V
SEL
= 0 V
Latch-OFF delay time before automatic restart
Turn-off output voltage clamp
I
OUT
= 1 A; L = 6 mH; T j
= -40 °C
I
OUT
= 1 A; L = 6 mH; T j
= 25°C to
150 °C
1. I
LIMH
guaranteed between 7V and 16V, -40°C < T j
< 150°C
2. I
LIMH2
guaranteed between 16V and 19V, -40°C < T j
< 150°C
3. Parameter guaranteed by design and characterization; not subject to production test.
Min.
-15%
-15%
-15%
-15%
150
140
135
3
V
CC
- 36
Typ.
68
56
53
43
20
175
7
80
55
10
50
Max.
Unit
15%
15%
A
15%
15%
A
210
20
°C
K
µs ms
V
V
CC
- 36 V
CC
- 38 V
CC
- 45 V page 10/40
DS12727 - Rev 3
VND9012AJ
Main electrical characteristics
Symbol
V
SENSE_CL
K
LED dK
LED
/K
LED
K
0 dK
0
/K
0
K
1 dK
1
/K
1
K
2 dK
2
/K
2
K
3 dK
3
/K
3
I
SENSE0
Table 9. Current sense
Parameter
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Test conditions
I
I
I
I
I
CS clamp voltage
OUT
/I
SENSE
Current sense ratio drift at calibration point
OUT
Current sense ratio drift
OUT
/I
SENSE
Current sense ratio drift
OUT
Current sense ratio drift
OUT
/I
/I
/I
SENSE
SENSE
SENSE
Current sense ratio drift
Current sense leakage current
V
SEn
= 0 V; I
SENSE
= 1 mA
V
SEn
= 0 V; I
SENSE
= -1 mA
Current sense characteristics
I
OUT
= 0.05 A; V
SENSE
= 0.5 V;
V
SEn
= 5 V
I
OUT
= 0.05 A; V
SENSE
= 0.5 V;
V
SEn
= 5 V
I
OUT
= 0.25 A; V
SENSE
= 0.5 V;
V
SEn
= 5 V
I
OUT
= 0.25 A; V
SENSE
= 0.5 V;
V
SEn
= 5 V
I
OUT
= 0.95 A; V
SENSE
= 3.5 V;
V
SEn
= 5 V
I
OUT
= 0.95 A; V
SENSE
= 3.5 V;
V
SEn
= 5 V
I
OUT
= 4.75 A; V
SENSE
= 3.5 V;
V
SEn
= 5 V
I
OUT
= 4.75 A; V
SENSE
= 3.5 V;
V
SEn
= 5 V
I
OUT
= 14 A; V
SENSE
= 3.5 V;
V
SEn
= 5 V
I
OUT
= 14 A; V
SENSE
= 3.5 V;
V
SEn
= 5 V
CS disabled: V
SEn
= 0 V
CS disabled:
-1 V < V
SENSE
< 5 V
•
CS enabled: V
SEn
= 5 V; All channels
ON; I
OUTX
= 0 A; Ch
X diagnostic selected;
E.g. Ch
0
:
V
IN0
= 5 V; V
IN1
= 5 V;
I
V
SEL
OUT1
= 0 V; I
OUT0
= 4.75 A
= 0 A;
•
CS enabled: V
SEn
Ch
X
= 5 V; Ch diagnostic selected:
X
OFF;
E.g. Ch
0
:
V
IN0
= 0 V; V
IN1
= 5 V;
V
SEL0
= 0 V; V
SEL1
= 0 V;
I
OUT1
= 4.75 A
Min.
-9
Typ.
-8
7
Max.
Unit
-7
V
-35% 10050 +35%
-25 25
-20% 10050 +20%
-15 15
-15% 10050 +15%
-10 10
7% 10050 +7%
-7 7
-5% 10050 +5%
-5
0
-1
0
0
5
0.5
1
10
1
%
%
%
%
%
µA page 11/40
DS12727 - Rev 3
VND9012AJ
Main electrical characteristics
V
I
SENSE_SAT
I
V
Symbol
OUT_MSD
SENSE_SAT
OUT_SAT t t
V t
I
V
OL
L(off2)
DSTKON
D_OL_V
D_VOL
SENSEH
Parameter
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Test conditions
Output Voltage for CS shutdown
Current sense saturation voltage
CS saturation current
Output saturation current
OFF-state open-load voltage detection threshold
OFF-state output sink current
OFF-state diagnostic delay time from falling edge of INPUT (see
)
•
V
SEn
= 5 V; R
SENSE
= 2.7 kΩ;
E.g. Ch
0
:
V
IN0
= 5 V; V
SEL
= 0 V;
I
OUT0
= 4.75 A
V
CC
= 7 V; R
SENSE
= 10 kΩ;
V
SEn
= 5 V; V
IN0
= 5 V; V
SEL
= 0 V;
I
OUT0
= 14; T j
= -40°C
V
CC
= 7 V; V
SENSE
= 3.5 V;
V
IN0
= 5 V; V
SEn
= 5 V; V
SEL
= 0 V;
T j
= 150°C
V
CC
= 7 V; V
SENSE
= 3.5 V;
V
IN0
= 5 V; V
SEn
= 5 V; V
SEL
= 0 V;
T j
= 150°C
OFF-state diagnostic
V
SEn
= 5 V; Ch
X
OFF;
•
Ch
X diagnostic selected
E.g: Ch
0
V
IN0
= 0 V; V
SEL
= 0 V;
V
IN
= 0 V; V
OUT
= V
OL
;
T j
= -40°C to 125°C
V
SEn
= 5 V; Ch
X
ON to OFF transition;
•
Ch
X diagnostic selected
E.g: Ch
0
I
V
IN0
= 5 V to 0 V; V
SEL
OUT0
= 0 A; V
OUT
= 0 V;
= 4 V
Settling time for valid OFFstate open load diagnostic indication from rising edge of
SEn
V
IN0
V
= 0 V; V
IN1
SEL0
V
OUT0
= 0 V; V
= 0 V; V
SEL1
= 4 V; V
SEn
FR
= 0 V;
= 0 V;
= 0 V to 5 V
OFF-state diagnostic delay time from rising edge of V
OUT
V
SEn
= 5 V; Ch
X
OFF;
•
Ch
X diagnostic selected
E.g: Ch
0
V
IN0
= 0 V; V
SEL
= 0 V;
V
OUT
= 0 V to 4 V
Fault diagnostic feedback (see
Current sense output voltage in fault condition
13 V < V
CC
< 18 V; Ch0 in open load;
R
SENSE
= 0.7 kΩ; V
IN0
= 0 V;
V
SEn
= 5 V; I
OUT0
= 0 A; V
OUT0
= 4 V
V
CC
= 7 V; Ch0 in open load;
R
SENSE
= 0.7 kΩ; V
IN0
= 0 V;
V
SEn
= 5 V; I
OUT0
= 0 A; V
OUT0
= 4 V
Min.
4.8
2
29
2
-150
100
5
4.3
Typ.
5
3
-40
170
5
Max.
Unit
4
-5
250
60
30
7.5
V
V mA
A
V
µA
µs
µs
µs
V page 12/40
DS12727 - Rev 3
VND9012AJ
Main electrical characteristics t
Symbol Parameter
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Test conditions Min.
Typ.
Max.
Unit
I
SENSEH
Current sense output current in fault condition
13 V < V
CC
< 18 V; V
SENSE
= 5 V;
Ch0 in open load;
V
IN0
= 0 V; V
SEn
= 5 V;
I
OUT0
= 0 A; V
OUT0
= 4 V
V
CC
= 7 V; V
SENSE
= 5 V;
Ch0 in open load;
V
IN0
= 0 V; V
SEn
= 5 V;
I
OUT0
= 0 A; V
OUT0
= 4 V
7
4.4
8.6
12 t t t t
DSENSE1H
Current sense settling time from rising edge of SEn
V
IN
= 5 V; V
SEn
= 0 V to 5 V;
R
SENSE
= 1 kΩ; R
L
= 2.8 Ω
60
DSENSE1L
DSENSE2H
Current sense disable delay time from falling edge of SEn
Current sense settling time from rising edge of INPUT
V
IN
= 5 V; V
SEn
= 5 V to 0 V;
R
SENSE
= 1 kΩ; R
L
= 2.8 Ω
V
IN
= 0 V to 5 V; V
SEn
= 5 V;
R
SENSE
= 1 kΩ; R
L
= 2.8 Ω
5
100
20
200
Δt
DSENSE2H
DSENSE2L
Current sense settling time from rising edge of I
OUT
(dynamic response to a step change of I
OUT
)
Current sense turn-off delay time from falling edge of
INPUT
I
V
R
R
IN
L
V
IN
= 5 V; V
SENSE
= 2.8 Ω
SENSE
SEn
= 5 V; R
= 90 % of I
= 5 V to 0 V; V
SEn
= 1 kΩ; R
L
SENSE
SENSEMAX
= 5 V;
= 2.8 Ω
;
= 1 kΩ;
50
100
250 mA
µs
µs
µs
µs
µs t
DSENSE3H t
D_XtoY
D_CStoVSENSEH
Current sense latch-OFF filtering time
Current sense timings (Multiplexer transition times)
Current sense transition delay from Ch
X
to Ch
Y
Current sense transition delay from stable current sense on
Ch
X
to V
SENSEH on Ch
Y
V
IN0
= 5 V; V
IN1
= 5 V; V
SEn
= 5 V;
V
SEL
= 0 V to 5 V; I
OUT0
I
OUT1
= 4.75 A; R
SENSE
= 0 A;
= 1 kΩ
V
IN0
= 5 V; V
IN1
V
SEL
= 0 V; V
SEn
= 0 V to 5 V; I
OUT0
= 5 V;
= 4.5 A;
V
OUT1
= 4 V; R
SENSE
= 1 kΩ
1.4
2.0
2.6
30
20 ms
µs
µs
1. Parameter guaranteed by design and characterization; not subject to production test.
2. All values refer to V
CC
= 13 V; T j
= 25°C, unless otherwise specified.
3. Transition delay is measured up to +/- 10% of final conditions.
page 13/40
DS12727 - Rev 3
IN
SEn
High
Low
I
OUT
CURRENT SENSE
VOUT
Vcc
Figure 4. Switching time and Pulse skew twon twoff
VND9012AJ
Main electrical characteristics dV
OUT
/dt
ON
80% Vcc
OFF dV
OUT
/dt
20% Vcc t
INPUT td(on) tpLH td(off) tpHL t
Figure 5. Current sense timings (current sense mode) t
DSENSE2H t
DSENSE1L t
DSENSE1H t
DSENSE2L
GAPG1003141014CFT page 14/40
DS12727 - Rev 3
Figure 6. T
DSTKON
V
OUT
> V
OL
VND9012AJ
Main electrical characteristics
V
INPUT
V
OUT
CS
T
DSTKON
GADG0112170745PS
Table 10. Truth table
Mode
Standby
Normal
Overload
Undervoltage
OFF-state diagnostics
Conditions
All logic inputs low
Nominal load connected;
T j
< 150 °C
Overload or short to GND causing:
T j
> T
TSD
or
ΔT j
> ΔT j _SD
V
CC
< V
USD
Short to V
Open-load
CC
(falling)
IN
X
FR SEn SEL
X
OUT
X
L
L
H
L
X
L
L
L
CS Comments
L Hi-Z
Low quiescent current consumption
L
H
Outputs configured for auto-restart
H
L
H
X
H
Outputs configured for
Latch-off
L
H
H
X
L
L
H
X
X
L X
X
X
H
Output cycles with temperature hysteresis
L
Output latches-off
L
L
Hi-Z
Hi-Z
Re-start when
V
CC
> V
USD
+
V
USDhyst
(rising)
H
H
External pull-up
Negative output voltage
Inductive loads turn-off
1. Refer to Table 11. Current sense multiplexer addressing
L X
page 15/40
VND9012AJ
Main electrical characteristics
SEn SEL
0
L
H
H
X
L
H
MUX channel
Table 11. Current sense multiplexer addressing
Normal mode
Channel 0 diagnostic I
SENSE
= 1/K * I
OUT0
Channel 1 diagnostic I
SENSE
= 1/K * I
OUT1
CS output
Overload OFF-state diag.
Hi-Z
V
SENSE
= V
SENSEH
V
SENSE
= V
SENSEH
V
SENSE
= V
SENSEH
V
SENSE
= V
SENSEH
Negative output
Hi-Z
Hi-Z
DS12727 - Rev 3 page 16/40
2.4
Waveforms
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
Figure 7. Latch-off mode - Intermittent short circuit
Normal condition
INPUT
Short circuit condition t
Unlatch command is stored, but no restart until
D_Restart is elapsed.
FaultRST
I
LIMH
I
OUT
I
NOM
CS t
D_Restart t > t
DSENSE3H
Figure 8. Auto-restart mode - Intermittent short circuit
Short circuit condition Normal condition
INPUT
FaultRST
I
OUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
I
LIMH
Power Limitation t
D_Restart
I
NOM t > t
DSENSE3H
VND9012AJ
Waveforms
DS12727 - Rev 3 page 17/40
DS12727 - Rev 3
Figure 9. Auto-restart mode - Permanent short circuit
INPUT
FaultRST
I
OUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
I
LIMH
Power Limitation t
D_Restart
I
LIMH
Power Limitation t < t
DSENSE3H
Figure 10. Standby mode activation
= Standby = t < t
D_STBY
= t > t
D_STBY
Figure 11. Standby state diagram
Normal Operation t > t
D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
Stand-by Mode
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
INPUT0
INPUT1
SEn
SEL
FaultRST
IS(ON)
VND9012AJ
Waveforms page 18/40
3
3.1
3.2
3.3
3.4
VND9012AJ
Protections
Protections
Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔT j
through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔT j
exceeds the safety level of ΔT j_SD
. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue.
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to T
R
(FaultRST = Low) or remains off (FaultRST = High).
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, I
LIMH
, by operating the output power MOSFET in the active region.
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, V
DEMAG
, allowing the inductor energy to be dissipated without damaging the device.
DS12727 - Rev 3 page 19/40
4
4.1
VND9012AJ
Application information
Application information
Figure 12. Application diagram
+5V
V
DD
OUT
OUT
OUT
OUT
ADC in
OUT
Rprot_SEn
SEn
INPUT
Rprot
Rprot
Rprot
FaultRST
SEL
Rprot
CS
Cext
Rsense
GND GND
Current mirror
Logic
R
GND
GND
GND
GND
GND protection network against reverse battery
Figure 13. Simplified internal structure
5V
Vcc
Rprot
INPUT
V
CC
D
GND
OUTPUT
GND GND
Dld
MCU
Rprot_SEn
SEn
Rprot
Rprot
FaultRST
CS
OUTPUT
Dld
Rsense
R
GND
GND
D
GND
GND
GAPGCFT00830
DS12727 - Rev 3 page 20/40
4.1.1
4.2
VND9012AJ
Immunity against transient electrical disturbances
Diode (DGND) in the ground line
A resistor (typ. R
GND
= 4.7 kΩ) should be inserted in parallel to D
GND
if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the V
CC
pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in
Table 12. ISO 7637-2 - electrical transient conduction along supply line
.
Test pulses are applied directly to DUT (device under test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4.
The DUT is intended as the current device only, with external components as shown in
Figure 14. M0-9 application schematic .
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level with Status II functional performance status
1
2a
3a
3b
Level
III
III
IV
IV
IV
U
S
-112 V
+55 V
-220 V
+150 V
-7 V
Load dump according to ISO 16750-2:2010
Test B
35 V
Minimum number of pulses or test time
500 pulses
500 pulses
1h
1h
1 pulse
5 pulse
Burst cycle / pulse repetition time min
0.5 s
0.2 s
90 ms
90 ms
1 min max
5 s
100 ms
100 ms
1. U
S
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 35 V external suppressor referred to ground (-40°C < T j
< 150 °C).
Pulse duration and pulse generator internal impedance
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
DS12727 - Rev 3 page 21/40
Note:
4.3
4.4
VND9012AJ
MCU I/Os protection
Figure 14. M0-9 application schematic
+5V
V
DD
OUT
V
CC
OUT
OUT
OUT
ADC in
OUT
Rprot_SEn
SEn
INPUT
Rprot
Rprot
Rprot
FaultRST
SEL
Rprot
CS
Cext
Rsense
GND GND
Current mirror
Logic
OUTPUT
1μF
R
GND
GND
D
GND
Rload_nom
GND GND
GND
GND
In case of multiple channels, each OUTPUT must be connected to the resistive nominal load.
MCU I/Os protection
If a ground protection network is used and negative transients are present on the V
CC
line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot
) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
V
CCpeak
/I latchup
≤ R prot
≤ (V
OHµC
- V
IH
- V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -150 V; I latchup
≥ 20 mA; V
OHµC
≥ 4.5 V
7.5 kΩ ≤ R prot
≤ 140 kΩ.
Recommended values: R prot
= 15 kΩ
A different value of the resistor has to be used for SEn pin, Rprot_SEn, as reported in
Figure 12. Application diagram .
CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals:
• Current monitor: current mirror of channel output current
Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and
SEn pins, according to the address map in Table 7.
DS12727 - Rev 3 page 22/40
Figure 15. CurrentSense and diagnostic – block diagram
VCC
VCC – GND
Clamp
Internal Supply
Undervoltage shut-down
FaultRST
R
PROT
To µC ADC
INPUT
SEL
1
SEL
0
SE n
I
SENSE
CS
R
SENSE
GND
MUX
Fault
Diagnostic
CURRENT
MONITOR
Fault
V
SENSEH
Control & Diagnostic
Gate Driver
VCC – OUT
Clamp
Current
Limitation
Power Limitation
Overtemperature
Short to VCC
Open-Load in OFF K factor
Current
Sense
T
VND9012AJ
CS - analog current sense
I
OUT
OUT
4.4.1
GADG2004171456PS
Principle of current sense signal generation
Figure 16. CurrentSense block diagram
Vcc
Sense MOS
INPUT
Main MOS
Fault
Current sense
Current sense Switch Block
OUT
To uC ADC
CS
R
PROT
R
SENSE
GAPG2307131200CFT
DS12727 - Rev 3 page 23/40
DS12727 - Rev 3
VND9012AJ
CS - analog current sense
Current sense
The output is capable to provide:
•
•
Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage V
SENSEH
The current delivered by the current sense circuit, I
SENSE
, can be easily converted to a voltage V
SENSE
by using an external sense resistor, R
SENSE
, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), V
SENSE
calculation can be done using simple equations
Current provided by MultiSense output: I
SENSE
= I
OUT
/K
Voltage on R
SENSE
: V
SENSE
= R
SENSE
· I
SENSE
= R
SENSE
· I
OUT
/K
Where:
•
•
•
•
V
SENSE
is voltage measurable on R
SENSE
resistor
I
SENSE
is current provided from CurrentSense pin in current output mode
I
OUT
is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between I
OUT
and I
SENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin which is switched to a
“current limited” voltage source, V
SENSEH
.
In any case, the current sourced by the CurrentSense in this condition is limited to I
SENSEH
.
The typical behavior in case of overload or hard short circuit is shown in Waveforms.
page 24/40
VND9012AJ
CS - analog current sense
+5V
Microcontroller V
DD
GND
100nF
OUT
GND
GND
2.2 k
OUT
15k
OUT
15k
OUT
15k
ADC in
15k
OUT
GND
15k
CEXT
Figure 17. Analog HSD – open-load detection in off-state
Vbat
100nF/50V
GND
V
CC
SEn
INPUT
FaultRST
SEL
CS
GND
Rsense
Cu rrent mirror
Logic
R
GND
4.7k
GND
D
GND
GND
OUTPUT
Vbat
Rpull-up
External
Pull -Up switch
OUTPUT
10nF /100V
GND
GAPG1201151432CFT
Figure 18. Open-load / short to V
CC
condition
V
IN
V
SENSE
Open-load
V
SENSE
Short to V
CC
t
DSTKON
V
SENSEH
V
SENSE
= 0
Pull-up connected
Pull-up disconnected
V
SENSEH
GADG2702181218RI
DS12727 - Rev 3 page 25/40
4.4.2
VND9012AJ
CS - analog current sense
Condition
Open-load
Short to V
CC
Nominal
Table 13. CS pin levels in off-state
Output
V
OUT
> V
OL
V
OUT
< V
OL
V
OUT
> V
OL
V
OUT
< V
OL
CS
Hi-Z
V
SENSEH
Hi-Z
0
Hi-Z
V
SENSEH
Hi-Z
0
Short to V
CC
and OFF-state open-load detection
Short to V
CC
A short circuit between V
CC and output is indicated by the relevant current sense pin set to V
SENSEH
during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short-circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor R
PU
connecting the output to a positive supply voltage V
PU
.
It is preferable that V
PU
is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, that is when load is connected.
R
PU must be selected in order to ensure V
OUT
> V
OLmax in accordance with the following equation:
R
PU
<
V
PU
- 4
I
L(off2)min @ 4V
H
L
H
L
H
L
SEn
L
H
DS12727 - Rev 3 page 26/40
5
VND9012AJ
Maximum demagnetization energy (VCC = 16 V)
Maximum demagnetization energy (V
CC
= 16 V)
Figure 19. Maximum turn off current versus inductance
100
Single Pulse Tjstart = 150°C
Repetitive pulse Tjstart = 100°C
Repetitive pulse Tjstart = 125°C
10
1
0
0.1
1000
1 10
L (mH)
100
Figure 20. Maximum turn off energy versus inductance
Single Pulse Tjstart = 150°C
Repetitive pulse Tjstart = 100°C
Repetitive pulse Tjstart = 125°C
100
1000
10
1
0.1
1 10
L (mH)
100 1000
DS12727 - Rev 3 page 27/40
6
6.1
VND9012AJ
Package and PCB thermal data
Package and PCB thermal data
PowerSSO-16 thermal data
Figure 21. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5)
Figure 22. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7)
DS12727 - Rev 3
Dimension
Board finish thickness
Board dimension
Board Material
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal vias separation
Thermal via diameter
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
Table 14. PCB properties
Value
1.6 mm +/- 10%
77 mm x 86 mm
FR4
0.070 mm
0.035 mm
1.2 mm
0.3 mm +/- 0.08 mm
0.025 mm
2.2 mm x 3.9 mm
Footprint, 2 cm 2 or 8 cm 2 page 28/40
RTHj_amb(°C/W)
VND9012AJ
PowerSSO-16 thermal data
Figure 23. R thj-amb
vs PCB copper area in open box free air condition (one channel on)
RTHj_amb(°C/W)
90
RTHjamb
80
70
60
50
40
30
0 2 4 6
PCB Cu heatsink area (cm^2)
8 10
Figure 24. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
100
Z
TH
(°C/W)
10
DS12727 - Rev 3
1
0.01
0.1
Equation: pulse calculation formula
Z
THδ
= R
TH
· δ + Z
THtp
(1 - δ) where δ = t
P
/T
1
Time (s)
10 100
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
1000 page 29/40
VND9012AJ
PowerSSO-16 thermal data
Figure 25. Thermal fitting model of a double-channel HSD in PowerSSO-16
Note: the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Area/island (cm²)
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W·s/°C)
C2 (W·s/°C)
C3 (W·s/°C)
C4 (W·s/°C)
C5 (W·s/°C)
C6 (W·s/°C)
Table 15. Thermal parameters
FP
30
26
0.00008
0.02
0.08
0.2
0.4
3
2
2.2
4.6
16
2
4.6
6
20
20
0.3
1
5
8
4.6
6
10
18
0.3
1
7
4L
3
7
4
4
0.4
4
18
DS12727 - Rev 3 page 30/40
7
7.1
VND9012AJ
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerSSO-16 package information
Bottom view
Figure 26. PowerSSO-16 package dimensions ggg C A-B D D2
D3 ggg C A-B D minimum solderable area
E3 E2
Section A-A
θ 2 h
A A2
A1 e for dual gauge only eee C b ddd C D
N
A
D
A ccc C
SEATING PLANE
C
2x f f f C A-B
D
θ 3
Section B-B
b
H
S h
B
θ 1
R1
R
GAUGE PLANE
θ
L1
B
L
WITH PLATING
1.2
for dual gauge only c c1
E1 E index area
(0.25D x 0.75E1)
2x aaa C D
Top view
1 2 3
B
8017965_Rev_9
A N/2
2x N/2 TIPS bbb C b1
BASE METAL
GAPG1605141159CFT
DS12727 - Rev 3 page 31/40
DS12727 - Rev 3
Symbol
E2
E3 h
L
L1
N
R
R1
S c1
D
D2
D3 e
E
E1
A
A1
A2 b b1 c
Θ
Θ1
Θ2
Θ3 aaa bbb ccc ddd eee fff ggg
Table 16. PowerSSO-16 mechanical data
Millimeters
Typ.
Min.
0°
0°
5°
5°
0.00
1.10
0.20
0.20
0.19
0.19
0.25
0.20
4.90 BSC
3.31
2.61
0.50 BSC
6.00 BSC
3.90 BSC
2.20
1.49
0.25
0.40
0.60
1.00 REF
16
0.07
0.07
0.20
Tolerance of form and position
0.10
0.10
0.08
0.08
0.10
0.10
0.15
VND9012AJ
PowerSSO-16 package information
2.80
0.50
0.85
Max.
8°
1.60
0.30
0.28
0.25
0.23
15°
15°
1.70
0.10
3.91
page 32/40
7.2
VND9012AJ
PowerSSO-16 packing information
PowerSSO-16 packing information
Figure 27. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
A D
Description
Base quantity
Bulk quantity
A (max)
B (min)
C (+0.5, -0.2)
D (min)
N
W1 (+2 /-0)
W2 (max)
1. All dimensions are in mm.
C
If present, tape slot in core for tape start:
2.5 mm min. width x
10.0 mm min. depth
B
Table 17. Reel dimensions
Value
2500
2500
330
1.5
13
20.2
100
12.4
18.4
W2
W1
N
TAPG2004151655CFT
DS12727 - Rev 3 page 33/40
DS12727 - Rev 3
VND9012AJ
PowerSSO-16 packing information
0.30 ±0.05
Figure 28. PowerSSO-16 carrier tape
P
2
2.0 ±0.1
P
0
4.0 ±0.1
1.55 ±0.05
X
1.75 ±0.1
1.6 ±0.1
F
W
B
0
K
1
K
0
SECTION X - X
R 0.5
Typical
Y
X
Y
P
1
REF 4.18
REF 0.6
SECTION Y - Y
REF 0.5
A
0
GAPG2204151242CFT
Table 18. PowerSSO-16 carrier tape dimensions
Description
A
0
B
0
K
0
K
1
F
P
1
W
1. All dimensions are in mm.
Value
6.50 ± 0.1
5.25 ± 0.1
2.10 ± 0.1
1.80 ± 0.1
5.50 ± 0.1
8.00 ± 0.1
12.00 ± 0.3
Figure 29. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Punched carrier
8 mm & 12 mm only
END
Carrier tape
Round sprocket holes
START
Top cover tape
Elongated sprocket holes
(32 mm tape and wider)
Trailer
160 mm minimum
Top cover tape
Components
User direction feed
100 mm min.
Leader
400 mm minimum
GAPG2004151511CFT page 34/40
7.3
PowerSSO-16 marking information
Figure 30. PowerSSO-16 marking information
VND9012AJ
PowerSSO-16 marking information
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS12727 - Rev 3 page 35/40
VND9012AJ
Revision history
Date
02-Oct-2018
03-Jun-2021
14-Jul-2022
Revision
1
2
3
Table 19. Document revision history
Changes
Initial release.
•
Added:
Application information.
•
•
•
•
•
•
Updated:
Table 3. Absolute maximum ratings
.
•
Minor text changes in:
Updated
Table 2. Suggested connections for unused and not connected pins
,
Table 3. Absolute maximum ratings
,
,
and
Section 4 Application information
.
Inserted
Section 5 Maximum demagnetization energy (VCC = 16 V)
and
Section 6 Package and PCB thermal data
.
Minor text changes.
DS12727 - Rev 3 page 36/40
VND9012AJ
Contents
Contents
and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5 Maximum demagnetization energy (V
= 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DS12727 - Rev 3 page 37/40
VND9012AJ
List of tables
List of tables
DS12727 - Rev 3 page 38/40
VND9012AJ
List of figures
List of figures
Figure 18. Open-load / short to V
DS12727 - Rev 3 page 39/40
VND9012AJ
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS12727 - Rev 3 page 40/40
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Related manuals
advertisement