STMicroelectronics VND9008AJ Datasheet

VND9008AJ
Datasheet
Double channel high-side driver with current sense analog feedback
for automotive applications
Features
PowerSSO-16
Max. transient supply voltage
VCC
36 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per channel)
RON
9.4 mΩ
Current limitation (typ.)
ILIMH
67 A
Standby current (max.)
ISTBY
0.5 µA
•
•
•
Product status link
VND9008AJ
•
Product summary
Order code
VND9008AJTR
Package
PowerSSO-16
Packing
Tape and reel
•
AEC-Q100 qualified
Extreme low voltage operation for deep cold cranking applications (compliant
with LV124, revision 2013)
General
–
Double channel smart high-side driver with current sense analog
feedback
–
Very low standby current
–
Compatible with 3 V and 5 V CMOS outputs
Current sense diagnostic functions
–
Multiplexed analog feedback of load current with high precision
proportional current mirror
–
Overload and short to ground (power limitation) indication
–
Thermal shutdown indication
–
OFF-state open-load detection
–
Output short to VCC detection
–
Sense enable/disable
Protections
–
Undervoltage shutdown
–
Overvoltage clamp
–
Load current limitation
–
Self limiting of fast thermal transients
–
Configurable latch-off on overtemperature or power limitation with
dedicated fault reset pin
–
Loss of ground and loss of VCC
–
–
Reverse battery through self turn-on
Electrostatic discharge protection
Applications
•
•
•
Automotive resistive, inductive and capacitive loads
Protected supply for ADAS systems: radars and sensors
Automotive headlamps (up to H7)
DS12148 - Rev 4 - December 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
VND9008AJ
Description
The device is a double channel high-side driver manufactured using ST proprietary VIPower M0-9 technology and
housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V
and 5 V CMOS-compatible interface, providing protection and diagnostics.
The device integrates advanced protective functions such as load current limitation, overload active management
by power limitation and overtemperature shutdown with configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog output pin delivers diagnostic functions including high precision
proportional load current sense, in addition to the detection of overload and short circuit to ground, short to VCC
and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as
external sense resistor sharing among similar devices.
DS12148 - Rev 4
page 2/38
VND9008AJ
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
VCC – GND
clamp
Internal supply
Undervoltage
shut-down
Channel 1
CH 1
Channel 0
control & diagnostic
VCC-OUT
clamp
CH 0
Gate driver
IN0
OUT1
IN1
SEn
Logic
Current
limitation
SEL
FaultRST
Power limitation
Overtemperature
Open-Load in OFF
Reverse battery
CS
Current
Sense
OUT0
GND
GADG0507181254PS
Table 1. Pin functions
Name
VCC
Function
Battery connection.
OUTPUT0,1 Power output.
GND
INPUT0,1
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch
state.
CS
Multiplexed analog sense output pin; it delivers a current proportional to the selected load current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin.
SEL
Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer.
FaultRST
DS12148 - Rev 4
Ground connection. Must be reverse battery protected by an external diode / resistor network.
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low,
sets the outputs in auto-restart mode.
page 3/38
VND9008AJ
Block diagram and pin description
Figure 2. Configuration diagram (top view)
PowerSSO-16
INPUT0
FaultRST
SEn
GND
SEL
N.C.
CS
INPUT1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = V CC
GADG1605171045PS
Table 2. Suggested connections for unused and not connected pins
Connection / pin
CS
N.C.
Output
Input
SEn, SELx, FaultRST
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 kΩ resistor
X
Not allowed
Through 15 kΩ resistor
Through 15 kΩ resistor
1. X: do not care.
DS12148 - Rev 4
page 4/38
VND9008AJ
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS
VCC
FaultRST
I SEn
I OUT
OUTPUT 0,1
CS
SEL
VSEn
V OUT
I SENSE
SE n
I SEL
VFR
VCC
VFn
I FR
VSENSE
I IN
VSEL
INPUT 0,1
VIN
I GND
GADG1605171029PS
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table
below for extended periods may affect the device reliability.
Table 3. Absolute maximum ratings
Symbol
Value
Unit
VCC
DC supply voltage
36
-VCC
Reverse DC supply voltage
16
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1 DC output current
Internally limited
-IOUT
Reverse DC output current
ISEn
SEn DC input current
IIN
SEL DC input current
IFR
FaultRST DC input current
EMAX
VESD
15
-1 to 10
CS pin DC output current (VGND = VCC and VSENSE < 0 V)
10
CS pin DC output current in reverse (VCC < 0 V)
-20
Maximum switching energy (single pulse) (TJstart = 150 °C)
26
Electrostatic discharge (JEDEC 22A-114F)
V
A
-1 to 1
INPUT0,1 DC input current
ISEL
ISENSE
DS12148 - Rev 4
Parameter
INPUT0,1
2000
CS
2000
SEn, SEL, FaultRST
2000
mA
mA
mJ
V
page 5/38
VND9008AJ
Thermal data
Symbol
VESD
Parameter
Electrostatic discharge (JEDEC 22A-114F)
Value
OUTPUT0,1
4000
VCC
4000
Charge device model (CDM-AEC-Q100-011)
TJ
Tstg
2.2
Unit
V
750
Operating junction temperature range
-40 to 150
°C
Storage temperature range
-55 to 150
°C
Thermal data
Table 4. Thermal data
Symbol
RthJB
RthJA
Parameter
Thermal resistance, junction-to-board (JEDEC JESD 51-5 /
Typ. value
Unit
6.3
°C/W
51-8)(1)(2)
Thermal resistance, junction-to-ambient (JEDEC JESD 51-5)(1)(3)
53.8
Thermal resistance, junction-to-ambient (JEDEC JESD 51-7)(1)(2)
22
°C/W
1. One channel ON.
2. Device mounted on a four-layer 2s2p PCB.
3. Device mounted on a two-layer 2s0p PCB with 2 cm2 heatsink copper trace.
2.3
Main electrical characteristics
7 V < VCC < 28 V; -40 °C < TJ < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; TJ = 25 °C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
Test conditions
Min. Typ. Max. Unit
4
13
28
V
2.1
2.7
V
4.5
V
VUSDReset Undervoltage shutdown reset
VUSDhyst
Undervoltage shutdown
hysteresis
0.15
IOUT = 4.6 A; TJ = 25°C
RON
On-state resistance(1)
9.4
IOUT = 4.6 A; TJ = 150 °C
20.7
IOUT = 4.6 A; VCC = 4 V; TJ = 25 °C
16
IOUT = 0.46 A; VCC = 2.7 V; VCC decreasing
RON_Rev
Vclamp
ISTBY
DS12148 - Rev 4
RDSON in reverse battery
condition
Clamp voltage
Supply current in standby at
VCC = 13 V(2)
V
mΩ
56.4
VCC = -13 V, IOUT = -4.6 A; TJ = 25 °C
9.4
IS = 20 mA; 25 °C < TJ < 150 °C
36
IS = 20 mA; TJ = -40 °C
36
38
mΩ
45
V
V
VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEn = 0 V;
VSEL = 0 V; TJ = 25 °C
0.5
VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEn = 0 V;
VSEL = 0 V; TJ = 85 °C(3)
0.5
VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEn = 0 V;
VSEL = 0 V; TJ = 125°C
3
µA
page 6/38
VND9008AJ
Main electrical characteristics
Symbol
tD_STBY
Parameter
IS(ON)
IGND(ON)
IL(off)
Test conditions
Standby mode blanking time
VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEL = 0 V;
VSEn = 5 V to 0 V
Supply current
VCC = 13 V; VSEn = VFR = VSEL = 0 V; VIN0 = 5 V;
VIN1 = 5 V; IOUT0 = 0 A; IOUT1 = 0 A
Control stage current
consumption in ON state. All
channels active.
VCC = 13 V; VSEn = 5 V; VFR = VSEL = 0 V;
VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 4.6 A; IOUT1 = 4.6 A
Off-state output current at
VCC = 13 V(2)
VIN0,1 = VOUT0,1 = 0 V; VCC = 13 V; TJ = 25°C
0
VIN0,1 = VOUT0,1 = 0 V; VCC = 13 V; TJ = 125 °C
0
Output - VCC diode voltage at
TJ = 150 °C
VF
Min. Typ. Max. Unit
60
260
550
µs
2.9
4
mA
4.5
mA
0.01
0.5
3
IOUT = -4.6 A; TJ = 150 °C
0.7
µA
V
1. For each channel.
2. Power MOSFET leakage included.
3. Parameter specified by design; not tested in production.
Table 6. Switching
VCC = 13 V; -40 °C < TJ < 150 °C, unless otherwise specified
Symbol
Parameter
td(on)(1)
Turn-on delay time at TJ = 25 °C
td(off)(1)
Turn-off delay time at TJ = 25 °C
(dVOUT/dt)on(1)
Turn-on voltage slope at TJ = 25 °C
(dVOUT/dt)off(1)
Turn-off voltage slope at TJ = 25 °C
Test conditions
RL = 2.8 Ω
RL = 2.8 Ω
Min.
Typ.
Max.
10
46
120
10
30
100
0.2
0.4
0.7
0.35
0.6
0.7
Unit
µs
V/µs
WON(2)
Switching energy losses at turn-on (twon)
RL = 2.8 Ω
0.55
1.38
mJ
WOFF
(2)
Switching energy losses at turn-off (twoff)
RL = 2.8 Ω
0.37
0.74
mJ
tSKEW(1)
Differential Pulse skew (tPHL - tPLH)
RL = 2.8 Ω
-25
25
µs
-75
1. See Figure 4. Switching time and pulse skew.
2. Parameter specified by design and evaluated by characterization; not tested in production.
DS12148 - Rev 4
page 7/38
VND9008AJ
Main electrical characteristics
Table 7. Logic inputs
7 V < VCC < 28 V; -40 °C < TJ < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.9
V
INPUT0,1 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
6
IIN = -1 mA
µA
8.5
-0.7
V
FaultRST characteristics
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
6
IIN = -1 mA
µA
8.5
-0.7
V
SEL characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
6
IIN = -1 mA
µA
8.5
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
DS12148 - Rev 4
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
IIN = -1 mA
V
µA
V
9
12
-0.7
V
page 8/38
VND9008AJ
Main electrical characteristics
Table 8. Protections
7 V < VCC < 18 V; -40 °C < TJ < 150 °C
Symbol
Parameter
ILIMH(1)
DC short circuit current
ILIMH2(2)
DC short circuit current
ILIMH at 22 V DC short circuit current
TTSD
TRS
THYST
ΔTJ_SD
Test conditions
Min.
Typ.
Max.
Unit
VCC = 16 V, TJ = -40 °C
-15%
74.5
+15%
A
VCC = 16 V, TJ = 150 °C
-15%
56
+15%
A
VCC = 19 V, TJ = -40 °C
-15%
56.5
+15%
A
VCC = 19 V, TJ = 150 °C
-15%
42.8
+15%
A
VCC = 22 V, TJ = 25 °C
Shutdown temperature
18.9
150
Shutdown temperature (VCC decreasing)
VCC = 2.7 V
140
Thermal reset of fault diagnostic indication
VFR = 0 V; VSEn = 5 V
135
Thermal hysteresis
210
°C
°C
7
°C
VCC = 16 V
80
K
VCC = 19 V
55
K
(TTSD - TRS)(3)
Dynamic temperature
175
A
VFR = 5 V to 0 V; VSEn = 5 V;
tLATCH_RST
tD_Restart
Fault reset time for output unlatch(3)
•
Latch-OFF delay time before automatic
restart
IOUT = 1 A; L = 6 mH;
VDEMAG
3
for example Ch0:
VIN0 = 5 V; VSEL = 0 V
Turn-off output voltage clamp
TJ = -40 °C
IOUT = 1 A; L = 6 mH;
TJ = 25 °C to 150 °C
10
20
µs
50
75
ms
VCC - 36
V
VCC - 36 VCC - 38 VCC - 45
V
1. ILIMH, guaranteed beteween 7 V and 16 V, -40 °C < TJ < 150 °C.
2. ILIMH2, guaranteed beteween 16 V and 19 V, -40 °C < TJ < 150 °C.
3. Parameter specified by design and evaluated by characterization; not tested in production.
DS12148 - Rev 4
page 9/38
VND9008AJ
Main electrical characteristics
Table 9. Current sense
7 V < VCC < 18 V; -40°C < TJ < 150°C
Symbol
Parameter
VSENSE_CL
Test conditions
VSEn = 0 V; ISENSE = 1 mA
CS clamp voltage
Min.
Typ.
-9
-8
VSEn = 0 V; ISENSE = -1 mA
Max. Unit
-7
7
V
Current sense characteristics
KOL
dKOL/KOL(1)(2)
K0
dK0/K0 (1) (2)
K1
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
(1)(2)
dK3/K3
IOUT/ISENSE
IOUT = 100 mA; VSENSE = 0.5 V; VSEn = 5 V
Current sense ratio drift at
calibration point
IOUT = 100 mA; VSENSE = 0.5 V; VSEn = 5 V
IOUT/ISENSE
IOUT = 0.5 A; VSENSE = 0.5 V; VSEn = 5 V
Current sense ratio drift
IOUT = 0.5 A; VSENSE = 0.5 V; VSEn = 5 V
IOUT/ISENSE
IOUT = 0.9 A; VSENSE = 3.5 V; VSEn = 5 V
Current sense ratio drift
IOUT = 0.9 A; VSENSE = 3.5 V; VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 4.6 A; VSENSE = 3.5 V; VSEn = 5 V
-7%
Current sense ratio drift
IOUT = 4.6 A; VSENSE = 3.5 V; VSEn = 5 V
-7
IOUT/ISENSE
IOUT = 13.8 A; VSENSE = 3.5 V; VSEn = 5 V
-5%
Current sense ratio drift
IOUT = 13.8 A; VSENSE = 3.5 V; VSEn = 5 V
-5
5
CS disabled: VSEn = 0 V
0
0.5
-1
1
0
10
0
1
CS disabled:
-1 V < VSENSE < 5 V(1)
-35% 9150 +35%
-25
25
%
-25% 9150 +25%
-20
20
%
-15% 9150 +15%
10
9150
+7%
7
9150
%
%
+5%
%
CS enabled: VSEn = 5 V; All channels ON;
IOUTX = 0 A; ChX diagnostic selected;
ISENSE0
Current sense leakage current
•
for example Ch0:
VIN0 = 5 V; VIN1 = 5 V; VSEL = 0 V;
IOUT0 = 0 A; IOUT1 = 4.6 A
µA
CS enabled: VSEn = 5 V; ChX OFF; ChX
diagnostic selected:
•
for example Ch0:
VIN0 = 0 V; VIN1 = 5 V; VSEL = 0 V;
IOUT0 = 0 A; IOUT1 = 4.6 A
VSEn = 5 V; RSENSE = 2.7 kΩ;
VOUT_MSD
(1)
Output Voltage for CS shutdown
•
VSENSE_SAT
CS saturation voltage
VCC = 7 V; RSENSE = 10 kΩ; VSEn = 5 V;
VIN0 = 5 V; VSEL = 0 V; IOUT0 = 13.8 A;
TJ = -40 °C
ISENSE_SAT (1)
CS saturation current
Output saturation current
IOUT_SAT (1)
5
for example Ch0:
VIN0 = 5 V; VSEL = 0 V; IOUT0 = 4.6 A
V
4.8
V
VCC = 7 V; VSENSE = 3.5 V; VIN0 = 5 V;
VSEn = 5 V; VSEL = 0 V; TJ = 150 °C
2
mA
VCC = 7 V; VSENSE = 3.5 V; VIN0 = 5 V;
VSEn = 5 V; VSEL = 0 V; TJ = 150 °C
30
A
OFF-state diagnostic
VSEn = 5 V; ChX OFF;
VOL
DS12148 - Rev 4
OFF-state open-load voltage
detection threshold
ChX diagnostic selected
•
2
3
4
V
for example: Ch0
VIN0 = 0 V; VSEL = 0 V;
page 10/38
VND9008AJ
Main electrical characteristics
7 V < VCC < 18 V; -40°C < TJ < 150°C
Symbol
IL(off2)
Parameter
OFF-state output sink current
Test conditions
VIN = 0 V; VOUT = VOL;
TJ = -40°C to 125°C
Min.
Typ.
Max. Unit
-150
-40
-5
µA
150
260
400
µs
60
µs
30
µs
VSEn = 5 V; ChX ON to OFF transition;
ChX diagnostic selected
tDSTKON
OFF-state diagnostic delay time
from falling edge of INPUT (see
Figure 6. TDSTKON )
•
tD_OL_V
Settling time for valid OFF-state
open load diagnostic indication
from rising edge of SEn
VIN0 = 0 V; VIN1 = 0 V; VFR = 0 V; VSEL = 0 V;
VOUT0 = 4 V; VSEn = 0 V to 5 V
for example: Ch0
VIN0 = 5 V to 0 V; VSEL = 0 V;
IOUT0 = 0 A; VOUT0 = 4 V
VSEn = 5 V; ChX OFF;
tD_VOL
OFF-state diagnostic delay time
from rising edge of VOUT
ChX diagnostic selected
•
5
for example: Ch0
VIN0 = 0 V; VSEL = 0 V;
VOUT = 0 V to 4 V
Fault diagnostic feedback (see Table 10. Truth table)
13 V < VCC < 18 V; Ch0 in open load;
RSENSE = 0.7 kΩ; VIN0 = 0 V;
VSENSEH
Current sense output voltage in
fault condition
5
7.5
VSEn = 5 V; IOUT0 = 0 A; VOUT0 = 4 V
V
VCC = 7 V; Ch0 in open load;
RSENSE = 0.7 kΩ; VIN0 = 0 V;
4.3
VSEn = 5 V; IOUT0 = 0 A; VOUT0 = 4 V
13 V < VCC < 18 V; VSENSE = 5 V;
Ch0 in open load;
VIN0 = 0 V; VSEn = 5 V;
ISENSEH
Current sense output current in
fault condition
7
8.6
12
IOUT0 = 0 A; VOUT0 = 4 V
mA
VCC = 7 V; VSENSE = 5 V;
Ch0 in open load;
VIN0 = 0 V; VSEn = 5 V;
4.4
IOUT0 = 0 A; VOUT0 = 4 V
Current sense timings (current sense mode - see Figure 5. Current sense timings (current sense mode)) (3)
DS12148 - Rev 4
tDSENSE1H
Current sense settling time from
rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 2.8 Ω
tDSENSE1L
Current sense disable delay time
from falling edge of SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 2.8 Ω
tDSENSE2H
Current sense settling time from
rising edge of INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 2.8 Ω
ΔtDSENSE2H
Current sense settling time from
rising edge of IOUT (dynamic
response to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ;
ISENSE = 90% of ISENSEMAX; RL = 2.8 Ω
tDSENSE2L
Current sense turn-off delay time
from falling edge of INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 2.8 Ω
60
µs
5
20
µs
100
200
µs
100
µs
250
µs
70
page 11/38
VND9008AJ
Main electrical characteristics
7 V < VCC < 18 V; -40°C < TJ < 150°C
Symbol
Parameter
Test conditions
tDSENSE3H
Current sense latch-OFF filtering
time
Min.
Typ.
1.4
2.0
Max. Unit
2.6
ms
30
µs
20
µs
Current sense timings (multiplexer transition times)(3)
VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V;
tD_XtoY
Current sense transition delay
from ChX to ChY
VSEL = 0 V to 5 V; IOUT0 = 0 A;
IOUT1 = 4.6 A; RSENSE = 1 kΩ
VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V;
Current sense transition delay
tD_CStoVSENSEH from stable current sense on ChX VSEL = 0 V to 5 V; IOUT0 = 4.6 A;
to VSENSEH on ChY
VOUT1 = 4 V; RSENSE = 1 kΩ
1. Parameter specified by design and evaluated by characterization; not tested in production.
2. All values refer to VCC = 13 V; TJ = 25°C, unless otherwise specified.
3. Transition delay is measured up to ±10% of final conditions.
Figure 4. Switching time and pulse skew
twon
VOUT
twoff
Vcc
80% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
20% Vcc
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
DS12148 - Rev 4
page 12/38
VND9008AJ
Main electrical characteristics
Figure 5. Current sense timings (current sense mode)
IN
High
SEn
Low
IOUT
CURRENT SENSE
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
GADG1007181523PS
Figure 6. TDSTKON
VINPUT
VOUT
VOUT > VOL
CS
TDSTKON
GADG0112170745PS
DS12148 - Rev 4
page 13/38
VND9008AJ
Main electrical characteristics
Table 10. Truth table
Mode
Conditions
Standby
INX FR SEn SEL OUTX
All logic inputs low
L
L
X
H
L
H
L
See (1)
H
See (1)
Outputs configured for autorestart
H
H
See (1)
Outputs configured for
Latch-off
L
X
L
See (1)
H
L
H
See (1)
H
H
L
See (1) Output latches-off
VCC < VUSD (falling)
X
X
Short to VCC
L
X
Open-load
L
X
Inductive loads turn-off
L
X
Overload or short to GND causing:
TJ > TTSD or
Overload
ΔTJ > ΔTJ _SD
Undervoltage
OFF-state
diagnostics
Negative output
voltage
L
Low quiescent current
consumption
Hi-Z
TJ < 150 °C
L
Comments
L
Nominal load connected;
Normal
L
CS
See (1)
See (1)
X
X
See (1)
See (1)
Output cycles with
temperature hysteresis
L
Hi-Z
Re-start when VCC > VUSD +
L
Hi-Z
VUSDhyst (rising)
H
See (1)
H
See (1) External pull-up
< 0 V See (1)
1. Refer to Table 11. Current sense multiplexer addressing
Table 11. Current sense multiplexer addressing
SEn SEL
DS12148 - Rev 4
MUX channel
CS output
Normal mode
Overload
OFF-state diag.
Negative output
L
X
H
L
Channel 0 diagnostic
ISENSE = 1/K * IOUT0
VSENSE = VSENSEH
VSENSE = VSENSEH
Hi-Z
H
H
Channel 1 diagnostic
ISENSE = 1/K * IOUT1
VSENSE = VSENSEH
VSENSE = VSENSEH
Hi-Z
Hi-Z
page 14/38
VND9008AJ
Waveforms
2.4
Waveforms
Figure 7. Latch-off mode - Intermittent short circuit
Short circuit condition
INPUT
Normal condition
Unlatch command is
stored, but no restart until
tD_Restart is elapsed.
FaultRST
ILIMH
INOM
IOUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
tD_Restart
(*) Not in scale
t > tDSENSE3H
Figure 8. Auto-restart mode - Intermittent short circuit
Short circuit condition
Normal condition
INPUT
FaultRST
ILIMH
Power Limitation
INOM
IOUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
DS12148 - Rev 4
tD_Restart
t > tDSENSE3H
page 15/38
VND9008AJ
Waveforms
Figure 9. Auto-restart mode - Permanent short circuit
INPUT
FaultRST
ILIMH
Power Limitation
ILIMH
Power Limitation
IOUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
tD_Restart
(*) Not in scale
t < tDSENSE3H
Figure 10. Standby mode activation
INPUT0
INPUT1
SEn
SEL
FaultRST
IS(ON)
= Standby
= t < t D_STBY
= t > t D_STBY
Figure 11. Standby state diagram
Normal Operation
t > t D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
Stand-by Mode
DS12148 - Rev 4
page 16/38
VND9008AJ
Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature
swing ΔTJ through the direct measurement of the spatial temperature gradient on the device surface in order
to automatically shut off the output MOSFET as soon as ΔTJ exceeds the safety level of ΔTJ_SD. According to
the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C),
it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or
remains off (FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other
components of the system (for example bonding wires, wiring harness, connectors, loads, etc.) from excessive
current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is
clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative
voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor
energy to be dissipated without damaging the device.
DS12148 - Rev 4
page 17/38
VND9008AJ
Application information
4
Application information
Figure 12. Application diagram
+5V
VDD
OUT
VCC
Rprot_SEn
OUT
SEn
INPUT
Rprot
OUT
Logic
OUT
Dld
Rprot
FaultRST
Rprot
SEL
OUTPUT
Rprot
ADC in
CS
Current mirror
GND
Cext
Rsense
OUT
R GND
GND
D GND
GND
GND
GND
GND
GND
4.1
GND protection network against reverse battery
Figure 13. Simplified internal structure
5V
Vcc
Rprot
Rprot_SEn
INPUT
SEn
MCU
Dld
Rprot
FaultRST
OUTPUT
Rprot
CS
GND
Rsense
D GND
R GND
GND
DS12148 - Rev 4
GAPGCFT00830
page 18/38
VND9008AJ
Immunity against transient electrical disturbances
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence
of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the
microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares
the same diode/resistor network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12. ISO 7637-2 - electrical transient
conduction along supply line.
Test pulses are applied directly to DUT (device under test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4.
The DUT is intended as the current device only, with external components as shown in Figure 14. M0-9
application schematic.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function
does not perform as designed during the test but returns automatically to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level
with Status II functional
performance status
Minimum number
of pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator internal
impedance
Level
US (1)
1
III
-112 V
500 pulses
0.5 s
2a
III
+55 V
500 pulses
0.2 s
5s
50 µs, 2 Ω
3a
IV
-220 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
IV
+150 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4 (2)
IV
-7 V
1 pulse
min
max
2 ms, 10 Ω
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3)
35 V
5 pulse
1 min
400 ms, 2 Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 35 V external suppressor referred to ground (-40°C < Tj < 150 °C).
DS12148 - Rev 4
page 19/38
VND9008AJ
MCU I/Os protection
Figure 14. M0-9 application schematic
+5V
VDD
OUT
VCC
Rprot_SEn
OUT
SEn
INPUT
Rprot
OUT
Logic
OUT
Rprot
FaultRST
Rprot
SEL
1μF
OUTPUT
Rprot
ADC in
CS
Current mirror
GND
Cext
Rload_nom
Rsense
OUT
R GND
GND
D GND
GND
GND
GND
GND
GND
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from
latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current
required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
A different value of the resistor has to be used for SEn pin, Rprot_SEn, as reported in Figure 12. Application
diagram.
4.4
CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the
following signals:
•
Current monitor: current mirror of channel output current
Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and
SEn pins, according to the address map in Table 11.
DS12148 - Rev 4
page 20/38
VND9008AJ
CS - analog current sense
Figure 15. CurrentSense and diagnostic – block diagram
VCC
VCC – GND
Clamp
Internal Supply
Undervoltage
shut-down
Control & Diagnostic
FaultRST
INPUT
VCC – OUT
Clamp
Gate Driver
T
SEL1
SEL 0
SE n
Current
Limitation
I SENSE
RPROT
CS
Fault
Diagnostic
Power Limitation
Overtemperature
MUX
Short to VCC
Open-Load in OFF
To µC ADC
K factor
R SENSE
Current
Sense
CURRENT
MONITOR
IOUT
OUT
Fault
VSENSEH
GND
GADG2004171456PS
4.4.1
Principle of current sense signal generation
Figure 16. CurrentSense block diagram
Vcc
INPUT
Sense MOS
Main MOS
OUT
Current sense
Current sense Switch Block
Fault
CS
To uC ADC
RPROT
RSENSE
GAPG2307131200CFT
DS12148 - Rev 4
page 21/38
VND9008AJ
CS - analog current sense
Current sense
The output is capable of providing:
•
•
Current mirror proportional to the load current in normal operation, delivering current proportional to the
load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using
an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using
simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
•
VSENSE is voltage measurable on RSENSE resistor
•
ISENSE is current provided from CurrentSense pin in current output mode
•
IOUT is current flowing through output
•
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric
factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying
ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin which is switched to a
“current limited” voltage source, VSENSEH.
In any case, the current sourced by the CurrentSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms.
DS12148 - Rev 4
page 22/38
VND9008AJ
CS - analog current sense
Figure 17. Analog HSD – open-load detection in off-state
+5V
Vbat
Vbat
100nF/ 50V
100nF
Rpull-up
GND
Microcontroller
GND
VDD
V CC
OUT
SEn
2.2 k
INPUT
External
Pull -Up
switch
OUT
Logic
15k
FaultRST
OUT
SEL
15k
OUTPUT
OUT
OUTPUT
CS
Cu rrent mirror
15k
GND
ADC in
R GN D
4.7k
Rsense
15k
DGN D
10nF /100V
OUT
15k
GND
GND
CEXT
GND
GND
GND
GND
GAPG1201151432CFT
Figure 18. Open-load / short to VCC condition
VIN
VSENSE
VSENSEH
Pull-up connected
Open-load
VSENSE = 0
VSENSE
Short to VCC
Pull-up
disconnected
tDSTKON
VSENSEH
GADG2702181218RI
DS12148 - Rev 4
page 23/38
VND9008AJ
CS - analog current sense
Table 13. CS pin levels in off-state
Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
CS
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the
device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature
of the short-circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive
supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby
current consumption to increase in normal conditions, that is when load is connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation:
RPU <
DS12148 - Rev 4
VPU - 4
IL(off2)min @ 4V
page 24/38
VND9008AJ
Maximum demagnetization energy (VCC = 16 V)
5
Maximum demagnetization energy (VCC = 16 V)
Figure 19. Maximum turn off current versus inductance
GADG131220220933GT
100
Single Pulse TJstart = 150 °C
Repetitive pulse TJstart = 100 °C
Repetitive pulse TJstart = 125 °C
I (A)
10
1
0
0.1
1
10
100
1000
L (mH)
Figure 20. Maximum turn off energy versus inductance
GADG131220221019GT
1000
Single Pulse TJstart = 150 °C
Repetitive pulse TJstart = 100 °C
Repetitive pulse TJstart = 125 °C
E (mJ)
100
10
1
0.1
1
10
100
1000
L (mH)
DS12148 - Rev 4
page 25/38
VND9008AJ
Package and PCB thermal data
6
Package and PCB thermal data
6.1
PowerSSO-16 thermal data
Figure 21. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5)
Figure 22. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7)
Cu coverage on top layer: 90%
Cu on mid1 layer: full coverage
Cu on mid2 layer: full coverage
Cu coverage on bottom layer: 90%
Table 14. PCB properties
Dimension
Board finish thickness
Board dimension
Board Material
1.6 mm ±10%
77 mm x 86 mm
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
Thermal via diameter
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
DS12148 - Rev 4
Value
1.2 mm
0.3 mm ±0.08 mm
0.025 mm
2.2 mm x 3.9 mm
Footprint, 2 cm2 or 8 cm2
page 26/38
VND9008AJ
PowerSSO-16 thermal data
Figure 23. RthJA vs PCB copper area in open box free air condition (one channel on)
90
RthJA
GADG131220221105GT
80
70
60
50
40
30
0
1
2
3
4
5
6
7
8
9
PCB Cu heatsink area (cm2)
Figure 24. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/W)
GADG131220221132GT
100
10
1
Cu=footprint
Cu=2 cm2
0.1
Cu=8 cm2
4 Layer
0.01
0.0001
0.001
0.01
0.1
Time (s)
1
10
100
1000
Equation: pulse calculation formula
Zthδ = Rth · δ + Zthtp (1 - δ)
where δ = tP/T
DS12148 - Rev 4
page 27/38
VND9008AJ
PowerSSO-16 thermal data
Figure 25. Thermal fitting model of a double-channel HSD in PowerSSO-16
PdCh1
PdCh2
TJ
TJ
C1
C2
R1
R2
C7
C8
R7
R8
C3
C4
C5
C6
R3
R4
R5
R6
GAPGCFT00438
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15. Thermal parameters
DS12148 - Rev 4
Area/island (cm2)
FP
R1 = R7 (°C/W)
1.35
R2 = R8 (°C/W)
2.45
R3 (°C/W)
2
8
4L
4
4
4
4
R4 (°C/W)
16
6
6
4.2
R5 (°C/W)
30
20
10
3
R6 (°C/W)
26
20
18
7
C1 = C7 (W·s/°C)
0.001
C2 = C8 (W·s/°C)
0.0152
C3 (W·s/°C)
0.09
C4 (W·s/°C)
0.2
0.3
0.3
0.4
C5 (W·s/°C)
0.4
1
1
4
C6 (W·s/°C)
3
5
7
18
page 28/38
VND9008AJ
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
7.1
PowerSSO-16 package information
Figure 26. PowerSSO-16 package dimensions
ggg
D2
D3
Bottom view
C A-B D
ggg
C A-B D
minimum solderable area
Section A-A
E3 E2
h
θ2
h
θ1
R1
H
B
for dual gauge only
eee C
GAUGE PLANE
S
A2
A
R
B
L
θ3
ccc C
θ
e
L1
SEATING PLANE
A1
b
ddd
C
CD
2x
f f f C A-B
D
A
N
Section B-B
D
A
b
WITH PLATING
1.2
for dual gauge only
c
c1
E1 E
index area
(0.25D x 0.75E1)
b1
2x
BASE METAL
aaa C D
Top view
2x N/2 TIPS
bbb C
1
2
3
A
N/2
B
8017965_Rev_9
DS12148 - Rev 4
GAPG1605141159CFT
page 29/38
VND9008AJ
PowerSSO-16 package information
Table 16. PowerSSO-16 mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
Θ
0°
Θ1
0°
Θ2
5°
15°
Θ3
5°
15°
8°
A
1.70
A1
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
0.25
0.28
0.25
0.20
0.23
4.9 BSC
D2
3.60
D3
2.90
4.20
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
2.50
E3
1.80
h
0.25
L
0.40
3.10
0.50
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
0.85
Tolerance of form and position
DS12148 - Rev 4
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
page 30/38
VND9008AJ
PowerSSO-16 packing information
7.2
PowerSSO-16 packing information
Figure 27. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
W2
A
N
D
C
W1
B
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
TAPG2004151655CFT
Table 17. Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2 /-0)
12.4
W2 (max)
18.4
1. All dimensions are in mm.
DS12148 - Rev 4
page 31/38
VND9008AJ
PowerSSO-16 packing information
Figure 28. PowerSSO-16 carrier tape
P0
P2
4.0 ±0.1
2.0 ±0.1
0.30 ±0.05
X
1.55 ±0.05
1.75 ±0.1
1.6 ±0.1
F
W
B0
R 0.5
Typical
Y
K1
Y
X
K0
P1
A0
SECTION X - X
REF 4.18
REF 0.6
REF 0.5
SECTION Y - Y
GAPG2204151242CFT
Table 18. PowerSSO-16 carrier tape dimensions
Description
Value(1)
A0
6.50 ± 0.1
B0
5.25 ± 0.1
K0
2.10 ± 0.1
K1
1.80 ± 0.1
F
5.50 ± 0.1
P1
8.00 ± 0.1
W
12.00 ± 0.3
1. All dimensions are in mm.
Figure 29. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Punched carrier
8 mm & 12 mm only
END
Carrier tape
Round sprocket holes
START
Top cover tape
Elongated sprocket holes
(32 mm tape and wider)
Trailer
160 mm minimum
Top cover tape
Components
100 mm min.
Leader
400 mm minimum
User direction feed
GAPG2004151511CFT
DS12148 - Rev 4
page 32/38
VND9008AJ
PowerSSO-16 marking information
7.3
PowerSSO-16 marking information
Figure 30. PowerSSO-16 marking information
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible
for any consequences resulting from such use. In no event will ST be liable for the customer using any of these
engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12148 - Rev 4
page 33/38
VND9008AJ
Revision history
Table 19. Document revision history
Date
Revision
Changes
06-Dec-2017
1
Initial release.
13-Dec-2017
2
No content changed, removed the watermark "Restricted".
Added:
•
Section 5 Package information.
Updated:
25-Jun-2021
3
•
•
•
•
•
•
•
•
Figure 1. Block diagram;
Table 5. Power section;
Table 6. Switching;
Table 8. Protections;
Table 9. Current sense;
Section Features;
Section Applications;
Section 2.4 Waveforms.
Minor text changes in:
•
•
Table 7. Logic inputs;
Table 3. Absolute maximum ratings.
Update Section 2.1 Absolute maximum ratings and Section 2.2 Thermal data.
Updated Table 5. Power section, Table 6. Switching,Table 8. Protections and Table 9. Current
sense.
23-Dec-2022
4
Updated Section 4 Application information.
Added Section 5 Maximum demagnetization energy (VCC = 16 V).
Added Section 6 Package and PCB thermal data.
Minor text changes.
DS12148 - Rev 4
page 34/38
VND9008AJ
Contents
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
2.1
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1
GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1
Diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4
CS - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4.1
Principle of current sense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4.2
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.1
7
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7.1
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2
PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3
PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DS12148 - Rev 4
page 35/38
VND9008AJ
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suggested connections for unused and not connected pins . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . .
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current sense multiplexer addressing . . . . . . . . . . . . . . . . .
ISO 7637-2 - electrical transient conduction along supply line
CS pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . .
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . .
DS12148 - Rev 4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 3
. 4
. 5
. 6
. 6
. 7
. 8
. 9
10
14
14
19
24
26
28
30
31
32
34
page 36/38
VND9008AJ
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
DS12148 - Rev 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching time and pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current sense timings (current sense mode). . . . . . . . . . . . . . . . . . . . . . . . . . .
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latch-off mode - Intermittent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-restart mode - Intermittent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-restart mode - Permanent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M0-9 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CurrentSense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . .
CurrentSense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog HSD – open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . .
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum turn off energy versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . .
PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . .
RthJA vs PCB copper area in open box free air condition (one channel on) . . . . . .
PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . .
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . .
PowerSSO-16 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 3
. 4
. 5
12
13
13
15
15
16
16
16
18
18
20
21
21
23
23
25
25
26
26
27
27
28
29
31
32
32
33
page 37/38
VND9008AJ
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS12148 - Rev 4
page 38/38
">