STMicroelectronics VND830AEP-E Datasheet

VND830AEP-E

Double channel high side driver

Features

Type

VND830AEP-E

1.

Per each channel.

R

DS(on)

60m Ω (1)

I

OUT

6A

(1)

V

CC

36V

■

■

■

■

■

■

■

■

■

■

■

DC short circuit current: 6A

CMOS compatible inputs

Proportional load current sense

Undervoltage and overvoltage shutdown

Overvoltage clamp

Thermal shutdown

Current limitation

Very low standby power dissipation

Protection against loss of ground and loss of

V

CC

Reverse battery protection

(a)

In compliance with the 2002/95/EC european directive a.

See

Application schematic on page 16

Table 1.

Device summary

Package

PowerSSO-24

PowerSSO-24

Description

The VND830AEP-E is a monolithic device made using | STMicroelectronics VIPower™ M0-3

Technology. The VND830AEP-E is intended for driving any type of multiple load with one side connected to ground.

The Active V

CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).

This device has two channels in high side configuration; each channel has an analog sense output on which the sensing current is proportional (according to a known ratio) to the corresponding load current. Built-in thermal shutdown and outputs current limitation protect the chip from over temperature and short circuit.

The device automatically turns off in the case where the ground pin becomes disconnected.

Order codes

Tube

VND830AEP-E

Tape and reel

VND830AEPTR-E

September 2013 Doc ID 11038 Rev 4 1/26 www.st.com

1

2/26

1

2

Contents

Contents

3

4

5

6

VND830AEP-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16

3.1.1

Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16

3.1.2

Solution 2: a diode (D

GND

) in the ground line . . . . . . . . . . . . . . . . . . . . 17

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3

MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4

Maximum demagnetization energy (V

CC

= 13.5V) . . . . . . . . . . . . . . . . . . 18

Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1

ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2

PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Doc ID 11038 Rev 4

VND830AEP-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 5.

Table 6.

Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7.

Table 8.

Table 9.

V

CC

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switching (V

CC

= 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 10.

Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 12.

Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 13.

Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 14.

Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 15.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 16.

PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Doc ID 11038 Rev 4 3/26

List of figures

List of figures

VND830AEP-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11.

Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13.

ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 14.

On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 16.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 17.

On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 19.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 20.

Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 21.

PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 19

Figure 23.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 20

Figure 24.

Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 20

Figure 25.

PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 26.

PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27.

PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4/26 Doc ID 11038 Rev 4

VND830AEP-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

INPUT 1

INPUT 2

GND

V

CC

CLAMP

LOGIC

OVERTEMP. 1

Ot1

OVERTEMP. 2

Ot2

V

CC

OVERVOLTAGE

UNDERVOLTAGE

PwCLAMP 1

DRIVER 1

I

OUT1

I

LIM1

V dslim1

K

PwCLAMP 2

DRIVER 2

I

OUT2

I

LIM2

V dslim2

K

Ot1

Ot2

OUTPUT 1

CURRENT

SENSE 1

OUTPUT 2

CURRENT

SENSE 2

Figure 2.

Configuration diagram (top view)

V

CC

GND

NC

INPUT2

NC

INPUT1

NC

C.SENSE1

NC

C.SENSE2

NC

V

CC

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

TAB = V

CC

Table 2.

Suggested connections for unused and not connected pins

Connection / pin Current sense N.C.

Output Input

Floating

To ground

Through 1K Ω resistor

X

X

X X

Through 10K Ω resistor

Doc ID 11038 Rev 4 5/26

Electrical specifications VND830AEP-E

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality document.

Table 3.

Symbol

Absolute maximum ratings

Parameter Value Unit

V

CC

- V

CC

- I

GND

I

OUT

I

R

I

IN

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

DC output current

Reverse DC output current

DC input current

41

- 0.3

- 200

Internally limited

- 6

+/- 10

V

V mA

A

A mA

V

CSENSE

V

E

ESD

MAX

P

T tot j

T c

T stg

Current sense maximum voltage

Case operating temperature

Storage temperature

- 3

15

V

V

Electrostatic discharge (human body model:R=1.5K

Ω; C=100pF)

– Input

– Current sense

– Output

– V

CC

Maximum switching energy

(L = 2.2mH; R

L

= 0 Ω ; V bat

= 13.5V; T jstart

= 150°C; I

L

= 10A)

Power dissipation (per island) at T lead

= 25°C

Junction operating temperature

4000

2000

5000

5000

153

8.3

mJ

W

Internally limited °C

V

V

V

V

- 40 to 150

- 55 to 150

°C

°C

6/26

Table 4.

Symbol

Thermal data (per island)

Parameter Max. value Unit

R thj-case

Thermal resistance junction-case 1.7

°C/W

R thj-amb

Thermal resistance junction-ambient (one chip ON) 55

(1)

°C/W

1.

When mounted on a standard single-sided FR-4 board with 0.5cm

2

of Cu (at least 35 µm thick) connected to all Vcc pins. Horizontal mounting and no artificial air flow.

Doc ID 11038 Rev 4

VND830AEP-E Electrical specifications

Values specified in this section are for 8V < V

CC

< 36V; -40°C < T j

< 150°C, unless otherwise stated.

Figure 3.

Current and voltage conventions

V

IN1

I

IN1

I

IN2

V

IN2

I

S

OUTPUT1

INPUT1

CURRENT SENSE 1

INPUT2

V

CC

OUTPUT2

CURRENT SENSE 2

GROUND

V

F1

(*)

I

OUT1

I

SENSE1

V

SENSE1

I

OUT2

V

I

SENSE2

OUT2

V

OUT1

V

SENSE2

I

GND

V

CC

Note: V

Fn

= V

CCn

- V

OUTn

during reverse battery condition.

Table 5.

Symbol

V

CC

V

USD

V

OV

Power output

Parameter

Operating supply voltage

Undervoltage shutdown

Overvoltage shutdown

Test conditions

R

ON

On-state resistance

V

CLAMP

Clamp voltage

I

OUT

= 2A; T j

= 25°C

I

OUT

= 2A; T j

= 125°C

I

CC

= 20mA

Off-state; V

CC

= 13V;

V

IN

= V

OUT

= 0V

I

S

Supply current

Off-state; V

CC

= 13V;

V

IN

= V

OUT

= 0V; T j

= 25°C

I

I

I

L(off1)

Off-state output current

L(off3)

L(off4)

Off-state output current

Off-state output current

On-state; V

CC

= 13V; V

IN

= 5V;

I

OUT

= 0A; R

SENSE

= 3.9K

Ω

V

IN

= V

OUT

= 0V; V

CC

= 36V;

T j

= 125°C

V

IN

= V

OUT

= 0V; V

CC

= 13V;

T j

= 125°C

V

IN

= V

OUT

= 0V; V

CC

= 13V;

T j

= 25°C

Min.

Typ.

Max.

Unit

5.5

13

3

36

4

36

5.5

41 48

60

120

55

V

V

V m Ω m Ω

V

0

12 40 µA

12 25 µA

7

50 mA

µA

5 µA

3 µA

Doc ID 11038 Rev 4 7/26

Electrical specifications

Note:

VND830AEP-E

Table 6.

Symbol

Protections

Parameter Test conditions

I lim

Current limitation

V

CC

= 13V

5.5V < V

CC

< 36V

T

TSD

T

R

T hyst

Shutdown temperature

Reset temperature

V demag

V

ON

Thermal hysteresis

Turn-off output clamp voltage

I

OUT

= 2A; V

IN

= 0V;

L = 6mH

Output voltage drop limitation I

OUT

= 10mA

Min.

Typ.

Max.

Unit

6 10 15

15

150 175 200

135

7 15

V

CC

41

V

CC

-

48

V

CC

55

-

50

A

A

°C

°C

°C

V mV

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

Table 7.

Symbol

V

F

V

CC

- output diode

Parameter

Forward on voltage

Test conditions

- I

OUT

= 1.3A; T j

= 150°C

Min.

Typ.

Max.

Unit

0.6

V

Table 8.

Symbol

Switching (V

CC

= 13V; T j

= 25°C)

Parameter Test conditions dV

OUT

/dt

(on)

Turn-on voltage slope dV t t d(on) d(off)

OUT

/dt

(off)

Turn-on delay time

Turn-off delay time

Turn-off voltage slope

R

L

= 6.5

Ω from V

IN

rising edge to V

OUT

= 1.3V (see

Figure 5 )

R

L

= 6.5

Ω from V

IN

falling edge to V

OUT

= 11.7V

(see

Figure 5

)

R

L

= 6.5

Ω from V

OUT

= 1.3V to

V

OUT

= 10.4V (see

Figure 5

)

R

L

= 6.5

Ω from V

OUT

= 11.7V to V

OUT

= 1.3V (see Figure 5 )

Min.

Typ.

30

30

See

Figure 10

See

Figure 12

Max.

Unit

µs

µs

V/µs

V/µs

Table 9.

Symbol

V

IL

I

IL

V

IH

I

IH

Logic inputs

Parameter

Input low level

Low level input current

Input high level

High level input current

Test conditions

V

IN

= 1.25V

V

IN

= 3.25V

Min.

Typ.

Max.

Unit

1.25

1

3.25

10

V

µA

V

µA

8/26 Doc ID 11038 Rev 4

VND830AEP-E

Table 9.

Symbol

V

I(hyst)

Logic inputs (continued)

Parameter

Input hysteresis voltage

V

ICL

Input clamp voltage

Test conditions

I

IN

= 1mA

I

IN

= -1mA

Electrical specifications

Min.

Typ.

Max.

Unit

0.5

6 6.8

- 0.7

8

V

V

V

Table 10.

Current sense

Symbol Parameter Test conditions Min.

Typ.

Max.

Unit dK dK dK

I

V

K

K

1

/K

K

2

/K

K

0

1

2

3

3

/K

1

2

3

SENSE

SENSE

I

I

I

I

OUT

OUT

Current sense ratio drift

OUT

Current sense ratio drift

OUT

/I

/I

/I

/I

SENSE

SENSE

SENSE

SENSE

Current sense ratio drift

Analog sense leakage current

Max. analog sense output voltage

I

OUT1 or I

OUT2

= 0.05A;

V

SENSE

= 0.5V; other channels open; T j

= -40°C...150°C

I

OUT1 or I

OUT2

= 0.25A;

V

SENSE

= 0.5V; other channels open; T j

= -40°C...150°C

I

OUT1 or I

OUT2

= 0.25A;

V

SENSE

= 0.5V; other channels open; T j

= -40°C...150°C

I

OUT1 or I

OUT2

= 1.6A;

V

SENSE

= 4V; other channels open; T j

= -40°C

T j

= 25°C...150°C

I

OUT1 or I

OUT2

= 1.6A;

V

SENSE

= 4V; other channels open; T j

= -40°C...150°C

I

OUT1 or I

OUT2

= 2.5A;

V

SENSE

= 4V; other channels open; T j

= -40°C

T j

= 25°C...150°C

I

OUT1 or I

OUT2

= 2.5A;

V

SENSE

= 4V; other channels open; T j

= -40°C...150°C

V

IN

= 0V; I

OUT

= 0A; V

SENSE

= 0V;

T j

= -40°C...150°C

V

IN

= 5V; I

OUT

= 0A; V

SENSE

= 0V;

T j

= -40°C...150°C

V

CC

= 5.5V; I

OUT1,2

= 1.3A;

R

SENSE

= 10k Ω

V

CC

> 8V, I

OUT1,2

= 2.5A;

R

SENSE

= 10k Ω

600

-10

-6

-6

0

0

2

4

1300 2000

1000 1400 1900

+10

1280 1500 1800

1300 1500 1780

+6

1280 1500 1680

1340 1500 1600

+6

5

10

%

%

%

µA

µA

V

V

V

SENSEH

Sense voltage in over temperature conditions

V

CC

= 13V; R

SENSE

= 3.9k

Ω 5.5

V

Doc ID 11038 Rev 4 9/26

10/26

Electrical specifications

0.5

1 1.5

Iout (A)

2 2.5

3

VND830AEP-E

Table 10.

Current sense (continued)

Symbol Parameter Test conditions

R

VSENSEH

Analog sense output impedance in over temperature condition

V

CC

= 13V; T j

> T

TSD

All channels open t

DSENSE

Current sense delay response

To 90% I

SENSE

(1)

1.

Current sense signal delay after positive input slope.

;

Figure 4.

I

OUT

/I

SENSE

versus I

OUT

Iout/Isense

2250

2000

1750

1500

Min.

Typ.

Max.

Unit

400 Ω m ax T j= -4 0ºC m ax T j=25...150ºC m in T j=25...150 ºC typ ical valu e m in T j= -40ºC

500 µs

1250

1000

750

500

0

Doc ID 11038 Rev 4

VND830AEP-E

Figure 5.

Switching characteristics

V

OUT

80% dV

OUT

/dt

(on) t r

I

SENSE

90%

10%

Electrical specifications

90% t f dV

OUT

/dt

(off) t t

INPUT t

DSENSE t d(on) t d(off)

Table 11.

Truth table

Conditions

Normal operation

Overtemperature

Undervoltage

Overvoltage

Short circuit to GND

Short circuit to V

CC

Negative output voltage clamp

Input

L

H

L

L

H

L

H

L

H

H

L

H

L

H

Output

H

H

L

L

L

L

L

L

L

L

L

L

L

H t

Sense

0

Nominal

0

V

SENSEH

0

0

0

0

0

(T

J

< T

TSD

) 0

(T

J

> T

TSD

) 0

0

< Nominal

0

Doc ID 11038 Rev 4 11/26

12/26

Electrical specifications VND830AEP-E

Table 12.

Electrical transient requirements (part 1/3)

Test level ISO T/R

7637/1

Test pulse

I II III IV

3b

4

5

1

2

3a

- 25V

+ 25V

- 25V

+ 25V

- 4V

+ 26.5V

- 50V

+ 50V

- 50V

+ 50V

- 5V

+ 46.5V

- 75V

+ 75V

- 100V

+ 75V

- 6V

+ 66.5V

- 100V

+ 100V

- 150V

+ 100V

- 7V

+ 86.5V

Delays and impedance

2ms, 10

Ω

0.2ms, 10 Ω

0.1µs, 50 Ω

0.1µs, 50 Ω

100ms, 0.01

Ω

400ms, 2 Ω

Table 13.

Electrical transient requirements (part 2/3)

Test level ISO T/R

7637/1

Test pulse

I II

3a

3b

1

2

4

5

C

C

C

C

C

C

C

C

C

C

C

E

III

C

C

C

C

C

E

IV

C

C

C

C

C

E

Table 14.

Electrical transient requirements (part 3/3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.

Doc ID 11038 Rev 4

VND830AEP-E

Figure 6.

Waveforms

NORMAL OPERATION

INPUT n

LOAD CURRENT n

SENSE n

V

CC

INPUT n

LOAD CURRENT n

SENSE n

V

USD

UNDERVOLTAGE

V

USDhyst

V

CC

INPUT n

LOAD CURRENT n

SENSE n

V

OV

V

CC

< V

OV

OVERVOLTAGE

V

CC

> V

OV

SHORT TO GROUND

INPUT n

LOAD CURRENT n

LOAD VOLTAGE n

SENSE n

SHORT TO V

CC

INPUT n

LOAD VOLTAGE n

LOAD CURRENT n

SENSE n

<Nominal

<Nominal

Electrical specifications

OVERTEMPERATURE

T j

INPUT n

LOAD CURRENT n

SENSE n

T

TSD

T

R

I

SENSE

=

V

SENSEH

R

SENSE

Doc ID 11038 Rev 4 13/26

Electrical specifications VND830AEP-E

Figure 7.

Off-state output current

IL(off1) (uA)

0.8

0.7

0.6

Off state

Vcc=13V

Vin=Vout=0V

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75

Tc (ºC)

100 125 150 175

Figure 9.

Input clamp voltage

Vicl (V)

8

6.8

6.6

6.4

6.2

6

-50

7.8

7.6

7.4

7.2

7

-25

Iin=1mA

0 25 50 75

Tc (ºC)

100 125 150 175

Figure 11.

Overvoltage shutdown

Vov (V)

50

47.5

45

42.5

40

37.5

35

32.5

30

-50 -25 0 25 50 75

Tc (ºC)

100 125 150 175

Figure 8.

High level input current

Iih (uA)

5

4.5

4

3.5

3

Vin=3.25V

2.5

2

1.5

1

-50 -25 0 25 50 75

Tc (ºC)

100 125 150 175

Figure 10.

Turn-on voltage slope dVout/dt(on)

900

800

Vcc=13V

RI=6.5Ohm

700

600

500

400

300

200

100

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 12.

Turn-off voltage slope dVout/dt(off) (V/ms)

500

450

400

350

300

250

200

150

100

50

0

-50

Vcc=13V

Rl=6.5Ohm

-25 0 25 50 75

Tc (ºC)

100 125 150 175

14/26 Doc ID 11038 Rev 4

VND830AEP-E

Figure 13.

I

LIM

vs T case

Ilim (A)

20

17.5

15

Vcc=13V

12.5

10

7.5

5

2.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 15.

Input high level

Vih (V)

3.6

3.4

3.2

3

2.8

Vcc=13V

2.6

2.4

2.2

2

-50 -25 0 25 50 75

Tc (ºC)

100 125 150 175

Figure 17.

On-state resistance vs Tcase

Ron (mOhm)

100

40

30

20

10

0

-50

90

80

70

60

50

-25

Iout=5A

Vcc=8V & 36V

0 25 50 75

Tc (ºC)

100 125 150 175

Electrical specifications

Figure 14.

On-state resistance vs V

CC

Ron (mOhm)

100

90

80

70

Iout=5A

Tc=150ºC

60

50

40

30

20

5 10 15 20

Vcc (V)

25

Tc=25ºC

Tc= -40ºC

30 35 40

Figure 16.

Input hysteresis voltage

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25

Vcc=13V

0 25 50 75

Tc (ºC)

100 125 150 175

Figure 18.

Input low level

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

Vcc=13V

1.4

1.2

1

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Doc ID 11038 Rev 4 15/26

Application information VND830AEP-E

Figure 19.

Application schematic

+5V

R prot

INPUT1

μ

C

R prot

R prot

CURRENT SENSE1

INPUT2

R prot

R

SENSE1

V

CC

OUTPUT1

R

CURRENT SENSE2

SENSE2

GND

V

GND

R

GND

D

GND

OUTPUT2

D ld

3.1

3.1.1

16/26

GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.

Solution 1: a resistor in the ground line (R

GND

only)

This can be used with any type of load.

The following show how to dimension the R

GND resistor:

1.

R

GND

≤ 600mV / 2 (I

S(on)max

)

2. R

GND

≥ (

V

CC

) / (- I

GND

) where - I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

< 0 during reverse battery situations) is:

P

D

= (- V

CC

)

2

/ R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the

R

GND will produce a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R

GND

.

Doc ID 11038 Rev 4

VND830AEP-E

3.1.2

Application information

If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below.

Solution 2: a diode (D

GND

) in the ground line

A resistor (R

GND

= 1k

Ω

) should be inserted in parallel to D

GND

if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD.

Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum

Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

3.2 Load dump protection

D ld

is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V

CC line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the V

CC

line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot

) in line to prevent the µC I/O pins from latching up.

The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC

I/Os:

- V

CCpeak

/ I latchup

≤ R prot

≤ (V

OH

μ

C

- V

IH

- V

GND

) / I

IHmax

Example

For the following conditions:

V

CCpeak

= - 100V

I latchup

≥ 20mA

V

OH

μ

C

≥

4.5V

5k Ω ≤ R prot

≤ 65k Ω .

Recommended values are:

R prot

= 10k

Ω

Doc ID 11038 Rev 4 17/26

Application information

3.4 Maximum demagnetization energy (V

CC

= 13.5V)

Figure 20.

Maximum turn-off current versus load inductance

I LMAX (A)

100

VND830AEP-E

10

A

C

B

1

0.1

1

L(mH)

10

A = single pulse at T

Jstart

= 150ºC

B= repetitive pulse at T

Jstart

= 100ºC

C= repetitive pulse at T

Jstart

= 125ºC

V

IN

, I

L

Demagnetization Demagnetization Demagnetization

Note: t

Values are generated with R

L

= 0 Ω.

In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.

18/26 Doc ID 11038 Rev 4

VND830AEP-E

4

Package and PC board thermal data

Package and PC board thermal data

4.1 PowerSSO-24 thermal data

Figure 21.

PowerSSO-24 PC board

Note: Layout condition of R th

and Z th

measurements (PCB FR4 area= 78 mm x 78 mm, PCB thickness=2 mm, Cu thickness=70 mm (front and back side), Copper areas: from minimum pad lay-out to 8 cm

2

).

Figure 22.

R thj-amb

vs PCB copper area in open box free air condition (one channel ON)

RTHj_amb(°C/W)

60

55

50

45

40

0 1 2 3 4 5

PCB Cu heatsink area (cm^2)

6 7 8 9

Doc ID 11038 Rev 4 19/26

Package and PC board thermal data VND830AEP-E

Figure 23.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)

100

ZTH (°C/W)

Footprint

8 cm

2

10

1

0.1

0.0001

0.001

0.01

0.1

Time (s)

1 10 100 1000

Figure 24.

Thermal fitting model of a double channel HSD in PowerSSO-24

(b)

20/26

Equation 1 : pulse calculation formula :

Z

TH δ = R

TH where δ = t

P

/T

⋅ δ

+ Z

THtp

( 1 –

δ ) b.

The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 11038 Rev 4

VND830AEP-E

Table 15.

Thermal parameters

Area/island (cm

2

)

R1 = R7 (°C/W)

R2 = R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 = C7 (W.s/°C)

C2 = C8 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Package and PC board thermal data

8 Footprint

0.0006

0.0025

0.025

0.08

0.7

3

0.1

0.9

1

4

13.5

37 22

5

Doc ID 11038 Rev 4 21/26

Package and packing information

5 Package and packing information

VND830AEP-E

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

5.2 PowerSSO-24 mechanical data

Figure 25.

PowerSSO-24 package dimensions

22/26 Doc ID 11038 Rev 4

VND830AEP-E Package and packing information

Table 16.

PowerSSO-24 mechanical data

(1) (2)

Millimeters

Symbol

Min.

Typ.

Max.

A

A2 a1 b c

D

(3)

E

(3) e

2.15

0

0.33

0.23

10.10

7.40

e3

F

G

G1

H h

10.1

0.8

8.8

2.3

Q

S

T

U k

L

O

0°

0.55

1.2

0.8

2.9

3.65

1

N

X 4.1

10º

4.7

Y

6.5

4.9

(4)

7.1

5.5

(4)

1.

No intrusion allowed inwards the leads.

2.

Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side

3.

“D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15 mm.

4.

Variations for small window leadframe option.

0.1

0.06

10.5

0.4

8°

0.85

2.45

2.35

0.10

0.51

0.32

10.50

7.60

Doc ID 11038 Rev 4 23/26

Package and packing information VND830AEP-E

Figure 26.

PowerSSO-24 tube shipment (no suffix)

C

B

Base Q.ty

Bulk Q.ty

49

1225

Tube length (± 0.5) 532

A 3.5

B

C (± 0.1)

13.8

0.6

All dimensions are in mm.

A

Figure 27.

PowerSSO-24 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

P

D (± 0.05) 1.55

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

24

4

12

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

Start

No components Components No components

500mm min 500mm min

Empty components pockets saled with cover tape.

User direction of feed

24/26 Doc ID 11038 Rev 4

VND830AEP-E

Table 17.

Document revision history

Date Revision

04-Feb-2005

27-Nov-2008

01-Jul-2009

23-Sep-2013

1

2

3

4

Changes

Initial release.

Document reformatted and restructured.

Added list of contents, tables and figures.

Added ECOPACK® packages

information.

Update

PowerSSO-24 mechanical data .

Updated Figure 16: PowerSSO-24 mechanical data

:

– Deleted A (min) value

– Changed A (max) value from 2.50 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Updated k values

– Changed L (min) value from 0.6 to 0.55

– Changed L (max) value from1 to 0.85

Updated disclaimer.

Revision history

Doc ID 11038 Rev 4 25/26

VND830AEP-E

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26/26 Doc ID 11038 Rev 4