STMicroelectronics VND5E050ACK-E Datasheet

VND5E050ACJ-E

VND5E050ACK-E

Double channel high-side driver with analog current sense for automotive applications

Features

Max transient supply voltage

Operating voltage range

V

CC

V

CC

Max On-state resistance (per ch.) R

ON

Current limitation (typ) I

LIMH

Off-state supply current I

S

41 V

4.5 to 28 V

50 m Ω

27 A

2 µA

(1)

1.

Typical value with all loads connected.

■

■

■

General

– Inrush current active management by power limitation

– Very low standby current

– 3.0 V CMOS compatible inputs

– Optimized electromagnetic emissions

– Very low electromagnetic susceptibility

– Compliance with European directive

2002/95/EC

– Very low current sense leakage

Diagnostic functions

– Proportional load current sense

– High current sense precision for wide currents range

– Current sense disable

– Off-state open load detection

– Output short to V

CC

detection

– Overload and short to ground (power limitation) indication

– Thermal shutdown indication

Protections

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Overtemperature shutdown with auto restart (thermal shutdown)

PowerSSO-12 PowerSSO-24

– Reverse battery protected

– Electrostatic discharge protection

Applications

■

■

All types of resistive, inductive and capacitive loads

Suitable as LED driver

Description

The VND5E050ACJ-E and VND5E050ACK-E are double channel high-side drivers manufactured using ST proprietary VIPower

®

M0-5 technology and housed in PowerSSO-12 and PowerSSO-24 packages. The devices are designed to drive 12 V automotive grounded loads, and to provide protection and diagnostics. They also implement a 3 V and 5 V CMOS-compatible interface for use with any microcontroller.

The devices integrate advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short-circuit to V

CC

diagnosis on-state and off-state open-load detection.

The current sensing and diagnostic feedback of the whole device can be disabled by pulling the

CS_DIS pin high to share the external sense resistor with similar devices.

September 2013 Doc ID 022515 Rev 2 1/43 www.st.com

1

6

7

1

2

Contents

Contents

3

4

5

VND5E050ACJ-E, VND5E050ACK-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24

3.1.1

3.1.2

Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24

Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 25

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4.1

Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 26

3.5

Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1

PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2

PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.2

PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3

PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.4

PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.5

PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5.

Table 6.

Table 7.

Table 8.

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Current sense (8 V < V

CC

< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Open load detection (8V<V

CC

<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12.

Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13.

Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14.

Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17.

PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18.

PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 19.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 20.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Doc ID 022515 Rev 2 3/43

List of figures

List of figures

VND5E050ACJ-E, VND5E050ACK-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

Open load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

Delay response time between rising edge of output current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

I

OUT

/I

SENSE

vs I

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11.

Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.

Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.

Off-state open load with external circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.

Short to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16.

T

J

evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 19.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 21.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 22.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23.

On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 24.

On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 25.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 26.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27.

ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 28.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 29.

CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30.

CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 31.

CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 32.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 33.

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 34.

Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28

Figure 35.

PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 36.

Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 29

Figure 37.

PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30

Figure 38.

Thermal fitting model of a double channel HSD in PowerSSO-12

. . . . . . . . . . . . . . . . . . . 30

Figure 39.

PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 40.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 32

Figure 41.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 33

Figure 42.

Thermal fitting model of a double channel HSD in PowerSSO-24

. . . . . . . . . . . . . . . . . . . 33

Figure 43.

PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 44.

PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 45.

PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 46.

PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 47.

PowerSS0-24

tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E List of figures

Figure 48.

PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Doc ID 022515 Rev 2 5/43

6/43

Block diagram and pin description

1

VND5E050ACJ-E, VND5E050ACK-E

Block diagram and pin description

Figure 1.

Block diagram

IN1

IN2

CS_

DIS

CS1

CS2

Signal Clamp

Undervoltage

LOGIC

Control & Diagnostic 1

Power

Clamp

DRIVER

V

ON

Limitation

Over temp.

Current

Limitation

OFF State

Open load

V

SENSEH

Current

Sense

OVERLOAD PROTECTION

(ACTIVE POWER LIMITATION)

CH 1

V

CC

GND

CH 2

OUT2

OUT1

Table 1.

Name

Pin function

Function

V

CC

OUTPUT

GND

INPUT

1,2

1,2

Battery connection.

Power output.

Ground connection. Must be reverse battery protected by an external diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.

CURRENT

SENSE

1,2

CS_DIS

Analog current sense pin, delivers a current proportional to the load current.

Active high CMOS compatible pin, to disable the current sense pin.

Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Block diagram and pin description

Figure 2.

Configuration diagram (top view)

TAB = V cc

GND

INPUT2

INPUT1

CURRENT SENSE1

CURRENT SENSE2

CS_DIS

3

4

5

6

1

2

9

8

7

12

11

10

V cc

OUTPUT2

OUTPUT2

OUTPUT1

OUTPUT1

V cc

V

CC

GND

N.C.

INPUT2

N.C.

INPUT1

N.C.

CURRENT SENSE1

N.C.

CURRENT SENSE2

CS_DIS.

V

CC

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

TAB = V

CC

PowerSSO-12 PowerSSO-24

Table 2.

Suggested connections for unused and not connected pins

Connection / pin Current sense N.C.

Output Input

Floating

To ground

Not allowed

Through 1 K Ω resistor

X

X

CS_DIS

X X X

Through 22 K Ω resistor

Through 10 K Ω resistor

Through 10 K Ω resistor

Doc ID 022515 Rev 2 7/43

Electrical specifications VND5E050ACJ-E, VND5E050ACK-E

Figure 3.

Current and voltage conventions

V

CSD

I

CSD

I

IN1

V

IN1

I

IN2

V

IN2

I

S

V

CC

CS_DIS

OUTPUT1

CURRENT

SENSE1

INPUT1

INPUT2

OUTPUT2

GND

CURRENT

SENSE2

V

Fn

I

OUT1

I

SENSE1

V

SENSE1

I

OUT2

I

SENSE2

V

SENSE2

V

OUT2

V

OUT1

I

GND

V

CC

Note: V

Fn

= V

OUTn

- V

CC

during reverse battery condition.

8/43

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in the table for extended periods may affect device reliability.

Table 3.

Symbol

Absolute maximum ratings

Parameter

V

CC

-V

CC

-I

GND

I

OUT

-I

OUT

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

DC output current

Reverse DC output current

I

IN

I

CSD

-I

CSENSE

DC input current

DC current sense disable input current

DC reverse CS pin current

V

CSENSE

Current sense maximum voltage

Value

41

0.3

200

Internally limited

20

-1 to 10

-1 to 10

200

V

CC

- 41 to

+V

CC

Unit

V

V mA

V

A

A mA mA mA

Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

Table 3.

Symbol

E

MAX

V

ESD

Absolute maximum ratings (continued)

Parameter

Maximum switching energy (single pulse)

(L = 3mH; R

L

=0 Ω ; V bat

=13.5V; T jstart

=150°C; I

OUT

Electrostatic discharge

(human body model: R=1.5K

Ω; C=100pF)

– Input

– Current sense

– CS_DIS

– Output

– V

CC

Charge device model (CDM-AEC-Q100-011) V

ESD

T j

T stg

Junction operating temperature

Storage temperature

Electrical specifications

Value

104

Unit mJ

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

°C

°C

V

V

V

V

V

V

Table 4.

Symbol

Thermal data

Parameter

R thj-case

Thermal resistance junction-case (with one channel ON)

R thj-amb

Thermal resistance junction-ambient

Max value

PowerSSO-12 PowerSSO-24

Unit

2.7

See

Figure 36

2.7

°C/W

See Figure 40

°C/W

Values specified in this section are for 8 V<V

CC

<28 V; -40 °C<T j

<150 °C, unless otherwise stated.

Table 5.

Symbol

Power section

Parameter

V

CC

Operating supply voltage

V

USD

Undervoltage shutdown

V

USDhyst

Undervoltage shutdown hysteresis

Test conditions Min.

Typ. Max. Unit

4.5

13

3.5

4.5

0.5

28 V

V

V

R

ON

On-state resistance

(1)

V clamp

Clamp voltage

I

OUT

= 2 A; T j

= 25°C

I

OUT

= 2 A; T j

= 150°C

I

OUT

= 2 A; V

CC

= 5 V; T j

= 25°C

I

S

= 20 mA 41 46

50

100

65

52 m

Ω

V

Doc ID 022515 Rev 2 9/43

Electrical specifications VND5E050ACJ-E, VND5E050ACK-E

Table 5.

Symbol

Power section (continued)

Parameter Test conditions

I

I

L(off1)

V

S

F

Supply current

Off-state output current

(1)

Off-state; V

CC

V

IN

= V

OUT

= V

= 13 V; T

SENSE j

= V

= 25°C;

CSD

= 0 V

I

On-state; V

CC

OUT

= 0 A

= 13 V; V

IN

= 5 V;

V

IN

T j

= V

OUT

= 25°C

= 0 V; V

CC

= 13 V;

V

IN

T j

= V

OUT

= 125°C

= 0 V; V

CC

= 13 V;

Output - V

CC

diode voltage

(1)

-I

OUT

= 4 A; T j

= 150°C

1.

For each channel.

2.

PowerMOS leakage included.

Min.

Typ. Max. Unit

0

2

(2)

5

(2)

3

µA

6 mA

0 0.01

3

5

0.7

µA

V

Table 6.

Symbol

Switching (V

CC

= 13V; T j

= 25°C)

Parameter Test conditions t d(on) t d(off)

Turn-on delay time

Turn-off delay time

R

L

= 6. 5

Ω

(see Figure 6 )

R

L

= 6. 5 Ω

(see Figure 6 )

dV

OUT

/dt

(on)

Turn-on voltage slope R

L

= 6. 5 Ω

Min.

—

—

—

—

Typ.

20

45

See

Figure 26

See

Figure 28

dV

OUT

/dt

(off)

Turn-off voltage slope R

L

= 6. 5 Ω

W

W

ON

OFF

Switching energy losses during t won

Switching energy losses during t woff

R

R

L

L

= 6. 5

= 6. 5

Ω

Ω

(see

(see

Figure 6

Figure 6 )

)

—

—

0.15

0.3

Max.

Unit

—

—

µs

µs

— V / µs

— V / µs

—

— mJ mJ

Table 7.

Symbol

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

Logic inputs

Parameter

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

ICL

Input clamp voltage

V

CSDL

I

CSDL

V

CSDH

CS_DIS low level voltage

Low level CS_DIS current

CS_DIS high level voltage

Test conditions

V

IN

= 0.9 V

V

IN

= 2.1 V

I

IN

= 1 mA

I

IN

= -1 mA

V

CSD

= 0.9 V

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

10

7

V

µA

V

µA

V

V

-0.7

1

2.1

0.9

V

µA

V

10/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Electrical specifications

Table 7.

Symbol

Logic inputs (continued)

Parameter

I

CSDH

V

CSD(hyst)

High level CS_DIS current

CS_DIS hysteresis voltage

Test conditions

V

CSD

= 2.1 V

V

CSCL

CS_DIS clamp voltage

I

CSD

= 1 mA

I

CSD

= -1 mA

Min.

Typ.

Max.

Unit

0.25

5.5

10

7

µA

V

V

-0.7

Table 8.

Protections and diagnostics

(1)

Symbol Parameter Test conditions Min.

Typ.

Max.

Unit

T

I

T

I limH limL

T

T

TSD

R

RS

HYST

DC short circuit current

Short circuit current during thermal cycling

Shutdown temperature

Reset temperature

Thermal reset of status

Thermal hysteresis

(T

TSD

-T

R

)

Turn-off output voltage clamp

V

CC

= 13 V

5 V < V

CC

< 28 V

V

T

CC

R

= 13 V;

< T j

< T

TSD

19

150 175

T

RS

+1 T

RS

+5

135

27

7

7

38

38

200

A

A

A

°C

V

DEMAG

V

ON

Output voltage drop limitation

I

OUT

= 2 A; V

L = 6 mH

IN

= 0;

I

OUT

T j

= 0.1 A;

= -40°C...+150°C

(see Figure 8 )

V

CC

-41 V

CC

-46 V

25

CC

-52

1.

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

V mV

°C

°C

°C

Table 9.

Symbol

K

K

0

1 dK

1

/K

1

(1)

K

2 dK

2

/K

2

(1)

Current sense (8 V < V

CC

< 18 V)

Parameter Test conditions Min.

Typ.

Max.

Unit

I

I

OUT

OUT

/I

/I

SENSE

SENSE

I

OUT

= 0.05 A;

V

SENSE

T j

= 0.5 V;V

CSD

= -40°C...150°C

= 0 V;

I

OUT

= 1 A; V

SENSE

= 4 V;V

CSD

= 0 V;

T j

= -40°C...150°C

T j

= 25°C...150°C

I

Current sense ratio drift

I

OUT

T

J

= 1 A; V

SENSE

= 4 V; V

= -40 °C to 150 °C

CSD

= 0 V;

OUT

/I

SENSE

I

OUT

= 2 A; V

SENSE

= 4 V;V

CSD

= 0 V;

T j

= -40°C...150°C

T j

= 25°C...150°C

Current sense ratio drift

I

OUT

T

J

= 2 A; V

SENSE

= 4 V; V

= -40 °C to 150 °C

CSD

= 0 V;

1440 2250 3630

1740

1750

-15

1900

1899

-9

2070

2070

2000

2000

2820

2562

15

2395

2282

9

%

%

Doc ID 022515 Rev 2 11/43

Electrical specifications VND5E050ACJ-E, VND5E050ACK-E

Table 9.

Symbol

Current sense (8 V < V

CC

< 18 V) (continued)

Parameter Test conditions Min.

Typ.

Max.

Unit dK

I

SENSE0

V

3

I

K

3

/K

3

(1)

OL

SENSE

I

OUT

/I

SENSE

I

OUT

= 4 A; V

SENSE

= 4 V; V

CSD

= 0 V;

T j

= -40°C...150°C

T j

= 25°C...150°C

Current sense ratio drift

I

OUT

= 4 A; V

SENSE

= 4 V; V

CSD

= 0 V;

T

J

= -40 °C to 150 °C

Analog sense leakage current

I

OUT

V

IN

= 0 A; V

= 0 V; T j

SENSE

= 0 V; V

CSD

= -40°C...150°C

= 5 V;

I

OUT

V

IN

= 0 A; V

= 5 V; T j

SENSE

= 0 V; V

CSD

= -40°C...150°C

= 0 V;

1969

1950

-6

0

0

I

OUT

V

IN

= 2 A; V

= 5 V; T j

SENSE

= 0 V; V

CSD

= -40°C...150°C

= 5 V;

Open load on-state current detection threshold

I

V

IN

= 5 V; 8 V < V

CC

SENSE

= 5 µA

< 18 V;

0

4

1990

1990

2210

2153

6

1

2

1

20

%

µA mA

Max analog sense output voltage

I

OUT

= 4 A; V

CSD

= 0 V 5 V

V

SENSEH

I

SENSEH

Analog sense output voltage in fault condition

(2)

Analog sense output current in fault condition

(2)

V

V

CC

CC

= 13 V; R

= 13 V; V

SENSE

SENSE

= 3.9 K

= 5 V

Ω 8

9

V mA t

DSENSE1H

Delay response time from falling edge of CS_DIS pin t

DSENSE1L

Delay response time from rising edge of CS_DIS pin

I

I

V

SENSE

(see

Figure 4

)

V

SENSE

SENSE

SENSE

< 4 V; 0.5 A < I

= 90% of I

SENSEMAX

< 4 V; 0.5 A < I

= 10% of I

(see

Figure 4

)

OUT

OUT

SENSEMAX

< 4 A;

< 4 A; t t

DSENSE2H

DSENSE2L

Delay response time from rising edge of INPUT pin

Delay response time from falling edge of INPUT pin

V

SENSE

I

SENSE

< 4 V; 0.5 A < I

= 90% of I

(see

Figure 4

)

OUT

SENSEMAX

< 4 A;

Δ t

DSENSE2H

Delay response time between rising edge of output current and rising edge of current sense

V

SENSE

I

SENSE

< 4V;

= 90% of I

SENSEMAX,

I

OUT

= 90% of I

OUTMAX

I

OUTMAX

= 2A (see

Figure 7

)

V

SENSE

< 4 V; 0.5 A < I

OUT

I

SENSE

=10% of I

SENSEMAX

< 4 A;

(see

Figure 4

)

40

5

80

80

100

20

250

40

250

µs

µs

µs

µs

µs

1.

Parameter guaranteed by design; it is not tested.

2.

Fault condition includes: power limitation, over temperature and open load off-state detection.

12/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Electrical specifications

Table 10.

Open load detection (8V<V

CC

<18V)

Symbol Parameter Test conditions

V

OL t

DSTKON

I

I

L(off2)r

L(off2)f td_vol

Open load off-state voltage detection threshold

Output short circuit to

V

CC

detection delay at turn-off

Off-state output current at V

OUT

= 4V

Off-state output current at V

OUT

= 2V

Delay response from output rising edge to

V

SENSE rising edge in open load

V

IN

= 0 V

See

Figure 5

Min.

2

180

V

IN

= 0 V; V

SENSE

= 0 V;

V

OUT rising from 0 V to 4 V

V

IN

= 0 V; V

SENSE

= V

SENSEH

V

OUT falling from V

CC

to 2 V

-120

-50

V

OUT

= 4 V; V

IN

V

SENSE

= 0 V;

= 90% of V

SENSEH

Typ.

Max. Unit

See

Figure 5

4

0

V

1200 µs

µA

90 µA

20 µs

Figure 4.

Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT t

DSENSE2H t

DSENSE1L t

DSENSE1H t

DSENSE2L

Figure 5.

Open load off-state delay timing

OUTPUT STUCK TO V

CC

V

IN

V

OUT

> V

OL

V

SENSEH

V

CS t

DSTKON

Doc ID 022515 Rev 2 13/43

Electrical specifications

Figure 6.

Switching characteristics

V

OUT t

Won

80% dV

OUT

/dt

(on) t r

10%

INPUT t d(on) t d(off)

VND5E050ACJ-E, VND5E050ACK-E t

Woff

90% t f dV

OUT

/dt

(off) t

14/43 t

Figure 7.

Delay response time between rising edge of output current and rising edge of current sense (CS enabled)

V

IN

Δ t

DSENSE2H t

I

OUT

90% I

OUTMAX

I

OUTMAX t

I

SENSE I

SENSEMAX

90% I

SENSEMAX t

Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

Figure 8.

Output voltage drop limitation

V cc

-V out

T j

=150 o

C

T j

=25 o

C

T j

=-40 o

C

Electrical specifications

V on

V on

/R on(T)

Figure 9.

I

OUT

/I

SENSE

vs I

OUT

I out

/ I sense

3000

2800 max Tj = -40 °C to 150 °C

2600

2400

2200 max Tj = 25 °C to 150 °C

2000 min Tj = 25 °C to 150 °C

1800

1600 min Tj = -40 °C to 150 °C

1400

1200

1 1,5 2 2,5

I

OUT

(A) typical value

3

I out

3,5 4

Doc ID 022515 Rev 2 15/43

Electrical specifications

Note:

VND5E050ACJ-E, VND5E050ACK-E

Figure 10.

Maximum current sense ratio drift vs load current dk/k(%)

20

15

10

5

0

-5

-10

-15

-20

1 2

I

OUT

(A)

Parameter guaranteed by design; it is not tested.

3 4

Table 11.

Truth table

Conditions

Normal operation

Overtemperature

Undervoltage

Overload

Input

L

H

L

H

L

H

H

H

Output

L

L

L

H

L

L

X

(no power limitation)

Cycling

(power limitation)

L

L

Sense (V

CSD

= 0 V)

(1)

0

Nominal

0

V

SENSEH

0

0

Nominal

V

SENSEH

Short circuit to GND

(power limitation)

L

H

0

V

SENSEH

Open load off-state (with external pull-up)

Short circuit to V

CC

(external pull-up disconnected)

L

L

H

H

H

H

V

V

SENSEH

SENSEH

< Nominal

Negative output voltage clamp

L L 0

1.

If the V

CSD

is high, the SENSE output is at high impedance; its potential depends on leakage currents and external circuits.

16/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Electrical specifications

Table 12.

Electrical transient requirements (part 1)

ISO 7637-2:

2004(E) test pulse

III

Test levels

(1)

IV

Number of pulses or test times

Burst cycle/pulse repetition time

Min.

Max.

1

2a

3a

3b

4

5b

(2)

-75V

+37V

-100V

+75V

-6V

+65V

-100V

+50V

-150V

+100V

-7V

+87V

5000 pulses

5000 pulses

1h

1h

1 pulse

1 pulse

0.5s

0.2s

90ms

90ms

5s

5s

100ms

100ms

1.

The above test levels must be considered referred to V

CC

= 13.5V except for pulse 5b.

2.

Valid in case of external load dump clamp: 40V maximum referred to ground.

Delays and

Impedance

2 ms, 10 Ω

50µs, 2 Ω

0.1µs, 50

Ω

0.1µs, 50 Ω

100ms, 0.01

Ω

400ms, 2 Ω

Table 13.

Electrical transient requirements (part 2)

Test level results ISO 7637-2:

2004E test pulse III

1

2a

3a

3b

4

5b

(1)

C

C

C

C

C

C

1.

Valid in case of external load dump clamp: 40V maximum referred to ground.

VI

C

C

C

C

C

C

Table 14.

Electrical transient requirements (part 3)

Class Contents

C

E

All functions of the device performed as designed after exposure to disturbance.

One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

Doc ID 022515 Rev 2 17/43

Electrical specifications

2.4 Waveforms

Figure 11.

Normal operation

VND5E050ACJ-E, VND5E050ACK-E

Normal operation

INPUT

I

OUT

V

SENSE

V

CS_DIS

Nominal load Nominal load

Figure 12.

Overload or short to GND

Overload or Short to GND

INPUT

I

LimH

>

I

OUT

Power Limitation

I

LimL

>

Thermal cycling

V

SENSE

V

CS_DIS

18/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

Figure 13.

Intermittent overload

Intermittent Overload

Electrical specifications

INPUT

I

LimH

>

I

OUT

V

SENSEH

>

V

SENSE

V

CS_DIS

Overload

I

LimL

>

Figure 14.

Off-state open load with external circuitry

OFF-State Open Load with external circuitry

Nominal load

INPUT

V

OUT

I

OUT

V

SENSE

V

CS_DIS

V

OL

V

OUT

V

SENSEH

> t

DSTK(on)

> V

OL

Doc ID 022515 Rev 2 19/43

Electrical specifications VND5E050ACJ-E, VND5E050ACK-E

Figure 15.

Short to V

CC

Resistive

Short to V

CC

Short to V

CC

Hard

Short to V

CC

V

OUT

I

OUT

V

OL

V

OUT

> V

OL t

DSTK(on) t

DSTK(on)

V

CS_DIS

Figure 16.

T

J

evolution in overload or short to GND

T

J

evolution in

Overload or Short to GND

INPUT

Self-limitation of fast thermal transients T

TSD

T

R

T

J

I

LimH

>

T

J_START

Power Limitation

T

HYST

< I

LimL

I

OUT

20/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Electrical specifications

Figure 17.

Off-state output current

Iloff (nA)

550

500

450

400

350

300

250

200

150

100

50

0

-50 -25

Off State

Vcc=13V

Vin=Vout=0V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 19.

Input clamp voltage

Vicl (V)

7

6,8

6,6

6,4

6,2

6

5,8

5,6

5,4

5,2

5

-50 -25 lin=1mA

0 25 50 75

Tc (°C)

100 125 150 175

Figure 21.

Input high level

Vih (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 18.

High level input current

Iih (µA)

5

4,5

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25

Vin=2.1V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 20.

Input low level

Vil (V)

2

1,8

1,6

1,4

1,2

1

0,8

0,6

0,4

0,2

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 22.

Input hysteresis voltage

Vihyst (V)

1

0,9

0,8

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Doc ID 022515 Rev 2 21/43

Electrical specifications

Figure 23.

On-state resistance vs T case

Ron (mOhm)

300

250

Iout= 2A

Vcc=13V

200

150

100

50

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 25.

Undervoltage shutdown

Vusd (V)

16

10

8

6

4

14

12

2

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 27.

I

LIMH

vs T case

Ilimh (A)

40

35

30

25

20

15

Vcc=13V

10

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

VND5E050ACJ-E, VND5E050ACK-E

Figure 24.

On-state resistance vs V

CC

Ron (mOhm)

100

80

Tc=150°C

Tc=125°C

60

40

Tc=25°C

Tc=-40°C

20

0

0 5 10 15 20

Vcc (V)

25 30 35 40

Figure 26.

Turn-on voltage slope

(dVout/dt )On (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25

Vcc=13V

RI=6.5 Ohm

50 75

Tc (°C)

100 125 150 175

Figure 28.

Turn-off voltage slope

(dVout/dt )Off (V/ms)

600

550

500

450

400

350

300

250

200

150

100

50

0

-50 -25 0 25

Vcc=13V

RI= 6.5 Ohm

50 75

Tc (°C)

100 125 150 175

22/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

Figure 29.

CS_DIS high level voltage

Vcsdh (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 31.

CS_DIS low level voltage

Vcsdl (V)

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Electrical specifications

Figure 30.

CS_DIS clamp voltage

Vcsdcl(V)

10

5

4

3

2

9

8

7

6

1

0

-50 -25 0 25

Icsd = 1 mA

50 75

Tc (°C)

100 125 150 175

Doc ID 022515 Rev 2 23/43

Application information VND5E050ACJ-E, VND5E050ACK-E

Figure 32.

Application schematic

+5V

Μ

CU

V

CC

R prot CS_DIS

R prot

R prot

INPUT

C

EXT

R

SENSE

CURRENT SENSE

GND

V

GND

R

GND

D

GND

OUTPUT

D ld

Note:

3.1

3.1.1

24/43

Channel 2 has the same internal circuit as channel 1.

GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.

Solution 1: resistor in the ground line (R

GND

only)

This can be used with any type of load.

The following is an indication on how to resize the R

GND resistor.

1.

R

GND

≤ 600 mV / (I

S(on)max

)

2. R

GND

≥ (−

V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

< 0: during reverse battery situations) is:

P

D

= (-V

CC

)

2

/R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the

R

GND produces a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift varies depending on how many devices are on in case of several high side drivers sharing the same R

GND

.

Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

3.1.2

Application information

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize

Section 3.1.2: Solution 2: diode (DGND) in the ground line .

Solution 2: diode (D

GND

) in the ground line

A resistor (R

GND inductive load.

= 1 k

Ω) should be inserted in parallel to D

GND

if the device drives an

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (

≈

600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

D ld

is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V

CC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3

3.4

MCU I/Os protection

If a ground protection network is used and negative transients are present on the V

CC

line, the control pins are pulled negative.

ST suggests to insert a resistor (R prot

) in line to prevent the microcontroller I/O pins from latching-up.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os:

-V

CCpeak

/I latchup

≤

R prot

≤

(V

OH

μ

C

-V

IH

-V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= - 100V and I latchup

≥

20mA; V

OHµC

≥

4.5V

5k

Ω ≤

R prot

≤

180k

Ω

Recommended values: R prot

=10k

Ω

, C

EXT

=10nF.

Current sense and diagnostic

The current sense pin performs a double function (see

Figure 33: Current sense and diagnostic

):

● Current mirror of the load current in normal operation, delivering a current proportional to the load current according to a known ratio K

X

.

The current I

SENSE

can be easily converted to a voltage V

SENSE

by means of an external resistor R

SENSE

. Linearity between I

OUT

and V

SENSE

is ensured up to 5V minimum (see parameter V

SENSE

in Table 9: Current sense (8 V < V

CC

< 18 V)

). The current sense accuracy depends on the output current (refer to current sense electrical

Doc ID 022515 Rev 2 25/43

Application information VND5E050ACJ-E, VND5E050ACK-E

● characteristics

Table 9: Current sense (8 V < V

CC

< 18 V) ).

Diagnostic flag in fault conditions, delivering a fixed voltage V

SENSEH

up to a maximum current I

SENSEH

in case of the following fault conditions (refer to

Table 11: Truth table ):

– Power limitation activation

– Overtemperature

– Short to V

CC

in off-state

– Open-load in off-state with additional external components.

A logic level high on the CS_DIS pin simultaneously sets all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing the sense resistance and ADC line among different devices.

Figure 33.

Current sense and diagnostic

V

BAT

V

PU

I

OUT

/K

X

CS_DIS

41V

I

SENSEH

R

PROT

To uC ADC

R

SENSE

CURRENT

SENSEn

V

SENSEH

V

SENSE

V

CC

Main MOSn

PU_CMD

Overtemperature

OL OFF

Pwr_Lim

INPUTn

+

-

R

PU

V

OL

OUTn

I

Loff2r

I

Loff2f

GND

R

PD

Load

3.4.1 Short to V

CC

and off-state open-load detection

Short to V

CC

A short circuit between V

CC and output is indicated by the relevant current sense pin set to

V

SENSEH

during the device off-state. Little or no current is delivered by the current sense during the on-state depending on the nature of the short circuit.

Off-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor (R

PU

) connecting the output to a positive supply voltage (V

PU

).

26/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Application information

It is preferable that V

PU

is switched off during the module standby mode to avoid an increase in overall standby current consumption in normal conditions, that is, when the load is connected.

An external pull-down resistor (R

PD

) connected between output and GND is mandatory to

avoid misdetection in case of floating outputs in off-state (see Figure 33: Current sense and diagnostic

).

R

PD

must be selected in order to ensure V circuitry:

OUT

< V

OLmin

unless pulled up by the external

V

OUT

Pull

− up _ OFF

=

R

PD

⋅

I

L ( off 2 ) f

<

V

OL min

=

2 V

R

PD

≤

22 K Ω is recommended.

For proper open load detection in off-state, the external pull-up resistor must be selected according to the following formula:

V

OUT

Pull − up _ ON

=

R

PD

⋅

V

PU

−

R

PU

R

PU

⋅

R

PD

+

R

PD

⋅

I

L ( off 2 ) r

>

V

OL max

=

4 V

For the values of V

OLmin

,V

OLmax

, I

L(off2)r and I

(8V<V

CC

<18V) .

L(off2)f see

Table 10: Open load detection

Doc ID 022515 Rev 2 27/43

Application information

3.5

VND5E050ACJ-E, VND5E050ACK-E

Maximum demagnetization energy (V

CC

= 13.5V)

Figure 34.

Maximum turn-off current versus inductance (for each channel)

100

10

C

A

B

1

0,1 1 L (mH) 10 100

A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

V

IN

, I

L

Demagnetization Demagnetization Demagnetization

Note: t

Values are generated with R

L

=0

Ω.

In case of repetitive pulses, T jstart

(at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

28/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

4 Package and PCB thermal data

Package and PCB thermal data

4.1 PowerSSO-12 thermal data

Figure 35.

PowerSSO-12 PC board

Note: Layout condition of R th

and Z th

measurements (PCB: double layer, thermal vias, FR4 area=

77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side), copper areas: from minimum pad lay-out to 8cm

2

).

Figure 36.

R thj-amb

Vs. PCB copper area in open box free air condition (one channel

ON)

RTHj _amb( ° C/ W)

70

65

60

55

50

45

40

35

30

0 2 4 6

PCB Cu heat sink area ( cm^ 2)

8 10

Doc ID 022515 Rev 2 29/43

Package and PCB thermal data VND5E050ACJ-E, VND5E050ACK-E

Figure 37.

PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON)

ZTH ( ° C/ W)

100 Footprint

2 cm

2

8 cm

2

10

1

0,1

0,0001 0,001 0,01 0,1

Time ( s)

1 10 100 1000

Equation 1: pulse calculation formula

Z

TH

δ where

= R

T H

⋅ δ + Z

THtp

( 1 – δ )

δ

= t p

⁄ T

Figure 38.

Thermal fitting model of a double channel HSD in PowerSSO-12

1.

The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

30/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

Table 15.

Thermal parameters

Area/island (cm

2

)

R1=R7 (°C/W)

R2=R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1=C7 (W.s/°C)

C2=C8 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Footprint

0.001

0.0025

0.05

0.2

0.27

3

0.7

2.8

4

8

22

26

4.2 PowerSSO-24 thermal data

Figure 39.

PowerSSO-24 PC board

Package and PCB thermal data

2

0.1

0.8

6

8

15

20

8

0.1

1

9

7

10

15

Note: Layout condition of R th

and Z th

measurements (PCB: double layer, thermal vias, FR4 area=

77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side), copper areas: from minimum pad lay-out to 8cm

2

).

Doc ID 022515 Rev 2 31/43

Package and PCB thermal data VND5E050ACJ-E, VND5E050ACK-E

Figure 40.

R thj-amb

vs PCB copper area in open box free air condition (one channel

ON)

RTHj_amb(°C/W)

55

50

45

40

35

30

0 2 4 6

PCB Cu heatsink area (cm^2)

8 10

32/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Package and PCB thermal data

Figure 41.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)

Equation 2: pulse calculation formula

Z

TH

δ where

= R

T H

⋅ δ + Z

THtp

( 1 – δ )

δ

= t p

⁄

T

Figure 42.

Thermal fitting model of a double channel HSD in PowerSSO-24

1.

The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 022515 Rev 2 33/43

Package and PCB thermal data

Table 16.

Thermal parameters

Area / island (cm

2

)

R1 = R7 (°C/W)

R2 = R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 = C7 (W.s/°C)

C2 = C8 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Footprint

0.001

0.0022

0.025

0.75

1

2.2

0.4

2

6

7.7

9

28

VND5E050ACJ-E, VND5E050ACK-E

2

4

5

9

17

8

8

10

9

17

34/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK® is an ST trademark.

5.2 PowerSSO-12 package information

Figure 43.

PowerSSO-12 package dimensions

Doc ID 022515 Rev 2 35/43

Package and packing information

Table 17.

PowerSSO-12 mechanical data

Symbol h

L k e

H

X

Y ddd

B

C

D

E

A

A1

A2

5.8

0.25

0.4

0°

1.9

3.6

0.23

0.19

4.8

3.8

Min.

1.25

0

1.10

VND5E050ACJ-E, VND5E050ACK-E

Millimeters

Typ.

0.8

6.2

0.5

1.27

8°

2.5

4.2

0.1

0.41

0.25

5.0

4.0

Max.

1.62

0.1

1.65

36/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

5.3 PowerSSO-24 package information

Figure 44.

PowerSSO-24 package dimensions

Package and packing information

Doc ID 022515 Rev 2 37/43

Package and packing information VND5E050ACJ-E, VND5E050ACK-E

Table 18.

PowerSSO-24 mechanical data

(1) (2)

Symbol

Millimeters

Typ.

Min.

Max.

A

A2 a1 b c

D

(3)

E

(3) e e3

F

2.15

0

0.33

0.23

10.10

7.40

0.8

8.8

2.3

2.45

2.35

0.1

0.51

0.32

10.50

7.60

h k

L

G

H

O

Q

10.1

0°

0.55

0.1

10.5

0.4

8°

0.85

1.2

0.8

S

T

2.9

3.65

1.0

U

N 10°

X

Y

4.1

6.5

4.7

7.1

1.

No intrusion allowed inwards the leads.

2.

Flash or bleeds on exposed die pad shall not exceed 0.5 mm per side

3.

“D and E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm per side

38/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

5.4

Package and packing information

PowerSSO-12 packing information

Figure 45.

PowerSSO-12 tube shipment (no suffix)

A

B

C

Base q.ty

Bulk q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

100

2000

532

1.85

6.75

0.6

Figure 46.

PowerSSO-12 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base q.ty

Bulk q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

2500

2500

330

1.5

13

20.2

12.4

60

18.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape hole spacing

Component spacing

Hole diameter

Hole diameter

Hole position

Compartment depth

Hole spacing

W

P0 (± 0.1)

P

D (± 0.05)

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

1.5

5.5

4.5

2

12

4

8

1.5

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

Doc ID 022515 Rev 2 39/43

Package and packing information

5.5

VND5E050ACJ-E, VND5E050ACK-E

PowerSSO-24 packing information

Figure 47.

PowerSS0-24 tube shipment (no suffix)

C

B

Base qty

Bulk qty

Tube length (±0.5)

A

B

C (±0.1)

All dimensions are in mm.

49

1225

532

3.5

13.8

0.6

A

Figure 48.

PowerSSO-24 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base qty

Bulk qty

A (max)

B (min)

C (±0.2)

F

G (+2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape hole spacing

Component spacing

Hole diameter

Hole diameter

Hole position

Compartment depth

Hole spacing

W

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

24

4

P 12

D (±0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

No components Components No components

500mm min 500mm min

Empty components pockets sealed with cover tape.

Start

User direction of feed

40/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E Order codes

Table 19.

Device summary

Package

PowerSSO-12

PowerSSO-24

Tube

VND5E050ACJ-E

VND5E050ACK-E

Order codes

Tape and reel

VND5E050ACJTR-E

VND5E050ACKTR-E

Doc ID 022515 Rev 2 41/43

Revision history VND5E050ACJ-E, VND5E050ACK-E

Table 20.

Document revision history

Date Revision

18-Nov-2011

18-Sep-2013

1

2

Initial release.

Updated disclaimer.

Changes

42/43 Doc ID 022515 Rev 2

VND5E050ACJ-E, VND5E050ACK-E

Please Read Carefully:

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Doc ID 022515 Rev 2 43/43